diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml new file mode 100644 index 0000000..e351e32 --- /dev/null +++ b/.github/workflows/lint.yml @@ -0,0 +1,34 @@ +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Nils Wistoff + +name: lint + +on: [ push, pull_request, workflow_dispatch ] + +jobs: + lint-license: + runs-on: ubuntu-latest + steps: + - name: lint license + uses: pulp-platform/pulp-actions/lint-license@v2.4.3 + with: + license: | + Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors). + (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details. + SPDX-License-Identifier: (SHL-0.51|Apache-2.0) + + lint-sv: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + - name: Run Verible + uses: chipsalliance/verible-linter-action@main + with: + paths: src + github_token: ${{ secrets.GITHUB_TOKEN }} + fail_on_error: true + reviewdog_reporter: github-check diff --git a/Bender.yml b/Bender.yml index 40ec53d..de3889a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -1,26 +1,20 @@ +# Copyright 2025 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + package: name: apb_uart - authors: [ - "Sebastian Witt", - "Jonathan Kimmitt" - ] + authors: + - "Nils Wistoff " + - "Paul Scheffler " dependencies: - apb: { git: "https://github.com/pulp-platform/apb", version: 0.2.1 } - register_interface: { git: "https://github.com/pulp-platform/register_interface", version: 0.3.6 } + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } + obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.7 } + obi_peripherals: { git: "https://github.com/pulp-platform/obi_peripherals.git", version: 0.1.0 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.6 } sources: - - src/slib_clock_div.sv - - src/slib_counter.sv - - src/slib_edge_detect.sv - - src/slib_fifo.sv - - src/slib_input_filter.sv - - src/slib_input_sync.sv - - src/slib_mv_filter.sv - - src/uart_baudgen.sv - - src/uart_interrupt.sv - - src/uart_receiver.sv - - src/uart_transmitter.sv - src/apb_uart.sv - src/apb_uart_wrap.sv - src/reg_uart_wrap.sv diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..6d2a11e --- /dev/null +++ b/LICENSE @@ -0,0 +1,176 @@ +SOLDERPAD HARDWARE LICENSE version 0.51 + +This license is based closely on the Apache License Version 2.0, but is not +approved or endorsed by the Apache Foundation. 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See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 -module apb_uart( - input wire CLK, - input wire RSTN, - input wire PSEL, - input wire PENABLE, - input wire PWRITE, - input wire [2:0] PADDR, - input wire [31:0] PWDATA, - output logic [31:0] PRDATA, - output logic PREADY, - output logic PSLVERR, - output logic INT, - output logic OUT1N, - output logic OUT2N, - output logic RTSN, - output logic DTRN, - input wire CTSN, - input wire DSRN, - input wire DCDN, - input wire RIN, - input wire SIN, - output logic SOUT); // 507 -/* design apb_uart */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -// Declare component uart_transmitter; // 950 -// Declare component uart_receiver; // 950 -// Declare component uart_interrupt; // 950 -// Declare component uart_baudgen; // 950 -// Declare component slib_edge_detect; // 950 -// Declare component slib_input_sync; // 950 -reg iWrite; // 612 -reg iRead; // 612 -reg iRST; // 612 -reg iRBRRead; // 612 -reg iTHRWrite; // 612 -reg iDLLWrite; // 612 -reg iDLMWrite; // 612 -reg iIERWrite; // 612 -reg iIIRRead; // 612 -reg iFCRWrite; // 612 -reg iLCRWrite; // 612 -reg iMCRWrite; // 612 -reg iLSRRead; // 612 -reg iMSRRead; // 612 -reg iSCRWrite; // 612 -reg [7:0] iTSR; // 605 -reg [7:0] iRBR; // 605 -reg [7:0] iDLL; // 605 -reg [7:0] iDLM; // 605 -reg [7:0] iIER; // 605 -reg [7:0] iIIR; // 605 -reg [7:0] iFCR; // 605 -reg [7:0] iLCR; // 605 -reg [7:0] iMCR; // 605 -reg [7:0] iLSR; // 605 -reg [7:0] iMSR; // 605 -reg [7:0] iSCR; // 605 -reg iIER_ERBI; // 612 -reg iIER_ETBEI; // 612 -reg iIER_ELSI; // 612 -reg iIER_EDSSI; // 612 -reg iIIR_PI; // 612 -reg iIIR_ID0; // 612 -reg iIIR_ID1; // 612 -reg iIIR_ID2; // 612 -reg iIIR_FIFO64; // 612 -reg iFCR_FIFOEnable; // 612 -reg iFCR_RXFIFOReset; // 612 -reg iFCR_TXFIFOReset; // 612 -reg iFCR_DMAMode; // 612 -reg iFCR_FIFO64E; // 612 -reg [1:0] iFCR_RXTrigger; // 605 -reg [1:0] iLCR_WLS; // 605 -reg iLCR_STB; // 612 -reg iLCR_PEN; // 612 -reg iLCR_EPS; // 612 -reg iLCR_SP; // 612 -reg iLCR_BC; // 612 -reg iLCR_DLAB; // 612 -reg iMCR_DTR; // 612 -reg iMCR_RTS; // 612 -reg iMCR_OUT1; // 612 -reg iMCR_OUT2; // 612 -reg iMCR_LOOP; // 612 -reg iMCR_AFE; // 612 -reg iLSR_DR; // 612 -reg iLSR_OE; // 612 -reg iLSR_PE; // 612 -reg iLSR_FE; // 612 -reg iLSR_BI; // 612 -reg iLSR_THRE; // 612 -reg iLSR_TEMT; // 612 -reg iLSR_FIFOERR; // 612 -reg iMSR_dCTS; // 612 -reg iMSR_dDSR; // 612 -reg iMSR_TERI; // 612 -reg iMSR_dDCD; // 612 -reg iMSR_CTS; // 612 -reg iMSR_DSR; // 612 -reg iMSR_RI; // 612 -reg iMSR_DCD; // 612 -reg iCTSNs; // 612 -reg iDSRNs; // 612 -reg iDCDNs; // 612 -reg iRINs; // 612 -reg iCTSn; // 612 -reg iDSRn; // 612 -reg iDCDn; // 612 -reg iRIn; // 612 -reg iCTSnRE; // 612 -reg iCTSnFE; // 612 -reg iDSRnRE; // 612 -reg iDSRnFE; // 612 -reg iDCDnRE; // 612 -reg iDCDnFE; // 612 -reg iRInRE; // 612 -reg iRInFE; // 612 -reg [15:0] iBaudgenDiv; // 605 -reg iBaudtick16x; // 612 -reg iBaudtick2x; // 612 -reg iRCLK; // 612 -reg iBAUDOUTN; // 612 -reg iTXFIFOClear; // 612 -reg iTXFIFOWrite; // 612 -reg iTXFIFORead; // 612 -reg iTXFIFOEmpty; // 612 -reg iTXFIFOFull; // 612 -reg iTXFIFO16Full; // 612 -reg iTXFIFO64Full; // 612 -reg [5:0] iTXFIFOUsage; // 605 -reg [7:0] iTXFIFOQ; // 605 -reg iRXFIFOClear; // 612 -reg iRXFIFOWrite; // 612 -reg iRXFIFORead; // 612 -reg iRXFIFOEmpty; // 612 -reg iRXFIFOFull; // 612 -reg iRXFIFO16Full; // 612 -reg iRXFIFO64Full; // 612 -reg [10:0] iRXFIFOD; // 605 -reg [10:0] iRXFIFOQ; // 605 -reg [5:0] iRXFIFOUsage; // 605 -reg iRXFIFOTrigger; // 612 -reg iRXFIFO16Trigger; // 612 -reg iRXFIFO64Trigger; // 612 -reg iRXFIFOPE; // 612 -reg iRXFIFOFE; // 612 -reg iRXFIFOBI; // 612 -reg iSOUT; // 612 -reg iTXStart; // 612 -reg iTXClear; // 612 -reg iTXFinished; // 612 -reg iTXRunning; // 612 -reg iSINr; // 612 -reg iSIN; // 612 -reg iRXFinished; // 612 -reg iRXClear; // 612 -reg [7:0] iRXData; // 605 -reg iRXPE; // 612 -reg iRXFE; // 612 -reg iRXBI; // 612 -reg iFERE; // 612 -reg iPERE; // 612 -reg iBIRE; // 612 -reg [6:0] iFECounter; // 900 -reg iFEIncrement; // 612 -reg iFEDecrement; // 612 -reg iRDAInterrupt; // 612 -reg [5:0] iTimeoutCount; // 605 -reg iCharTimeout; // 612 -reg iLSR_THRERE; // 612 -reg iTHRInterrupt; // 612 -reg iTXEnable; // 612 -reg iRTS; // 612 -assign /*903*/ iWrite = (PSEL == 1'b1 && PENABLE == 1'b1) && PWRITE == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iRead = (PSEL == 1'b1 && PENABLE == 1'b1) && PWRITE == 1'b0 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iRST = RSTN == 1'b0 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iRBRRead = (iRead == 1'b1 && PADDR == 3'b000) && iLCR_DLAB == 1'b0 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iTHRWrite = (iWrite == 1'b1 && PADDR == 3'b000) && iLCR_DLAB == 1'b0 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iDLLWrite = (iWrite == 1'b1 && PADDR == 3'b000) && iLCR_DLAB == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iDLMWrite = (iWrite == 1'b1 && PADDR == 3'b001) && iLCR_DLAB == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iIERWrite = (iWrite == 1'b1 && PADDR == 3'b001) && iLCR_DLAB == 1'b0 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iIIRRead = iRead == 1'b1 && PADDR == 3'b010 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iFCRWrite = iWrite == 1'b1 && PADDR == 3'b010 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iLCRWrite = iWrite == 1'b1 && PADDR == 3'b011 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iMCRWrite = iWrite == 1'b1 && PADDR == 3'b100 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iLSRRead = iRead == 1'b1 && PADDR == 3'b101 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iMSRRead = iRead == 1'b1 && PADDR == 3'b110 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iSCRWrite = iWrite == 1'b1 && PADDR == 3'b111 ? 1'b1 : 1'b0; // 905 -slib_input_sync UART_IS_SIN (CLK,iRST,SIN,iSINr); // 879 -slib_input_sync UART_IS_CTS (CLK,iRST,CTSN,iCTSNs); // 879 -slib_input_sync UART_IS_DSR (CLK,iRST,DSRN,iDSRNs); // 879 -slib_input_sync UART_IS_DCD (CLK,iRST,DCDN,iDCDNs); // 879 -slib_input_sync UART_IS_RI (CLK,iRST,RIN,iRINs); // 879 -slib_input_filter #(.SIZE(2)) UART_IF_CTS (CLK,iRST,iBaudtick2x,iCTSNs,iCTSn); // 879 -slib_input_filter #(.SIZE(2)) UART_IF_DSR (CLK,iRST,iBaudtick2x,iDSRNs,iDSRn); // 879 -slib_input_filter #(.SIZE(2)) UART_IF_DCD (CLK,iRST,iBaudtick2x,iDCDNs,iDCDn); // 879 -slib_input_filter #(.SIZE(2)) UART_IF_RI (CLK,iRST,iBaudtick2x,iRINs,iRIn); // 879 - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - /* block const 263 */ - iDLL <= (0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(1<<0); - /* block const 263 */ - iDLM <= (0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - end - else - begin - if ((iDLLWrite == 1'b1)) - begin - iDLL <= PWDATA[7:0] ; // 413 - end - if ((iDLMWrite == 1'b1)) - begin - iDLM <= PWDATA[7:0] ; // 413 - end - end - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iIER[3:0] <= 0; - end - else - begin - if ((iIERWrite == 1'b1)) - begin - iIER[3:0] <= PWDATA[3:0]; - end - end - -assign /*432*/ iIER_ERBI = iIER[0]; // 434 -assign /*432*/ iIER_ETBEI = iIER[1]; // 434 -assign /*432*/ iIER_ELSI = iIER[2]; // 434 -assign /*432*/ iIER_EDSSI = iIER[3]; // 434 -assign iIER[7:4] = 0; - -uart_interrupt UART_IIC ( - .CLK(CLK), - .RST(iRST), - .IER(iIER[3:0] ), - .LSR(iLSR[4:0] ), - .THI(iTHRInterrupt), - .RDA(iRDAInterrupt), - .CTI(iCharTimeout), - .AFE(iMCR_AFE), - .MSR(iMSR[3:0] ), - .IIR(iIIR[3:0] ), - .INT(INT)); // 879 -slib_edge_detect UART_IIC_THRE_ED ( - .CLK(CLK), - .RST(iRST), - .D(iLSR_THRE), - .RE(iLSR_THRERE), - .FE()); // 879 - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iTHRInterrupt <= 1'b0; // 413 - end - else - begin - if (((iLSR_THRERE == 1'b1 | iFCR_TXFIFOReset == 1'b1) | ((iIERWrite == 1'b1 && PWDATA[1] == 1'b1) && iLSR_THRE == 1'b1))) - begin - iTHRInterrupt <= 1'b1; // 413 - end - else if (((iIIRRead == 1'b1 && iIIR[3:1] == 3'b001) | iTHRWrite == 1'b1)) - begin - iTHRInterrupt <= 1'b0; // 413 - end - end - -assign /*903*/ iRDAInterrupt = (iFCR_FIFOEnable == 1'b0 && iLSR_DR == 1'b1) | (iFCR_FIFOEnable == 1'b1 && iRXFIFOTrigger == 1'b1) ? 1'b1 : 1'b0; // 905 -assign /*432*/ iIIR_PI = iIIR[0]; // 434 -assign /*432*/ iIIR_ID0 = iIIR[1]; // 434 -assign /*432*/ iIIR_ID1 = iIIR[2]; // 434 -assign /*432*/ iIIR_ID2 = iIIR[3]; // 434 -assign /*432*/ iIIR_FIFO64 = iIIR[5]; // 434 -assign iIIR[4] = 0; -assign iIIR[5] = iFCR_FIFOEnable ? iFCR_FIFO64E : 1'b0; -assign iIIR[6] = iFCR_FIFOEnable; -assign iIIR[7] = iFCR_FIFOEnable; - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - /* block const 263 */ - iTimeoutCount <= (0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - iCharTimeout <= 1'b0; // 413 - end - else - begin - if (((iRXFIFOEmpty == 1'b1 | iRBRRead == 1'b1) | iRXFIFOWrite == 1'b1)) - begin - /* block const 263 */ - iTimeoutCount <= (0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - end - else if (((iRXFIFOEmpty == 1'b0 && iBaudtick2x == 1'b1) && iTimeoutCount[5] == 1'b0)) - begin - iTimeoutCount <= iTimeoutCount + 1; // 413 - end - if ((iFCR_FIFOEnable == 1'b1)) - begin - if ((iRBRRead == 1'b1)) - begin - iCharTimeout <= 1'b0; // 413 - end - else if ((iTimeoutCount[5] == 1'b1)) - begin - iCharTimeout <= 1'b1; // 413 - end - end - else - begin - iCharTimeout <= 1'b0; // 413 - end - end - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iFCR_FIFOEnable <= 1'b0; // 413 - iFCR_RXFIFOReset <= 1'b0; // 413 - iFCR_TXFIFOReset <= 1'b0; // 413 - iFCR_DMAMode <= 1'b0; // 413 - iFCR_FIFO64E <= 1'b0; // 413 - /* block const 263 */ - iFCR_RXTrigger <= (0<<1)|(0<<0); - end - else - begin - iFCR_RXFIFOReset <= 1'b0; // 413 - iFCR_TXFIFOReset <= 1'b0; // 413 - if ((iFCRWrite == 1'b1)) - begin - iFCR_FIFOEnable <= PWDATA[0]; // 413 - iFCR_DMAMode <= PWDATA[3]; // 413 - iFCR_RXTrigger <= PWDATA[7:6] ; // 413 - if ((iLCR_DLAB == 1'b1)) - begin - iFCR_FIFO64E <= PWDATA[5]; // 413 - end - - if (((PWDATA[1] == 1'b1 | (iFCR_FIFOEnable == 1'b0 && PWDATA[0] == 1'b1)) | (iFCR_FIFOEnable == 1'b1 && PWDATA[0] == 1'b0))) - begin - iFCR_RXFIFOReset <= 1'b1; // 413 - end - - if (((PWDATA[2] == 1'b1 | (iFCR_FIFOEnable == 1'b0 && PWDATA[0] == 1'b1)) | (iFCR_FIFOEnable == 1'b1 && PWDATA[0] == 1'b0))) - begin - iFCR_TXFIFOReset <= 1'b1; // 413 - end - end - end - -assign iFCR[0] = iFCR_FIFOEnable; -assign iFCR[1] = iFCR_RXFIFOReset; -assign iFCR[2] = iFCR_TXFIFOReset; -assign iFCR[3] = iFCR_DMAMode; -assign iFCR[4] = 1'b0; -assign iFCR[5] = iFCR_FIFO64E; -assign iFCR[7:6] = iFCR_RXTrigger; - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - /* block const 263 */ - iLCR <= (0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - end - else - begin - if ((iLCRWrite == 1'b1)) - begin - iLCR <= PWDATA[7:0] ; // 413 - end - end - -assign /*432*/ iLCR_WLS = iLCR[1:0] ; // 434 -assign /*432*/ iLCR_STB = iLCR[2]; // 434 -assign /*432*/ iLCR_PEN = iLCR[3]; // 434 -assign /*432*/ iLCR_EPS = iLCR[4]; // 434 -assign /*432*/ iLCR_SP = iLCR[5]; // 434 -assign /*432*/ iLCR_BC = iLCR[6]; // 434 -assign /*432*/ iLCR_DLAB = iLCR[7]; // 434 - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iMCR[5:0] <= 0; - end - else - begin - if ((iMCRWrite == 1'b1)) - begin - iMCR[5:0] <= PWDATA[5:0]; - end - end - -assign /*432*/ iMCR_DTR = iMCR[0]; // 434 -assign /*432*/ iMCR_RTS = iMCR[1]; // 434 -assign /*432*/ iMCR_OUT1 = iMCR[2]; // 434 -assign /*432*/ iMCR_OUT2 = iMCR[3]; // 434 -assign /*432*/ iMCR_LOOP = iMCR[4]; // 434 -assign /*432*/ iMCR_AFE = iMCR[5]; // 434 -assign iMCR[7:6] = 0; - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iLSR_OE <= 1'b0; // 413 - iLSR_PE <= 1'b0; // 413 - iLSR_FE <= 1'b0; // 413 - iLSR_BI <= 1'b0; // 413 - iFECounter <= 0; // 413 - iLSR_FIFOERR <= 1'b0; // 413 - end - else - begin - if ((((iFCR_FIFOEnable == 1'b0 && iLSR_DR == 1'b1) && iRXFinished == 1'b1) | ((iFCR_FIFOEnable == 1'b1 && iRXFIFOFull == 1'b1) && iRXFinished == 1'b1))) - begin - iLSR_OE <= 1'b1; // 413 - end - else if ((iLSRRead == 1'b1)) - begin - iLSR_OE <= 1'b0; // 413 - end - if ((iPERE == 1'b1)) - begin - iLSR_PE <= 1'b1; // 413 - end - else if ((iLSRRead == 1'b1)) - begin - iLSR_PE <= 1'b0; // 413 - end - if ((iFERE == 1'b1)) - begin - iLSR_FE <= 1'b1; // 413 - end - else if ((iLSRRead == 1'b1)) - begin - iLSR_FE <= 1'b0; // 413 - end - if ((iBIRE == 1'b1)) - begin - iLSR_BI <= 1'b1; // 413 - end - else if ((iLSRRead == 1'b1)) - begin - iLSR_BI <= 1'b0; // 413 - end - if ((iFECounter != 0)) - begin - iLSR_FIFOERR <= 1'b1; // 413 - end - else if ((iRXFIFOEmpty == 1'b1 | iRXFIFOQ[10:8] == 3'b000)) - begin - iLSR_FIFOERR <= 1'b0; // 413 - end - if ((iRXFIFOClear == 1'b1)) - begin - iFECounter <= 0; // 413 - end - else - begin - if ((iFEIncrement == 1'b1 && iFEDecrement == 1'b0)) - begin - iFECounter <= iFECounter + 1; // 413 - end - else if ((iFEIncrement == 1'b0 && iFEDecrement == 1'b1)) - begin - iFECounter <= iFECounter - 1; // 413 - end - end - end +// Nils Wistoff -assign /*903*/ iRXFIFOPE = iRXFIFOEmpty == 1'b0 && iRXFIFOQ[8] == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iRXFIFOFE = iRXFIFOEmpty == 1'b0 && iRXFIFOQ[9] == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iRXFIFOBI = iRXFIFOEmpty == 1'b0 && iRXFIFOQ[10] == 1'b1 ? 1'b1 : 1'b0; // 905 -slib_edge_detect UART_PEDET (.CLK,.RST(iRST),.D(iRXFIFOPE),.RE(iPERE),.FE()); // 879 -slib_edge_detect UART_FEDET (.CLK,.RST(iRST),.D(iRXFIFOFE),.RE(iFERE),.FE()); // 879 -slib_edge_detect UART_BIDET (.CLK,.RST(iRST),.D(iRXFIFOBI),.RE(iBIRE),.FE()); // 879 -assign /*903*/ iFEIncrement = iRXFIFOWrite == 1'b1 && iRXFIFOD[10:8] != 3'b000 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iFEDecrement = (iFECounter != 0 && iRXFIFOEmpty == 1'b0) && ((iPERE == 1'b1 | iFERE == 1'b1) | iBIRE == 1'b1) ? 1'b1 : 1'b0; // 905 -assign iLSR[0] = iLSR_DR; -assign iLSR[1] = iLSR_OE; -assign iLSR[2] = iLSR_PE; -assign iLSR[3] = iLSR_FE; -assign iLSR[4] = iLSR_BI; -assign iLSR[5] = iLSR_THRE; -assign iLSR[6] = iLSR_TEMT; -assign iLSR[7] = iFCR_FIFOEnable && iLSR_FIFOERR; - -assign /*903*/ iLSR_DR = iRXFIFOEmpty == 1'b0 | iRXFIFOWrite == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iLSR_THRE = iTXFIFOEmpty == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iLSR_TEMT = iTXRunning == 1'b0 && iLSR_THRE == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iMSR_CTS = (iMCR_LOOP == 1'b1 && iRTS == 1'b1) | (iMCR_LOOP == 1'b0 && iCTSn == 1'b0) ? 1'b1 : 1'b0; // 905 -assign /*903*/ iMSR_DSR = (iMCR_LOOP == 1'b1 && iMCR_DTR == 1'b1) | (iMCR_LOOP == 1'b0 && iDSRn == 1'b0) ? 1'b1 : 1'b0; // 905 -assign /*903*/ iMSR_RI = (iMCR_LOOP == 1'b1 && iMCR_OUT1 == 1'b1) | (iMCR_LOOP == 1'b0 && iRIn == 1'b0) ? 1'b1 : 1'b0; // 905 -assign /*903*/ iMSR_DCD = (iMCR_LOOP == 1'b1 && iMCR_OUT2 == 1'b1) | (iMCR_LOOP == 1'b0 && iDCDn == 1'b0) ? 1'b1 : 1'b0; // 905 -slib_edge_detect UART_ED_CTS ( - .CLK(CLK), - .RST(iRST), - .D(iMSR_CTS), - .RE(iCTSnRE), - .FE(iCTSnFE)); // 879 -slib_edge_detect UART_ED_DSR ( - .CLK(CLK), - .RST(iRST), - .D(iMSR_DSR), - .RE(iDSRnRE), - .FE(iDSRnFE)); // 879 -slib_edge_detect UART_ED_RI ( - .CLK(CLK), - .RST(iRST), - .D(iMSR_RI), - .RE(iRInRE), - .FE(iRInFE)); // 879 -slib_edge_detect UART_ED_DCD ( - .CLK(CLK), - .RST(iRST), - .D(iMSR_DCD), - .RE(iDCDnRE), - .FE(iDCDnFE)); // 879 +`include "apb/typedef.svh" -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iMSR_dCTS <= 1'b0; // 413 - iMSR_dDSR <= 1'b0; // 413 - iMSR_TERI <= 1'b0; // 413 - iMSR_dDCD <= 1'b0; // 413 - end - else - begin - if ((iCTSnRE == 1'b1 | iCTSnFE == 1'b1)) - begin - iMSR_dCTS <= 1'b1; // 413 - end - else if ((iMSRRead == 1'b1)) - begin - iMSR_dCTS <= 1'b0; // 413 - end - if ((iDSRnRE == 1'b1 | iDSRnFE == 1'b1)) - begin - iMSR_dDSR <= 1'b1; // 413 - end - else if ((iMSRRead == 1'b1)) - begin - iMSR_dDSR <= 1'b0; // 413 - end - if ((iRInFE == 1'b1)) - begin - iMSR_TERI <= 1'b1; // 413 - end - else if ((iMSRRead == 1'b1)) - begin - iMSR_TERI <= 1'b0; // 413 - end - if ((iDCDnRE == 1'b1 | iDCDnFE == 1'b1)) - begin - iMSR_dDCD <= 1'b1; // 413 - end - else if ((iMSRRead == 1'b1)) - begin - iMSR_dDCD <= 1'b0; // 413 - end - end - -assign iMSR[0] = iMSR_dCTS; -assign iMSR[1] = iMSR_dDSR; -assign iMSR[2] = iMSR_TERI; -assign iMSR[3] = iMSR_dDCD; -assign iMSR[4] = iMSR_CTS; -assign iMSR[5] = iMSR_DSR; -assign iMSR[6] = iMSR_RI; -assign iMSR[7] = iMSR_DCD; - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - /* block const 263 */ - iSCR <= (0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - end - else - begin - if ((iSCRWrite == 1'b1)) - begin - iSCR <= PWDATA[7:0] ; // 413 - end - end - -assign /*432*/ iBaudgenDiv = {iDLM, iDLL} -; // 434 -uart_baudgen UART_BG16 ( - .CLK(CLK), - .RST(iRST), - .CE( 1'b1), - .CLEAR( 1'b0), - .DIVIDER(iBaudgenDiv), - .BAUDTICK(iBaudtick16x)); // 879 -slib_clock_div #(.RATIO(8)) UART_BG2 ( - .CLK(CLK), - .RST(iRST), - .CE(iBaudtick16x), - .Q(iBaudtick2x)); // 879 -slib_edge_detect UART_RCLK ( - .CLK(CLK), - .RST(iRST), - .D(iBAUDOUTN), - .RE(iRCLK), - .FE()); // 879 -slib_fifo #(.WIDTH(8), .SIZE_E(6)) UART_TXFF ( - .CLK(CLK), - .RST(iRST), - .CLEAR(iTXFIFOClear), - .WRITE(iTXFIFOWrite), - .READ(iTXFIFORead), - .D(PWDATA[7:0] ), - .Q(iTXFIFOQ), - .EMPTY(iTXFIFOEmpty), - .FULL(iTXFIFO64Full), - .USAGE(iTXFIFOUsage)); // 879 -assign /*432*/ iTXFIFO16Full = iTXFIFOUsage[4]; // 434 -assign /*903*/ iTXFIFOFull = iFCR_FIFO64E == 1'b0 ? iTXFIFO16Full : iTXFIFO64Full; // 905 -assign /*903*/ iTXFIFOWrite = ((iFCR_FIFOEnable == 1'b0 && iTXFIFOEmpty == 1'b1) | (iFCR_FIFOEnable == 1'b1 && iTXFIFOFull == 1'b0)) && iTHRWrite == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iTXFIFOClear = iFCR_TXFIFOReset == 1'b1 ? 1'b1 : 1'b0; // 905 -slib_fifo #(.WIDTH(11), .SIZE_E(6)) UART_RXFF ( - .CLK(CLK), - .RST(iRST), - .CLEAR(iRXFIFOClear), - .WRITE(iRXFIFOWrite), - .READ(iRXFIFORead), - .D(iRXFIFOD), - .Q(iRXFIFOQ), - .EMPTY(iRXFIFOEmpty), - .FULL(iRXFIFO64Full), - .USAGE(iRXFIFOUsage)); // 879 -assign /*903*/ iRXFIFORead = iRBRRead == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*432*/ iRXFIFO16Full = iRXFIFOUsage[4]; // 434 -assign /*903*/ iRXFIFOFull = iFCR_FIFO64E == 1'b0 ? iRXFIFO16Full : iRXFIFO64Full; // 905 -assign /*432*/ iRBR = iRXFIFOQ[7:0] ; // 434 -assign /*903*/ iRXFIFO16Trigger = ((((iFCR_RXTrigger == 2'b00 && iRXFIFOEmpty == 1'b0) | (iFCR_RXTrigger == 2'b01 && (iRXFIFOUsage[2] == 1'b1 | iRXFIFOUsage[3] == 1'b1))) | (iFCR_RXTrigger == 2'b10 && iRXFIFOUsage[3] == 1'b1)) | (((iFCR_RXTrigger == 2'b11 && iRXFIFOUsage[3] == 1'b1) && iRXFIFOUsage[2] == 1'b1) && iRXFIFOUsage[1] == 1'b1)) | iRXFIFO16Full == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iRXFIFO64Trigger = ((((iFCR_RXTrigger == 2'b00 && iRXFIFOEmpty == 1'b0) | (iFCR_RXTrigger == 2'b01 && (iRXFIFOUsage[4] == 1'b1 | iRXFIFOUsage[5] == 1'b1))) | (iFCR_RXTrigger == 2'b10 && iRXFIFOUsage[5] == 1'b1)) | (((iFCR_RXTrigger == 2'b11 && iRXFIFOUsage[5] == 1'b1) && iRXFIFOUsage[4] == 1'b1) && iRXFIFOUsage[3] == 1'b1)) | iRXFIFO64Full == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iRXFIFOTrigger = iFCR_FIFO64E == 1'b0 ? iRXFIFO16Trigger : iRXFIFO64Trigger; // 905 -uart_transmitter UART_TX ( - .CLK(CLK), - .RST(iRST), - .TXCLK(iBaudtick2x), - .TXSTART(iTXStart), - .CLEAR(iTXClear), - .WLS(iLCR_WLS), - .STB(iLCR_STB), - .PEN(iLCR_PEN), - .EPS(iLCR_EPS), - .SP(iLCR_SP), - .BC(iLCR_BC), - .DIN(iTSR), - .TXFINISHED(iTXFinished), - .SOUT(iSOUT)); // 879 -assign /*432*/ iTXClear = 1'b0; // 434 -uart_receiver UART_RX ( - .CLK(CLK), - .RST(iRST), - .RXCLK(iRCLK), - .RXCLEAR(iRXClear), - .WLS(iLCR_WLS), - .STB(iLCR_STB), - .PEN(iLCR_PEN), - .EPS(iLCR_EPS), - .SP(iLCR_SP), - .SIN(iSIN), - .PE(iRXPE), - .FE(iRXFE), - .BI(iRXBI), - .DOUT(iRXData), - .RXFINISHED(iRXFinished)); // 879 -assign /*432*/ iRXClear = 1'b0; // 434 -assign /*903*/ iSIN = iMCR_LOOP == 1'b0 ? iSINr : iSOUT; // 905 -assign /*903*/ iTXEnable = iTXFIFOEmpty == 1'b0 && (iMCR_AFE == 1'b0 | (iMCR_AFE == 1'b1 && iMSR_CTS == 1'b1)) ? 1'b1 : 1'b0; // 905 - - typedef enum logic [1:0] {TXIDLE, TXSTART, TXRUN, TXEND} tx_state_type; - typedef enum logic {RXIDLE, RXSAVE} rx_state_type; - - rx_state_type rx_State; - tx_state_type tx_State; - - // Transmitter process - always @ (posedge CLK or posedge iRST) - if (iRST == 1'b1) - begin - tx_State <= TXIDLE; - iTSR <= 0; - iTXStart <= 1'b0; - iTXFIFORead <= 1'b0; - iTXRunning <= 1'b0; - end - else - begin - // Defaults - iTXStart <= 1'b0; - iTXFIFORead <= 1'b0; - iTXRunning <= 1'b0; - - case(tx_State) - TXIDLE : - begin - if (iTXEnable == 1'b1) - begin - iTXStart <= 1'b1; // Start transmitter - tx_State <= TXSTART; - end - else - tx_State <= TXIDLE; - end - TXSTART : - begin - iTSR <= iTXFIFOQ; - iTXStart <= 1'b1; // Start transmitter - iTXFIFORead <= 1'b1; // Increment TX FIFO read counter - tx_State <= TXRUN; - end - TXRUN : - begin - if (iTXFinished == 1'b1) // TX finished - tx_State <= TXEND; - else - tx_State <= TXRUN; - iTXRunning <= 1'b1; - iTXStart <= 1'b1; - end - TXEND : tx_State <= TXIDLE; - default : tx_State <= TXIDLE; - endcase; - end - - // Receiver process - always @(posedge CLK or posedge iRST) - if (iRST == 1'b1) - begin - rx_State <= RXIDLE; - iRXFIFOWrite <= 1'b0; - iRXFIFOClear <= 1'b0; - iRXFIFOD <= 0; - end - else - begin - // Defaults - iRXFIFOWrite <= 1'b0; - iRXFIFOClear <= iFCR_RXFIFOReset; - - case (rx_State) - RXIDLE : - begin - if (iRXFinished == 1'b1) - begin // Receive finished - iRXFIFOD <= {iRXBI, iRXFE, iRXPE, iRXData}; - if (iFCR_FIFOEnable == 1'b0) - iRXFIFOClear <= 1'b1; // Non-FIFO mode - rx_State <= RXSAVE; - end - else - rx_State <= RXIDLE; - end - RXSAVE : - begin - if (iFCR_FIFOEnable == 1'b0) - iRXFIFOWrite <= 1'b1; // Non-FIFO mode: Overwrite - else if (iRXFIFOFull == 1'b0) - iRXFIFOWrite <= 1'b1; // FIFO mode - rx_State <= RXIDLE; - end - default : rx_State <= RXIDLE; - endcase; // case rx_State - end - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iRTS <= 1'b0; // 413 - end - else - begin - if ((iMCR_RTS == 1'b0 | (iMCR_AFE == 1'b1 && iRXFIFOTrigger == 1'b1))) - begin - iRTS <= 1'b0; // 413 - end - else if ((iMCR_RTS == 1'b1 && (iMCR_AFE == 1'b0 | (iMCR_AFE == 1'b1 && iRXFIFOEmpty == 1'b1)))) - begin - iRTS <= 1'b1; // 413 - end - end - -always @(posedge CLK or posedge iRST) - if ((iRST == 1'b1)) - begin - iBAUDOUTN <= 1'b1; // 413 - OUT1N <= 1'b1; // 413 - OUT2N <= 1'b1; // 413 - RTSN <= 1'b1; // 413 - DTRN <= 1'b1; // 413 - SOUT <= 1'b1; // 413 - end - else - begin - iBAUDOUTN <= 1'b0; // 413 - OUT1N <= 1'b0; // 413 - OUT2N <= 1'b0; // 413 - RTSN <= 1'b0; // 413 - DTRN <= 1'b0; // 413 - SOUT <= 1'b0; // 413 - if ((iBaudtick16x == 1'b0)) - begin - iBAUDOUTN <= 1'b1; // 413 - end - - if ((iMCR_LOOP == 1'b1 | iMCR_OUT1 == 1'b0)) - begin - OUT1N <= 1'b1; // 413 - end - - if ((iMCR_LOOP == 1'b1 | iMCR_OUT2 == 1'b0)) - begin - OUT2N <= 1'b1; // 413 - end - - if ((iMCR_LOOP == 1'b1 | iRTS == 1'b0)) - begin - RTSN <= 1'b1; // 413 - end - - if ((iMCR_LOOP == 1'b1 | iMCR_DTR == 1'b0)) - begin - DTRN <= 1'b1; // 413 - end - - if ((iMCR_LOOP == 1'b1 | iSOUT == 1'b1)) - begin - SOUT <= 1'b1; // 413 - end - end - -always @(PADDR or iLCR_DLAB or iRBR or iDLL or iDLM or iIER or iIIR or iLCR or iMCR or iLSR or iMSR or iSCR) - begin - case (PADDR) - 3'b000: - begin - if ((iLCR_DLAB == 1'b0)) - begin - PRDATA[7:0] <= iRBR; - end - else - begin - PRDATA[7:0] <= iDLL; - end - end - - 3'b001: - begin - if ((iLCR_DLAB == 1'b0)) - begin - PRDATA[7:0] <= iIER; - end - else - begin - PRDATA[7:0] <= iDLM; - end - end - - 3'b010: - begin - PRDATA[7:0] <= iIIR; - end - - 3'b011: - begin - PRDATA[7:0] <= iLCR; - end - - 3'b100: - begin - PRDATA[7:0] <= iMCR; - end - - 3'b101: - begin - PRDATA[7:0] <= iLSR; - end - - 3'b110: - begin - PRDATA[7:0] <= iMSR; - end - - 3'b111: - begin - PRDATA[7:0] <= iSCR; - end - - default: - begin - PRDATA[7:0] <= iRBR; - end - - endcase - - end - -assign PRDATA[31:8] = 24'b0; -assign /*432*/ PREADY = 1'b1; // 434 -assign /*432*/ PSLVERR = 1'b0; // 434 - -endmodule // apb_uart +/// A legacy APB wrapper of the OBI UART. +module apb_uart( + input wire CLK, + input wire RSTN, + input wire PSEL, + input wire PENABLE, + input wire PWRITE, + input wire [2:0] PADDR, + input wire [31:0] PWDATA, + output logic [31:0] PRDATA, + output logic PREADY, + output logic PSLVERR, + output logic INT, + output logic OUT1N, + output logic OUT2N, + output logic RTSN, + output logic DTRN, + input wire CTSN, + input wire DSRN, + input wire DCDN, + input wire RIN, + input wire SIN, + output logic SOUT +); + + `APB_TYPEDEF_ALL(apb, logic [4:0], logic [31:0], logic [3:0]) + apb_req_t apb_req; + apb_resp_t apb_rsp; + + assign apb_req = '{ + paddr: {PADDR, 2'b0}, + pprot: '0, // confirm + psel: PSEL, + penable: PENABLE, + pwrite: PWRITE, + pwdata: PWDATA, + pstrb: '1 + }; + + assign PREADY = apb_rsp.pready; + assign PRDATA = apb_rsp.prdata; + assign PSLVERR = apb_rsp.pslverr; + + apb_uart_wrap #( + .apb_req_t ( apb_req_t ), + .apb_rsp_t ( apb_resp_t ) + ) i_apb_uart_wrap ( + .clk_i ( CLK ), + .rst_ni ( RSTN ), + .apb_req_i ( apb_req ), + .apb_rsp_o ( apb_rsp ), + .intr_o ( INT ), + .out1_no ( OUT1N ), + .out2_no ( OUT2N ), + .rts_no ( RTSN ), + .dtr_no ( DTRN ), + .cts_ni ( CTSN ), + .dsr_ni ( DSRN ), + .dcd_ni ( DCDN ), + .rin_ni ( RIN ), + .sin_i ( SIN ), + .sout_o ( SOUT ) + ); + +endmodule diff --git a/src/apb_uart_wrap.sv b/src/apb_uart_wrap.sv index 2076d59..f8025b4 100644 --- a/src/apb_uart_wrap.sv +++ b/src/apb_uart_wrap.sv @@ -1,32 +1,16 @@ -// -// UART 16750 -// -// Author: Paul Scheffler -// -// Description: This wrapper adapts the flat interface of apb_uart to -// an interface using passed structs for APB and port -// names aligned with our style guide. Note that your -// APB must have a datawidth of 32 to match the IP. -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// Paul Scheffler +// Nils Wistoff + +`include "obi/typedef.svh" + +// A UART with APB struct ports. module apb_uart_wrap #( - parameter type apb_req_t = logic, - parameter type apb_rsp_t = logic + parameter type apb_req_t = logic, + parameter type apb_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -49,28 +33,53 @@ module apb_uart_wrap #( output logic sout_o // TX ); - apb_uart i_apb_uart ( - .CLK ( clk_i ), - .RSTN ( rst_ni ), - .PSEL ( apb_req_i.psel ), - .PENABLE ( apb_req_i.penable ), - .PWRITE ( apb_req_i.pwrite ), - .PADDR ( apb_req_i.paddr[4:2] ), - .PWDATA ( apb_req_i.pwdata ), - .PRDATA ( apb_rsp_o.prdata ), - .PREADY ( apb_rsp_o.pready ), - .PSLVERR ( apb_rsp_o.pslverr ), - .INT ( intr_o ), - .OUT1N ( out1_no ), - .OUT2N ( out2_no ), - .RTSN ( rts_no ), - .DTRN ( dtr_no ), - .CTSN ( cts_ni ), - .DSRN ( dsr_ni ), - .DCDN ( dcd_ni ), - .RIN ( rin_ni ), - .SIN ( sin_i ), - .SOUT ( sout_o ) + localparam obi_pkg::obi_cfg_t ObiCfg = obi_pkg::obi_default_cfg( + $bits(apb_req_i.paddr), + 32, + 1, + obi_pkg::ObiMinimalOptionalConfig + ); + + `OBI_TYPEDEF_DEFAULT_ALL(obi, ObiCfg) + obi_req_t obi_req; + obi_rsp_t obi_rsp; + + apb_to_obi #( + .ObiCfg ( ObiCfg ), + .apb_req_t ( apb_req_t ), + .apb_rsp_t ( apb_rsp_t ), + .obi_req_t ( obi_req_t ), + .obi_rsp_t ( obi_rsp_t ) + ) i_apb_to_obi ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .apb_req_i ( apb_req_i ), + .apb_rsp_o ( apb_rsp_o ), + .obi_req_o ( obi_req ), + .obi_rsp_i ( obi_rsp ) + ); + + obi_uart #( + .ObiCfg ( ObiCfg ), + .obi_req_t ( obi_req_t ), + .obi_rsp_t ( obi_rsp_t ) + ) i_obi_uart ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .obi_req_i ( obi_req ), + .obi_rsp_o ( obi_rsp ), + .irq_o ( intr_o ), + .irq_no ( ), + .rxd_i ( sin_i ), + .txd_o ( sout_o ), + .cts_ni ( cts_ni ), + .dsr_ni ( dsr_ni ), + .ri_ni ( rin_ni ), + .cd_ni ( dcd_ni ), + .rts_no ( rts_no ), + .dtr_no ( dtr_no ), + .out1_no ( out1_no ), + .out2_no ( out2_no ) ); endmodule diff --git a/src/reg_uart_wrap.sv b/src/reg_uart_wrap.sv index 8b95531..b15ee24 100644 --- a/src/reg_uart_wrap.sv +++ b/src/reg_uart_wrap.sv @@ -1,37 +1,18 @@ -// -// UART 16750 -// -// Authors: +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + // Paul Scheffler // Nicole Narr // Christopher Reinwardt -// -// Description: This wrapper adapts the flat interface of apb_uart to -// the Regbus interface. Note that your Regbus must have -// a datawidth of 32 to match the IP. -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// +// Nils Wistoff `include "apb/typedef.svh" module reg_uart_wrap #( - parameter int unsigned AddrWidth = -1, - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic + parameter int unsigned AddrWidth = -1, + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -53,48 +34,44 @@ module reg_uart_wrap #( input logic sin_i, // RX output logic sout_o // TX ); - `APB_TYPEDEF_REQ_T(reg_uart_apb_req_t, logic [AddrWidth-1:0], logic [31:0], logic [3:0]) - `APB_TYPEDEF_RESP_T(reg_uart_apb_rsp_t, logic [31:0]) - reg_uart_apb_req_t uart_apb_req; - reg_uart_apb_rsp_t uart_apb_rsp; + `APB_TYPEDEF_ALL(apb, logic [AddrWidth-1:0], logic [31:0], logic [3:0]) + apb_req_t apb_req; + apb_resp_t apb_rsp; reg_to_apb #( - .reg_req_t ( reg_req_t ), - .reg_rsp_t ( reg_rsp_t ), - .apb_req_t ( reg_uart_apb_req_t ), - .apb_rsp_t ( reg_uart_apb_rsp_t ) - ) i_reg_uart_reg_to_apb ( + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ), + .apb_req_t ( apb_req_t ), + .apb_rsp_t ( apb_resp_t ) + ) i_reg_to_apb ( .clk_i, .rst_ni, .reg_req_i, .reg_rsp_o, - .apb_req_o ( uart_apb_req ), - .apb_rsp_i ( uart_apb_rsp ) + .apb_req_o ( apb_req ), + .apb_rsp_i ( apb_rsp ) ); - apb_uart i_apb_uart ( - .CLK ( clk_i ), - .RSTN ( rst_ni ), - .PSEL ( uart_apb_req.psel ), - .PENABLE ( uart_apb_req.penable ), - .PWRITE ( uart_apb_req.pwrite ), - .PADDR ( uart_apb_req.paddr[4:2] ), - .PWDATA ( uart_apb_req.pwdata ), - .PRDATA ( uart_apb_rsp.prdata ), - .PREADY ( uart_apb_rsp.pready ), - .PSLVERR ( uart_apb_rsp.pslverr ), - .INT ( intr_o ), - .OUT1N ( out1_no ), - .OUT2N ( out2_no ), - .RTSN ( rts_no ), - .DTRN ( dtr_no ), - .CTSN ( cts_ni ), - .DSRN ( dsr_ni ), - .DCDN ( dcd_ni ), - .RIN ( rin_ni ), - .SIN ( sin_i ), - .SOUT ( sout_o ) + apb_uart_wrap #( + .apb_req_t ( apb_req_t ), + .apb_rsp_t ( apb_resp_t ) + ) i_apb_uart_wrap ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .apb_req_i ( apb_req ), + .apb_rsp_o ( apb_rsp ), + .intr_o ( intr_o ), + .out1_no ( out1_no ), + .out2_no ( out2_no ), + .rts_no ( rts_no ), + .dtr_no ( dtr_no ), + .cts_ni ( cts_ni ), + .dsr_ni ( dsr_ni ), + .dcd_ni ( dcd_ni ), + .rin_ni ( rin_ni ), + .sin_i ( sin_i ), + .sout_o ( sout_o ) ); endmodule diff --git a/src/slib_clock_div.sv b/src/slib_clock_div.sv deleted file mode 100644 index c522242..0000000 --- a/src/slib_clock_div.sv +++ /dev/null @@ -1,75 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module slib_clock_div #(parameter RATIO = 4) ( - input wire CLK, - input wire RST, - input wire CE, - output logic Q); // 507 -/* design slib_clock_div */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg iQ; // 612 -reg [$clog2(RATIO-1)-1:0] iCounter; - -always @(posedge CLK or posedge RST) -begin -if ((RST == 1'b1)) - begin - iCounter <= 0; // 413 - iQ <= 1'b0; // 413 - end - else - begin - iQ <= 1'b0; // 413 - if ((CE == 1'b1)) - begin - if ((iCounter == (RATIO - 1))) - begin - iQ <= 1'b1; // 413 - iCounter <= 0; // 413 - end - else - begin - iCounter <= iCounter + 1; // 413 - end - end - - end - -end - -assign /*432*/ Q = iQ; // 434 - -endmodule // slib_clock_div diff --git a/src/slib_counter.sv b/src/slib_counter.sv deleted file mode 100644 index 59cdd5a..0000000 --- a/src/slib_counter.sv +++ /dev/null @@ -1,88 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module slib_counter # (parameter WIDTH = 4) ( - input wire CLK, - input wire RST, - input wire CLEAR, - input wire LOAD, - input wire ENABLE, - input wire DOWN, - input wire [WIDTH - 1:0] D, - output logic [WIDTH - 1:0] Q, - output logic OVERFLOW); // 507 -/* design slib_counter */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg [WIDTH:0] iCounter; // 605 - -always @(posedge CLK or posedge RST) -if (RST) - begin - /* block const 263 */ - iCounter <= 0; - end -else - begin - if ((CLEAR == 1'b1)) - begin - /* block const 263 */ - iCounter <= 0; - end - else if ((LOAD == 1'b1)) - begin - iCounter <= $unsigned({ 1'b0, D}); // 413 - end - - else if ((ENABLE == 1'b1)) - begin - if ((DOWN == 1'b0)) - begin - iCounter <= iCounter + 1; // 413 - end - else - begin - iCounter <= iCounter - 1; // 413 - end - end - - if ((iCounter[WIDTH] == 1'b1)) - begin - iCounter[WIDTH] <= 0; - end - end - -assign /*432*/ Q = iCounter[WIDTH - 1:0]; // 434 -assign /*432*/ OVERFLOW = iCounter[WIDTH]; // 434 -endmodule // slib_counter diff --git a/src/slib_edge_detect.sv b/src/slib_edge_detect.sv deleted file mode 100644 index 768b2a0..0000000 --- a/src/slib_edge_detect.sv +++ /dev/null @@ -1,62 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module slib_edge_detect( - input wire CLK, - input wire RST, - input wire D, - output logic RE, - output logic FE); // 507 -/* design slib_edge_detect */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg iDd; // 612 - -always @(posedge CLK or posedge RST) -begin -if ((RST == 1'b1)) - begin - iDd <= 1'b0; // 413 - end - else - begin - iDd <= D; // 413 - end - -end - -assign /*903*/ RE = iDd == 1'b0 && D == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ FE = iDd == 1'b1 && D == 1'b0 ? 1'b1 : 1'b0; // 905 - -endmodule // slib_edge_detect diff --git a/src/slib_fifo.sv b/src/slib_fifo.sv deleted file mode 100644 index 255b7a9..0000000 --- a/src/slib_fifo.sv +++ /dev/null @@ -1,159 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module slib_fifo # (parameter WIDTH = 8, parameter SIZE_E=6) ( - input wire CLK, - input wire RST, - input wire CLEAR, - input wire WRITE, - input wire READ, - input wire [WIDTH - 1:0] D, - output logic [WIDTH - 1:0] Q, - output logic EMPTY, - output logic FULL, - output logic [SIZE_E - 1:0] USAGE); // 507 -/* design slib_fifo */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg iEMPTY; // 612 -reg iFULL; // 612 -reg [SIZE_E:0] iWRAddr; // 605 -reg [SIZE_E:0] iRDAddr; // 605 -reg [SIZE_E:0] init; // 605 -reg [SIZE_E - 1:0] iUSAGE; // 605 -reg [WIDTH-1:0] iFIFOMem [0:2**SIZE_E-1]; - -assign /*903*/ iFULL = (iRDAddr[SIZE_E - 1:0] == iWRAddr[SIZE_E - 1:0] ) && (iRDAddr[SIZE_E] != iWRAddr[SIZE_E]) ? 1'b1 : 1'b0; // 905 - -always @(posedge CLK or posedge RST) -begin -if ((RST == 1'b1)) - begin - /* block const 263 */ -iWRAddr <= 0; -/* block const 263 */ -iRDAddr <= 0; -iEMPTY <= 1'b1; // 413 - end - else - begin - if ((WRITE == 1'b1 && iFULL == 1'b0)) - begin - iWRAddr <= iWRAddr + 1; // 413 - end - -if ((READ == 1'b1 && iEMPTY == 1'b0)) - begin - iRDAddr <= iRDAddr + 1; // 413 - end - -if ((CLEAR == 1'b1)) - begin - /* block const 263 */ -iWRAddr <= 0; -/* block const 263 */ -iRDAddr <= 0; - end - -if ((iRDAddr == iWRAddr)) - begin - iEMPTY <= 1'b1; // 413 - end - else - begin - iEMPTY <= 1'b0; // 413 - end - end - -end - - -always @(posedge CLK or posedge RST) -begin -if ((RST == 1'b1)) - begin - /* block const 263 */ - for (init = 0; init < 2**SIZE_E; init++) - iFIFOMem[init[SIZE_E-1:0]] <= 0; - Q <= (0<<0); - end - else - begin - if ((WRITE == 1'b1 && iFULL == 1'b0)) - begin - iFIFOMem[iWRAddr[SIZE_E-1:0]] <= D; - end - -Q <= iFIFOMem[iRDAddr[SIZE_E - 1:0]]; // 413 - end - -end - - -always @(posedge CLK or posedge RST) -begin -if ((RST == 1'b1)) - begin - /* block const 263 */ -iUSAGE <= 0; - end - else - begin - if ((CLEAR == 1'b1)) - begin - /* block const 263 */ -iUSAGE <= 0; - end - else - begin - if (((READ == 1'b0 && WRITE == 1'b1) && iFULL == 1'b0)) - begin - iUSAGE <= iUSAGE + 1; // 413 - end - -if (((WRITE == 1'b0 && READ == 1'b1) && iEMPTY == 1'b0)) - begin - iUSAGE <= iUSAGE - 1; // 413 - end - - end - end - -end - -assign /*432*/ EMPTY = iEMPTY; // 434 -assign /*432*/ FULL = iFULL; // 434 -assign /*432*/ USAGE = iUSAGE; // 434 - -endmodule // slib_fifo diff --git a/src/slib_input_filter.sv b/src/slib_input_filter.sv deleted file mode 100644 index 3ddab47..0000000 --- a/src/slib_input_filter.sv +++ /dev/null @@ -1,81 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module slib_input_filter #(parameter SIZE = 4) ( - input wire CLK, - input wire RST, - input wire CE, - input wire D, - output logic Q); // 507 -/* design slib_input_filter */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 - -reg [$clog2(SIZE+1)-1:0] iCount; - -always @(posedge CLK or posedge RST) - begin - if ((RST == 1'b1)) - begin - iCount <= 0; // 413 - Q <= 1'b0; // 413 - end - else - begin - if ((CE == 1'b1)) - begin - if ((D == 1'b1) && (iCount != SIZE)) - begin - iCount <= iCount + 1; // 413 - end - else if ((D == 1'b0) && (iCount != 0)) - begin - iCount <= iCount - 1; // 413 - end - end - - if ((iCount == SIZE)) - begin - Q <= 1'b1; // 413 - end - else if ((iCount == 0)) - begin - Q <= 1'b0; // 413 - end - end - - end - - -endmodule diff --git a/src/slib_input_sync.sv b/src/slib_input_sync.sv deleted file mode 100644 index e2eb76f..0000000 --- a/src/slib_input_sync.sv +++ /dev/null @@ -1,60 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module slib_input_sync( - input wire CLK, - input wire RST, - input wire D, - output logic Q); // 507 -/* design slib_input_sync */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg [1:0] iD; // 605 - -always @(posedge CLK or posedge RST) - begin - if ((RST == 1'b1)) - begin - /* block const 263 */ - iD <= (0<<1)|(0<<0); - end - else - begin - iD[0] <= D; - iD[1] <= iD[0]; - end - end - -assign /*432*/ Q = iD[1]; // 434 -endmodule // slib_input_sync diff --git a/src/slib_mv_filter.sv b/src/slib_mv_filter.sv deleted file mode 100644 index d5b50a9..0000000 --- a/src/slib_mv_filter.sv +++ /dev/null @@ -1,78 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module slib_mv_filter #(parameter WIDTH = 4, THRESHOLD = 10) ( - input wire CLK, - input wire RST, - input wire SAMPLE, - input wire CLEAR, - input wire D, - output logic Q); // 507 -/* design slib_mv_filter */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg [WIDTH:0] iCounter; // 605 -reg iQ; // 612 - -always @(posedge CLK or posedge RST) - if (RST) - begin - /* block const 263 */ - iCounter <= 0; - iQ <= 1'b0; // 413 - end - else - begin - if (iCounter >= THRESHOLD) - begin - iQ <= 1'b1; // 413 - end - else - begin - if ((SAMPLE == 1'b1 && D == 1'b1)) - begin - iCounter <= iCounter + 1; // 413 - end - end - if ((CLEAR == 1'b1)) - begin - /* block const 263 */ - iCounter <= 0; - iQ <= 1'b0; // 413 - end - end - -assign /*432*/ Q = iQ; // 434 - -endmodule // slib_mv_filter diff --git a/src/uart_baudgen.sv b/src/uart_baudgen.sv deleted file mode 100644 index 47904ac..0000000 --- a/src/uart_baudgen.sv +++ /dev/null @@ -1,78 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module uart_baudgen( - input wire CLK, - input wire RST, - input wire CE, - input wire CLEAR, - input wire [15:0] DIVIDER, - output logic BAUDTICK); // 507 -/* design uart_baudgen */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg [15:0] iCounter; // 605 - -always @(posedge CLK or posedge RST) -begin -if ((RST == 1'b1)) - begin - /* block const 263 */ -iCounter <= (0<<15)|(0<<14)|(0<<13)|(0<<12)|(0<<11)|(0<<10)|(0<<9)|(0<<8)|(0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); -BAUDTICK <= 1'b0; // 413 - end - else - begin - if ((CLEAR == 1'b1)) - begin - /* block const 263 */ -iCounter <= (0<<15)|(0<<14)|(0<<13)|(0<<12)|(0<<11)|(0<<10)|(0<<9)|(0<<8)|(0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - end - else if ((CE == 1'b1)) - begin - iCounter <= iCounter - 1; // 413 - end - BAUDTICK <= 1'b0; // 413 - if (iCounter == '0) - begin - /* block const 263 */ -iCounter <= $unsigned(DIVIDER) - 1; -BAUDTICK <= 1'b1; // 413 - end - - end - -end - -endmodule // uart_baudgen diff --git a/src/uart_interrupt.sv b/src/uart_interrupt.sv deleted file mode 100644 index 98b3324..0000000 --- a/src/uart_interrupt.sv +++ /dev/null @@ -1,98 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module uart_interrupt( - input wire CLK, - input wire RST, - input wire [3:0] IER, - input wire [4:0] LSR, - input wire THI, - input wire RDA, - input wire CTI, - input wire AFE, - input wire [3:0] MSR, - output logic [3:0] IIR, - output logic INT); // 507 -/* design uart_interrupt */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -reg iRLSInterrupt; // 612 -reg iRDAInterrupt; // 612 -reg iCTIInterrupt; // 612 -reg iTHRInterrupt; // 612 -reg iMSRInterrupt; // 612 -reg [3:0] iIIR; // 605 -assign /*432*/ iRLSInterrupt = IER[2] && (((LSR[1] | LSR[2]) | LSR[3]) | LSR[4]); // 434 -assign /*432*/ iRDAInterrupt = IER[0] && RDA; // 434 -assign /*432*/ iCTIInterrupt = IER[0] && CTI; // 434 -assign /*432*/ iTHRInterrupt = IER[1] && THI; // 434 -assign /*432*/ iMSRInterrupt = IER[3] && ((((MSR[0] && ~ AFE) | MSR[1]) | MSR[2]) | MSR[3]); // 434 - -always @(posedge CLK or posedge RST) - if ((RST == 1'b1)) - begin - iIIR <= 4'b0001; // 413 - end - else - begin - if ((iRLSInterrupt == 1'b1)) - begin - iIIR <= 4'b0110; // 413 - end - else if ((iCTIInterrupt == 1'b1)) - begin - iIIR <= 4'b1100; // 413 - end - else if ((iRDAInterrupt == 1'b1)) - begin - iIIR <= 4'b0100; // 413 - end - else if ((iTHRInterrupt == 1'b1)) - begin - iIIR <= 4'b0010; // 413 - end - else if ((iMSRInterrupt == 1'b1)) - begin - iIIR <= 4'b0000; // 413 - end - else - begin - iIIR <= 4'b0001; // 413 - end - end - -assign /*432*/ IIR = iIIR; // 434 -assign /*432*/ INT = ~ iIIR[0]; // 434 - -endmodule // uart_interrupt diff --git a/src/uart_receiver.sv b/src/uart_receiver.sv deleted file mode 100644 index 0cf7959..0000000 --- a/src/uart_receiver.sv +++ /dev/null @@ -1,315 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module uart_receiver( - input wire CLK, - input wire RST, - input wire RXCLK, - input wire RXCLEAR, - input wire [1:0] WLS, - input wire STB, - input wire PEN, - input wire EPS, - input wire SP, - input wire SIN, - output logic PE, - output logic FE, - output logic BI, - output logic [7:0] DOUT, - output logic RXFINISHED); // 507 -/* design uart_receiver */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -typedef enum logic [2:0] {IDLE, -START, -DATA, -PAR, -STOP, -MWAIT} state_type; // 674 -state_type CState, NState; // 908 -reg [3:0] iBaudCount; // 605 -reg iBaudCountClear; // 612 -reg iBaudStep; // 612 -reg iBaudStepD; // 612 -reg iFilterClear; // 612 -reg iFSIN; // 612 -reg iFStopBit; // 612 -reg iParity; // 612 -reg iParityReceived; // 612 -reg [3:0] iDataCount; // 900 -reg iDataCountInit; // 612 -reg iDataCountFinish; // 612 -reg iRXFinished; // 612 -reg iFE; // 612 -reg iBI; // 612 -reg iNoStopReceived; // 612 -reg [7:0] iDOUT; // 605 -slib_counter #(.WIDTH(4)) RX_BRC ( - .CLK(CLK), - .RST(RST), - .CLEAR(iBaudCountClear), - .LOAD( 1'b0), - .ENABLE(RXCLK), - .DOWN( 1'b0), - .D(4'b0000), - .Q(iBaudCount), - .OVERFLOW(iBaudStep)); // 879 -slib_mv_filter #(.WIDTH(4),.THRESHOLD(10)) RX_MVF ( - .CLK(CLK), - .RST(RST), - .SAMPLE(RXCLK), - .CLEAR(iFilterClear), - .D(SIN), - .Q(iFSIN)); // 879 -slib_input_filter #(.SIZE(4)) RX_IFSB ( - .CLK(CLK), - .RST(RST), - .CE(RXCLK), - .D(SIN), - .Q(iFStopBit)); // 879 - -always @(posedge CLK or posedge RST) - begin - if ((RST == 1'b1)) - begin - iBaudStepD <= 1'b0; // 413 - end - else - begin - iBaudStepD <= iBaudStep; // 413 - end - end - -assign /*432*/ iFilterClear = iBaudStepD | iBaudCountClear; // 434 - -always @(iDOUT or EPS) -begin -iParity <= (((((((iDOUT[7] ^ iDOUT[6]) ^ iDOUT[5]) ^ iDOUT[4]) ^ iDOUT[3]) ^ iDOUT[2]) ^ iDOUT[1]) ^ iDOUT[0]) ^ ~ EPS; // 413 - -end - - -always @(posedge CLK or posedge RST) - if ((RST == 1'b1)) - begin - iDataCount <= 0; // 413 - /* block const 263 */ - iDOUT <= (0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - end - else - begin - if ((iDataCountInit == 1'b1)) - begin - iDataCount <= 0; // 413 - /* block const 263 */ - iDOUT <= (0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0); - end - else - begin - if ((iBaudStep == 1'b1 && iDataCountFinish == 1'b0)) - begin - iDOUT[iDataCount] <= iFSIN; - iDataCount <= iDataCount + 1; // 413 - end - end - end - -assign /*903*/ iDataCountFinish = (((WLS == 2'b00 && iDataCount == 5) | (WLS == 2'b01 && iDataCount == 6)) | (WLS == 2'b10 && iDataCount == 7)) | (WLS == 2'b11 && iDataCount == 8) ? 1'b1 : 1'b0; // 905 - -always @(posedge CLK or posedge RST) - if ((RST == 1'b1)) - begin - CState <= IDLE; // 413 - end - else - begin - CState <= NState; // 413 - end - -always @(CState or SIN or iFSIN or iFStopBit or iBaudStep or iBaudCount or iDataCountFinish or PEN or WLS or STB) -begin -NState <= IDLE; // 413 -iBaudCountClear <= 1'b0; // 413 -iDataCountInit <= 1'b0; // 413 -iRXFinished <= 1'b0; // 413 -case (CState) - IDLE: - begin - if ((SIN == 1'b0)) - begin - NState <= START; // 413 - end - -iBaudCountClear <= 1'b1; // 413 - iDataCountInit <= 1'b1; // 413 - end - - START: - begin - iDataCountInit <= 1'b1; // 413 - if ((iBaudStep == 1'b1)) - begin - if ((iFSIN == 1'b0)) - begin - NState <= DATA; // 413 - end - - end - else - begin - NState <= START; // 413 - end - end - - DATA: - begin - if ((iDataCountFinish == 1'b1)) - begin - if ((PEN == 1'b1)) - begin - NState <= PAR; // 413 - end - else - begin - NState <= STOP; // 413 - end - end - else - begin - NState <= DATA; // 413 - end - end - - PAR: - begin - if ((iBaudStep == 1'b1)) - begin - NState <= STOP; // 413 - end - else - begin - NState <= PAR; // 413 - end - end - - STOP: - begin - if ((iBaudCount[3] == 1'b1)) - begin - if ((iFStopBit == 1'b0)) - begin - iRXFinished <= 1'b1; // 413 - NState <= MWAIT; // 413 - end - else - begin - iRXFinished <= 1'b1; // 413 - NState <= IDLE; // 413 - end - end - else - begin - NState <= STOP; // 413 - end - end - - MWAIT: - begin - if ((SIN == 1'b0)) - begin - NState <= MWAIT; // 413 - end - - end - - default: - begin - begin end end - -endcase - -end - - -always @(posedge CLK or posedge RST) -begin -if ((RST == 1'b1)) - begin - PE <= 1'b0; // 413 - iParityReceived <= 1'b0; // 413 - end - else - begin - if ((CState == PAR && iBaudStep == 1'b1)) - begin - iParityReceived <= iFSIN; // 413 - end - -if ((PEN == 1'b1)) - begin - PE <= 1'b0; // 413 - if ((SP == 1'b1)) - begin - if (((EPS ^ iParityReceived) == 1'b0)) - begin - PE <= 1'b1; // 413 - end - - end - else - begin - if ((iParity != iParityReceived)) - begin - PE <= 1'b1; // 413 - end - - end - end - else - begin - PE <= 1'b0; // 413 - iParityReceived <= 1'b0; // 413 - end - end - -end - -assign /*903*/ iNoStopReceived = iFStopBit == 1'b0 && (CState == STOP) ? 1'b1 : 1'b0; // 905 -assign /*903*/ iBI = (iDOUT == 8'b00000000 && iParityReceived == 1'b0) && iNoStopReceived == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*903*/ iFE = iNoStopReceived == 1'b1 ? 1'b1 : 1'b0; // 905 -assign /*432*/ DOUT = iDOUT; // 434 -assign /*432*/ BI = iBI; // 434 -assign /*432*/ FE = iFE; // 434 -assign /*432*/ RXFINISHED = iRXFinished; // 434 -endmodule diff --git a/src/uart_transmitter.sv b/src/uart_transmitter.sv deleted file mode 100644 index 8d57a6b..0000000 --- a/src/uart_transmitter.sv +++ /dev/null @@ -1,320 +0,0 @@ -// -// UART 16750 -// -// Converted to System Verilog by Jonathan Kimmitt -// This version has been partially checked with formality but some bugs remain -// Original Author: Sebastian Witt -// Date: 14.03.2019 -// Version: 1.6 -// -// History: 1.0 - Initial version -// 1.1 - THR empty interrupt register connected to RST -// 1.2 - Registered outputs -// 1.3 - Automatic flow control -// 1.4 - De-assert IIR FIFO64 when FIFO is disabled -// 1.5 - Inverted low active outputs when RST is active -// 1.6 - Converted to System Verilog -// -// -// This code is free software; you can redistribute it and/or -// modify it under the terms of the GNU Lesser General Public -// License as published by the Free Software Foundation; either -// version 2.1 of the License, or (at your option) any later version. -// -// This code is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// Lesser General Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with this library; if not, write to the -// Free Software Foundation, Inc., 59 Temple Place, Suite 330, -// Boston, MA 02111-1307 USA -// - -module uart_transmitter( - input wire CLK, - input wire RST, - input wire TXCLK, - input wire TXSTART, - input wire CLEAR, - input wire [1:0] WLS, - input wire STB, - input wire PEN, - input wire EPS, - input wire SP, - input wire BC, - input wire [7:0] DIN, - output logic TXFINISHED, - output logic SOUT); // 507 -/* design uart_transmitter */ -/* architecture rtl */ -typedef enum {FALSE,TRUE} bool_t; // 527 -typedef enum logic [3:0] {IDLE, -START, -BIT0, -BIT1, -BIT2, -BIT3, -BIT4, -BIT5, -BIT6, -BIT7, -PAR, -STOP, -STOP2} state_type; // 674 -state_type CState, NState; // 908 -reg iTx2; // 612 -reg iSout; // 612 -reg iParity; // 612 -reg iFinished; // 612 - -always @(posedge CLK or posedge RST) - if ((RST == 1'b1)) - begin - CState <= IDLE; // 413 - iTx2 <= 1'b0; // 413 - end - else - begin - if ((TXCLK == 1'b1)) - begin - if ((iTx2 == 1'b0)) - begin - CState <= NState; // 413 - iTx2 <= 1'b1; // 413 - end - else - begin - if ((((WLS == 2'b00) && (STB == 1'b1)) && CState == STOP2)) - begin - CState <= NState; // 413 - iTx2 <= 1'b1; // 413 - end - else - begin - CState <= CState; // 413 - iTx2 <= 1'b0; // 413 - end - end - end - end - -always @(CState or TXSTART or DIN or WLS or PEN or SP or EPS or STB or iParity) - begin - NState <= IDLE; // 413 - iSout <= 1'b1; // 413 - case (CState) - IDLE: - begin - if ((TXSTART == 1'b1)) - begin - NState <= START; // 413 - end - - end - - START: - begin - iSout <= 1'b0; // 413 - NState <= BIT0; // 413 - end - - BIT0: - begin - iSout <= DIN[0]; // 413 - NState <= BIT1; // 413 - end - - BIT1: - begin - iSout <= DIN[1]; // 413 - NState <= BIT2; // 413 - end - - BIT2: - begin - iSout <= DIN[2]; // 413 - NState <= BIT3; // 413 - end - - BIT3: - begin - iSout <= DIN[3]; // 413 - NState <= BIT4; // 413 - end - - BIT4: - begin - iSout <= DIN[4]; // 413 - if ((WLS == 2'b00)) - begin - if ((PEN == 1'b1)) - begin - NState <= PAR; // 413 - end - else - begin - NState <= STOP; // 413 - end - end - else - begin - NState <= BIT5; // 413 - end - end - - BIT5: - begin - iSout <= DIN[5]; // 413 - if ((WLS == 2'b01)) - begin - if ((PEN == 1'b1)) - begin - NState <= PAR; // 413 - end - else - begin - NState <= STOP; // 413 - end - end - else - begin - NState <= BIT6; // 413 - end - end - - BIT6: - begin - iSout <= DIN[6]; // 413 - if ((WLS == 2'b10)) - begin - if ((PEN == 1'b1)) - begin - NState <= PAR; // 413 - end - else - begin - NState <= STOP; // 413 - end - end - else - begin - NState <= BIT7; // 413 - end - end - - BIT7: - begin - iSout <= DIN[7]; // 413 - if ((PEN == 1'b1)) - begin - NState <= PAR; // 413 - end - else - begin - NState <= STOP; // 413 - end - end - - PAR: - begin - if ((SP == 1'b1)) - begin - if ((EPS == 1'b1)) - begin - iSout <= 1'b0; // 413 - end - else - begin - iSout <= 1'b1; // 413 - end - end - else - begin - if ((EPS == 1'b1)) - begin - iSout <= iParity; // 413 - end - else - begin - iSout <= ~ iParity; // 413 - end - end - NState <= STOP; // 413 - end - - STOP: - begin - if ((STB == 1'b1)) - begin - NState <= STOP2; // 413 - end - else - begin - if ((TXSTART == 1'b1)) - begin - NState <= START; // 413 - end - - end - end - - STOP2: - begin - if ((TXSTART == 1'b1)) - begin - NState <= START; // 413 - end - - end - - default: - begin - begin end end - - endcase - - end - - // Parity generation - always @ (DIN or WLS) - begin:TX_PAR - logic iP40, iP50, iP60, iP70; - iP40 = DIN[4] ^ DIN[3] ^ DIN[2] ^ DIN[1] ^ DIN[0]; - iP50 = DIN[5] ^ iP40; - iP60 = DIN[6] ^ iP50; - iP70 = DIN[7] ^ iP60; - - case(WLS) - 2'b00: iParity <= iP40; - 2'b01: iParity <= iP50; - 2'b10: iParity <= iP60; - default: iParity <= iP70; - endcase; - end - - reg iLast; - always @(posedge CLK or posedge RST) - begin:TX_FIN - if (RST) - begin - iFinished <= 1'b0; - iLast <= 1'b0; - end - else - begin - iFinished <= 1'b0; - if (iLast == 1'b0 && CState == STOP) - iFinished <= 1'b1; - if (CState == STOP) - iLast <= 1'b1; - else - iLast <= 1'b0; - end - end - -assign /*903*/ SOUT = BC == 1'b0 ? iSout : 1'b0; // 905 -assign /*432*/ TXFINISHED = iFinished; // 434 - -endmodule // uart_transmitter diff --git a/src/vhdl_orig/apb_uart.vhd b/src/vhdl_orig/apb_uart.vhd deleted file mode 100644 index ccd00d0..0000000 --- a/src/vhdl_orig/apb_uart.vhd +++ /dev/null @@ -1,1031 +0,0 @@ --- --- UART 16750 --- --- Author: Sebastian Witt --- Date: 29.01.2008 --- Version: 1.5 --- --- History: 1.0 - Initial version --- 1.1 - THR empty interrupt register connected to RST --- 1.2 - Registered outputs --- 1.3 - Automatic flow control --- 1.4 - De-assert IIR FIFO64 when FIFO is disabled --- 1.5 - Inverted low active outputs when RST is active --- --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART -entity apb_uart is - port ( - CLK : in std_logic; -- Clock - RSTN : in std_logic; -- Reset negated - - PSEL : in std_logic; -- APB psel signal - PENABLE : in std_logic; -- APB penable signal - PWRITE : in std_logic; -- APB pwrite signal - PADDR : in std_logic_vector(2 downto 0); -- APB paddr signal - PWDATA : in std_logic_vector(31 downto 0); -- APB pwdata signal - PRDATA : out std_logic_vector(31 downto 0); -- APB prdata signal - PREADY : out std_logic; -- APB pready signal - PSLVERR : out std_logic; -- APB pslverr signal - - INT : out std_logic; -- Interrupt output - - OUT1N : out std_logic; -- Output 1 - OUT2N : out std_logic; -- Output 2 - RTSN : out std_logic; -- RTS output - DTRN : out std_logic; -- DTR output - CTSN : in std_logic; -- CTS input - DSRN : in std_logic; -- DSR input - DCDN : in std_logic; -- DCD input - RIN : in std_logic; -- RI input - SIN : in std_logic; -- Receiver input - SOUT : out std_logic -- Transmitter output - ); -end apb_uart; - -architecture rtl of apb_uart is - -- UART transmitter - component uart_transmitter is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - TXCLK : in std_logic; -- Transmitter clock (2x baudrate) - TXSTART : in std_logic; -- Start transmitter - CLEAR : in std_logic; -- Clear transmitter state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - BC : in std_logic; -- Break control - DIN : in std_logic_vector(7 downto 0); -- Input data - TXFINISHED : out std_logic; -- Transmitter operation finished - SOUT : out std_logic -- Transmitter output - ); - end component; - -- UART receiver - component uart_receiver is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - RXCLK : in std_logic; -- Receiver clock (16x baudrate) - RXCLEAR : in std_logic; -- Reset receiver state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - SIN : in std_logic; -- Receiver input - PE : out std_logic; -- Parity error - FE : out std_logic; -- Framing error - BI : out std_logic; -- Break interrupt - DOUT : out std_logic_vector(7 downto 0); -- Output data - RXFINISHED : out std_logic -- Receiver operation finished - ); - end component; - -- UART interrupt control - component uart_interrupt is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - IER : in std_logic_vector(3 downto 0); -- IER 3:0 - LSR : in std_logic_vector(4 downto 0); -- LSR 4:0 - THI : in std_logic; -- Transmitter holding register empty interrupt - RDA : in std_logic; -- Receiver data available - CTI : in std_logic; -- Character timeout indication - AFE : in std_logic; -- Automatic flow control enable - MSR : in std_logic_vector(3 downto 0); -- MSR 3:0 - IIR : out std_logic_vector(3 downto 0); -- IIR 3:0 - INT : out std_logic -- Interrupt - ); - end component; - -- UART baudrate generator - component uart_baudgen is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - CLEAR : in std_logic; -- Reset generator (synchronization) - DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider - BAUDTICK : out std_logic -- 16xBaudrate tick - ); - end component; - -- UART FIFO - component slib_fifo is - generic ( - WIDTH : integer := 8; -- FIFO width - SIZE_E : integer := 6 -- FIFO size (2^SIZE_E) - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear FIFO - WRITE : in std_logic; -- Write to FIFO - READ : in std_logic; -- Read from FIFO - D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input - Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output - EMPTY : out std_logic; -- FIFO is empty - FULL : out std_logic; -- FIFO is full - USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage - ); - end component; - -- Edge detect - component slib_edge_detect is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - RE : out std_logic; -- Rising edge detected - FE : out std_logic -- Falling edge detected - ); - end component; - -- Input synchronization - component slib_input_sync is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); - end component; - -- Input filter - component slib_input_filter is - generic ( - SIZE : natural := 4 -- Filter width - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); - end component; - -- Clock enable generation - component slib_clock_div is - generic ( - RATIO : integer := 8 -- Clock divider ratio - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable input - Q : out std_logic -- New clock enable output - ); - end component; - - -- Global device signals - signal iWrite : std_logic; -- Write to UART - signal iRead : std_logic; -- Read from UART - signal iRST : std_logic; -- RST negated - - -- UART registers read/write signals - signal iRBRRead : std_logic; -- Read from RBR - signal iTHRWrite : std_logic; -- Write to THR - signal iDLLWrite : std_logic; -- Write to DLL - signal iDLMWrite : std_logic; -- Write to DLM - signal iIERWrite : std_logic; -- Write to IER - signal iIIRRead : std_logic; -- Read from IIR - signal iFCRWrite : std_logic; -- Write to FCR - signal iLCRWrite : std_logic; -- Write to LCR - signal iMCRWrite : std_logic; -- Write to MCR - signal iLSRRead : std_logic; -- Read from LSR - signal iMSRRead : std_logic; -- Read from MSR - signal iSCRWrite : std_logic; -- Write to SCR - - -- UART registers - signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register - signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register - signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB - signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB - signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register - signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register - signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register - signal iLCR : std_logic_vector(7 downto 0); -- Line control register - signal iMCR : std_logic_vector(7 downto 0); -- Modem control register - signal iLSR : std_logic_vector(7 downto 0); -- Line status register - signal iMSR : std_logic_vector(7 downto 0); -- Modem status register - signal iSCR : std_logic_vector(7 downto 0); -- Scratch register - - -- IER register signals - signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt - signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt - signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt - signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt - - -- IIR register signals - signal iIIR_PI : std_logic; -- IIR: Pending interrupt - signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0 - signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1 - signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2 - signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled - - -- FCR register signals - signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable - signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset - signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset - signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select - signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable - signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger - - -- LCR register signals - signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select - signal iLCR_STB : std_logic; -- LCR: Number of stop bits - signal iLCR_PEN : std_logic; -- LCR: Parity enable - signal iLCR_EPS : std_logic; -- LCR: Even parity select - signal iLCR_SP : std_logic; -- LCR: Sticky parity - signal iLCR_BC : std_logic; -- LCR: Break control - signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit - - -- MCR register signals - signal iMCR_DTR : std_logic; -- MCR: Data terminal ready - signal iMCR_RTS : std_logic; -- MCR: Request to send - signal iMCR_OUT1 : std_logic; -- MCR: OUT1 - signal iMCR_OUT2 : std_logic; -- MCR: OUT2 - signal iMCR_LOOP : std_logic; -- MCR: Loop - signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable - - -- LSR register signals - signal iLSR_DR : std_logic; -- LSR: Data ready - signal iLSR_OE : std_logic; -- LSR: Overrun error - signal iLSR_PE : std_logic; -- LSR: Parity error - signal iLSR_FE : std_logic; -- LSR: Framing error - signal iLSR_BI : std_logic; -- LSR: Break Interrupt - signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty - signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty - signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO - - -- MSR register signals - signal iMSR_dCTS : std_logic; -- MSR: Delta CTS - signal iMSR_dDSR : std_logic; -- MSR: Delta DSR - signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator - signal iMSR_dDCD : std_logic; -- MSR: Delta DCD - signal iMSR_CTS : std_logic; -- MSR: CTS - signal iMSR_DSR : std_logic; -- MSR: DSR - signal iMSR_RI : std_logic; -- MSR: RI - signal iMSR_DCD : std_logic; -- MSR: DCD - - -- UART MSR signals - signal iCTSNs : std_logic; -- Synchronized CTSN input - signal iDSRNs : std_logic; -- Synchronized DSRN input - signal iDCDNs : std_logic; -- Synchronized DCDN input - signal iRINs : std_logic; -- Synchronized RIN input - signal iCTSn : std_logic; -- Filtered CTSN input - signal iDSRn : std_logic; -- Filtered DSRN input - signal iDCDn : std_logic; -- Filtered DCDN input - signal iRIn : std_logic; -- Filtered RIN input - signal iCTSnRE : std_logic; -- CTSn rising edge - signal iCTSnFE : std_logic; -- CTSn falling edge - signal iDSRnRE : std_logic; -- DSRn rising edge - signal iDSRnFE : std_logic; -- DSRn falling edge - signal iDCDnRE : std_logic; -- DCDn rising edge - signal iDCDnFE : std_logic; -- DCDn falling edge - signal iRInRE : std_logic; -- RIn rising edge - signal iRInFE : std_logic; -- RIn falling edge - - -- UART baudrate generation signals - signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider - signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator - signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter - signal iRCLK : std_logic; -- 16x Baudrate for receiver - signal iBAUDOUTN : std_logic; - - -- UART FIFO signals - signal iTXFIFOClear : std_logic; -- Clear TX FIFO - signal iTXFIFOWrite : std_logic; -- Write to TX FIFO - signal iTXFIFORead : std_logic; -- Read from TX FIFO - signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty - signal iTXFIFOFull : std_logic; -- TX FIFO is full - signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full - signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full - signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage - signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output - signal iRXFIFOClear : std_logic; -- Clear RX FIFO - signal iRXFIFOWrite : std_logic; -- Write to RX FIFO - signal iRXFIFORead : std_logic; -- Read from RX FIFO - signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty - signal iRXFIFOFull : std_logic; -- RX FIFO is full - signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full - signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full - signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input - signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output - signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage - signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached - signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached - signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached - signal iRXFIFOPE : std_logic; -- Parity error from FIFO - signal iRXFIFOFE : std_logic; -- Frame error from FIFO - signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO - - -- UART transmitter signals - signal iSOUT : std_logic; -- Transmitter output - signal iTXStart : std_logic; -- Start transmitter - signal iTXClear : std_logic; -- Clear transmitter status - signal iTXFinished : std_logic; -- TX finished, character transmitted - signal iTXRunning : std_logic; -- TX in progress - - -- UART receiver signals - signal iSINr : std_logic; -- Synchronized SIN input - signal iSIN : std_logic; -- Receiver input - signal iRXFinished : std_logic; -- RX finished, character received - signal iRXClear : std_logic; -- Clear receiver status - signal iRXData : std_logic_vector(7 downto 0); -- RX data - signal iRXPE : std_logic; -- RX parity error - signal iRXFE : std_logic; -- RX frame error - signal iRXBI : std_logic; -- RX break interrupt - - -- UART control signals - signal iFERE : std_logic; -- Frame error detected - signal iPERE : std_logic; -- Parity error detected - signal iBIRE : std_logic; -- Break interrupt detected - signal iFECounter : integer range 0 to 64; -- FIFO error counter - signal iFEIncrement : std_logic; -- FIFO error counter increment - signal iFEDecrement : std_logic; -- FIFO error counter decrement - signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level) - signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode) - signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode) - signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation - signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt - signal iTXEnable : std_logic; -- Transmitter enable signal - signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control - - -begin - - -- Global device signals - iWrite <= '1' when PSEL = '1' and PENABLE = '1' and PWRITE = '1' else '0'; - iRead <= '1' when PSEL = '1' and PENABLE = '1' and PWRITE = '0' else '0'; - iRST <= '1' when RSTN = '0' else '0'; - - -- UART registers read/write signals - iRBRRead <= '1' when iRead = '1' and PADDR = "000" and iLCR_DLAB = '0' else '0'; - iTHRWrite <= '1' when iWrite = '1' and PADDR = "000" and iLCR_DLAB = '0' else '0'; - iDLLWrite <= '1' when iWrite = '1' and PADDR = "000" and iLCR_DLAB = '1' else '0'; - iDLMWrite <= '1' when iWrite = '1' and PADDR = "001" and iLCR_DLAB = '1' else '0'; - iIERWrite <= '1' when iWrite = '1' and PADDR = "001" and iLCR_DLAB = '0' else '0'; - iIIRRead <= '1' when iRead = '1' and PADDR = "010" else '0'; - iFCRWrite <= '1' when iWrite = '1' and PADDR = "010" else '0'; - iLCRWrite <= '1' when iWrite = '1' and PADDR = "011" else '0'; - iMCRWrite <= '1' when iWrite = '1' and PADDR = "100" else '0'; - iLSRRead <= '1' when iRead = '1' and PADDR = "101" else '0'; - iMSRRead <= '1' when iRead = '1' and PADDR = "110" else '0'; - iSCRWrite <= '1' when iWrite = '1' and PADDR = "111" else '0'; - - -- Async. input synchronization - UART_IS_SIN: slib_input_sync port map (CLK, iRST, SIN, iSINr); - UART_IS_CTS: slib_input_sync port map (CLK, iRST, CTSN, iCTSNs); - UART_IS_DSR: slib_input_sync port map (CLK, iRST, DSRN, iDSRNs); - UART_IS_DCD: slib_input_sync port map (CLK, iRST, DCDN, iDCDNs); - UART_IS_RI: slib_input_sync port map (CLK, iRST, RIN, iRINs); - - -- Input filter for UART control signals - UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iCTSNs, iCTSn); - UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iDSRNs, iDSRn); - UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iDCDNs, iDCDn); - UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iRINs, iRIn); - - - -- Divisor latch register - UART_DLR: process (CLK, iRST) - begin - if (iRST = '1') then - iDLL <= std_logic_vector(to_unsigned(1,iDLL'length)); - iDLM <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iDLLWrite = '1') then - iDLL <= PWDATA(7 downto 0); - end if; - if (iDLMWrite = '1') then - iDLM <= PWDATA(7 downto 0); - end if; - end if; - end process; - - -- Interrupt enable register - UART_IER: process (CLK, iRST) - begin - if (iRST = '1') then - iIER(3 downto 0) <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iIERWrite = '1') then - iIER(3 downto 0) <= PWDATA(3 downto 0); - end if; - end if; - end process; - - iIER_ERBI <= iIER(0); - iIER_ETBEI <= iIER(1); - iIER_ELSI <= iIER(2); - iIER_EDSSI <= iIER(3); - iIER(7 downto 4) <= (others => '0'); - - -- Interrupt control and IIR - UART_IIC: uart_interrupt port map (CLK => CLK, - RST => iRST, - IER => iIER(3 downto 0), - LSR => iLSR(4 downto 0), - THI => iTHRInterrupt, - RDA => iRDAInterrupt, - CTI => iCharTimeout, - AFE => iMCR_AFE, - MSR => iMSR(3 downto 0), - IIR => iIIR(3 downto 0), - INT => INT - ); - -- THR empty interrupt - UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iLSR_THRE, RE => iLSR_THRERE); - UART_IIC_THREI: process (CLK, iRST) - begin - if (iRST = '1') then - iTHRInterrupt <= '0'; - elsif (CLK'event and CLK = '1') then - if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and PWDATA(1) = '1' and iLSR_THRE = '1')) then - iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable - elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then - iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write - end if; - end if; - end process; - - iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or - (iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0'; - iIIR_PI <= iIIR(0); - iIIR_ID0 <= iIIR(1); - iIIR_ID1 <= iIIR(2); - iIIR_ID2 <= iIIR(3); - iIIR_FIFO64 <= iIIR(5); - iIIR(4) <= '0'; - iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0'; - iIIR(6) <= iFCR_FIFOEnable; - iIIR(7) <= iFCR_FIFOEnable; - - -- Character timeout indication - UART_CTI: process (CLK, iRST) - begin - if (iRST = '1') then - iTimeoutCount <= (others => '0'); - iCharTimeout <= '0'; - elsif (CLK'event and CLK = '1') then - if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then - iTimeoutCount <= (others => '0'); - elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then - iTimeoutCount <= iTimeoutCount + 1; - end if; - - -- Timeout indication - if (iFCR_FIFOEnable = '1') then - if (iRBRRead = '1') then - iCharTimeout <= '0'; - elsif (iTimeoutCount(5) = '1') then - iCharTimeout <= '1'; - end if; - else - iCharTimeout <= '0'; - end if; - end if; - end process; - - -- FIFO control register - UART_FCR: process (CLK, iRST) - begin - if (iRST = '1') then - iFCR_FIFOEnable <= '0'; - iFCR_RXFIFOReset <= '0'; - iFCR_TXFIFOReset <= '0'; - iFCR_DMAMode <= '0'; - iFCR_FIFO64E <= '0'; - iFCR_RXTrigger <= (others => '0'); - elsif (CLK'event and CLK = '1') then - -- FIFO reset pulse only - iFCR_RXFIFOReset <= '0'; - iFCR_TXFIFOReset <= '0'; - - if (iFCRWrite = '1') then - iFCR_FIFOEnable <= PWDATA(0); - iFCR_DMAMode <= PWDATA(3); - iFCR_RXTrigger <= PWDATA(7 downto 6); - - if (iLCR_DLAB = '1') then - iFCR_FIFO64E <= PWDATA(5); - end if; - - -- RX FIFO reset control, reset on FIFO enable/disable - if (PWDATA(1) = '1' or (iFCR_FIFOEnable = '0' and PWDATA(0) = '1') or (iFCR_FIFOEnable = '1' and PWDATA(0) = '0')) then - iFCR_RXFIFOReset <= '1'; - end if; - -- TX FIFO reset control, reset on FIFO enable/disable - if (PWDATA(2) = '1' or (iFCR_FIFOEnable = '0' and PWDATA(0) = '1') or (iFCR_FIFOEnable = '1' and PWDATA(0) = '0')) then - iFCR_TXFIFOReset <= '1'; - end if; - end if; - end if; - end process; - - iFCR(0) <= iFCR_FIFOEnable; - iFCR(1) <= iFCR_RXFIFOReset; - iFCR(2) <= iFCR_TXFIFOReset; - iFCR(3) <= iFCR_DMAMode; - iFCR(4) <= '0'; - iFCR(5) <= iFCR_FIFO64E; - iFCR(7 downto 6) <= iFCR_RXTrigger; - - -- Line control register - UART_LCR: process (CLK, iRST) - begin - if (iRST = '1') then - iLCR <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iLCRWrite = '1') then - iLCR <= PWDATA(7 downto 0); - end if; - end if; - end process; - - iLCR_WLS <= iLCR(1 downto 0); - iLCR_STB <= iLCR(2); - iLCR_PEN <= iLCR(3); - iLCR_EPS <= iLCR(4); - iLCR_SP <= iLCR(5); - iLCR_BC <= iLCR(6); - iLCR_DLAB <= iLCR(7); - - -- Modem control register - UART_MCR: process (CLK, iRST) - begin - if (iRST = '1') then - iMCR(5 downto 0) <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iMCRWrite = '1') then - iMCR(5 downto 0) <= PWDATA(5 downto 0); - end if; - end if; - end process; - - iMCR_DTR <= iMCR(0); - iMCR_RTS <= iMCR(1); - iMCR_OUT1 <= iMCR(2); - iMCR_OUT2 <= iMCR(3); - iMCR_LOOP <= iMCR(4); - iMCR_AFE <= iMCR(5); - iMCR(6) <= '0'; - iMCR(7) <= '0'; - - -- Line status register - UART_LSR: process (CLK, iRST) - begin - if (iRST = '1') then - iLSR_OE <= '0'; - iLSR_PE <= '0'; - iLSR_FE <= '0'; - iLSR_BI <= '0'; - iFECounter <= 0; - iLSR_FIFOERR <= '0'; - elsif (CLK'event and CLK = '1') then - -- Overrun error - if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or - (iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then - iLSR_OE <= '1'; - elsif (iLSRRead = '1') then - iLSR_OE <= '0'; - end if; - -- Parity error - if (iPERE = '1') then - iLSR_PE <= '1'; - elsif (iLSRRead = '1') then - iLSR_PE <= '0'; - end if; - -- Frame error - if (iFERE = '1') then - iLSR_FE <= '1'; - elsif (iLSRRead = '1') then - iLSR_FE <= '0'; - end if; - -- Break interrupt - if (iBIRE = '1') then - iLSR_BI <= '1'; - elsif (iLSRRead = '1') then - iLSR_BI <= '0'; - end if; - - -- FIFO error - -- Datasheet: Cleared by LSR read when no subsequent errors in FIFO - -- Observed: Cleared when no subsequent errors in FIFO - if (iFECounter /= 0) then - iLSR_FIFOERR <= '1'; - --elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then - elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then - iLSR_FIFOERR <= '0'; - end if; - - -- FIFO error counter - if (iRXFIFOClear = '1') then - iFECounter <= 0; - else - if (iFEIncrement = '1' and iFEDecrement = '0') then - iFECounter <= iFECounter + 1; - elsif (iFEIncrement = '0' and iFEDecrement = '1') then - iFECounter <= iFECounter - 1; - end if; - end if; - end if; - end process; - - iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0'; - iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0'; - iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0'; - UART_PEDET: slib_edge_detect port map (CLK, iRST, iRXFIFOPE, iPERE); - UART_FEDET: slib_edge_detect port map (CLK, iRST, iRXFIFOFE, iFERE); - UART_BIDET: slib_edge_detect port map (CLK, iRST, iRXFIFOBI, iBIRE); - iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0'; - iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0'; - - iLSR(0) <= iLSR_DR; - iLSR(1) <= iLSR_OE; - iLSR(2) <= iLSR_PE; - iLSR(3) <= iLSR_FE; - iLSR(4) <= iLSR_BI; - iLSR(5) <= iLSR_THRE; - iLSR(6) <= iLSR_TEMT; - iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0'; - iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0'; - iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0'; - iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0'; - - -- Modem status register - iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0'; - iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0'; - iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0'; - iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0'; - - -- Edge detection for CTS, DSR, DCD and RI - UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE); - UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE); - UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_RI, RE => iRInRE, FE => iRInFE); - UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE); - - UART_MSR: process (CLK, iRST) - begin - if (iRST = '1') then - iMSR_dCTS <= '0'; - iMSR_dDSR <= '0'; - iMSR_TERI <= '0'; - iMSR_dDCD <= '0'; - elsif (CLK'event and CLK = '1') then - -- Delta CTS - if (iCTSnRE = '1' or iCTSnFE = '1') then - iMSR_dCTS <= '1'; - elsif (iMSRRead = '1') then - iMSR_dCTS <= '0'; - end if; - -- Delta DSR - if (iDSRnRE = '1' or iDSRnFE = '1') then - iMSR_dDSR <= '1'; - elsif (iMSRRead = '1') then - iMSR_dDSR <= '0'; - end if; - -- Trailing edge RI - if (iRInFE = '1') then - iMSR_TERI <= '1'; - elsif (iMSRRead = '1') then - iMSR_TERI <= '0'; - end if; - -- Delta DCD - if (iDCDnRE = '1' or iDCDnFE = '1') then - iMSR_dDCD <= '1'; - elsif (iMSRRead = '1') then - iMSR_dDCD <= '0'; - end if; - end if; - end process; - - iMSR(0) <= iMSR_dCTS; - iMSR(1) <= iMSR_dDSR; - iMSR(2) <= iMSR_TERI; - iMSR(3) <= iMSR_dDCD; - iMSR(4) <= iMSR_CTS; - iMSR(5) <= iMSR_DSR; - iMSR(6) <= iMSR_RI; - iMSR(7) <= iMSR_DCD; - - -- Scratch register - UART_SCR: process (CLK, iRST) - begin - if (iRST = '1') then - iSCR <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iSCRWrite = '1') then - iSCR <= PWDATA(7 downto 0); - end if; - end if; - end process; - - - -- Baudrate generator - iBaudgenDiv <= iDLM & iDLL; - UART_BG16: uart_baudgen port map (CLK => CLK, - RST => iRST, - CE => '1', - CLEAR => '0', - DIVIDER => iBaudgenDiv, - BAUDTICK => iBaudtick16x - ); - UART_BG2: slib_clock_div generic map (RATIO => 8) - port map (CLK => CLK, - RST => iRST, - CE => iBaudtick16x, - Q => iBaudtick2x - ); - UART_RCLK: slib_edge_detect port map (CLK => CLK, - RST => iRST, - D => iBAUDOUTN, - RE => iRCLK - ); - - -- Transmitter FIFO - UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6) - port map (CLK => CLK, - RST => iRST, - CLEAR => iTXFIFOClear, - WRITE => iTXFIFOWrite, - READ => iTXFIFORead, - D => PWDATA(7 downto 0), - Q => iTXFIFOQ, - EMPTY => iTXFIFOEmpty, - FULL => iTXFIFO64Full, - USAGE => iTXFIFOUsage - ); - -- Transmitter FIFO inputs - iTXFIFO16Full <= iTXFIFOUsage(4); - iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full; - iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0'; - iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0'; - - -- Receiver FIFO - UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6) - port map (CLK => CLK, - RST => iRST, - CLEAR => iRXFIFOClear, - WRITE => iRXFIFOWrite, - READ => iRXFIFORead, - D => iRXFIFOD, - Q => iRXFIFOQ, - EMPTY => iRXFIFOEmpty, - FULL => iRXFIFO64Full, - USAGE => iRXFIFOUsage - ); - -- Receiver FIFO inputs - iRXFIFORead <= '1' when iRBRRead = '1' else '0'; - iRXFIFO16Full <= iRXFIFOUsage(4); - iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full; - - - -- Receiver FIFO outputs - iRBR <= iRXFIFOQ(7 downto 0); - - -- FIFO trigger level: 1, 4, 8, 14 - iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or - (iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or - (iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or - (iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or - iRXFIFO16Full = '1' else '0'; - -- FIFO 64 trigger level: 1, 16, 32, 56 - iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or - (iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or - (iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or - (iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or - iRXFIFO64Full = '1' else '0'; - iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger; - - -- Transmitter - UART_TX: uart_transmitter port map (CLK => CLK, - RST => iRST, - TXCLK => iBaudtick2x, - TXSTART => iTXStart, - CLEAR => iTXClear, - WLS => iLCR_WLS, - STB => iLCR_STB, - PEN => iLCR_PEN, - EPS => iLCR_EPS, - SP => iLCR_SP, - BC => iLCR_BC, - DIN => iTSR, - TXFINISHED => iTXFinished, - SOUT => iSOUT - ); - iTXClear <= '0'; - - -- Receiver - UART_RX: uart_receiver port map (CLK => CLK, - RST => iRST, - RXCLK => iRCLK, - RXCLEAR => iRXClear, - WLS => iLCR_WLS, - STB => iLCR_STB, - PEN => iLCR_PEN, - EPS => iLCR_EPS, - SP => iLCR_SP, - SIN => iSIN, - PE => iRXPE, - FE => iRXFE, - BI => iRXBI, - DOUT => iRXData, - RXFINISHED => iRXFinished - ); - iRXClear <= '0'; - iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT; - - -- Transmitter enable signal - -- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition. - iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0'; - - -- Transmitter process - UART_TXPROC: process (CLK, iRST) - type state_type is (IDLE, TXSTART, TXRUN, TXEND); - variable State : state_type; - begin - if (iRST = '1') then - State := IDLE; - iTSR <= (others => '0'); - iTXStart <= '0'; - iTXFIFORead <= '0'; - iTXRunning <= '0'; - elsif (CLK'event and CLK = '1') then - -- Defaults - iTXStart <= '0'; - iTXFIFORead <= '0'; - iTXRunning <= '0'; - - case State is - when IDLE => if (iTXEnable = '1') then - iTXStart <= '1'; -- Start transmitter - State := TXSTART; - else - State := IDLE; - end if; - when TXSTART => iTSR <= iTXFIFOQ; - iTXStart <= '1'; -- Start transmitter - iTXFIFORead <= '1'; -- Increment TX FIFO read counter - State := TXRUN; - when TXRUN => if (iTXFinished = '1') then -- TX finished - State := TXEND; - else - State := TXRUN; - end if; - iTXRunning <= '1'; - iTXStart <= '1'; - when TXEND => State := IDLE; - when others => State := IDLE; - end case; - end if; - end process; - - -- Receiver process - UART_RXPROC: process (CLK, iRST) - type state_type is (IDLE, RXSAVE); - variable State : state_type; - begin - if (iRST = '1') then - State := IDLE; - iRXFIFOWrite <= '0'; - iRXFIFOClear <= '0'; - iRXFIFOD <= (others => '0'); - elsif (CLK'event and CLK = '1') then - -- Defaults - iRXFIFOWrite <= '0'; - iRXFIFOClear <= iFCR_RXFIFOReset; - - case State is - when IDLE => if (iRXFinished = '1') then -- Receive finished - iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData; - if (iFCR_FIFOEnable = '0') then - iRXFIFOClear <= '1'; -- Non-FIFO mode - end if; - State := RXSAVE; - else - State := IDLE; - end if; - when RXSAVE => if (iFCR_FIFOEnable = '0') then - iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite - elsif (iRXFIFOFull = '0') then - iRXFIFOWrite <= '1'; -- FIFO mode - end if; - State := IDLE; - when others => State := IDLE; - end case; - end if; - end process; - - -- Automatic flow control - UART_AFC: process (CLK, iRST) - begin - if (iRST = '1') then - iRTS <= '0'; - elsif (CLK'event and CLK = '1') then - if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then - -- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached - iRTS <= '0'; - elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then - -- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty - iRTS <= '1'; - end if; - end if; - end process; - - -- Output registers - UART_OUTREGS: process (CLK, iRST) - begin - if (iRST = '1') then - iBAUDOUTN <= '1'; - OUT1N <= '1'; - OUT2N <= '1'; - RTSN <= '1'; - DTRN <= '1'; - SOUT <= '1'; - elsif (CLK'event and CLK = '1') then - -- Default values - iBAUDOUTN <= '0'; - OUT1N <= '0'; - OUT2N <= '0'; - RTSN <= '0'; - DTRN <= '0'; - SOUT <= '0'; - - -- BAUDOUTN - if (iBaudtick16x = '0') then - iBAUDOUTN <= '1'; - end if; - -- OUT1N - if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then - OUT1N <= '1'; - end if; - -- OUT2N - if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then - OUT2N <= '1'; - end if; - -- RTS - if (iMCR_LOOP = '1' or iRTS = '0') then - RTSN <= '1'; - end if; - -- DTR - if (iMCR_LOOP = '1' or iMCR_DTR = '0') then - DTRN <= '1'; - end if; - -- SOUT - if (iMCR_LOOP = '1' or iSOUT = '1') then - SOUT <= '1'; - end if; - end if; - end process; - - - -- UART data output - UART_DOUT: process (PADDR, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR) - begin - case PADDR is - when "000" => if (iLCR_DLAB = '0') then - PRDATA(7 downto 0) <= iRBR; - else - PRDATA(7 downto 0) <= iDLL; - end if; - when "001" => if (iLCR_DLAB = '0') then - PRDATA(7 downto 0) <= iIER; - else - PRDATA(7 downto 0) <= iDLM; - end if; - when "010" => PRDATA(7 downto 0) <= iIIR; - when "011" => PRDATA(7 downto 0) <= iLCR; - when "100" => PRDATA(7 downto 0) <= iMCR; - when "101" => PRDATA(7 downto 0) <= iLSR; - when "110" => PRDATA(7 downto 0) <= iMSR; - when "111" => PRDATA(7 downto 0) <= iSCR; - when others => PRDATA(7 downto 0) <= iRBR; - end case; - end process; - - PRDATA(31 downto 8) <= (others => '0'); - PREADY <= '1'; - PSLVERR <= '0'; - -end rtl; - - diff --git a/src/vhdl_orig/slib_clock_div.vhd b/src/vhdl_orig/slib_clock_div.vhd deleted file mode 100644 index a0ac743..0000000 --- a/src/vhdl_orig/slib_clock_div.vhd +++ /dev/null @@ -1,70 +0,0 @@ --- --- Clock divider (clock enable generator) --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - - -entity slib_clock_div is - generic ( - RATIO : integer := 4 -- Clock divider ratio - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable input - Q : out std_logic -- New clock enable output - ); -end slib_clock_div; - -architecture rtl of slib_clock_div is - -- Signals - signal iQ : std_logic; -- Internal Q - signal iCounter : integer range 0 to RATIO-1; -- Counter - -begin - -- Main process - CD_PROC: process (RST, CLK) - begin - if (RST = '1') then - iCounter <= 0; - iQ <= '0'; - elsif (CLK'event and CLK='1') then - iQ <= '0'; - if (CE = '1') then - if (iCounter = (RATIO-1)) then - iQ <= '1'; - iCounter <= 0; - else - iCounter <= iCounter + 1; - end if; - end if; - end if; - end process; - - -- Output signals - Q <= iQ; - -end rtl; - diff --git a/src/vhdl_orig/slib_counter.vhd b/src/vhdl_orig/slib_counter.vhd deleted file mode 100644 index d1e6d41..0000000 --- a/src/vhdl_orig/slib_counter.vhd +++ /dev/null @@ -1,77 +0,0 @@ --- --- Counter --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.2 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Counter -entity slib_counter is - generic ( - WIDTH : natural := 4 -- Counter width - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear counter register - LOAD : in std_logic; -- Load counter register - ENABLE : in std_logic; -- Enable count operation - DOWN : in std_logic; -- Count direction down - D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input - Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output - OVERFLOW : out std_logic -- Counter overflow - ); -end slib_counter; - -architecture rtl of slib_counter is - signal iCounter : unsigned(WIDTH downto 0); -- Counter register -begin - -- Counter process - COUNT_SHIFT: process (RST, CLK) - begin - if (RST = '1') then - iCounter <= (others => '0'); -- Reset counter register - elsif (CLK'event and CLK='1') then - if (CLEAR = '1') then - iCounter <= (others => '0'); -- Clear counter register - elsif (LOAD = '1') then -- Load counter register - iCounter <= unsigned('0' & D); - elsif (ENABLE = '1') then -- Enable counter - if (DOWN = '0') then -- Count up - iCounter <= iCounter + 1; - else -- Count down - iCounter <= iCounter - 1; - end if; - end if; - if (iCounter(WIDTH) = '1') then -- Clear overflow - iCounter(WIDTH) <= '0'; - end if; - end if; - - end process; - - -- Output ports - Q <= std_logic_vector(iCounter(WIDTH-1 downto 0)); - OVERFLOW <= iCounter(WIDTH); -end rtl; - diff --git a/src/vhdl_orig/slib_edge_detect.vhd b/src/vhdl_orig/slib_edge_detect.vhd deleted file mode 100644 index 206ddc3..0000000 --- a/src/vhdl_orig/slib_edge_detect.vhd +++ /dev/null @@ -1,57 +0,0 @@ --- --- Signal edge detect --- --- Author: Sebastian Witt --- Data: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity slib_edge_detect is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - RE : out std_logic; -- Rising edge detected - FE : out std_logic -- Falling edge detected - ); -end slib_edge_detect; - -architecture rtl of slib_edge_detect is - signal iDd : std_logic; -- D register -begin - -- Store D - ED_D: process (RST, CLK) - begin - if (RST = '1') then - iDd <= '0'; - elsif (CLK'event and CLK='1') then - iDd <= D; - end if; - end process; - - -- Output ports - RE <= '1' when iDd = '0' and D = '1' else '0'; - FE <= '1' when iDd = '1' and D = '0' else '0'; - -end rtl; - - diff --git a/src/vhdl_orig/slib_fifo.vhd b/src/vhdl_orig/slib_fifo.vhd deleted file mode 100644 index 60cae24..0000000 --- a/src/vhdl_orig/slib_fifo.vhd +++ /dev/null @@ -1,133 +0,0 @@ --- --- FIFO --- --- Author: Sebastian Witt --- Date: 29.01.2008 --- Version: 1.3 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - - -entity slib_fifo is - generic ( - WIDTH : integer := 8; -- FIFO width - SIZE_E : integer := 6 -- FIFO size (2^SIZE_E) - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear FIFO - WRITE : in std_logic; -- Write to FIFO - READ : in std_logic; -- Read from FIFO - D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input - Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output - EMPTY : out std_logic; -- FIFO is empty - FULL : out std_logic; -- FIFO is full - USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage - ); -end slib_fifo; - -architecture rtl of slib_fifo is - -- Signals - signal iEMPTY : std_logic; -- Internal EMPTY - signal iFULL : std_logic; -- Internal FULL - signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address - signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address - signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage - -- FIFO memory - type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0); - signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0')); - -begin - -- Full signal (biggest difference of read and write address) - iFULL <= '1' when (iRDAddr(SIZE_E-1 downto 0) = iWRAddr(SIZE_E-1 downto 0)) and - (iRDAddr(SIZE_E) /= iWRAddr(SIZE_E)) else '0'; - - -- Write/read address counter and empty signal - FF_ADDR: process (RST, CLK) - begin - if (RST = '1') then - iWRAddr <= (others => '0'); - iRDAddr <= (others => '0'); - iEMPTY <= '1'; - elsif (CLK'event and CLK='1') then - if (WRITE = '1' and iFULL = '0') then -- Write to FIFO - iWRAddr <= iWRAddr + 1; - end if; - - if (READ = '1' and iEMPTY = '0') then -- Read from FIFO - iRDAddr <= iRDAddr + 1; - end if; - - if (CLEAR = '1') then -- Reset FIFO - iWRAddr <= (others => '0'); - iRDAddr <= (others => '0'); - end if; - - if (iRDAddr = iWRAddr) then -- Empty signal (read address same as write address) - iEMPTY <= '1'; - else - iEMPTY <= '0'; - end if; - end if; - end process; - - -- FIFO memory process - FF_MEM: process (RST, CLK) - begin - if (RST = '1') then - iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0')); - Q <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (WRITE = '1' and iFULL = '0') then - iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D; - end if; - Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0))); - end if; - end process; - - -- Usage counter - FF_USAGE: process (RST, CLK) - begin - if (RST = '1') then - iUSAGE <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (CLEAR = '1') then - iUSAGE <= (others => '0'); - else - if (READ = '0' and WRITE = '1' and iFULL = '0') then - iUSAGE <= iUSAGE + 1; - end if; - if (WRITE = '0' and READ = '1' and iEMPTY = '0') then - iUSAGE <= iUSAGE - 1; - end if; - end if; - end if; - end process; - - -- Output signals - EMPTY <= iEMPTY; - FULL <= iFULL; - USAGE <= std_logic_vector(iUSAGE); - -end rtl; - - diff --git a/src/vhdl_orig/slib_input_filter.vhd b/src/vhdl_orig/slib_input_filter.vhd deleted file mode 100644 index 8fc25f6..0000000 --- a/src/vhdl_orig/slib_input_filter.vhd +++ /dev/null @@ -1,69 +0,0 @@ --- --- Input filter --- --- Author: Sebastian Witt --- Data: 06.03.2008 --- Version: 1.0 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity slib_input_filter is - generic ( - SIZE : natural := 4 -- Filter counter size - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); -end slib_input_filter; - -architecture rtl of slib_input_filter is - signal iCount : integer range 0 to SIZE; -begin - IF_D: process (RST, CLK) - begin - if (RST = '1') then - iCount <= 0; - Q <= '0'; - elsif (CLK'event and CLK='1') then - -- Input counter - if (CE = '1' ) then - if (D = '1' and iCount /= SIZE) then - iCount <= iCount + 1; - elsif (D = '0' and iCount /= 0) then - iCount <= iCount - 1; - end if; - end if; - - -- Output - if (iCount = SIZE) then - Q <= '1'; - elsif (iCount = 0) then - Q <= '0'; - end if; - end if; - end process; - -end rtl; - diff --git a/src/vhdl_orig/slib_input_sync.vhd b/src/vhdl_orig/slib_input_sync.vhd deleted file mode 100644 index 2190751..0000000 --- a/src/vhdl_orig/slib_input_sync.vhd +++ /dev/null @@ -1,54 +0,0 @@ --- --- Input synchronization --- --- Author: Sebastian Witt --- Data: 27.01.2008 --- Version: 1.0 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity slib_input_sync is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); -end slib_input_sync; - -architecture rtl of slib_input_sync is - signal iD : std_logic_vector(1 downto 0); -begin - IS_D: process (RST, CLK) - begin - if (RST = '1') then - iD <= (others => '0'); - elsif (CLK'event and CLK='1') then - iD(0) <= D; - iD(1) <= iD(0); - end if; - end process; - - -- Output ports - Q <= iD(1); - -end rtl; - diff --git a/src/vhdl_orig/slib_mv_filter.vhd b/src/vhdl_orig/slib_mv_filter.vhd deleted file mode 100644 index 8f1dc0e..0000000 --- a/src/vhdl_orig/slib_mv_filter.vhd +++ /dev/null @@ -1,78 +0,0 @@ --- --- Majority voting filter --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - - -entity slib_mv_filter is - generic ( - WIDTH : natural := 4; - THRESHOLD : natural := 10 - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - SAMPLE : in std_logic; -- Clock enable for sample process - CLEAR : in std_logic; -- Reset process - D : in std_logic; -- Signal input - Q : out std_logic -- Signal D was at least THRESHOLD samples high - ); -end slib_mv_filter; - -architecture rtl of slib_mv_filter is - - -- Signals - signal iCounter : unsigned(WIDTH downto 0); -- Sample counter - signal iQ : std_logic; -- Internal Q - -begin - -- Main process - MV_PROC: process (RST, CLK) - begin - if (RST = '1') then - iCounter <= (others => '0'); - iQ <= '0'; - elsif (CLK'event and CLK='1') then - if (iCounter >= THRESHOLD) then -- Compare with threshold - iQ <= '1'; - else - if (SAMPLE = '1' and D = '1') then -- Take sample - iCounter <= iCounter + 1; - end if; - end if; - - if (CLEAR = '1') then -- Reset logic - iCounter <= (others => '0'); - iQ <= '0'; - end if; - - end if; - end process; - - -- Output signals - Q <= iQ; - -end rtl; - diff --git a/src/vhdl_orig/uart_baudgen.vhd b/src/vhdl_orig/uart_baudgen.vhd deleted file mode 100644 index 75f26aa..0000000 --- a/src/vhdl_orig/uart_baudgen.vhd +++ /dev/null @@ -1,67 +0,0 @@ --- --- UART Baudrate generator --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART baudrate generator -entity uart_baudgen is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - CLEAR : in std_logic; -- Reset generator (synchronization) - DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider - BAUDTICK : out std_logic -- 16xBaudrate tick - ); -end uart_baudgen; - -architecture rtl of uart_baudgen is - -- Signals - signal iCounter : unsigned(15 downto 0); -begin - -- Baudrate counter - BG_COUNT: process (CLK, RST) - begin - if (RST = '1') then - iCounter <= (others => '0'); - BAUDTICK <= '0'; - elsif (CLK'event and CLK = '1') then - if (CLEAR = '1') then - iCounter <= (others => '0'); - elsif (CE = '1') then - iCounter <= iCounter - 1; - end if; - - BAUDTICK <= '0'; - if (unsigned(iCounter) = 0) then - iCounter <= unsigned(DIVIDER) - 1; - BAUDTICK <= '1'; - end if; - end if; - end process; - -end rtl; - - diff --git a/src/vhdl_orig/uart_interrupt.vhd b/src/vhdl_orig/uart_interrupt.vhd deleted file mode 100644 index 49c3b98..0000000 --- a/src/vhdl_orig/uart_interrupt.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- --- UART interrupt control --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- History: 1.0 - Initial version --- 1.1 - Automatic flow control --- --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART interrupt control -entity uart_interrupt is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - IER : in std_logic_vector(3 downto 0); -- IER 3:0 - LSR : in std_logic_vector(4 downto 0); -- LSR 4:0 - THI : in std_logic; -- Transmitter holding register empty interrupt - RDA : in std_logic; -- Receiver data available - CTI : in std_logic; -- Character timeout indication - AFE : in std_logic; -- Automatic flow control enable - MSR : in std_logic_vector(3 downto 0); -- MSR 3:0 - IIR : out std_logic_vector(3 downto 0); -- IIR 3:0 - INT : out std_logic -- Interrupt - ); -end uart_interrupt; - -architecture rtl of uart_interrupt is - -- Signals - signal iRLSInterrupt : std_logic; -- Receiver line status interrupt - signal iRDAInterrupt : std_logic; -- Received data available interrupt - signal iCTIInterrupt : std_logic; -- Character timeout indication interrupt - signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt - signal iMSRInterrupt : std_logic; -- Modem status interrupt - signal iIIR : std_logic_vector(3 downto 0); -- IIR register -begin - - -- Priority 1: Receiver line status interrupt on: Overrun error, parity error, framing error or break interrupt - iRLSInterrupt <= IER(2) and (LSR(1) or LSR(2) or LSR(3) or LSR(4)); - - -- Priority 2: Received data available or trigger level reached in FIFO mode - iRDAInterrupt <= IER(0) and RDA; - - -- Priority 2: Character timeout indication - iCTIInterrupt <= IER(0) and CTI; - - -- Priority 3: Transmitter holding register empty - iTHRInterrupt <= IER(1) and THI; - - -- Priority 4: Modem status interrupt: dCTS (when AFC is disabled), dDSR, TERI, dDCD - iMSRInterrupt <= IER(3) and ((MSR(0) and not AFE) or MSR(1) or MSR(2) or MSR(3)); - - -- IIR - IC_IIR: process (CLK, RST) - begin - if (RST = '1') then - iIIR <= "0001"; -- TODO: Invert later - elsif (CLK'event and CLK = '1') then - -- IIR register - if (iRLSInterrupt = '1') then - iIIR <= "0110"; - elsif (iCTIInterrupt = '1') then - iIIR <= "1100"; - elsif (iRDAInterrupt = '1') then - iIIR <= "0100"; - elsif (iTHRInterrupt = '1') then - iIIR <= "0010"; - elsif (iMSRInterrupt = '1') then - iIIR <= "0000"; - else - iIIR <= "0001"; - end if; - end if; - end process; - - -- Outputs - IIR <= iIIR; - INT <= not iIIR(0); - -end rtl; - diff --git a/src/vhdl_orig/uart_receiver.vhd b/src/vhdl_orig/uart_receiver.vhd deleted file mode 100644 index 777d220..0000000 --- a/src/vhdl_orig/uart_receiver.vhd +++ /dev/null @@ -1,311 +0,0 @@ --- --- UART receiver --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.2 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART receiver -entity uart_receiver is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - RXCLK : in std_logic; -- Receiver clock (16x baudrate) - RXCLEAR : in std_logic; -- Reset receiver state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - SIN : in std_logic; -- Receiver input - PE : out std_logic; -- Parity error - FE : out std_logic; -- Framing error - BI : out std_logic; -- Break interrupt - DOUT : out std_logic_vector(7 downto 0); -- Output data - RXFINISHED : out std_logic -- Receiver operation finished - ); -end uart_receiver; - -architecture rtl of uart_receiver is - -- Majority voting logic - component slib_mv_filter is - generic ( - WIDTH : natural := 4; - THRESHOLD : natural := 10 - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - SAMPLE : in std_logic; -- Clock enable for sample process - CLEAR : in std_logic; -- Reset process - D : in std_logic; -- Signal input - Q : out std_logic -- Signal D was at least THRESHOLD samples high - ); - end component; - component slib_input_filter is - generic ( - SIZE : natural := 4 -- Filter counter size - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); - end component; - - -- Counter - component slib_counter is - generic ( - WIDTH : natural := 4 -- Counter width - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear counter register - LOAD : in std_logic; -- Load counter register - ENABLE : in std_logic; -- Enable count operation - DOWN : in std_logic; -- Count direction down - D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input - Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output - OVERFLOW : out std_logic -- Counter overflow - ); - end component; - - -- FSM - type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT); - signal CState, NState : state_type; - - -- Signals - signal iBaudCount : std_logic_vector(3 downto 0); -- Baud counter output - signal iBaudCountClear : std_logic; -- Baud counter clear - signal iBaudStep : std_logic; -- Next symbol pulse - signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock - signal iFilterClear : std_logic; -- Reset input filter - signal iFSIN : std_logic; -- Filtered SIN - signal iFStopBit : std_logic; -- Filtered SIN for stop bit detection - signal iParity : std_logic; -- Data parity - signal iParityReceived : std_logic; -- Parity received - signal iDataCount : integer range 0 to 8; -- Data bit counter - signal iDataCountInit : std_logic; -- Initialize data bit counter to word length - signal iDataCountFinish : std_logic; -- Data bit counter finished - signal iRXFinished : std_logic; -- Word received, output data valid - signal iFE : std_logic; -- Internal frame error - signal iBI : std_logic; -- Internal break interrupt - signal iNoStopReceived : std_logic; -- No valid stop bit received - signal iDOUT : std_logic_vector(7 downto 0); -- Data output - -begin - - -- Baudrate counter: RXCLK/16 - RX_BRC: slib_counter generic map ( - WIDTH => 4 - ) port map ( - CLK => CLK, - RST => RST, - CLEAR => iBaudCountClear, - LOAD => '0', - ENABLE => RXCLK, - DOWN => '0', - D => x"0", - Q => iBaudCount, - OVERFLOW => iBaudStep - ); - - -- Input filter - RX_MVF: slib_mv_filter generic map ( - WIDTH => 4, - THRESHOLD => 10 - ) port map ( - CLK => CLK, - RST => RST, - SAMPLE => RXCLK, - CLEAR => iFilterClear, - D => SIN, - Q => iFSIN - ); - - -- Input filter for the stop bit - RX_IFSB: slib_input_filter generic map ( - SIZE => 4 - ) port map ( - CLK => CLK, - RST => RST, - CE => RXCLK, - D => SIN, - Q => iFStopBit - ); - - -- iBaudStepD - RX_IFC: process (CLK, RST) - begin - if (RST = '1') then - iBaudStepD <= '0'; - elsif (CLK'event and CLK = '1') then - iBaudStepD <= iBaudStep; - end if; - end process; - - iFilterClear <= iBaudStepD or iBaudCountClear; - - -- Parity generation - RX_PAR: process (iDOUT, EPS) - begin - iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS; - end process; - - -- Data bit capture - RX_DATACOUNT: process (CLK, RST) - begin - if (RST = '1') then - iDataCount <= 0; - iDOUT <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iDataCountInit = '1') then - iDataCount <= 0; - iDOUT <= (others => '0'); - else - if (iBaudStep = '1' and iDataCountFinish = '0') then - iDOUT(iDataCount) <= iFSIN; - iDataCount <= iDataCount + 1; - end if; - end if; - end if; - end process; - - iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or - (WLS = "01" and iDataCount = 6) or - (WLS = "10" and iDataCount = 7) or - (WLS = "11" and iDataCount = 8) else '0'; - - -- FSM update process - RX_FSMUPDATE: process (CLK, RST) - begin - if (RST = '1') then - CState <= IDLE; - elsif (CLK'event and CLK = '1') then - CState <= NState; - end if; - end process; - - -- RX FSM - RX_FSM: process (CState, SIN, iFSIN, iFStopBit, iBaudStep, iBaudCount, iDataCountFinish, PEN, WLS, STB) - begin - -- Defaults - NState <= IDLE; - iBaudCountClear <= '0'; - iDataCountInit <= '0'; - iRXFinished <= '0'; - - case CState is - when IDLE => if (SIN = '0') then -- Start detected - NState <= START; - end if; - iBaudCountClear <= '1'; - iDataCountInit <= '1'; - when START => iDataCountInit <= '1'; - if (iBaudStep = '1') then -- Wait for start bit end - if (iFSIN = '0') then - NState <= DATA; - end if; - else - NState <= START; - end if; - when DATA => if (iDataCountFinish = '1') then -- Received all data bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= DATA; - end if; - when PAR => if (iBaudStep = '1') then -- Wait for parity bit - NState <= STOP; - else - NState <= PAR; - end if; - when STOP => if (iBaudCount(3) = '1') then -- Wait for stop bit - if (iFStopBit = '0') then -- No stop bit received - iRXFinished <= '1'; - NState <= MWAIT; - else - iRXFinished <= '1'; - NState <= IDLE; -- Stop bit end - end if; - else - NState <= STOP; - end if; - when MWAIT => if (SIN = '0') then -- Wait for mark - NState <= MWAIT; - end if; - when others => null; - end case; - end process; - - -- Check parity - RX_PARCHECK: process (CLK, RST) - begin - if (RST = '1') then - PE <= '0'; - iParityReceived <= '0'; - elsif (CLK'event and CLK = '1') then - if (CState = PAR and iBaudStep = '1') then - iParityReceived <= iFSIN; -- Received parity bit - end if; - - -- Check parity - if (PEN = '1') then -- Parity enabled - PE <= '0'; - if (SP = '1') then -- Sticky parity - if ((EPS xor iParityReceived) = '0') then - PE <= '1'; -- Parity error - end if; - else - if (iParity /= iParityReceived) then - PE <= '1'; -- Parity error - end if; - end if; - else - PE <= '0'; -- Parity disabled - iParityReceived <= '0'; - end if; - end if; - end process; - - -- Framing error and break interrupt - iNoStopReceived <= '1' when iFStopBit = '0' and (CState = STOP) else '0'; - iBI <= '1' when iDOUT = "00000000" and - iParityReceived = '0' and - iNoStopReceived = '1' else '0'; - iFE <= '1' when iNoStopReceived = '1' else '0'; - - -- Output signals - DOUT <= iDOUT; - BI <= iBI; - FE <= iFE; - RXFINISHED <= iRXFinished; - -end rtl; - diff --git a/src/vhdl_orig/uart_transmitter.vhd b/src/vhdl_orig/uart_transmitter.vhd deleted file mode 100644 index d24d182..0000000 --- a/src/vhdl_orig/uart_transmitter.vhd +++ /dev/null @@ -1,216 +0,0 @@ --- --- UART transmitter --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.0 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART transmitter -entity uart_transmitter is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - TXCLK : in std_logic; -- Transmitter clock (2x baudrate) - TXSTART : in std_logic; -- Start transmitter - CLEAR : in std_logic; -- Clear transmitter state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - BC : in std_logic; -- Break control - DIN : in std_logic_vector(7 downto 0); -- Input data - TXFINISHED : out std_logic; -- Transmitter operation finished - SOUT : out std_logic -- Transmitter output - ); -end uart_transmitter; - -architecture rtl of uart_transmitter is - -- FSM - type state_type is (IDLE, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PAR, STOP, STOP2); - signal CState, NState : state_type; - - -- Signals - signal iTx2 : std_logic; -- Next TX step - signal iSout : std_logic; -- Transmitter output - signal iParity : std_logic; -- Parity - signal iFinished : std_logic; -- TX finished - -begin - -- Transmitter FSM update process - TX_PROC: process (RST, CLK) - begin - if (RST = '1') then - CState <= IDLE; - iTx2 <= '0'; - elsif (CLK'event and CLK='1') then - if (TXCLK = '1') then -- TX clock - if (iTx2 = '0') then -- Two TX clocks per step - CState <= NState; -- Next step - iTx2 <= '1'; - else - if ((WLS = "00") and (STB = '1') and CState = STOP2) then - CState <= NState; -- 1.5 stop bits for 5 bit word mode - iTx2 <= '1'; - else - CState <= CState; -- First TX clock, wait - iTx2 <= '0'; - end if; - end if; - end if; - end if; - end process; - - -- Transmitter FSM - TX_FSM: process (CState, TXSTART, DIN, WLS, PEN, SP, EPS, STB, iParity) - begin - -- Defaults - NState <= IDLE; - iSout <= '1'; - - case CState is - when IDLE => if (TXSTART = '1') then - NState <= START; - end if; - when START => iSout <= '0'; - NState <= BIT0; - when BIT0 => iSout <= DIN(0); - NState <= BIT1; - when BIT1 => iSout <= DIN(1); - NState <= BIT2; - when BIT2 => iSout <= DIN(2); - NState <= BIT3; - when BIT3 => iSout <= DIN(3); - NState <= BIT4; - when BIT4 => iSout <= DIN(4); - if (WLS = "00") then -- 5 bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= BIT5; - end if; - when BIT5 => iSout <= DIN(5); - if (WLS = "01") then -- 6 bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= BIT6; - end if; - when BIT6 => iSout <= DIN(6); - if (WLS = "10") then -- 7 bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= BIT7; - end if; - when BIT7 => iSout <= DIN(7); - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - when PAR => if (SP = '1') then -- Sticky parity - if (EPS = '1') then - iSout <= '0'; -- Even parity -> cleared - else - iSout <= '1'; -- Odd parity -> set - end if; - else - if (EPS = '1') then - iSout <= iParity; -- Even parity - else - iSout <= not iParity; -- Odd parity - end if; - end if; - NState <= STOP; - when STOP => if (STB = '1') then -- 2 stop bits - NState <= STOP2; - else - if (TXSTART = '1') then -- Next transmission - NState <= START; - end if; - end if; - when STOP2 => if (TXSTART = '1') then -- Next transmission - NState <= START; - end if; - when others => null; - end case; - - - end process; - - - -- Parity generation - TX_PAR: process (DIN, WLS) - variable iP40, iP50, iP60, iP70 : std_logic; - begin - iP40 := DIN(4) xor DIN(3) xor DIN(2) xor DIN(1) xor DIN(0); - iP50 := DIN(5) xor iP40; - iP60 := DIN(6) xor iP50; - iP70 := DIN(7) xor iP60; - - case WLS is - when "00" => iParity <= iP40; - when "01" => iParity <= iP50; - when "10" => iParity <= iP60; - when others => iParity <= iP70; - end case; - end process; - - - -- Signal TX finished on STOP bit transmission - TX_FIN: process (CLK, RST) - variable iLast : std_logic; - begin - if (RST = '1') then - iFinished <= '0'; - iLast := '0'; - elsif (CLK'event and CLK = '1') then - iFinished <= '0'; - if (iLast = '0' and CState = STOP) then - iFinished <= '1'; - end if; - - if (CState = STOP) then - iLast := '1'; - else - iLast := '0'; - end if; - end if; - end process; - - -- Output signals - SOUT <= iSout when BC = '0' else '0'; - TXFINISHED <= iFinished; - -end rtl; - diff --git a/src_files.yml b/src_files.yml deleted file mode 100644 index e4b51c4..0000000 --- a/src_files.yml +++ /dev/null @@ -1,17 +0,0 @@ -apb_uart: - files: [ - src/apb_uart_wrap.sv, - src/apb_uart.sv, - src/reg_uart_wrap.sv, - src/slib_clock_div.sv, - src/slib_counter.sv, - src/slib_edge_detect.sv, - src/slib_fifo.sv, - src/slib_input_filter.sv, - src/slib_input_sync.sv, - src/slib_mv_filter.sv, - src/uart_baudgen.sv, - src/uart_interrupt.sv, - src/uart_receiver.sv, - src/uart_transmitter.sv, - ] diff --git a/util/equiv_check.fm.tcl b/util/equiv_check.fm.tcl deleted file mode 100644 index 3a7c640..0000000 --- a/util/equiv_check.fm.tcl +++ /dev/null @@ -1,36 +0,0 @@ -set hdlin_warn_on_mismatch_message "FMR_ELAB-146 FMR_ELAB-149 FMR_VHDL-1002" -read_vhdl -container r -libname WORK -2008 { \ - ../src/vhdl_orig/apb_uart.vhd \ - ../src/vhdl_orig/slib_clock_div.vhd \ - ../src/vhdl_orig/slib_counter.vhd \ - ../src/vhdl_orig/slib_edge_detect.vhd \ - ../src/vhdl_orig/slib_fifo.vhd \ - ../src/vhdl_orig/slib_input_filter.vhd \ - ../src/vhdl_orig/slib_input_sync.vhd \ - ../src/vhdl_orig/slib_mv_filter.vhd \ - ../src/vhdl_orig/uart_baudgen.vhd \ - ../src/vhdl_orig/uart_interrupt.vhd \ - ../src/vhdl_orig/uart_receiver.vhd \ - ../src/vhdl_orig/uart_transmitter.vhd \ -} -set_top r:/WORK/apb_uart -read_sverilog -container i -libname WORK -12 { \ - ../src/apb_uart.sv \ - ../src/slib_clock_div.sv \ - ../src/slib_counter.sv \ - ../src/slib_edge_detect.sv \ - ../src/slib_fifo.sv \ - ../src/slib_input_filter.sv \ - ../src/slib_input_sync.sv \ - ../src/slib_mv_filter.sv \ - ../src/uart_baudgen.sv \ - ../src/uart_interrupt.sv \ - ../src/uart_receiver.sv \ - ../src/uart_transmitter.sv \ -} -set_top i:/WORK/apb_uart -match -verify -report_hdlin_mismatches -analyze_points -all -quit