diff --git a/litespi/__init__.py b/litespi/__init__.py index 8a7a2e1..b54ad52 100644 --- a/litespi/__init__.py +++ b/litespi/__init__.py @@ -77,7 +77,7 @@ def __init__(self, phy, clock_domain="sys", cs_width=len(phy.cs) self.crossbar = crossbar = LiteSPICrossbar(clock_domain, cs_width) - self.comb += phy.cs.eq(crossbar.cs) + crossbar.comb += phy.cs.eq(crossbar.cs) if with_mmap and phy.flash: self.mmap = mmap = LiteSPIMMAP(flash=phy.flash, @@ -88,12 +88,12 @@ def __init__(self, phy, clock_domain="sys", cs_mask=mmap_cs_mask) port_mmap = crossbar.get_port(mmap.cs, mmap.request) self.bus = mmap.bus - self.comb += [ + mmap.comb += [ port_mmap.source.connect(mmap.sink), mmap.source.connect(port_mmap.sink), ] if hasattr(phy, "dummy_bits"): - self.comb += phy.dummy_bits.eq(mmap._spi_dummy_bits) + mmap.comb += phy.dummy_bits.eq(mmap._spi_dummy_bits) if with_master: self.master = master = LiteSPIMaster( tx_fifo_depth = master_tx_fifo_depth, @@ -101,7 +101,7 @@ def __init__(self, phy, clock_domain="sys", with_irq = master_with_irq, cs_width = cs_width) port_master = crossbar.get_port(master.cs) - self.comb += [ + master.comb += [ port_master.source.connect(master.sink), master.source.connect(port_master.sink), ] @@ -109,12 +109,12 @@ def __init__(self, phy, clock_domain="sys", self.ev = master.ev if clock_domain != "sys": - self.comb += [ + crossbar.comb += [ crossbar.tx_cdc.source.connect(phy.sink), phy.source.connect(crossbar.rx_cdc.sink), ] else: - self.comb += [ + crossbar.comb += [ crossbar.master.source.connect(phy.sink), phy.source.connect(crossbar.master.sink), ]