FPGA Miner Project update and how to run it on a board(xilinx ZCU102 Development board) that is not in the tested projects directory

[kapoor7997]

Hello All,

I have a xilinx ZCU102 board.

I just have two questions:

1. This project is pretty old. Has there been no update in bitcoin code in last 11 years? I am asking because ethereum code changed quite a lot since its launch. Has bitcoin code been the same? Is this project still valid for current bitcoin?
2. The changes that I need to make in this project build and work on ZCU102 board.
   Not looking for you to do my work. Just want to know the steps/flow of changes I need to make to get it to work on a new board.
   NOTE: Sorry I am new to fpga development board.
   Does anyone have a project build for zcu102 board or other latest xilins boards??

Thanks,
Kapoor7997

[penguin359]

Bitcoin, at a fundamental level, has never really changed. It's all about producing blocks with valid data that have a SHA-256 hash with a lot of leading zeros. The next miner to find a valid block gets the credit, or at least his pool. The higher levels that do change like Segwit and other changes will be mostly managed by the pool service and it will hand out tidbits of work to anyone willing to work that pool as a share. The actual work by the FPGA is to just be a very fast (though not compared to modern ASICs) SHA-256 hasher. That has never changed.

[penguin359]

As for your second question, I would first start by creating a new project in your Xilinx IDE of choice and then adding in all the Verilog source files into it from the src/ folder and see if you can get it to build or simulate in iSim or ModelSim. I assume that your board/FPGA is pretty new and that you will probably be using Vivado as I doubt their older IDE called ISE I believe is no longer supported. I looked through the projects folder and did not see any projects right off the BAT for Vivado, but I did see several ISE projects for a few different boards and looking though how an existing project is set up might help as well.

[kapoor7997]

Hi penguin359,

Thank you for your reply. I appreciate that a lot.
I will be working on hardware today.
but does this code need an application/host side to trigger the hardware Ip that will be running this HDL code on the board?

Thanks,
kapoor7997

[penguin359]

The HDL code will be continually hashing data while it's loaded and powered, but it won't be doing any useful work unless it's loaded with data that needs hashing. How that does is specific to each project and board. For the Altera FPGA I have, it uses a special probe that talks over the JTAG interface to read and write to internal state in the FPGA for the system to hash and return. That probe logic is Altera-specific. You will need to come up with something that matches what your board and FPGA can do.

[kapoor7997]

Hi penguin359,

Thank you so much for your reply again. I really appreciate that.
The probe that talks over jtag in Altera. Is that using serial port(UART or usb-uart) for communication?
I am looking at the code from the projects/VHDL_Xilinx_Port folder and it has UART and miner hdl files and miner.py.
I am not experiences with python. Any guidance on how to get this going and what changes to make?

Thank you,
Rahul Kapoor

[kapoor7997]

Hello penguin359,

I went over the code to see the flow of the code a little bit and the top level entity is only taking clk and rx as input and outputting tx. How will this code get input from the pool. Can you just give me a starting point, which will be enough for me to go through the code. I am just trying to figure out what I need in my Vivado hardware to set this up.

I will really really appreciate that.

Thanks,
kapoor7997

[penguin359]

In the reference example with the UART that you are looking for, all input and output is through the UART. This is used for the reference because it is universal. Any FPGA can run a UART and those pins would be wired to either a RS-232 DE-9 serial connecter (this is connector with two rows of 5 and 4 pins), or to some kind of USB Serial chip such as an FTDI chip. For my board, there was an alternate solution supported by Altera using the JTAG programming and debug interface. It can generate probe signals that can be buried into an HDL project somewhere. This uses a different set of signals that communicate over JTAG. This kind of interface is normally just used during development, but it works well enough for this situation and is simpler than UART, typically.

Does your development board have a DE-9 or USB Serial connector? If so, you could wire that to the to the signals in the top-level of the project to use it for a UART. The baud rate will be dependent on the clock signal into the project, but you should be able to add a clock divider to set it to something reasonable.

If you want to try the UART approach, I would recommend becoming more familiar with how UARTs work and RS-232 protocols. Try to create a new project that just does something very simple with the UART such as send out two ASCII characters, 'H' and 'i', with some delay between them and just have it repeat that. Generating serial data in HDL code for transmission is not too difficult and is a good warm-up project. It also verifies that your board and set-up will work with serial. However, even before this, I would recommend something simpler like turning on and blinking LEDs on the board. See if you can get it to blink exactly once per second. This will help make sure you have the timing correct. For both of these warm-ups, there is plenty of examples and tutorials online to help.

[kapoor7997]

Hi penguin359,

My board is ZCU102 and it has USB-UART chip and also USB-JTAG.

Once again I really appreciate your reply.
I went over the code and the top level entity is only taking bit inputs. So looks like this code is not taking any real work from the miner.py script.
So looks like the code I am looking at in projects/VHDL_Xilinx_Port https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_Xilinx_Port is not mineable.
Did you use this code to mine? or are you talking about some other code that can mine.
The inputs to UART are txdata, txstrobe, txwidth are being given from top level entity and are mostly constants
and UART's outputs are rxdata and rxstrobe are used to change the input data that goes to the miner.
But how is this code going to receive anything from the pool to do actual mining?

I have worked in RS232 and can set that up but I am trying to just understand which entity in this code will receive work from the host machine connected to the pool. Will the UART entity in this code receive data from the host via USB-uart chip? Or this code is just showing UART as a dummy entity that represents the data coming from actual UART.

Thanks,
kapoor7997

[rockydemag]

Hi kapoor7997,

Have you had any progress/luck with getting the project running with zcu102 board.

Thanks,
Rocky