diff --git a/i2c/imx6ull/imx6ull-i2c-def.h b/i2c/imx6ull/imx6ull-i2c-def.h
new file mode 100644
index 000000000..ea7c46401
--- /dev/null
+++ b/i2c/imx6ull/imx6ull-i2c-def.h
@@ -0,0 +1,98 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * i.MX6ULL I2C driver
+ *
+ * Default pin definitions
+ *
+ * Copyright 2025 Phoenix Systems
+ * Author: Jacek Maksymowicz
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _IMX6ULL_I2C_DEF_H_
+#define _IMX6ULL_I2C_DEF_H_
+
+#ifndef CONFIG_I2C1_SCL_MUX_PAD
+#define CONFIG_I2C1_SCL_MUX_PAD mux_gpio1_02
+#endif
+#ifndef CONFIG_I2C1_SCL_MUX_VAL
+#define CONFIG_I2C1_SCL_MUX_VAL 0
+#endif
+#ifndef CONFIG_I2C1_SDA_MUX_PAD
+#define CONFIG_I2C1_SDA_MUX_PAD mux_gpio1_03
+#endif
+#ifndef CONFIG_I2C1_SDA_MUX_VAL
+#define CONFIG_I2C1_SDA_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_I2C2_SCL_MUX_PAD
+#define CONFIG_I2C2_SCL_MUX_PAD mux_gpio1_00
+#endif
+#ifndef CONFIG_I2C2_SCL_MUX_VAL
+#define CONFIG_I2C2_SCL_MUX_VAL 0
+#endif
+#ifndef CONFIG_I2C2_SDA_MUX_PAD
+#define CONFIG_I2C2_SDA_MUX_PAD mux_gpio1_01
+#endif
+#ifndef CONFIG_I2C2_SDA_MUX_VAL
+#define CONFIG_I2C2_SDA_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_I2C3_SCL_MUX_PAD
+#define CONFIG_I2C3_SCL_MUX_PAD mux_lcd_d1
+#endif
+#ifndef CONFIG_I2C3_SCL_MUX_VAL
+#define CONFIG_I2C3_SCL_MUX_VAL 4
+#endif
+#ifndef CONFIG_I2C3_SDA_MUX_PAD
+#define CONFIG_I2C3_SDA_MUX_PAD mux_lcd_d0
+#endif
+#ifndef CONFIG_I2C3_SDA_MUX_VAL
+#define CONFIG_I2C3_SDA_MUX_VAL 4
+#endif
+
+#ifndef CONFIG_I2C4_SCL_MUX_PAD
+#define CONFIG_I2C4_SCL_MUX_PAD mux_lcd_d3
+#endif
+#ifndef CONFIG_I2C4_SCL_MUX_VAL
+#define CONFIG_I2C4_SCL_MUX_VAL 4
+#endif
+#ifndef CONFIG_I2C4_SDA_MUX_PAD
+#define CONFIG_I2C4_SDA_MUX_PAD mux_lcd_d2
+#endif
+#ifndef CONFIG_I2C4_SDA_MUX_VAL
+#define CONFIG_I2C4_SDA_MUX_VAL 4
+#endif
+
+#ifndef CONFIG_I2C1_SCL_ISEL
+#define CONFIG_I2C1_SCL_ISEL 0
+#endif
+#ifndef CONFIG_I2C1_SDA_ISEL
+#define CONFIG_I2C1_SDA_ISEL 1
+#endif
+#ifndef CONFIG_I2C2_SCL_ISEL
+#define CONFIG_I2C2_SCL_ISEL 1
+#endif
+#ifndef CONFIG_I2C2_SDA_ISEL
+#define CONFIG_I2C2_SDA_ISEL 1
+#endif
+#ifndef CONFIG_I2C3_SCL_ISEL
+#define CONFIG_I2C3_SCL_ISEL 2
+#endif
+#ifndef CONFIG_I2C3_SDA_ISEL
+#define CONFIG_I2C3_SDA_ISEL 2
+#endif
+#ifndef CONFIG_I2C4_SCL_ISEL
+#define CONFIG_I2C4_SCL_ISEL 2
+#endif
+#ifndef CONFIG_I2C4_SDA_ISEL
+#define CONFIG_I2C4_SDA_ISEL 2
+#endif
+
+#endif /* _IMX6ULL_I2C_DEF_H_ */
diff --git a/i2c/imx6ull/libimx6ull-i2c.c b/i2c/imx6ull/libimx6ull-i2c.c
index 4406bea26..08a519899 100644
--- a/i2c/imx6ull/libimx6ull-i2c.c
+++ b/i2c/imx6ull/libimx6ull-i2c.c
@@ -24,6 +24,12 @@
 
 #include <phoenix/arch/armv7a/imx6ull/imx6ull.h>
 
+#include <board_config.h>
+#include "imx6ull-i2c-def.h"
+
+#define XCAT2(a, b) a##b
+#define PCTL(x)     XCAT2(pctl_, x)
+
 
 /* clang-format off */
 /* NOTE: i2c registers are 16-bit and every second offset is reserved for future use */
@@ -41,17 +47,17 @@ typedef struct {
 } i2c_pctl_t;
 
 static const i2c_pctl_t i2c_pctl_mux[4][2] = {
-	{ { pctl_mux_gpio1_02, 0 }, { pctl_mux_gpio1_03, 0 } },
-	{ { pctl_mux_gpio1_00, 0 }, { pctl_mux_gpio1_01, 0 } },
-	{ { pctl_mux_lcd_d1, 4 }, { pctl_mux_lcd_d0, 4 } },
-	{ { pctl_mux_lcd_d3, 4 }, { pctl_mux_lcd_d2, 4 } },
+	{ { PCTL(CONFIG_I2C1_SCL_MUX_PAD), CONFIG_I2C1_SCL_MUX_VAL }, { PCTL(CONFIG_I2C1_SDA_MUX_PAD), CONFIG_I2C1_SDA_MUX_VAL } },
+	{ { PCTL(CONFIG_I2C2_SCL_MUX_PAD), CONFIG_I2C2_SCL_MUX_VAL }, { PCTL(CONFIG_I2C2_SDA_MUX_PAD), CONFIG_I2C2_SDA_MUX_VAL } },
+	{ { PCTL(CONFIG_I2C3_SCL_MUX_PAD), CONFIG_I2C3_SCL_MUX_VAL }, { PCTL(CONFIG_I2C3_SDA_MUX_PAD), CONFIG_I2C3_SDA_MUX_VAL } },
+	{ { PCTL(CONFIG_I2C4_SCL_MUX_PAD), CONFIG_I2C4_SCL_MUX_VAL }, { PCTL(CONFIG_I2C4_SDA_MUX_PAD), CONFIG_I2C4_SDA_MUX_VAL } },
 };
 
 static const i2c_pctl_t i2c_pctl_isel[4][2] = {
-	{ { pctl_isel_i2c1_scl, 0 }, { pctl_isel_i2c1_sda, 1 } },
-	{ { pctl_isel_i2c2_scl, 1 }, { pctl_isel_i2c2_sda, 1 } },
-	{ { pctl_isel_i2c3_scl, 2 }, { pctl_isel_i2c3_sda, 2 } },
-	{ { pctl_isel_i2c4_scl, 2 }, { pctl_isel_i2c4_sda, 2 } },
+	{ { pctl_isel_i2c1_scl, CONFIG_I2C1_SCL_ISEL }, { pctl_isel_i2c1_sda, CONFIG_I2C1_SDA_ISEL } },
+	{ { pctl_isel_i2c2_scl, CONFIG_I2C2_SCL_ISEL }, { pctl_isel_i2c2_sda, CONFIG_I2C2_SDA_ISEL } },
+	{ { pctl_isel_i2c3_scl, CONFIG_I2C3_SCL_ISEL }, { pctl_isel_i2c3_sda, CONFIG_I2C3_SDA_ISEL } },
+	{ { pctl_isel_i2c4_scl, CONFIG_I2C4_SCL_ISEL }, { pctl_isel_i2c4_sda, CONFIG_I2C4_SDA_ISEL } },
 };
 
 
diff --git a/spi/imx6ull-ecspi/libecspi-def.h b/spi/imx6ull-ecspi/libecspi-def.h
new file mode 100644
index 000000000..ac4140f59
--- /dev/null
+++ b/spi/imx6ull-ecspi/libecspi-def.h
@@ -0,0 +1,317 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * i.MX6ULL ECSPI driver
+ *
+ * Default pin definitions
+ *
+ * Copyright 2025 Phoenix Systems
+ * Author: Jacek Maksymowicz
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+
+#ifndef _LIBECSPI_DEF_H_
+#define _LIBECSPI_DEF_H_
+
+#ifndef CONFIG_ECSPI1_MISO_MUX_PAD
+#define CONFIG_ECSPI1_MISO_MUX_PAD mux_lcd_d23
+#endif
+
+#ifndef CONFIG_ECSPI1_MISO_MUX_VAL
+#define CONFIG_ECSPI1_MISO_MUX_VAL 2
+#endif
+
+#ifndef CONFIG_ECSPI1_MOSI_MUX_PAD
+#define CONFIG_ECSPI1_MOSI_MUX_PAD mux_lcd_d22
+#endif
+
+#ifndef CONFIG_ECSPI1_MOSI_MUX_VAL
+#define CONFIG_ECSPI1_MOSI_MUX_VAL 2
+#endif
+
+#ifndef CONFIG_ECSPI1_SCLK_MUX_PAD
+#define CONFIG_ECSPI1_SCLK_MUX_PAD mux_lcd_d20
+#endif
+
+#ifndef CONFIG_ECSPI1_SCLK_MUX_VAL
+#define CONFIG_ECSPI1_SCLK_MUX_VAL 2
+#endif
+
+#ifndef CONFIG_ECSPI1_SS0_MUX_PAD
+#define CONFIG_ECSPI1_SS0_MUX_PAD mux_lcd_d21
+#endif
+
+#ifndef CONFIG_ECSPI1_SS0_MUX_VAL
+#define CONFIG_ECSPI1_SS0_MUX_VAL 2
+#endif
+
+#ifndef CONFIG_ECSPI1_SS1_MUX_PAD
+#define CONFIG_ECSPI1_SS1_MUX_PAD mux_lcd_d5
+#endif
+
+#ifndef CONFIG_ECSPI1_SS1_MUX_VAL
+#define CONFIG_ECSPI1_SS1_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI1_SS2_MUX_PAD
+#define CONFIG_ECSPI1_SS2_MUX_PAD mux_lcd_d6
+#endif
+
+#ifndef CONFIG_ECSPI1_SS2_MUX_VAL
+#define CONFIG_ECSPI1_SS2_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI1_SS3_MUX_PAD
+#define CONFIG_ECSPI1_SS3_MUX_PAD mux_lcd_d7
+#endif
+
+#ifndef CONFIG_ECSPI1_SS3_MUX_VAL
+#define CONFIG_ECSPI1_SS3_MUX_VAL 8
+#endif
+
+
+#ifndef CONFIG_ECSPI2_MISO_MUX_PAD
+#define CONFIG_ECSPI2_MISO_MUX_PAD mux_csi_d3
+#endif
+
+#ifndef CONFIG_ECSPI2_MISO_MUX_VAL
+#define CONFIG_ECSPI2_MISO_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI2_MOSI_MUX_PAD
+#define CONFIG_ECSPI2_MOSI_MUX_PAD mux_csi_d2
+#endif
+
+#ifndef CONFIG_ECSPI2_MOSI_MUX_VAL
+#define CONFIG_ECSPI2_MOSI_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI2_SCLK_MUX_PAD
+#define CONFIG_ECSPI2_SCLK_MUX_PAD mux_csi_d0
+#endif
+
+#ifndef CONFIG_ECSPI2_SCLK_MUX_VAL
+#define CONFIG_ECSPI2_SCLK_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI2_SS0_MUX_PAD
+#define CONFIG_ECSPI2_SS0_MUX_PAD mux_csi_d1
+#endif
+
+#ifndef CONFIG_ECSPI2_SS0_MUX_VAL
+#define CONFIG_ECSPI2_SS0_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI2_SS1_MUX_PAD
+#define CONFIG_ECSPI2_SS1_MUX_PAD mux_lcd_hsync
+#endif
+
+#ifndef CONFIG_ECSPI2_SS1_MUX_VAL
+#define CONFIG_ECSPI2_SS1_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI2_SS2_MUX_PAD
+#define CONFIG_ECSPI2_SS2_MUX_PAD mux_lcd_vsync
+#endif
+
+#ifndef CONFIG_ECSPI2_SS2_MUX_VAL
+#define CONFIG_ECSPI2_SS2_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI2_SS3_MUX_PAD
+#define CONFIG_ECSPI2_SS3_MUX_PAD mux_lcd_rst
+#endif
+
+#ifndef CONFIG_ECSPI2_SS3_MUX_VAL
+#define CONFIG_ECSPI2_SS3_MUX_VAL 8
+#endif
+
+
+#ifndef CONFIG_ECSPI3_MISO_MUX_PAD
+#define CONFIG_ECSPI3_MISO_MUX_PAD mux_uart2_rts
+#endif
+
+#ifndef CONFIG_ECSPI3_MISO_MUX_VAL
+#define CONFIG_ECSPI3_MISO_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI3_MOSI_MUX_PAD
+#define CONFIG_ECSPI3_MOSI_MUX_PAD mux_uart2_cts
+#endif
+
+#ifndef CONFIG_ECSPI3_MOSI_MUX_VAL
+#define CONFIG_ECSPI3_MOSI_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI3_SCLK_MUX_PAD
+#define CONFIG_ECSPI3_SCLK_MUX_PAD mux_uart2_rx
+#endif
+
+#ifndef CONFIG_ECSPI3_SCLK_MUX_VAL
+#define CONFIG_ECSPI3_SCLK_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI3_SS0_MUX_PAD
+#define CONFIG_ECSPI3_SS0_MUX_PAD mux_uart2_tx
+#endif
+
+#ifndef CONFIG_ECSPI3_SS0_MUX_VAL
+#define CONFIG_ECSPI3_SS0_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI3_SS1_MUX_PAD
+#define CONFIG_ECSPI3_SS1_MUX_PAD mux_nand_ale
+#endif
+
+#ifndef CONFIG_ECSPI3_SS1_MUX_VAL
+#define CONFIG_ECSPI3_SS1_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI3_SS2_MUX_PAD
+#define CONFIG_ECSPI3_SS2_MUX_PAD mux_nand_re
+#endif
+
+#ifndef CONFIG_ECSPI3_SS2_MUX_VAL
+#define CONFIG_ECSPI3_SS2_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI3_SS3_MUX_PAD
+#define CONFIG_ECSPI3_SS3_MUX_PAD mux_nand_we
+#endif
+
+#ifndef CONFIG_ECSPI3_SS3_MUX_VAL
+#define CONFIG_ECSPI3_SS3_MUX_VAL 8
+#endif
+
+
+#ifndef CONFIG_ECSPI4_MISO_MUX_PAD
+#define CONFIG_ECSPI4_MISO_MUX_PAD mux_enet2_txclk
+#endif
+
+#ifndef CONFIG_ECSPI4_MISO_MUX_VAL
+#define CONFIG_ECSPI4_MISO_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI4_MOSI_MUX_PAD
+#define CONFIG_ECSPI4_MOSI_MUX_PAD mux_enet2_txen
+#endif
+
+#ifndef CONFIG_ECSPI4_MOSI_MUX_VAL
+#define CONFIG_ECSPI4_MOSI_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI4_SCLK_MUX_PAD
+#define CONFIG_ECSPI4_SCLK_MUX_PAD mux_enet2_tx1
+#endif
+
+#ifndef CONFIG_ECSPI4_SCLK_MUX_VAL
+#define CONFIG_ECSPI4_SCLK_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI4_SS0_MUX_PAD
+#define CONFIG_ECSPI4_SS0_MUX_PAD mux_enet2_rxer
+#endif
+
+#ifndef CONFIG_ECSPI4_SS0_MUX_VAL
+#define CONFIG_ECSPI4_SS0_MUX_VAL 3
+#endif
+
+#ifndef CONFIG_ECSPI4_SS1_MUX_PAD
+#define CONFIG_ECSPI4_SS1_MUX_PAD mux_nand_d1
+#endif
+
+#ifndef CONFIG_ECSPI4_SS1_MUX_VAL
+#define CONFIG_ECSPI4_SS1_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI4_SS2_MUX_PAD
+#define CONFIG_ECSPI4_SS2_MUX_PAD mux_nand_d2
+#endif
+
+#ifndef CONFIG_ECSPI4_SS2_MUX_VAL
+#define CONFIG_ECSPI4_SS2_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_ECSPI4_SS3_MUX_PAD
+#define CONFIG_ECSPI4_SS3_MUX_PAD mux_nand_d3
+#endif
+
+#ifndef CONFIG_ECSPI4_SS3_MUX_VAL
+#define CONFIG_ECSPI4_SS3_MUX_VAL 8
+#endif
+
+
+#ifndef CONFIG_ECSPI1_MISO_ISEL
+#define CONFIG_ECSPI1_MISO_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI1_MOSI_ISEL
+#define CONFIG_ECSPI1_MOSI_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI1_SCLK_ISEL
+#define CONFIG_ECSPI1_SCLK_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI1_SS0_ISEL
+#define CONFIG_ECSPI1_SS0_ISEL 0
+#endif
+
+
+#ifndef CONFIG_ECSPI2_MISO_ISEL
+#define CONFIG_ECSPI2_MISO_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI2_MOSI_ISEL
+#define CONFIG_ECSPI2_MOSI_ISEL 1
+#endif
+
+#ifndef CONFIG_ECSPI2_SCLK_ISEL
+#define CONFIG_ECSPI2_SCLK_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI2_SS0_ISEL
+#define CONFIG_ECSPI2_SS0_ISEL 0
+#endif
+
+
+#ifndef CONFIG_ECSPI3_MISO_ISEL
+#define CONFIG_ECSPI3_MISO_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI3_MOSI_ISEL
+#define CONFIG_ECSPI3_MOSI_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI3_SCLK_ISEL
+#define CONFIG_ECSPI3_SCLK_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI3_SS0_ISEL
+#define CONFIG_ECSPI3_SS0_ISEL 0
+#endif
+
+
+#ifndef CONFIG_ECSPI4_MISO_ISEL
+#define CONFIG_ECSPI4_MISO_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI4_MOSI_ISEL
+#define CONFIG_ECSPI4_MOSI_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI4_SCLK_ISEL
+#define CONFIG_ECSPI4_SCLK_ISEL 0
+#endif
+
+#ifndef CONFIG_ECSPI4_SS0_ISEL
+#define CONFIG_ECSPI4_SS0_ISEL 0
+#endif
+
+#endif /* _LIBECSPI_DEF_H_ */
diff --git a/spi/imx6ull-ecspi/libecspi.c b/spi/imx6ull-ecspi/libecspi.c
index 80affacb1..e559b6aff 100644
--- a/spi/imx6ull-ecspi/libecspi.c
+++ b/spi/imx6ull-ecspi/libecspi.c
@@ -18,17 +18,25 @@
 
 #include <phoenix/arch/armv7a/imx6ull/imx6ull.h>
 
+#include <board_config.h>
+#include "libecspi-def.h"
+
 #include "imx6ull-ecspi.h"
 
 
-#define BYTES_2_RXTHRESHOLD(LEN) (((LEN) + 3) / 4 - 1)
+#define BYTES_2_RXTHRESHOLD(LEN)   (((LEN) + 3) / 4 - 1)
 #define BITS_2_BYTES_ROUND_UP(LEN) (((LEN) + 7) / 8)
-#define GET_BURST_IN_BYTES(ECSPI) (BITS_2_BYTES_ROUND_UP((*((ECSPI)->base + conreg) >> 20) + 1))
+#define GET_BURST_IN_BYTES(ECSPI)  (BITS_2_BYTES_ROUND_UP((*((ECSPI)->base + conreg) >> 20) + 1))
+
+#define XCAT2(a, b) a##b
+#define PCTL(x)     XCAT2(pctl_, x)
 
 
+/* clang-format off */
 enum { rxdata = 0, txdata, conreg, configreg, intreg, dmareg, statreg, periodreg, testreg, msgdata = 16 };
 
 typedef enum { mode_sync_exchange, mode_async_write, mode_async_exchange, mode_async_periodical } ecspi_mode_t;
+/* clang-format on */
 
 typedef struct {
 	volatile uint32_t *base;
@@ -42,47 +50,96 @@ typedef struct {
 
 typedef struct {
 	int pctl;
-	char val;
+	int8_t val;
 } ecspi_pctl_t;
 
 
 static const addr_t ecspi_addr[4] = { 0x2008000, 0x200C000, 0x2010000, 0x2014000 };
 static const unsigned int ecspi_intr_number[4] = { 63, 64, 65, 66 };
 
-ecspi_pctl_t ecspi_pctl_mux[4][7] = {
-	{ { pctl_mux_lcd_d23,     2 }, { pctl_mux_lcd_d22,    2 }, { pctl_mux_lcd_d20,   2 }, { pctl_mux_lcd_d21,    2 },
-	  { pctl_mux_lcd_d5,      8 }, { pctl_mux_lcd_d6,     8 }, { pctl_mux_lcd_d7,    8 } },
-	{ { pctl_mux_csi_d3,      3 }, { pctl_mux_csi_d2,     3 }, { pctl_mux_csi_d0,    3 }, { pctl_mux_csi_d1,     3 },
-	  { pctl_mux_lcd_hsync,   8 }, { pctl_mux_lcd_vsync,  8 }, { pctl_mux_lcd_rst,   8 } },
-	{ { pctl_mux_uart2_rts,   8 }, { pctl_mux_uart2_cts,  8 }, { pctl_mux_uart2_rx,  8 }, { pctl_mux_uart2_tx,   8 },
-	  { pctl_mux_nand_ale,    8 }, { pctl_mux_nand_re,    8 }, { pctl_mux_nand_we,   8 } },
-	{ { pctl_mux_enet2_txclk, 3 }, { pctl_mux_enet2_txen, 3 }, { pctl_mux_enet2_tx1, 3 }, { pctl_mux_enet2_rxer, 3 },
-	  { pctl_mux_nand_d1,     8 }, { pctl_mux_nand_d2,    8 }, { pctl_mux_nand_d3,   8 } }
+static const ecspi_pctl_t ecspi_pctl_mux[4][7] = {
+	{
+		{ PCTL(CONFIG_ECSPI1_MISO_MUX_PAD), CONFIG_ECSPI1_MISO_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI1_MOSI_MUX_PAD), CONFIG_ECSPI1_MOSI_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI1_SCLK_MUX_PAD), CONFIG_ECSPI1_SCLK_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI1_SS0_MUX_PAD), CONFIG_ECSPI1_SS0_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI1_SS1_MUX_PAD), CONFIG_ECSPI1_SS1_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI1_SS2_MUX_PAD), CONFIG_ECSPI1_SS2_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI1_SS3_MUX_PAD), CONFIG_ECSPI1_SS3_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_ECSPI2_MISO_MUX_PAD), CONFIG_ECSPI2_MISO_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI2_MOSI_MUX_PAD), CONFIG_ECSPI2_MOSI_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI2_SCLK_MUX_PAD), CONFIG_ECSPI2_SCLK_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI2_SS0_MUX_PAD), CONFIG_ECSPI2_SS0_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI2_SS1_MUX_PAD), CONFIG_ECSPI2_SS1_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI2_SS2_MUX_PAD), CONFIG_ECSPI2_SS2_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI2_SS3_MUX_PAD), CONFIG_ECSPI2_SS3_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_ECSPI3_MISO_MUX_PAD), CONFIG_ECSPI3_MISO_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI3_MOSI_MUX_PAD), CONFIG_ECSPI3_MOSI_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI3_SCLK_MUX_PAD), CONFIG_ECSPI3_SCLK_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI3_SS0_MUX_PAD), CONFIG_ECSPI3_SS0_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI3_SS1_MUX_PAD), CONFIG_ECSPI3_SS1_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI3_SS2_MUX_PAD), CONFIG_ECSPI3_SS2_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI3_SS3_MUX_PAD), CONFIG_ECSPI3_SS3_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_ECSPI4_MISO_MUX_PAD), CONFIG_ECSPI4_MISO_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI4_MOSI_MUX_PAD), CONFIG_ECSPI4_MOSI_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI4_SCLK_MUX_PAD), CONFIG_ECSPI4_SCLK_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI4_SS0_MUX_PAD), CONFIG_ECSPI4_SS0_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI4_SS1_MUX_PAD), CONFIG_ECSPI4_SS1_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI4_SS2_MUX_PAD), CONFIG_ECSPI4_SS2_MUX_VAL },
+		{ PCTL(CONFIG_ECSPI4_SS3_MUX_PAD), CONFIG_ECSPI4_SS3_MUX_VAL },
+	},
 };
 
-ecspi_pctl_t ecspi_pctl_isel[4][4] = {
-	{ { pctl_isel_ecspi1_miso, 0 }, { pctl_isel_ecspi1_mosi, 0 }, { pctl_isel_ecspi1_sclk, 0 }, { pctl_isel_ecspi1_ss0, 0 } },
-	{ { pctl_isel_ecspi2_miso, 0 }, { pctl_isel_ecspi2_mosi, 1 }, { pctl_isel_ecspi2_sclk, 0 }, { pctl_isel_ecspi2_ss0, 0 } },
-	{ { pctl_isel_ecspi3_miso, 0 }, { pctl_isel_ecspi3_mosi, 0 }, { pctl_isel_ecspi3_sclk, 0 }, { pctl_isel_ecspi3_ss0, 0 } },
-	{ { pctl_isel_ecspi4_miso, 0 }, { pctl_isel_ecspi4_mosi, 0 }, { pctl_isel_ecspi4_sclk, 0 }, { pctl_isel_ecspi4_ss0, 0 } }
+static const ecspi_pctl_t ecspi_pctl_isel[4][4] = {
+	{
+		{ pctl_isel_ecspi1_miso, CONFIG_ECSPI1_MISO_ISEL },
+		{ pctl_isel_ecspi1_mosi, CONFIG_ECSPI1_MOSI_ISEL },
+		{ pctl_isel_ecspi1_sclk, CONFIG_ECSPI1_SCLK_ISEL },
+		{ pctl_isel_ecspi1_ss0, CONFIG_ECSPI1_SS0_ISEL },
+	},
+	{
+		{ pctl_isel_ecspi2_miso, CONFIG_ECSPI2_MISO_ISEL },
+		{ pctl_isel_ecspi2_mosi, CONFIG_ECSPI2_MOSI_ISEL },
+		{ pctl_isel_ecspi2_sclk, CONFIG_ECSPI2_SCLK_ISEL },
+		{ pctl_isel_ecspi2_ss0, CONFIG_ECSPI2_SS0_ISEL },
+	},
+	{
+		{ pctl_isel_ecspi3_miso, CONFIG_ECSPI3_MISO_ISEL },
+		{ pctl_isel_ecspi3_mosi, CONFIG_ECSPI3_MOSI_ISEL },
+		{ pctl_isel_ecspi3_sclk, CONFIG_ECSPI3_SCLK_ISEL },
+		{ pctl_isel_ecspi3_ss0, CONFIG_ECSPI3_SS0_ISEL },
+	},
+	{
+		{ pctl_isel_ecspi4_miso, CONFIG_ECSPI4_MISO_ISEL },
+		{ pctl_isel_ecspi4_mosi, CONFIG_ECSPI4_MOSI_ISEL },
+		{ pctl_isel_ecspi4_sclk, CONFIG_ECSPI4_SCLK_ISEL },
+		{ pctl_isel_ecspi4_ss0, CONFIG_ECSPI4_SS0_ISEL },
+	},
 };
 
-uint32_t ecspi_pctl_clk[4] = { pctl_clk_ecspi1, pctl_clk_ecspi2, pctl_clk_ecspi3, pctl_clk_ecspi4 };
+static const uint32_t ecspi_pctl_clk[4] = { pctl_clk_ecspi1, pctl_clk_ecspi2, pctl_clk_ecspi3, pctl_clk_ecspi4 };
 
-static ecspi_t ecspi[4] = {0};
+static ecspi_t ecspi[4] = { 0 };
 
 
-#define RESET_ECSPI(ECSPI) do { \
-	uint32_t reg_backup[3]; \
-	reg_backup[0] = *((ECSPI)->base + configreg); \
-	reg_backup[1] = *((ECSPI)->base + intreg); \
-	reg_backup[2] = *((ECSPI)->base + periodreg); \
-	*((ECSPI)->base + conreg) &= ~(1 << 0); \
-	*((ECSPI)->base + conreg) |= (1 << 0); \
-	*((ECSPI)->base + configreg) = reg_backup[0]; \
-	*((ECSPI)->base + intreg) = reg_backup[1]; \
-	*((ECSPI)->base + periodreg) = reg_backup[2]; \
-} while (0)
+#define RESET_ECSPI(ECSPI) \
+	do { \
+		uint32_t reg_backup[3]; \
+		reg_backup[0] = *((ECSPI)->base + configreg); \
+		reg_backup[1] = *((ECSPI)->base + intreg); \
+		reg_backup[2] = *((ECSPI)->base + periodreg); \
+		*((ECSPI)->base + conreg) &= ~(1 << 0); \
+		*((ECSPI)->base + conreg) |= (1 << 0); \
+		*((ECSPI)->base + configreg) = reg_backup[0]; \
+		*((ECSPI)->base + intreg) = reg_backup[1]; \
+		*((ECSPI)->base + periodreg) = reg_backup[2]; \
+	} while (0)
 
 
 static void readFifo(int dev_no, uint8_t *in, size_t len);
@@ -93,9 +150,9 @@ static void writeFifo(int dev_no, const uint8_t *out, size_t len);
 
 static int ecspi_irqHandler(unsigned int n, void *arg)
 {
-	(void) n;
+	(void)n;
 
-	ecspi_t *e = &ecspi[(int) arg];
+	ecspi_t *e = &ecspi[(int)arg];
 
 	if (e->mode != mode_sync_exchange) {
 		return -1;
@@ -110,7 +167,7 @@ static int ecspi_irqHandler(unsigned int n, void *arg)
 
 static int ecspi_irqHandlerAsync(unsigned int n, void *arg)
 {
-	(void) n;
+	(void)n;
 
 	size_t count;
 	int res = -1;
@@ -157,7 +214,8 @@ static int ecspi_irqHandlerAsync(unsigned int n, void *arg)
 				/* The only way to reset the internal period counter is to reenable the ECSPI. */
 				RESET_ECSPI(e);
 				res = 1;
-			} else {
+			}
+			else {
 				writeFifo(ctx->dev_no, ctx->out_periodical, count);
 				*(e->base + conreg) |= (1 << 2);
 				res = -1;
@@ -196,6 +254,11 @@ static void set_mux(int dev_no, uint8_t chan_msk)
 	for (i = 0; i < 7; i++) {
 		/* Skip SS lines not enabled in chan_msk */
 		if (i < 3 || (chan_msk & (1 << (i - 3)))) {
+			/* Skip if a given mux should not be configured */
+			if ((ecspi_pctl_mux[(dev_no - 1)][i].val < 0)) {
+				continue;
+			}
+
 			ctl.iomux.mux = ecspi_pctl_mux[(dev_no - 1)][i].pctl;
 			ctl.iomux.mode = ecspi_pctl_mux[(dev_no - 1)][i].val;
 			platformctl(&ctl);
@@ -207,6 +270,11 @@ static void set_mux(int dev_no, uint8_t chan_msk)
 
 	for (i = 0; i < 4; i++) {
 		if (i < 3 || (chan_msk & (1 << (i - 3)))) {
+			/* Skip if a given ISEL should not be configured */
+			if ((ecspi_pctl_isel[(dev_no - 1)][i].val < 0)) {
+				continue;
+			}
+
 			ctl.ioisel.isel = ecspi_pctl_isel[(dev_no - 1)][i].pctl;
 			ctl.ioisel.daisy = ecspi_pctl_isel[(dev_no - 1)][i].val;
 			platformctl(&ctl);
@@ -247,7 +315,7 @@ static void writeFifo(int dev_no, const uint8_t *out, size_t len)
 	}
 
 	while (len > 0) {
-		word = out[3] | ((uint32_t) out[2] << 8) | ((uint32_t) out[1] << 16) | ((uint32_t) out[0] << 24);
+		word = out[3] | ((uint32_t)out[2] << 8) | ((uint32_t)out[1] << 16) | ((uint32_t)out[0] << 24);
 
 		*(e->base + txdata) = word;
 
@@ -438,7 +506,6 @@ int ecspi_exchange(int dev_no, const uint8_t *out, uint8_t *in, size_t len)
 }
 
 
-
 int ecspi_exchangeBusy(int dev_no, const uint8_t *out, uint8_t *in, size_t len)
 {
 	ecspi_t *e;
@@ -486,7 +553,7 @@ int ecspi_registerContext(int dev_no, ecspi_ctx_t *ctx, handle_t cond)
 		.dev_no = dev_no,
 	};
 
-	return interrupt(ecspi_intr_number[dev_no - 1], ecspi_irqHandlerAsync, (void *) ctx, cond, &ctx->inth);
+	return interrupt(ecspi_intr_number[dev_no - 1], ecspi_irqHandlerAsync, (void *)ctx, cond, &ctx->inth);
 }
 
 
@@ -531,7 +598,7 @@ int ecspi_exchangeAsync(ecspi_ctx_t *ctx, const uint8_t *out, size_t len)
 		current_burst = (*(e->base + conreg) >> 20) + 1;
 		rxfifo_word_cnt = (*(e->base + testreg) >> 8) & 0x7F;
 
-		if (current_burst == (len * 8) && (int) (len / 4) <= (64 - txfifo_word_cnt) && (int) (len / 4) < (64 - rxfifo_word_cnt)) {
+		if (current_burst == (len * 8) && (int)(len / 4) <= (64 - txfifo_word_cnt) && (int)(len / 4) < (64 - rxfifo_word_cnt)) {
 			writeFifo(ctx->dev_no, out, len);
 			*(e->base + conreg) |= (1 << 2);
 			written = len;
@@ -622,7 +689,7 @@ int ecspi_writeAsync(ecspi_ctx_t *ctx, const uint8_t *out, size_t len)
 	else if (e->mode == mode_async_write) {
 		current_burst = (*(e->base + conreg) >> 20) + 1;
 
-		if (current_burst == (len * 8) && (int) (len / 4) <= (64 - txfifo_word_cnt)) {
+		if (current_burst == (len * 8) && (int)(len / 4) <= (64 - txfifo_word_cnt)) {
 			writeFifo(ctx->dev_no, out, len);
 			*(e->base + conreg) |= (1 << 2);
 
@@ -659,7 +726,7 @@ int ecspi_init(int dev_no, uint8_t chan_msk)
 	e->mode = mode_sync_exchange;
 
 	if ((e->base = mmap(NULL, _PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_DEVICE | MAP_PHYSMEM | MAP_ANONYMOUS, -1, ecspi_addr[dev_no - 1])) == MAP_FAILED) {
-		printf("ecspi: could not map ecspi%d paddr %p.\n", dev_no, (void*) ecspi_addr[dev_no - 1]);
+		printf("ecspi: could not map ecspi%d paddr %p.\n", dev_no, (void *)ecspi_addr[dev_no - 1]);
 		return -1;
 	}
 
@@ -669,7 +736,7 @@ int ecspi_init(int dev_no, uint8_t chan_msk)
 	mutexCreate(&e->irqlock);
 	condCreate(&e->cond);
 
-	interrupt(ecspi_intr_number[dev_no - 1], ecspi_irqHandler, (void *) (dev_no - 1), e->cond, &e->inth);
+	interrupt(ecspi_intr_number[dev_no - 1], ecspi_irqHandler, (void *)(dev_no - 1), e->cond, &e->inth);
 
 	/* Enable ECSPI. Defaults: 8-bit burst, multi burst, mode 0, all master, no cock division */
 	*(e->base + conreg) = 0x007000F1;
diff --git a/tty/imx6ull-uart/imx6ull-uart-def.h b/tty/imx6ull-uart/imx6ull-uart-def.h
new file mode 100644
index 000000000..e6a70cafd
--- /dev/null
+++ b/tty/imx6ull-uart/imx6ull-uart-def.h
@@ -0,0 +1,343 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * i.MX6ULL UART driver
+ *
+ * Default pin definitions
+ *
+ * Copyright 2025 Phoenix Systems
+ * Author: Jacek Maksymowicz
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+
+#ifndef _IMX6ULL_UART_DEF_H_
+#define _IMX6ULL_UART_DEF_H_
+
+#ifndef CONFIG_UART1_CTS_MUX_PAD
+#define CONFIG_UART1_CTS_MUX_PAD mux_uart1_cts
+#endif
+
+#ifndef CONFIG_UART1_CTS_MUX_VAL
+#define CONFIG_UART1_CTS_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART1_RTS_MUX_PAD
+#define CONFIG_UART1_RTS_MUX_PAD mux_uart1_rts
+#endif
+
+#ifndef CONFIG_UART1_RTS_MUX_VAL
+#define CONFIG_UART1_RTS_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART1_RX_MUX_PAD
+#define CONFIG_UART1_RX_MUX_PAD mux_uart1_rx
+#endif
+
+#ifndef CONFIG_UART1_RX_MUX_VAL
+#define CONFIG_UART1_RX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART1_TX_MUX_PAD
+#define CONFIG_UART1_TX_MUX_PAD mux_uart1_tx
+#endif
+
+#ifndef CONFIG_UART1_TX_MUX_VAL
+#define CONFIG_UART1_TX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART2_CTS_MUX_PAD
+#define CONFIG_UART2_CTS_MUX_PAD mux_uart2_cts
+#endif
+
+#ifndef CONFIG_UART2_CTS_MUX_VAL
+#define CONFIG_UART2_CTS_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART2_RTS_MUX_PAD
+#define CONFIG_UART2_RTS_MUX_PAD mux_uart2_rts
+#endif
+
+#ifndef CONFIG_UART2_RTS_MUX_VAL
+#define CONFIG_UART2_RTS_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART2_RX_MUX_PAD
+#define CONFIG_UART2_RX_MUX_PAD mux_uart2_rx
+#endif
+
+#ifndef CONFIG_UART2_RX_MUX_VAL
+#define CONFIG_UART2_RX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART2_TX_MUX_PAD
+#define CONFIG_UART2_TX_MUX_PAD mux_uart2_tx
+#endif
+
+#ifndef CONFIG_UART2_TX_MUX_VAL
+#define CONFIG_UART2_TX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART3_CTS_MUX_PAD
+#define CONFIG_UART3_CTS_MUX_PAD mux_uart3_cts
+#endif
+
+#ifndef CONFIG_UART3_CTS_MUX_VAL
+#define CONFIG_UART3_CTS_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART3_RTS_MUX_PAD
+#define CONFIG_UART3_RTS_MUX_PAD mux_uart3_rts
+#endif
+
+#ifndef CONFIG_UART3_RTS_MUX_VAL
+#define CONFIG_UART3_RTS_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART3_RX_MUX_PAD
+#define CONFIG_UART3_RX_MUX_PAD mux_uart3_rx
+#endif
+
+#ifndef CONFIG_UART3_RX_MUX_VAL
+#define CONFIG_UART3_RX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART3_TX_MUX_PAD
+#define CONFIG_UART3_TX_MUX_PAD mux_uart3_tx
+#endif
+
+#ifndef CONFIG_UART3_TX_MUX_VAL
+#define CONFIG_UART3_TX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART4_CTS_MUX_PAD
+#define CONFIG_UART4_CTS_MUX_PAD mux_lcd_hsync
+#endif
+
+#ifndef CONFIG_UART4_CTS_MUX_VAL
+#define CONFIG_UART4_CTS_MUX_VAL 2
+#endif
+
+#ifndef CONFIG_UART4_RTS_MUX_PAD
+#define CONFIG_UART4_RTS_MUX_PAD mux_lcd_vsync
+#endif
+
+#ifndef CONFIG_UART4_RTS_MUX_VAL
+#define CONFIG_UART4_RTS_MUX_VAL 2
+#endif
+
+#ifndef CONFIG_UART4_RX_MUX_PAD
+#define CONFIG_UART4_RX_MUX_PAD mux_uart4_rx
+#endif
+
+#ifndef CONFIG_UART4_RX_MUX_VAL
+#define CONFIG_UART4_RX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART4_TX_MUX_PAD
+#define CONFIG_UART4_TX_MUX_PAD mux_uart4_tx
+#endif
+
+#ifndef CONFIG_UART4_TX_MUX_VAL
+#define CONFIG_UART4_TX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART5_CTS_MUX_PAD
+#define CONFIG_UART5_CTS_MUX_PAD mux_gpio1_09
+#endif
+
+#ifndef CONFIG_UART5_CTS_MUX_VAL
+#define CONFIG_UART5_CTS_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_UART5_RTS_MUX_PAD
+#define CONFIG_UART5_RTS_MUX_PAD mux_gpio1_08
+#endif
+
+#ifndef CONFIG_UART5_RTS_MUX_VAL
+#define CONFIG_UART5_RTS_MUX_VAL 8
+#endif
+
+#ifndef CONFIG_UART5_RX_MUX_PAD
+#define CONFIG_UART5_RX_MUX_PAD mux_uart5_rx
+#endif
+
+#ifndef CONFIG_UART5_RX_MUX_VAL
+#define CONFIG_UART5_RX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART5_TX_MUX_PAD
+#define CONFIG_UART5_TX_MUX_PAD mux_uart5_tx
+#endif
+
+#ifndef CONFIG_UART5_TX_MUX_VAL
+#define CONFIG_UART5_TX_MUX_VAL 0
+#endif
+
+#ifndef CONFIG_UART6_CTS_MUX_PAD
+#define CONFIG_UART6_CTS_MUX_PAD mux_enet1_tx1
+#endif
+
+#ifndef CONFIG_UART6_CTS_MUX_VAL
+#define CONFIG_UART6_CTS_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART6_RTS_MUX_PAD
+#define CONFIG_UART6_RTS_MUX_PAD mux_enet1_txen
+#endif
+
+#ifndef CONFIG_UART6_RTS_MUX_VAL
+#define CONFIG_UART6_RTS_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART6_RX_MUX_PAD
+#define CONFIG_UART6_RX_MUX_PAD mux_enet2_rx1
+#endif
+
+#ifndef CONFIG_UART6_RX_MUX_VAL
+#define CONFIG_UART6_RX_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART6_TX_MUX_PAD
+#define CONFIG_UART6_TX_MUX_PAD mux_enet2_rx0
+#endif
+
+#ifndef CONFIG_UART6_TX_MUX_VAL
+#define CONFIG_UART6_TX_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART7_CTS_MUX_PAD
+#define CONFIG_UART7_CTS_MUX_PAD mux_lcd_d6
+#endif
+
+#ifndef CONFIG_UART7_CTS_MUX_VAL
+#define CONFIG_UART7_CTS_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART7_RTS_MUX_PAD
+#define CONFIG_UART7_RTS_MUX_PAD mux_lcd_d7
+#endif
+
+#ifndef CONFIG_UART7_RTS_MUX_VAL
+#define CONFIG_UART7_RTS_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART7_RX_MUX_PAD
+#define CONFIG_UART7_RX_MUX_PAD mux_lcd_d17
+#endif
+
+#ifndef CONFIG_UART7_RX_MUX_VAL
+#define CONFIG_UART7_RX_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART7_TX_MUX_PAD
+#define CONFIG_UART7_TX_MUX_PAD mux_lcd_d16
+#endif
+
+#ifndef CONFIG_UART7_TX_MUX_VAL
+#define CONFIG_UART7_TX_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART8_CTS_MUX_PAD
+#define CONFIG_UART8_CTS_MUX_PAD mux_lcd_d4
+#endif
+
+#ifndef CONFIG_UART8_CTS_MUX_VAL
+#define CONFIG_UART8_CTS_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART8_RTS_MUX_PAD
+#define CONFIG_UART8_RTS_MUX_PAD mux_lcd_d5
+#endif
+
+#ifndef CONFIG_UART8_RTS_MUX_VAL
+#define CONFIG_UART8_RTS_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART8_RX_MUX_PAD
+#define CONFIG_UART8_RX_MUX_PAD mux_lcd_d21
+#endif
+
+#ifndef CONFIG_UART8_RX_MUX_VAL
+#define CONFIG_UART8_RX_MUX_VAL 1
+#endif
+
+#ifndef CONFIG_UART8_TX_MUX_PAD
+#define CONFIG_UART8_TX_MUX_PAD mux_lcd_d20
+#endif
+
+#ifndef CONFIG_UART8_TX_MUX_VAL
+#define CONFIG_UART8_TX_MUX_VAL 1
+#endif
+
+
+#ifndef CONFIG_UART1_RTS_ISEL
+#define CONFIG_UART1_RTS_ISEL 3
+#endif
+
+#ifndef CONFIG_UART1_RX_ISEL
+#define CONFIG_UART1_RX_ISEL 3
+#endif
+
+#ifndef CONFIG_UART2_RTS_ISEL
+#define CONFIG_UART2_RTS_ISEL 1
+#endif
+
+#ifndef CONFIG_UART2_RX_ISEL
+#define CONFIG_UART2_RX_ISEL 1
+#endif
+
+#ifndef CONFIG_UART3_RTS_ISEL
+#define CONFIG_UART3_RTS_ISEL 1
+#endif
+
+#ifndef CONFIG_UART3_RX_ISEL
+#define CONFIG_UART3_RX_ISEL 1
+#endif
+
+#ifndef CONFIG_UART4_RTS_ISEL
+#define CONFIG_UART4_RTS_ISEL 3
+#endif
+
+#ifndef CONFIG_UART4_RX_ISEL
+#define CONFIG_UART4_RX_ISEL 1
+#endif
+
+#ifndef CONFIG_UART5_RTS_ISEL
+#define CONFIG_UART5_RTS_ISEL 1
+#endif
+
+#ifndef CONFIG_UART5_RX_ISEL
+#define CONFIG_UART5_RX_ISEL 7
+#endif
+
+#ifndef CONFIG_UART6_RTS_ISEL
+#define CONFIG_UART6_RTS_ISEL 3
+#endif
+
+#ifndef CONFIG_UART6_RX_ISEL
+#define CONFIG_UART6_RX_ISEL 2
+#endif
+
+#ifndef CONFIG_UART7_RTS_ISEL
+#define CONFIG_UART7_RTS_ISEL 3
+#endif
+
+#ifndef CONFIG_UART7_RX_ISEL
+#define CONFIG_UART7_RX_ISEL 3
+#endif
+
+#ifndef CONFIG_UART8_RTS_ISEL
+#define CONFIG_UART8_RTS_ISEL 3
+#endif
+
+#ifndef CONFIG_UART8_RX_ISEL
+#define CONFIG_UART8_RX_ISEL 3
+#endif
+
+#endif /* _IMX6ULL_UART_DEF_H_ */
diff --git a/tty/imx6ull-uart/imx6ull-uart.c b/tty/imx6ull-uart/imx6ull-uart.c
index d4aabcaa4..e47db20de 100644
--- a/tty/imx6ull-uart/imx6ull-uart.c
+++ b/tty/imx6ull-uart/imx6ull-uart.c
@@ -38,6 +38,9 @@
 
 #include <phoenix/arch/armv7a/imx6ull/imx6ull.h>
 
+#include <board_config.h>
+#include "imx6ull-uart-def.h"
+
 #define KMSG_CTRL_ID 100
 
 #define LOG_TAG "imx6ull-uart"
@@ -81,6 +84,9 @@
 #define UCR3_DCD       (1 << 9)
 #define UCR3_DSR       (1 << 10)
 
+#define XCAT2(a, b) a##b
+#define PCTL(x)     XCAT2(pctl_, x)
+
 
 /* clang-format off */
 enum { urxd = 0, utxd = 16, ucr1 = 32, ucr2, ucr3, ucr4, ufcr, usr1, usr2,
@@ -88,10 +94,10 @@ enum { urxd = 0, utxd = 16, ucr1 = 32, ucr2, ucr3, ucr4, ufcr, usr1, usr2,
 /* clang-format on */
 
 
-static uint32_t uart_addr[8] = { 0x02020000, 0x021E8000, 0x021EC000, 0x021F0000,
+static const uint32_t uart_addr[8] = { 0x02020000, 0x021E8000, 0x021EC000, 0x021F0000,
 	0x021F4000, 0x021FC000, 0x02018000, 0x02288000 };
 
-static uint32_t uart_pctl_clk[8] = { pctl_clk_uart1, pctl_clk_uart2, pctl_clk_uart3, pctl_clk_uart4,
+static const uint32_t uart_pctl_clk[8] = { pctl_clk_uart1, pctl_clk_uart2, pctl_clk_uart3, pctl_clk_uart4,
 	pctl_clk_uart5, pctl_clk_uart6, pctl_clk_uart7, pctl_clk_uart8 };
 
 typedef struct {
@@ -99,31 +105,69 @@ typedef struct {
 	char val;
 } uart_pctl_t;
 
-/* clang-format off */
-static uart_pctl_t uart_pctl_mux[8][4] = {
-	{ { pctl_mux_uart1_cts, 0 }, { pctl_mux_uart1_rts,  0 }, { pctl_mux_uart1_rx,  0 }, { pctl_mux_uart1_tx,  0 } },
-	{ { pctl_mux_uart2_cts, 0 }, { pctl_mux_uart2_rts,  0 }, { pctl_mux_uart2_rx,  0 }, { pctl_mux_uart2_tx,  0 } },
-	{ { pctl_mux_uart3_cts, 0 }, { pctl_mux_uart3_rts,  0 }, { pctl_mux_uart3_rx,  0 }, { pctl_mux_uart3_tx,  0 } },
-	{ { pctl_mux_lcd_hsync, 2 }, { pctl_mux_lcd_vsync,  2 }, { pctl_mux_uart4_rx,  0 }, { pctl_mux_uart4_tx,  0 } },
-	{ { pctl_mux_gpio1_09,  8 }, { pctl_mux_gpio1_08,   8 }, { pctl_mux_uart5_rx,  0 }, { pctl_mux_uart5_tx,  0 } },
-	{ { pctl_mux_enet1_tx1, 1 }, { pctl_mux_enet1_txen, 1 }, { pctl_mux_enet2_rx1, 1 }, { pctl_mux_enet2_rx0, 1 } },
-	{ { pctl_mux_lcd_d6,    1 }, { pctl_mux_lcd_d7,     1 }, { pctl_mux_lcd_d17,   1 }, { pctl_mux_lcd_d16,   1 } },
-	{ { pctl_mux_lcd_d4,    1 }, { pctl_mux_lcd_d5,     1 }, { pctl_mux_lcd_d21,   1 }, { pctl_mux_lcd_d20,   1 } },
+static const uart_pctl_t uart_pctl_mux[8][4] = {
+	{
+		{ PCTL(CONFIG_UART1_CTS_MUX_PAD), CONFIG_UART1_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART1_RTS_MUX_PAD), CONFIG_UART1_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART1_RX_MUX_PAD), CONFIG_UART1_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART1_TX_MUX_PAD), CONFIG_UART1_TX_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_UART2_CTS_MUX_PAD), CONFIG_UART2_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART2_RTS_MUX_PAD), CONFIG_UART2_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART2_RX_MUX_PAD), CONFIG_UART2_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART2_TX_MUX_PAD), CONFIG_UART2_TX_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_UART3_CTS_MUX_PAD), CONFIG_UART3_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART3_RTS_MUX_PAD), CONFIG_UART3_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART3_RX_MUX_PAD), CONFIG_UART3_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART3_TX_MUX_PAD), CONFIG_UART3_TX_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_UART4_CTS_MUX_PAD), CONFIG_UART4_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART4_RTS_MUX_PAD), CONFIG_UART4_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART4_RX_MUX_PAD), CONFIG_UART4_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART4_TX_MUX_PAD), CONFIG_UART4_TX_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_UART5_CTS_MUX_PAD), CONFIG_UART5_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART5_RTS_MUX_PAD), CONFIG_UART5_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART5_RX_MUX_PAD), CONFIG_UART5_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART5_TX_MUX_PAD), CONFIG_UART5_TX_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_UART6_CTS_MUX_PAD), CONFIG_UART6_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART6_RTS_MUX_PAD), CONFIG_UART6_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART6_RX_MUX_PAD), CONFIG_UART6_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART6_TX_MUX_PAD), CONFIG_UART6_TX_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_UART7_CTS_MUX_PAD), CONFIG_UART7_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART7_RTS_MUX_PAD), CONFIG_UART7_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART7_RX_MUX_PAD), CONFIG_UART7_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART7_TX_MUX_PAD), CONFIG_UART7_TX_MUX_VAL },
+	},
+	{
+		{ PCTL(CONFIG_UART8_CTS_MUX_PAD), CONFIG_UART8_CTS_MUX_VAL },
+		{ PCTL(CONFIG_UART8_RTS_MUX_PAD), CONFIG_UART8_RTS_MUX_VAL },
+		{ PCTL(CONFIG_UART8_RX_MUX_PAD), CONFIG_UART8_RX_MUX_VAL },
+		{ PCTL(CONFIG_UART8_TX_MUX_PAD), CONFIG_UART8_TX_MUX_VAL },
+	},
 };
-/* clang-format on */
 
-static uart_pctl_t uart_pctl_isel[8][2] = {
-	{ { pctl_isel_uart1_rts, 3 }, { pctl_isel_uart1_rx, 3 } },
-	{ { pctl_isel_uart2_rts, 1 }, { pctl_isel_uart2_rx, 1 } },
-	{ { pctl_isel_uart3_rts, 1 }, { pctl_isel_uart3_rx, 1 } },
-	{ { pctl_isel_uart4_rts, 3 }, { pctl_isel_uart4_rx, 1 } },
-	{ { pctl_isel_uart5_rts, 1 }, { pctl_isel_uart5_rx, 7 } },
-	{ { pctl_isel_uart6_rts, 3 }, { pctl_isel_uart6_rx, 2 } },
-	{ { pctl_isel_uart7_rts, 3 }, { pctl_isel_uart7_rx, 3 } },
-	{ { pctl_isel_uart8_rts, 3 }, { pctl_isel_uart8_rx, 3 } },
+static const uart_pctl_t uart_pctl_isel[8][2] = {
+	{ { pctl_isel_uart1_rts, CONFIG_UART1_RTS_ISEL }, { pctl_isel_uart1_rx, CONFIG_UART1_RX_ISEL } },
+	{ { pctl_isel_uart2_rts, CONFIG_UART2_RTS_ISEL }, { pctl_isel_uart2_rx, CONFIG_UART2_RX_ISEL } },
+	{ { pctl_isel_uart3_rts, CONFIG_UART3_RTS_ISEL }, { pctl_isel_uart3_rx, CONFIG_UART3_RX_ISEL } },
+	{ { pctl_isel_uart4_rts, CONFIG_UART4_RTS_ISEL }, { pctl_isel_uart4_rx, CONFIG_UART4_RX_ISEL } },
+	{ { pctl_isel_uart5_rts, CONFIG_UART5_RTS_ISEL }, { pctl_isel_uart5_rx, CONFIG_UART5_RX_ISEL } },
+	{ { pctl_isel_uart6_rts, CONFIG_UART6_RTS_ISEL }, { pctl_isel_uart6_rx, CONFIG_UART6_RX_ISEL } },
+	{ { pctl_isel_uart7_rts, CONFIG_UART7_RTS_ISEL }, { pctl_isel_uart7_rx, CONFIG_UART7_RX_ISEL } },
+	{ { pctl_isel_uart8_rts, CONFIG_UART8_RTS_ISEL }, { pctl_isel_uart8_rx, CONFIG_UART8_RX_ISEL } },
 };
 
-static unsigned uart_intr_number[8] = { 58, 59, 60, 61, 62, 49, 71, 72 };
+static const unsigned uart_intr_number[8] = { 58, 59, 60, 61, 62, 49, 71, 72 };
 
 typedef struct {
 	volatile uint32_t *base;
@@ -575,6 +619,7 @@ static void print_usage(const char *progname)
 	printf("\t-t - make it a default console device, might be empty (default yes)\n");
 	printf("\t-e - report UART errors (default no)\n");
 	printf("\t-s - use syslog for logs (default no)\n");
+	printf("\t-d - DTE mode, swap RX and TX signals (default no)\n");
 }
 
 
@@ -595,6 +640,7 @@ int main(int argc, char **argv)
 	int is_cooked = 1;
 	int use_rts_cts = 0;
 	int is_console = 0;
+	int dte_mode = 0; /* Default to DCE mode */
 
 	libtty_callbacks_t callbacks = {
 		.arg = &uart,
@@ -611,7 +657,7 @@ int main(int argc, char **argv)
 		uart.dev_no = 1;
 		is_console = 1;
 	}
-	else if ((argc >= 6) && (argc <= 8)) {
+	else if ((argc >= 6) && (argc <= 9)) {
 		is_cooked = atoi(argv[1]);
 		uart.dev_no = atoi(argv[2]);
 		baud = atoi(argv[3]);
@@ -628,6 +674,9 @@ int main(int argc, char **argv)
 			else if (strcmp(argv[num], "-s") == 0) {
 				uart.use_syslog = 1;
 			}
+			else if (strcmp(argv[num], "-d") == 0) {
+				dte_mode = 1;
+			}
 			else {
 				print_usage(argv[0]);
 				return 0;
@@ -705,8 +754,9 @@ int main(int argc, char **argv)
 
 	interrupt(uart_intr_number[uart.dev_no - 1], uart_intr, NULL, uart.cond, &uart.inth);
 
-	/* set TX & RX FIFO watermark, DCE mode */
-	*(uart.base + ufcr) = (0x04 << 10) | (0 << 6) | (0x1);
+	/* set TX & RX FIFO watermark, DCE/DTE mode as selected */
+	uint32_t dcedte = (dte_mode != 0) ? (1 << 6) : 0;
+	*(uart.base + ufcr) = (0x04 << 10) | dcedte | (0x1);
 
 	/* set Reference Frequency Divider */
 	*(uart.base + ufcr) &= ~(0b111 << 7);