[Model] Gemma 4 M1 12B

[FeathBow]

Description

Parent: #758. Crate: pegainfer-gemma4 · feature: gemma4.

M1 covers the whole 12B line: local sliding-window attention at head_dim 256 with full RoPE and global attention at head_dim 512 with proportional RoPE, the two KV groups with their different head counts and cache shapes, K and V projection sharing, the scaled embedding, four norm sites per decoder layer, the Q/K/V norm details, the tied LM head and the logit softcap, then paged prefill and decode, continuous batching, cancellation and release, sampling and logprobs, and the chat template. The architecture freeze, the target table and the correctness contract stay in the parent; this issue holds the 12B scope and its gates.

Proposed Plan

• Run the correctness set on each platform the parent commits this line to, rather than carrying one platform's results to another: tokenizer and chat-template identifier parity, the HF logits and intermediate probes across single token, short prefill, prefill plus decode and mixed batch, the sliding-window boundaries at 1023, 1024 and 1025 with multiple-window continuation, local and global alternation including the final-global-layer assertion, batch invariance, KV release and reuse, admission failure and post-failure recovery, and the declared long-context gate.
• Write the serving envelope for each committed platform and context and concurrency cell: weights, scales and metadata, allocator reserve, graph and GEMM workspaces, activations, both KV families, and peak observed device memory. Each committed platform is budgeted on its own; neither is inferred from the other.
• Run and retain a same-host comparison against a pinned vLLM version across the concurrency and QPS cells, recording completed and failed counts, output sanity, and every serve and bench flag on both sides. Every number carries the hardware it was taken on.
• Set regression thresholds against the retained snapshot per docs/conventions/bench-regression.md, so a later change that costs this line performance fails a gate instead of being noticed later.
• Publish the recipe and hardware-matrix entry, and make unsupported options fail explicitly rather than degrade silently.
• Close or re-scope the open KV cache contract sub-issue: what it describes is implemented and inherited by the MoE line, so it either becomes the written contract or it goes.

Acceptance Criteria

• A written 12B serving envelope with peak observed device memory for each committed platform and context/concurrency cell; a hardware claim that quotes weight bytes alone does not satisfy this.
• Zero failed requests and output sanity across the retained HTTP concurrency and QPS cells, with the pinned vLLM comparison alongside on the same host.
• A retained snapshot with thresholds, so a later change that regresses this line fails a gate rather than a memory.
• A recipe and hardware-matrix entry that a reader can follow without this issue open next to them.