Upgrade cortex-m-rt and PACs to ~2022

I noticed that our cortex-m-rt version was generating potentially
invalid code in the Reset function -- setting up and tearing down a
stack frame, before we've turned on RAM! This bug got fixed in the
upstream cortex-m-rt crate, but we haven't upgraded in ... quite a
while.

This upgrades to a compromise point -- 0.15 of the stm32 pacs. Upgrading
farther than that causes massive API incompatibilities, since it looks
like they've comprehensively changed the svd2rust generated code. Rather
than touch literally every driver in the system, I've settled on 0.15
and left 0.16 as a trap for the future.

As you can see, this still required a fair amount of churn, mostly due
to renamed enum variants.

Author: cbiffle

Cargo.lock

@@ -63,7 +63,7 @@ colored = { version = "2.0", default-features = false }
 convert_case = { version = "0.4", default-features = false }
 corncobs = { version = "0.1.1", default-features = false }
 cortex-m = { version = "0.7", default-features = false, features = ["inline-asm"]}
-cortex-m-rt = { version = "0.6.12", default-features = false }
+cortex-m-rt = { version = "0.7.5", default-features = false }
 cortex-m-semihosting = { version = "0.5.0", default-features = false }
 crc = { version = "3.0.0", default-features = false }
 critical-section = { version = "1.1.2" }
@@ -89,7 +89,7 @@ indexmap = { version = "1.4.0", default-features = false, features = ["serde-1"]
 indoc = { version = "2.0.3", default-features = false }
 itertools = { version = "0.10.5", default-features = false }
 leb128 = { version = "0.2.5", default-features = false }
-lpc55-pac = { version = "0.4", default-features = false }
+lpc55-pac = { version = "0.5", default-features = false }
 memchr = { version = "2.4", default-features = false }
 memoffset = { version = "0.6.5", default-features = false }
 minicbor = { version = "2.1.1", default-features = false }
@@ -127,10 +127,10 @@ ssh-key = { version = "0.6.6", default-features = false, features = ["std", "p25
 spin = { version = "0.9.4", default-features = false, features = ["mutex", "spin_mutex"]}
 ssmarshal = { version = "1.0.0", default-features = false }
 static_assertions = { version = "1", default-features = false }
-stm32f3 = { version = "0.13.0", default-features = false }
-stm32f4 = { version = "0.13.0", default-features = false }
-stm32h7 = { version = "0.14", default-features = false }
-stm32g0 = { version = "0.15.1", default-features = false }
+stm32f3 = { version = "0.15", default-features = false }
+stm32f4 = { version = "0.15", default-features = false }
+stm32h7 = { version = "0.15", default-features = false }
+stm32g0 = { version = "0.15", default-features = false }
 strsim = { version = "0.10.0", default-features = false }
 syn = { version = "2", default-features = false, features = ["derive", "parsing", "proc-macro", "extra-traits", "full", "printing"] }
 toml = { version = "0.9.6", default-features = false, features = ["parse", "display", "serde", "preserve_order"] }

Cargo.toml

@@ -1288,7 +1288,7 @@ input = {port = "E", pin = 5, af = 5}
 [config.spi.spi4.devices.rot]
 mux = "rot"
 cs = [{port = "E", pin = 4}]
-clock_divider = "DIV256"
+clock_divider = "Div256"
 
 # VLAN configuration
 [config.net.vlans.sidecar1]

app/gimlet/base.toml

@@ -137,8 +137,8 @@ fn system_init() {
             // the prescaler.
             divm: 1,
             // VCO must tolerate an 8MHz input range:
-            vcosel: device::rcc::pllcfgr::PLL1VCOSEL_A::WIDEVCO,
-            pllrange: device::rcc::pllcfgr::PLL1RGE_A::RANGE8,
+            vcosel: device::rcc::pllcfgr::PLL1VCOSEL_A::WideVco,
+            pllrange: device::rcc::pllcfgr::PLL1RGE_A::Range8,
             // DIVN governs the multiplication of the VCO input frequency to produce
             // the intermediate frequency. We want an IF of 800MHz, or a
             // multiplication of 100x.
@@ -148,23 +148,23 @@ fn system_init() {
             divn: 100 - 1,
             // P is the divisor from the VCO IF to the system frequency. We want
             // 400MHz, so:
-            divp: device::rcc::pll1divr::DIVP1_A::DIV2,
+            divp: device::rcc::pll1divr::DIVP1_A::Div2,
             // Q produces kernel clocks; we set it to 200MHz:
             divq: 4 - 1,
             // R is mostly used by the trace unit and we leave it fast:
             divr: 2 - 1,
 
             // We run the CPU at the full core rate of 400MHz:
-            cpu_div: device::rcc::d1cfgr::D1CPRE_A::DIV1,
+            cpu_div: device::rcc::d1cfgr::D1CPRE_A::Div1,
             // We down-shift the AHB by a factor of 2, to 200MHz, to meet its
             // constraints:
-            ahb_div: device::rcc::d1cfgr::HPRE_A::DIV2,
+            ahb_div: device::rcc::d1cfgr::HPRE_A::Div2,
             // We configure all APB for 100MHz. These are relative to the AHB
             // frequency.
-            apb1_div: device::rcc::d2cfgr::D2PPRE1_A::DIV2,
-            apb2_div: device::rcc::d2cfgr::D2PPRE2_A::DIV2,
-            apb3_div: device::rcc::d1cfgr::D1PPRE_A::DIV2,
-            apb4_div: device::rcc::d3cfgr::D3PPRE_A::DIV2,
+            apb1_div: device::rcc::d2cfgr::D2PPRE1_A::Div2,
+            apb2_div: device::rcc::d2cfgr::D2PPRE2_A::Div2,
+            apb3_div: device::rcc::d1cfgr::D1PPRE_A::Div2,
+            apb4_div: device::rcc::d3cfgr::D3PPRE_A::Div2,
 
             // Flash runs at 200MHz: 2WS, 2 programming cycles. See reference manual
             // Table 13.

app/gimlet/src/main.rs

@@ -85,23 +85,24 @@ pub struct DeviceDescriptorConfig {
     pub cs: Vec<GpioPinConfig>,
 }
 
+// N.B. the names in this enum _must_ match those used in the PAC!
 #[derive(Copy, Clone, Debug, Deserialize)]
 pub enum ClockDivider {
-    DIV2,
-    DIV4,
-    DIV8,
-    DIV16,
-    DIV32,
-    DIV64,
-    DIV128,
-    DIV256,
+    Div2,
+    Div4,
+    Div8,
+    Div16,
+    Div32,
+    Div64,
+    Div128,
+    Div256,
 }
 
 impl Default for ClockDivider {
     fn default() -> ClockDivider {
         // When this config mechanism was introduced, we had everything set at
-        // DIV64 for a ~1.5625 MHz SCK rate.
-        Self::DIV64
+        // Div64 for a ~1.5625 MHz SCK rate.
+        Self::Div64
     }
 }
 

build/spi/src/lib.rs

@@ -318,14 +318,14 @@ impl Hash {
         // The hash is read out as words into little endian ARM world.
         // Since the bit order needs to be maintained, read as B.E.
         let result = [
-            u32::from_be(self.reg.hash_hr0.read().bits()),
-            u32::from_be(self.reg.hash_hr1.read().bits()),
-            u32::from_be(self.reg.hash_hr2.read().bits()),
-            u32::from_be(self.reg.hash_hr3.read().bits()),
-            u32::from_be(self.reg.hash_hr4.read().bits()),
-            u32::from_be(self.reg.hash_hr5.read().bits()),
-            u32::from_be(self.reg.hash_hr6.read().bits()),
-            u32::from_be(self.reg.hash_hr7.read().bits()),
+            u32::from_be(self.reg.hash_hr[0].read().bits()),
+            u32::from_be(self.reg.hash_hr[1].read().bits()),
+            u32::from_be(self.reg.hash_hr[2].read().bits()),
+            u32::from_be(self.reg.hash_hr[3].read().bits()),
+            u32::from_be(self.reg.hash_hr[4].read().bits()),
+            u32::from_be(self.reg.hash_hr[5].read().bits()),
+            u32::from_be(self.reg.hash_hr[6].read().bits()),
+            u32::from_be(self.reg.hash_hr[7].read().bits()),
         ];
         out.clone_from_slice(result.as_bytes());
         Ok(())

drv/stm32h7-hash/src/lib.rs

@@ -136,13 +136,13 @@ impl SpiServerCore {
 
         // This should correspond to '0' in the standard SPI parlance
         spi.initialize(
-            device::spi1::cfg1::MBR_A::DIV64,
+            device::spi1::cfg1::MBR_A::Div64,
             8,
-            device::spi1::cfg2::COMM_A::FULLDUPLEX,
-            device::spi1::cfg2::LSBFRST_A::MSBFIRST,
-            device::spi1::cfg2::CPHA_A::FIRSTEDGE,
-            device::spi1::cfg2::CPOL_A::IDLELOW,
-            device::spi1::cfg2::SSOM_A::ASSERTED,
+            device::spi1::cfg2::COMM_A::FullDuplex,
+            device::spi1::cfg2::LSBFRST_A::Msbfirst,
+            device::spi1::cfg2::CPHA_A::FirstEdge,
+            device::spi1::cfg2::CPOL_A::IdleLow,
+            device::spi1::cfg2::SSOM_A::Asserted,
         );
 
         // Configure all devices' CS pins to be deasserted (set).

drv/stm32h7-spi-server-core/src/lib.rs

@@ -24,8 +24,8 @@ const CLOCK_CONFIG: ClockConfig = ClockConfig {
     // the prescaler.
     divm: 1,
     // VCO must tolerate an 8MHz input range:
-    vcosel: device::rcc::pllcfgr::PLL1VCOSEL_A::WIDEVCO,
-    pllrange: device::rcc::pllcfgr::PLL1RGE_A::RANGE8,
+    vcosel: device::rcc::pllcfgr::PLL1VCOSEL_A::WideVco,
+    pllrange: device::rcc::pllcfgr::PLL1RGE_A::Range8,
     // DIVN governs the multiplication of the VCO input frequency to produce
     // the intermediate frequency. We want an IF of 800MHz, or a
     // multiplication of 100x.
@@ -35,23 +35,23 @@ const CLOCK_CONFIG: ClockConfig = ClockConfig {
     divn: 100 - 1,
     // P is the divisor from the VCO IF to the system frequency. We want
     // 400MHz, so:
-    divp: device::rcc::pll1divr::DIVP1_A::DIV2,
+    divp: device::rcc::pll1divr::DIVP1_A::Div2,
     // Q produces kernel clocks; we set it to 200MHz:
     divq: 4 - 1,
     // R is mostly used by the trace unit and we leave it fast:
     divr: 2 - 1,
 
     // We run the CPU at the full core rate of 400MHz:
-    cpu_div: device::rcc::d1cfgr::D1CPRE_A::DIV1,
+    cpu_div: device::rcc::d1cfgr::D1CPRE_A::Div1,
     // We down-shift the AHB by a factor of 2, to 200MHz, to meet its
     // constraints:
-    ahb_div: device::rcc::d1cfgr::HPRE_A::DIV2,
+    ahb_div: device::rcc::d1cfgr::HPRE_A::Div2,
     // We configure all APB for 100MHz. These are relative to the AHB
     // frequency.
-    apb1_div: device::rcc::d2cfgr::D2PPRE1_A::DIV2,
-    apb2_div: device::rcc::d2cfgr::D2PPRE2_A::DIV2,
-    apb3_div: device::rcc::d1cfgr::D1PPRE_A::DIV2,
-    apb4_div: device::rcc::d3cfgr::D3PPRE_A::DIV2,
+    apb1_div: device::rcc::d2cfgr::D2PPRE1_A::Div2,
+    apb2_div: device::rcc::d2cfgr::D2PPRE2_A::Div2,
+    apb3_div: device::rcc::d1cfgr::D1PPRE_A::Div2,
+    apb4_div: device::rcc::d3cfgr::D3PPRE_A::Div2,
 
     // Flash runs at 200MHz: 2WS, 2 programming cycles. See reference manual
     // Table 13.