SystemRDL

All

17 repositories

systemrdl-compiler
Public
SystemRDL 2.0 language compiler front-end
asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation
C++
•
MIT License
•74•255•11•1•Updated Jul 29, 2025Jul 29, 2025
PeakRDL-Markdown
Public
Markdown exporter for the PeakRDL toolchain
Python
•
GNU General Public License v3.0
•11•7•6•2•Updated Jul 28, 2025Jul 28, 2025
PeakRDL-regblock
Public
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
asic fpga csr systemverilog registers systemverilog-hdl systemrdl systemrdl-compiler
Python
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GNU General Public License v3.0
•48•70•15•3•Updated Jul 16, 2025Jul 16, 2025
PeakRDL-ipxact
Public
Import and export IP-XACT XML register models
asic fpga eda ip-xact register-descriptions systemrdl-compiler ipxact
Python
•
GNU Lesser General Public License v3.0
•17•35•3•3•Updated Jun 21, 2025Jun 21, 2025
PeakRDL-html
Public
Generate address space documentation HTML from compiled SystemRDL input
documentation asic fpga eda documentation-generator registers design-automation html systemrdl-compiler
JavaScript
•
GNU Lesser General Public License v3.0
•20•55•12•2•Updated Jun 19, 2025Jun 19, 2025
PeakRDL-cheader
Public
Python
•
GNU Lesser General Public License v3.0
•15•11•7•2•Updated Jun 19, 2025Jun 19, 2025
pygments-systemrdl
Public
SystemRDL lexer for Pygments syntax highlighting
syntax-highlighting documentation systemrdl pygments
Python
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GNU Lesser General Public License v3.0
•3•1•0•0•Updated Jun 19, 2025Jun 19, 2025
sphinx-peakrdl
Public
Python
•
GNU Lesser General Public License v3.0
•0•0•4•0•Updated Jun 19, 2025Jun 19, 2025
PeakRDL
Public
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi
Python
•
GNU Lesser General Public License v3.0
•29•141•7•0•Updated May 23, 2025May 23, 2025
PeakRDL-systemrdl
Public
Convert a compiled register model into SystemRDL code.
Python
•
GNU Lesser General Public License v3.0
•5•2•3•0•Updated May 23, 2025May 23, 2025
.github
Public
4•0•0•0•Updated May 17, 2025May 17, 2025
PeakRDL-regblock-vhdl
Public
Generate VHDL RTL that implements a register block from compiled SystemRDL input.
Python
•
GNU General Public License v3.0
•48•5•0•0•Updated Apr 30, 2025Apr 30, 2025
PeakRDL-uvm
Public
Generate UVM register model from compiled SystemRDL input
asic fpga eda uvm registers uvm-ral-model uvm-register-model
Python
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GNU General Public License v3.0
•33•57•13•4•Updated Sep 3, 2024Sep 3, 2024
tree-sitter-systemrdl
Public
SystemRDL grammar for tree-sitter
JavaScript
•
MIT License
•5•8•1•3•Updated May 12, 2024May 12, 2024
vscode-systemrdl
Public
SystemRDL language support for VS Code
systemrdl vscode-language
MIT License
•3•7•0•0•Updated Aug 25, 2023Aug 25, 2023
PeakRDL-svd
Public
Import and export CMSIS-SVD register models
4•1•1•0•Updated Jun 1, 2023Jun 1, 2023
atom-language-systemrdl
Public
SystemRDL language support for Atom
JavaScript
•
MIT License
•1•1•0•0•Updated Jul 25, 2019Jul 25, 2019