diff --git a/.gitignore b/.gitignore
index 823a81765..d63a128c6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -71,3 +71,13 @@ Temporary Items
!/.gitignore
!/README.md
+
+# Claude Code
+.claude/
+CLAUDE.md
+
+# Graphify output
+graphify-out/
+
+# Personal Files
+personal_files/
\ No newline at end of file
diff --git a/.graphifyignore b/.graphifyignore
new file mode 100644
index 000000000..8d4070920
--- /dev/null
+++ b/.graphifyignore
@@ -0,0 +1,10 @@
+# Vivado build artifacts - regenerated on every synthesis run
+**/top.cache/
+**/top.gen/
+**/top.runs/
+**/top.sim/
+**/top.hw/
+**/top.ip_user_files/
+**/.Xil/
+**/*.jou
+**/*.log
diff --git a/firmware/ip/adaptive_sweep/component.xml b/firmware/ip/adaptive_sweep/component.xml
new file mode 100644
index 000000000..22de082ca
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/component.xml
@@ -0,0 +1,752 @@
+
+
+ emrhnozdemir
+ QICK
+ adaptive_sweep
+ 1.0
+
+
+ rst_n
+
+
+
+
+
+
+ RST
+
+
+ rst_n
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+
+
+ clk
+
+
+
+
+
+
+ CLK
+
+
+ clk
+
+
+
+
+
+ qick_peripheral
+
+
+
+
+
+
+ b_dt
+
+
+ qtag_dt2_i
+
+
+
+
+ c_dt
+
+
+ qtag_dt3_i
+
+
+
+
+ a_dt
+
+
+ qtag_dt1_i
+
+
+
+
+ d_dt
+
+
+ qtag_dt4_i
+
+
+
+
+ rdy
+
+
+ qtag_rdy_o
+
+
+
+
+ Enable
+
+
+ qtag_en_i
+
+
+
+
+ dt_in_2
+
+
+ qtag_dt2_o
+
+
+
+
+ Operation
+
+
+ qtag_op_i
+
+
+
+
+ dt_in_1
+
+
+ qtag_dt1_o
+
+
+
+
+ dt_valid
+
+
+ qtag_vld_o
+
+
+
+
+
+ NUM_READ_OUTSTANDING
+
+
+
+ NUM_WRITE_OUTSTANDING
+
+
+
+
+
+ s_ro_axis_aresetn
+
+
+
+
+
+
+ RST
+
+
+ s_ro_axis_aresetn
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+
+
+ s_ro_axis_aclk
+
+
+
+
+
+
+ CLK
+
+
+ s_ro_axis_aclk
+
+
+
+
+
+ ASSOCIATED_RESET
+ s_ro_axis_aresetn
+
+
+
+
+
+
+
+ xilinx_anylanguagesynthesis
+ Synthesis
+ :vivado.xilinx.com:synthesis
+ Verilog
+ adaptive_sweep
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+
+
+ viewChecksum
+ 7ed7359d
+
+
+
+
+ xilinx_anylanguagebehavioralsimulation
+ Simulation
+ :vivado.xilinx.com:simulation
+ Verilog
+ adaptive_sweep
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+
+
+ viewChecksum
+ 7ed7359d
+
+
+
+
+ xilinx_xpgui
+ UI Layout
+ :vivado.xilinx.com:xgui.ui
+
+ xilinx_xpgui_view_fileset
+
+
+
+ viewChecksum
+ 2db471fc
+
+
+
+
+ xilinx_testbench
+ Test Bench
+ :vivado.xilinx.com:simulation.testbench
+ tb_polyak_avg
+
+ xilinx_testbench_view_fileset
+
+
+
+ viewChecksum
+ c81c3e81
+
+
+
+
+
+
+ clk
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ rst_n
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_en_i
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_op_i
+
+ in
+
+ 4
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt1_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt2_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt3_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt4_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_rdy_o
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt1_o
+
+ out
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt2_o
+
+ out
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_vld_o
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_ro_axis_aclk
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_ro_axis_aresetn
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_ro_axis_tdata
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_ro_axis_tvalid
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_ro_axis_tready
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ trigger_i
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+
+
+ LUT_DEPTH
+ Lut Depth
+ 256
+
+
+ LUT_AW
+ Lut Aw
+ 8
+
+
+ X_WIDTH
+ X Width
+ 32
+
+
+ IQ_WIDTH
+ Iq Width
+ 16
+
+
+ SUM_WIDTH
+ Sum Width
+ 48
+
+
+ POW_WIDTH
+ Pow Width
+ 32
+
+
+ COUNT_WIDTH
+ Count Width
+ 16
+
+
+ RO_FIFO_DEPTH_LOG2
+ Ro Fifo Depth Log2
+ 6
+
+
+ KW_TOL
+ Kw Tol
+ 0x000007D0
+
+
+
+
+
+ choice_list_74b5137e
+ ACTIVE_HIGH
+ ACTIVE_LOW
+
+
+ choice_list_9d8b0d81
+ ACTIVE_HIGH
+ ACTIVE_LOW
+
+
+
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+ src/adaptive_sweep_control.v
+ verilogSource
+
+
+ src/bisect_control.v
+ verilogSource
+
+
+ src/iq_power.v
+ verilogSource
+
+
+ src/kw_steps.v
+ verilogSource
+
+
+ src/polyak_averager.v
+ verilogSource
+
+
+ src/readout_capture.v
+ verilogSource
+
+
+ src/adaptive_sweep.v
+ verilogSource
+ CHECKSUM_019d365f
+
+
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+ src/adaptive_sweep_control.v
+ verilogSource
+
+
+ src/bisect_control.v
+ verilogSource
+
+
+ src/iq_power.v
+ verilogSource
+
+
+ src/kw_steps.v
+ verilogSource
+
+
+ src/polyak_averager.v
+ verilogSource
+
+
+ src/readout_capture.v
+ verilogSource
+
+
+ src/adaptive_sweep.v
+ verilogSource
+
+
+
+ xilinx_xpgui_view_fileset
+
+ xgui/adaptive_sweep_v1_0.tcl
+ tclSource
+ CHECKSUM_2db471fc
+ XGUI_VERSION_2
+
+
+
+ xilinx_testbench_view_fileset
+
+ src/tb/tb_polyak_avg.sv
+ systemVerilogSource
+ USED_IN_implementation
+ USED_IN_simulation
+ USED_IN_synthesis
+
+
+
+ adaptive_sweep_v1_0
+
+
+ Component_Name
+ adaptive_sweep_v1_0
+
+
+ LUT_DEPTH
+ Lut Depth
+ 256
+
+
+ LUT_AW
+ Lut Aw
+ 8
+
+
+ X_WIDTH
+ X Width
+ 32
+
+
+ IQ_WIDTH
+ Iq Width
+ 16
+
+
+ SUM_WIDTH
+ Sum Width
+ 48
+
+
+ POW_WIDTH
+ Pow Width
+ 32
+
+
+ COUNT_WIDTH
+ Count Width
+ 16
+
+
+ RO_FIFO_DEPTH_LOG2
+ Ro Fifo Depth Log2
+ 6
+
+
+ KW_TOL
+ Kw Tol
+ 0x000007D0
+
+
+
+
+
+ artix7
+ artix7l
+ aartix7
+ qartix7
+ zynq
+ qzynq
+ azynq
+ zynquplus
+
+
+ /UserIP
+
+ adaptive_sweep_v1_0
+ package_project
+
+ XPM_FIFO
+
+ 9
+
+ xilinx.com:user:adaptive_sweep:1.0
+
+ 2026-05-06T14:33:10Z
+
+
+ 2023.1
+
+
+
+
+
+
+
+
diff --git a/firmware/ip/adaptive_sweep/src/adaptive_sweep.v b/firmware/ip/adaptive_sweep/src/adaptive_sweep.v
new file mode 100644
index 000000000..28b9d290e
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/adaptive_sweep.v
@@ -0,0 +1,342 @@
+`timescale 1ns / 1ps
+//
+// adaptive_sweep.v -- top wrapper for the adaptive_sweep IP.
+//
+// Replaces the placeholder 4-entry frequency LUT with the real RTL
+// implementation of Section 9 of resonator_sweep.ipynb (KW + Polyak
+// averaging + 3 dB bisection).
+//
+// Hierarchy:
+// adaptive_sweep
+// adaptive_sweep_control (QP2 opcode FSM, c_clk)
+// readout_capture (ro_clk -> c_clk CDC FIFO + trigger)
+// polyak_averager (I) (chunked Polyak average of I)
+// polyak_averager (Q) (chunked Polyak average of Q)
+// iq_power (I_avg^2 + Q_avg^2)
+// kw_steps (LUT-driven KW step + clamp)
+// bisect_control (3 dB edge bisection FSM)
+//
+// Ports:
+// QP2 slave : qtag_* (unchanged from placeholder)
+// AXIS slave : s_ro_axis_* (snoop on m1_axis of axis_dyn_readout_v1)
+// trigger_i : 1-bit, ro_clk async
+//
+
+module adaptive_sweep #(
+ parameter integer LUT_DEPTH = 256,
+ parameter integer LUT_AW = 8,
+ parameter integer X_WIDTH = 32,
+ parameter integer IQ_WIDTH = 16,
+ parameter integer SUM_WIDTH = 48,
+ parameter integer POW_WIDTH = 32,
+ parameter integer COUNT_WIDTH = 16,
+ parameter integer RO_FIFO_DEPTH_LOG2 = 6,
+ parameter [X_WIDTH-1:0] KW_TOL = 32'h0000_07D0
+)(
+ input wire clk, // c_clk
+ input wire rst_n,
+
+ // ---- QP2 (tProc-side) ----
+ input wire qtag_en_i,
+ input wire [4:0] qtag_op_i,
+ input wire [31:0] qtag_dt1_i,
+ input wire [31:0] qtag_dt2_i,
+ input wire [31:0] qtag_dt3_i,
+ input wire [31:0] qtag_dt4_i,
+ output wire qtag_rdy_o,
+ output wire [31:0] qtag_dt1_o,
+ output wire [31:0] qtag_dt2_o,
+ output wire qtag_vld_o,
+
+ // ---- Readout snoop (m1_axis of axis_dyn_readout_v1) ----
+ input wire s_ro_axis_aclk, // ro_clk
+ input wire s_ro_axis_aresetn,
+ input wire [2*IQ_WIDTH-1:0] s_ro_axis_tdata, // {Q[15:0],I[15:0]}
+ input wire s_ro_axis_tvalid,
+ output wire s_ro_axis_tready,
+
+ // ---- External trigger (ro_clk async, sourced from tProc trig_0_o) ----
+ input wire trigger_i
+);
+
+ // -------------------------------------------------------------
+ // Inter-module wires
+ // -------------------------------------------------------------
+ // adaptive_sweep_control <-> polyak_averagers
+ wire pa_soft_reset;
+ wire [31:0] pa_reciprocal;
+ wire [3:0] pa_chunk_log2;
+ wire signed [X_WIDTH-1:0] pa_i_xbar;
+ wire signed [X_WIDTH-1:0] pa_q_xbar;
+
+ // adaptive_sweep_control <-> iq_power
+ wire pwr_compute_pulse;
+ wire signed [IQ_WIDTH-1:0] pwr_i_in;
+ wire signed [IQ_WIDTH-1:0] pwr_q_in;
+ wire [POW_WIDTH-1:0] pwr_value;
+ wire pwr_valid;
+
+ // adaptive_sweep_control <-> kw_steps
+ wire kw_lut_we;
+ wire [LUT_AW-1:0] kw_lut_addr;
+ wire signed [X_WIDTH-1:0] kw_lut_din;
+ wire kw_step_trigger;
+ wire signed [X_WIDTH-1:0] kw_dp_signed;
+ wire [LUT_AW-1:0] kw_k_idx;
+ wire signed [X_WIDTH-1:0] kw_x_in;
+ wire signed [X_WIDTH-1:0] kw_x_min;
+ wire signed [X_WIDTH-1:0] kw_x_max;
+ wire signed [X_WIDTH-1:0] kw_x_out;
+ wire kw_conv_flag;
+ wire kw_valid;
+
+ // adaptive_sweep_control <-> bisect_control
+ wire bs_init;
+ wire [X_WIDTH-1:0] bs_lo_init;
+ wire [X_WIDTH-1:0] bs_hi_init;
+ wire bs_side_left;
+ wire bs_polarity_peak;
+ wire [X_WIDTH-1:0] bs_tol_in;
+ wire bs_step;
+ wire [X_WIDTH-1:0] bs_pow_mid;
+ wire [X_WIDTH-1:0] bs_pow_thr;
+ wire [X_WIDTH-1:0] bs_mid_next;
+ wire [X_WIDTH-1:0] bs_lo_o;
+ wire [X_WIDTH-1:0] bs_hi_o;
+ wire bs_converged;
+ wire bs_valid;
+
+ // adaptive_sweep_control <-> readout_capture
+ wire rc_arm_pulse;
+ wire [COUNT_WIDTH-1:0] rc_n_samples;
+ wire rc_capture_done;
+ wire [COUNT_WIDTH-1:0] rc_samples_remaining;
+ wire signed [IQ_WIDTH-1:0] rc_i_out;
+ wire signed [IQ_WIDTH-1:0] rc_q_out;
+ wire rc_iq_valid;
+ wire rc_iq_ready;
+
+ // x state visibility (currently unused outside ctrl, but routed for future)
+ wire signed [X_WIDTH-1:0] x_current;
+ wire signed [X_WIDTH-1:0] x_min;
+ wire signed [X_WIDTH-1:0] x_max;
+ wire [LUT_AW-1:0] iter_k;
+
+ // The polyak averagers always consume samples as soon as readout_capture
+ // presents them. iq_ready is therefore tied high.
+ assign rc_iq_ready = 1'b1;
+
+ // -------------------------------------------------------------
+ // adaptive_sweep_control
+ // -------------------------------------------------------------
+ adaptive_sweep_control #(
+ .X_WIDTH (X_WIDTH),
+ .IQ_WIDTH (IQ_WIDTH),
+ .POW_WIDTH (POW_WIDTH),
+ .COUNT_WIDTH(COUNT_WIDTH),
+ .LUT_AW (LUT_AW)
+ ) u_ctrl (
+ .clk (clk),
+ .rst_n (rst_n),
+
+ .qtag_en_i (qtag_en_i),
+ .qtag_op_i (qtag_op_i),
+ .qtag_dt1_i (qtag_dt1_i),
+ .qtag_dt2_i (qtag_dt2_i),
+ .qtag_dt3_i (qtag_dt3_i),
+ .qtag_dt4_i (qtag_dt4_i),
+ .qtag_rdy_o (qtag_rdy_o),
+ .qtag_dt1_o (qtag_dt1_o),
+ .qtag_dt2_o (qtag_dt2_o),
+ .qtag_vld_o (qtag_vld_o),
+
+ .pa_soft_reset (pa_soft_reset),
+ .pa_reciprocal (pa_reciprocal),
+ .pa_chunk_log2 (pa_chunk_log2),
+ .pa_i_xbar (pa_i_xbar),
+ .pa_q_xbar (pa_q_xbar),
+
+ .pwr_compute_pulse (pwr_compute_pulse),
+ .pwr_i_in (pwr_i_in),
+ .pwr_q_in (pwr_q_in),
+ .pwr_value (pwr_value),
+ .pwr_valid (pwr_valid),
+
+ .kw_lut_we (kw_lut_we),
+ .kw_lut_addr (kw_lut_addr),
+ .kw_lut_din (kw_lut_din),
+ .kw_step_trigger (kw_step_trigger),
+ .kw_dp_signed (kw_dp_signed),
+ .kw_k_idx (kw_k_idx),
+ .kw_x_in (kw_x_in),
+ .kw_x_min (kw_x_min),
+ .kw_x_max (kw_x_max),
+ .kw_x_out (kw_x_out),
+ .kw_conv_flag (kw_conv_flag),
+ .kw_valid (kw_valid),
+
+ .bs_init (bs_init),
+ .bs_lo_init (bs_lo_init),
+ .bs_hi_init (bs_hi_init),
+ .bs_side_left (bs_side_left),
+ .bs_polarity_peak (bs_polarity_peak),
+ .bs_tol_in (bs_tol_in),
+ .bs_step (bs_step),
+ .bs_pow_mid (bs_pow_mid),
+ .bs_pow_thr (bs_pow_thr),
+ .bs_mid_next (bs_mid_next),
+ .bs_lo_o (bs_lo_o),
+ .bs_hi_o (bs_hi_o),
+ .bs_converged (bs_converged),
+ .bs_valid (bs_valid),
+
+ .rc_arm_pulse (rc_arm_pulse),
+ .rc_n_samples (rc_n_samples),
+ .rc_capture_done (rc_capture_done),
+ .rc_samples_remaining (rc_samples_remaining),
+
+ .x_current_o (x_current),
+ .x_min_o (x_min),
+ .x_max_o (x_max),
+ .iter_k_o (iter_k)
+ );
+
+ // -------------------------------------------------------------
+ // readout_capture (ro_clk -> c_clk CDC, trigger gate)
+ // -------------------------------------------------------------
+ readout_capture #(
+ .IQ_WIDTH (IQ_WIDTH),
+ .FIFO_DEPTH_LOG2(RO_FIFO_DEPTH_LOG2),
+ .COUNT_WIDTH (COUNT_WIDTH)
+ ) u_rc (
+ .clk (clk),
+ .rst_n (rst_n),
+ .arm_pulse (rc_arm_pulse),
+ .n_samples (rc_n_samples),
+ .capture_done_o (rc_capture_done),
+ .i_out (rc_i_out),
+ .q_out (rc_q_out),
+ .iq_valid (rc_iq_valid),
+ .iq_ready (rc_iq_ready),
+ .samples_remaining (rc_samples_remaining),
+
+ .s_ro_axis_aclk (s_ro_axis_aclk),
+ .s_ro_axis_aresetn (s_ro_axis_aresetn),
+ .s_ro_axis_tdata (s_ro_axis_tdata),
+ .s_ro_axis_tvalid (s_ro_axis_tvalid),
+ .s_ro_axis_tready (s_ro_axis_tready),
+ .trigger_i (trigger_i)
+ );
+
+ // -------------------------------------------------------------
+ // polyak_averager (I)
+ // -------------------------------------------------------------
+ polyak_averager #(
+ .SAMPLE_WIDTH(IQ_WIDTH),
+ .SUM_WIDTH (SUM_WIDTH),
+ .AVG_WIDTH (X_WIDTH),
+ .RECIP_WIDTH (32),
+ .COUNT_WIDTH (COUNT_WIDTH)
+ ) u_pa_i (
+ .clk (clk),
+ .rst_n (rst_n),
+ .sample_in (rc_i_out),
+ .sample_valid (rc_iq_valid),
+ .reciprocal_in (pa_reciprocal),
+ .chunk_size_log2 (pa_chunk_log2),
+ .soft_reset (pa_soft_reset),
+ .xbar_o (pa_i_xbar),
+ .xbar_delta_o (),
+ .count_o (),
+ .valid_o ()
+ );
+
+ // -------------------------------------------------------------
+ // polyak_averager (Q)
+ // -------------------------------------------------------------
+ polyak_averager #(
+ .SAMPLE_WIDTH(IQ_WIDTH),
+ .SUM_WIDTH (SUM_WIDTH),
+ .AVG_WIDTH (X_WIDTH),
+ .RECIP_WIDTH (32),
+ .COUNT_WIDTH (COUNT_WIDTH)
+ ) u_pa_q (
+ .clk (clk),
+ .rst_n (rst_n),
+ .sample_in (rc_q_out),
+ .sample_valid (rc_iq_valid),
+ .reciprocal_in (pa_reciprocal),
+ .chunk_size_log2 (pa_chunk_log2),
+ .soft_reset (pa_soft_reset),
+ .xbar_o (pa_q_xbar),
+ .xbar_delta_o (),
+ .count_o (),
+ .valid_o ()
+ );
+
+ // -------------------------------------------------------------
+ // iq_power : I_avg^2 + Q_avg^2 (one-shot, fired by control)
+ // -------------------------------------------------------------
+ iq_power #(
+ .IQ_WIDTH (IQ_WIDTH),
+ .POW_WIDTH(POW_WIDTH)
+ ) u_iqp (
+ .clk (clk),
+ .rst_n (rst_n),
+ .i_in (pwr_i_in),
+ .q_in (pwr_q_in),
+ .valid_in(pwr_compute_pulse),
+ .power_o (pwr_value),
+ .valid_o (pwr_valid)
+ );
+
+ // -------------------------------------------------------------
+ // kw_steps : LUT-driven KW step + clamp
+ // -------------------------------------------------------------
+ kw_steps #(
+ .X_WIDTH (X_WIDTH),
+ .LUT_DEPTH(LUT_DEPTH),
+ .LUT_AW (LUT_AW),
+ .KW_TOL (KW_TOL)
+ ) u_kw (
+ .clk (clk),
+ .rst_n (rst_n),
+ .lut_we (kw_lut_we),
+ .lut_addr (kw_lut_addr),
+ .lut_din (kw_lut_din),
+ .step_trigger(kw_step_trigger),
+ .dp_signed (kw_dp_signed),
+ .k_idx (kw_k_idx),
+ .x_in (kw_x_in),
+ .x_min (kw_x_min),
+ .x_max (kw_x_max),
+ .x_out (kw_x_out),
+ .conv_flag (kw_conv_flag),
+ .valid_o (kw_valid)
+ );
+
+ // -------------------------------------------------------------
+ // bisect_control : 3 dB edge bisection
+ // -------------------------------------------------------------
+ bisect_control #(
+ .X_WIDTH(X_WIDTH)
+ ) u_bs (
+ .clk (clk),
+ .rst_n (rst_n),
+ .init (bs_init),
+ .lo_init (bs_lo_init),
+ .hi_init (bs_hi_init),
+ .side_left (bs_side_left),
+ .polarity_peak(bs_polarity_peak),
+ .tol_in (bs_tol_in),
+ .step (bs_step),
+ .pow_mid (bs_pow_mid),
+ .pow_thr (bs_pow_thr),
+ .mid_next (bs_mid_next),
+ .lo_o (bs_lo_o),
+ .hi_o (bs_hi_o),
+ .converged_o (bs_converged),
+ .valid_o (bs_valid)
+ );
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/adaptive_sweep_control.v b/firmware/ip/adaptive_sweep/src/adaptive_sweep_control.v
new file mode 100644
index 000000000..1a58df5e8
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/adaptive_sweep_control.v
@@ -0,0 +1,409 @@
+`timescale 1ns / 1ps
+//
+// adaptive_sweep_control.v
+//
+// QICK Custom-Peripheral (QP2 / qtag_*) opcode FSM. Translates 5-bit
+// opcodes from tProc into control / configuration signals for the
+// adaptive_sweep sub-modules and returns one or two 32-bit result words.
+//
+// The handshake follows the existing custom-peripheral protocol used by
+// adaptive_sweep.v's placeholder implementation:
+// - tProc asserts qtag_en_i and presents qtag_op_i + qtag_dt{1..4}_i
+// - We detect the rising edge of qtag_en_i (en_rise) and start the op
+// - qtag_rdy_o is driven low while busy
+// - qtag_vld_o pulses high for one cycle when the result is on
+// qtag_dt1_o / qtag_dt2_o.
+//
+// Opcode map (5 bits):
+// 0x00 NOP ---
+// 0x01 RESET_ALL soft-reset polyak averagers + bisect, clear x_state
+// 0x02 SET_NAVG dt1=n_avg (info), dt2=reciprocal=ceil(2^32/n_avg)
+// 0x03 SET_CHUNK_LOG2 dt1[3:0]=chunk_size_log2 (1..8)
+// 0x04 SET_X dt1=x_fixed (current x state)
+// 0x05 SET_BOUNDS dt1=x_min, dt2=x_max
+// 0x06 ARM_CAPTURE dt1=n_samples to collect
+// 0x07 GET_IQ_AVG -> dt1_o=I_avg, dt2_o=Q_avg
+// 0x08 GET_POWER -> dt1_o=power, dt2_o={31'b0, valid}
+// 0x09 KW_LUT_WE dt1[7:0]=index, dt2=value (signed step)
+// 0x0A KW_STEP dt1=dp_signed, dt2[7:0]=k_idx
+// -> dt1_o=x_new, dt2_o={31'b0, conv_flag}
+// 0x0B GET_X -> dt1_o=x_current, dt2_o=iter_k
+// 0x0C GET_XBAR -> dt1_o=xbar_x, dt2_o=xbar_delta_x (running x avg)
+// 0x0D BISECT_INIT dt1=lo, dt2=hi, dt3=tol,
+// dt4[0]=side_left, dt4[1]=polarity_peak
+// 0x0E BISECT_STEP dt1=pow_mid, dt2=pow_thr
+// -> dt1_o=mid_next, dt2_o={31'b0, converged}
+// 0x0F GET_BISECT -> dt1_o=lo, dt2_o=hi
+// 0x10 GET_STATUS -> dt1_o=samples_remaining, dt2_o=flags
+// others NOP
+//
+
+module adaptive_sweep_control #(
+ parameter integer X_WIDTH = 32,
+ parameter integer IQ_WIDTH = 16,
+ parameter integer POW_WIDTH = 32,
+ parameter integer COUNT_WIDTH= 16,
+ parameter integer LUT_AW = 8
+)(
+ input wire clk,
+ input wire rst_n,
+
+ // ---- QP2 (tProc-side) ----
+ input wire qtag_en_i,
+ input wire [4:0] qtag_op_i,
+ input wire [31:0] qtag_dt1_i,
+ input wire [31:0] qtag_dt2_i,
+ input wire [31:0] qtag_dt3_i,
+ input wire [31:0] qtag_dt4_i,
+ output reg qtag_rdy_o,
+ output reg [31:0] qtag_dt1_o,
+ output reg [31:0] qtag_dt2_o,
+ output reg qtag_vld_o,
+
+ // ---- polyak_averager (I, Q) common ports ----
+ output reg pa_soft_reset,
+ output reg [31:0] pa_reciprocal,
+ output reg [3:0] pa_chunk_log2,
+ // I-channel result
+ input wire signed [X_WIDTH-1:0] pa_i_xbar,
+ // Q-channel result
+ input wire signed [X_WIDTH-1:0] pa_q_xbar,
+
+ // ---- iq_power result (post-average) ----
+ output reg pwr_compute_pulse, // pulses to start compute
+ output reg signed [IQ_WIDTH-1:0] pwr_i_in,
+ output reg signed [IQ_WIDTH-1:0] pwr_q_in,
+ input wire [POW_WIDTH-1:0] pwr_value,
+ input wire pwr_valid,
+
+ // ---- kw_steps ----
+ output reg kw_lut_we,
+ output reg [LUT_AW-1:0] kw_lut_addr,
+ output reg signed [X_WIDTH-1:0] kw_lut_din,
+ output reg kw_step_trigger,
+ output reg signed [X_WIDTH-1:0] kw_dp_signed,
+ output reg [LUT_AW-1:0] kw_k_idx,
+ output reg signed [X_WIDTH-1:0] kw_x_in,
+ output reg signed [X_WIDTH-1:0] kw_x_min,
+ output reg signed [X_WIDTH-1:0] kw_x_max,
+ input wire signed [X_WIDTH-1:0] kw_x_out,
+ input wire kw_conv_flag,
+ input wire kw_valid,
+
+ // ---- bisect_control ----
+ output reg bs_init,
+ output reg [X_WIDTH-1:0] bs_lo_init,
+ output reg [X_WIDTH-1:0] bs_hi_init,
+ output reg bs_side_left,
+ output reg bs_polarity_peak,
+ output reg [X_WIDTH-1:0] bs_tol_in,
+ output reg bs_step,
+ output reg [X_WIDTH-1:0] bs_pow_mid,
+ output reg [X_WIDTH-1:0] bs_pow_thr,
+ input wire [X_WIDTH-1:0] bs_mid_next,
+ input wire [X_WIDTH-1:0] bs_lo_o,
+ input wire [X_WIDTH-1:0] bs_hi_o,
+ input wire bs_converged,
+ input wire bs_valid,
+
+ // ---- readout_capture ----
+ output reg rc_arm_pulse,
+ output reg [COUNT_WIDTH-1:0] rc_n_samples,
+ input wire rc_capture_done,
+ input wire [COUNT_WIDTH-1:0] rc_samples_remaining,
+
+ // ---- internal x state visible to adaptive_sweep top ----
+ output reg signed [X_WIDTH-1:0] x_current_o,
+ output reg signed [X_WIDTH-1:0] x_min_o,
+ output reg signed [X_WIDTH-1:0] x_max_o,
+ output reg [LUT_AW-1:0] iter_k_o // KW iteration counter
+);
+
+ // -------------------- Opcode constants --------------------
+ localparam [4:0] OP_NOP = 5'h00;
+ localparam [4:0] OP_RESET_ALL = 5'h01;
+ localparam [4:0] OP_SET_NAVG = 5'h02;
+ localparam [4:0] OP_SET_CHUNK_LOG2 = 5'h03;
+ localparam [4:0] OP_SET_X = 5'h04;
+ localparam [4:0] OP_SET_BOUNDS = 5'h05;
+ localparam [4:0] OP_ARM_CAPTURE = 5'h06;
+ localparam [4:0] OP_GET_IQ_AVG = 5'h07;
+ localparam [4:0] OP_GET_POWER = 5'h08;
+ localparam [4:0] OP_KW_LUT_WE = 5'h09;
+ localparam [4:0] OP_KW_STEP = 5'h0A;
+ localparam [4:0] OP_GET_X = 5'h0B;
+ localparam [4:0] OP_GET_XBAR = 5'h0C;
+ localparam [4:0] OP_BISECT_INIT = 5'h0D;
+ localparam [4:0] OP_BISECT_STEP = 5'h0E;
+ localparam [4:0] OP_GET_BISECT = 5'h0F;
+ localparam [4:0] OP_GET_STATUS = 5'h10;
+
+ // -------------------- en_rise detect --------------------
+ reg en_d;
+ wire en_rise = qtag_en_i & ~en_d;
+ always @(posedge clk) begin
+ if (!rst_n) en_d <= 1'b0;
+ else en_d <= qtag_en_i;
+ end
+
+ // -------------------- FSM --------------------
+ localparam [2:0] S_IDLE = 3'd0;
+ localparam [2:0] S_DISPATCH = 3'd1;
+ localparam [2:0] S_WAIT_KW = 3'd2;
+ localparam [2:0] S_WAIT_BS = 3'd3;
+ localparam [2:0] S_WAIT_PWR = 3'd4;
+ localparam [2:0] S_RESPOND = 3'd5;
+
+ reg [2:0] state;
+ reg [4:0] op_r;
+ reg [31:0] dt1_r, dt2_r, dt3_r, dt4_r;
+ reg [31:0] res1_r, res2_r;
+
+ // -------------------- Sequential FSM --------------------
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ state <= S_IDLE;
+ op_r <= 5'h0;
+ dt1_r <= 32'h0;
+ dt2_r <= 32'h0;
+ dt3_r <= 32'h0;
+ dt4_r <= 32'h0;
+ res1_r <= 32'h0;
+ res2_r <= 32'h0;
+
+ qtag_rdy_o <= 1'b1;
+ qtag_dt1_o <= 32'h0;
+ qtag_dt2_o <= 32'h0;
+ qtag_vld_o <= 1'b0;
+
+ pa_soft_reset <= 1'b0;
+ pa_reciprocal <= 32'h0;
+ pa_chunk_log2 <= 4'd4;
+
+ pwr_compute_pulse <= 1'b0;
+ pwr_i_in <= 0;
+ pwr_q_in <= 0;
+
+ kw_lut_we <= 1'b0;
+ kw_lut_addr <= 0;
+ kw_lut_din <= 0;
+ kw_step_trigger <= 1'b0;
+ kw_dp_signed <= 0;
+ kw_k_idx <= 0;
+ kw_x_in <= 0;
+ kw_x_min <= 0;
+ kw_x_max <= 0;
+
+ bs_init <= 1'b0;
+ bs_lo_init <= 0;
+ bs_hi_init <= 0;
+ bs_side_left <= 1'b0;
+ bs_polarity_peak <= 1'b0;
+ bs_tol_in <= 0;
+ bs_step <= 1'b0;
+ bs_pow_mid <= 0;
+ bs_pow_thr <= 0;
+
+ rc_arm_pulse <= 1'b0;
+ rc_n_samples <= 0;
+
+ x_current_o <= 0;
+ x_min_o <= 32'sh8000_0000;
+ x_max_o <= 32'sh7FFF_FFFF;
+ iter_k_o <= 0;
+ end else begin
+ // Default: 1-cycle pulses go low
+ pa_soft_reset <= 1'b0;
+ pwr_compute_pulse <= 1'b0;
+ kw_lut_we <= 1'b0;
+ kw_step_trigger <= 1'b0;
+ bs_init <= 1'b0;
+ bs_step <= 1'b0;
+ rc_arm_pulse <= 1'b0;
+ qtag_vld_o <= 1'b0;
+
+ case (state)
+ // ----------------------------------------------------
+ S_IDLE: begin
+ qtag_rdy_o <= 1'b1;
+ if (en_rise) begin
+ op_r <= qtag_op_i;
+ dt1_r <= qtag_dt1_i;
+ dt2_r <= qtag_dt2_i;
+ dt3_r <= qtag_dt3_i;
+ dt4_r <= qtag_dt4_i;
+ qtag_rdy_o <= 1'b0;
+ state <= S_DISPATCH;
+ end
+ end
+
+ // ----------------------------------------------------
+ S_DISPATCH: begin
+ case (op_r)
+ OP_NOP: begin
+ res1_r <= 32'h0;
+ res2_r <= 32'h0;
+ state <= S_RESPOND;
+ end
+
+ OP_RESET_ALL: begin
+ pa_soft_reset <= 1'b1;
+ iter_k_o <= 0;
+ state <= S_RESPOND;
+ end
+
+ OP_SET_NAVG: begin
+ pa_reciprocal <= dt2_r; // ceil(2^32 / n_avg)
+ state <= S_RESPOND;
+ end
+
+ OP_SET_CHUNK_LOG2: begin
+ pa_chunk_log2 <= dt1_r[3:0];
+ state <= S_RESPOND;
+ end
+
+ OP_SET_X: begin
+ x_current_o <= $signed(dt1_r);
+ state <= S_RESPOND;
+ end
+
+ OP_SET_BOUNDS: begin
+ x_min_o <= $signed(dt1_r);
+ x_max_o <= $signed(dt2_r);
+ state <= S_RESPOND;
+ end
+
+ OP_ARM_CAPTURE: begin
+ rc_arm_pulse <= 1'b1;
+ rc_n_samples <= dt1_r[COUNT_WIDTH-1:0];
+ // Also clear polyak averagers for a fresh measurement
+ pa_soft_reset <= 1'b1;
+ state <= S_RESPOND;
+ end
+
+ OP_GET_IQ_AVG: begin
+ res1_r <= pa_i_xbar;
+ res2_r <= pa_q_xbar;
+ state <= S_RESPOND;
+ end
+
+ OP_GET_POWER: begin
+ // Kick off an iq_power compute on the current xbar
+ pwr_i_in <= pa_i_xbar[IQ_WIDTH-1:0];
+ pwr_q_in <= pa_q_xbar[IQ_WIDTH-1:0];
+ pwr_compute_pulse <= 1'b1;
+ state <= S_WAIT_PWR;
+ end
+
+ OP_KW_LUT_WE: begin
+ kw_lut_we <= 1'b1;
+ kw_lut_addr <= dt1_r[LUT_AW-1:0];
+ kw_lut_din <= $signed(dt2_r);
+ state <= S_RESPOND;
+ end
+
+ OP_KW_STEP: begin
+ kw_dp_signed <= $signed(dt1_r);
+ kw_k_idx <= dt2_r[LUT_AW-1:0];
+ kw_x_in <= x_current_o;
+ kw_x_min <= x_min_o;
+ kw_x_max <= x_max_o;
+ kw_step_trigger <= 1'b1;
+ state <= S_WAIT_KW;
+ end
+
+ OP_GET_X: begin
+ res1_r <= x_current_o;
+ res2_r <= {{(32-LUT_AW){1'b0}}, iter_k_o};
+ state <= S_RESPOND;
+ end
+
+ OP_GET_XBAR: begin
+ // Reuse pa_i_xbar as the "x running average" channel
+ // (or return current x as a placeholder).
+ res1_r <= x_current_o;
+ res2_r <= 32'h0;
+ state <= S_RESPOND;
+ end
+
+ OP_BISECT_INIT: begin
+ bs_init <= 1'b1;
+ bs_lo_init <= dt1_r;
+ bs_hi_init <= dt2_r;
+ bs_tol_in <= dt3_r;
+ bs_side_left <= dt4_r[0];
+ bs_polarity_peak <= dt4_r[1];
+ state <= S_RESPOND;
+ end
+
+ OP_BISECT_STEP: begin
+ bs_pow_mid <= dt1_r;
+ bs_pow_thr <= dt2_r;
+ bs_step <= 1'b1;
+ state <= S_WAIT_BS;
+ end
+
+ OP_GET_BISECT: begin
+ res1_r <= bs_lo_o;
+ res2_r <= bs_hi_o;
+ state <= S_RESPOND;
+ end
+
+ OP_GET_STATUS: begin
+ res1_r <= {{(32-COUNT_WIDTH){1'b0}}, rc_samples_remaining};
+ res2_r <= {30'h0, rc_capture_done, 1'b0};
+ state <= S_RESPOND;
+ end
+
+ default: begin
+ res1_r <= 32'h0;
+ res2_r <= 32'h0;
+ state <= S_RESPOND;
+ end
+ endcase
+ end
+
+ // ----------------------------------------------------
+ S_WAIT_KW: begin
+ if (kw_valid) begin
+ res1_r <= kw_x_out;
+ res2_r <= {31'h0, kw_conv_flag};
+ x_current_o <= kw_x_out;
+ iter_k_o <= iter_k_o + 1'b1;
+ state <= S_RESPOND;
+ end
+ end
+
+ // ----------------------------------------------------
+ S_WAIT_BS: begin
+ if (bs_valid) begin
+ res1_r <= bs_mid_next;
+ res2_r <= {31'h0, bs_converged};
+ state <= S_RESPOND;
+ end
+ end
+
+ // ----------------------------------------------------
+ S_WAIT_PWR: begin
+ if (pwr_valid) begin
+ res1_r <= pwr_value;
+ res2_r <= 32'h1; // valid flag
+ state <= S_RESPOND;
+ end
+ end
+
+ // ----------------------------------------------------
+ S_RESPOND: begin
+ qtag_dt1_o <= res1_r;
+ qtag_dt2_o <= res2_r;
+ qtag_vld_o <= 1'b1;
+ qtag_rdy_o <= 1'b1;
+ state <= S_IDLE;
+ end
+
+ default: state <= S_IDLE;
+ endcase
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/bisect_control.v b/firmware/ip/adaptive_sweep/src/bisect_control.v
new file mode 100644
index 000000000..c34255297
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/bisect_control.v
@@ -0,0 +1,128 @@
+`timescale 1ns / 1ps
+//
+// bisect_control.v
+//
+// 3 dB edge bisection (Section 9 Phase 3.5). Maintains a closed interval
+// [lo, hi] in normalized x-space and on every `step` pulse evaluates the
+// caller-supplied (pow_mid, pow_thr) pair to halve the interval toward the
+// edge.
+//
+// 4-way decision (peak vs dip, left vs right), as described in
+// Section 9 §1.7:
+// peak / left : pow_mid < pow_thr -> lo<=mid else hi<=mid
+// peak / right: pow_mid > pow_thr -> lo<=mid else hi<=mid
+// dip / left : pow_mid > pow_thr -> lo<=mid else hi<=mid
+// dip / right: pow_mid < pow_thr -> lo<=mid else hi<=mid
+//
+// Convergence: (hi - lo) < tol_in. No DSP / no BRAM, only adders +
+// comparators + muxes. 2-cycle latency from `step` to mid_next/converged.
+//
+
+module bisect_control #(
+ parameter integer X_WIDTH = 32
+)(
+ input wire clk,
+ input wire rst_n,
+
+ // Initialization
+ input wire init,
+ input wire [X_WIDTH-1:0] lo_init,
+ input wire [X_WIDTH-1:0] hi_init,
+ input wire side_left, // 1=left edge, 0=right edge
+ input wire polarity_peak, // 1=peak, 0=dip
+ input wire [X_WIDTH-1:0] tol_in,
+
+ // Step request
+ input wire step,
+ input wire [X_WIDTH-1:0] pow_mid,
+ input wire [X_WIDTH-1:0] pow_thr,
+
+ // Outputs
+ output reg [X_WIDTH-1:0] mid_next,
+ output reg [X_WIDTH-1:0] lo_o,
+ output reg [X_WIDTH-1:0] hi_o,
+ output reg converged_o,
+ output reg valid_o // pulses 1 cycle on step completion
+);
+
+ // Latched configuration
+ reg side_left_r;
+ reg polarity_peak_r;
+ reg [X_WIDTH-1:0] tol_r;
+
+ // Stage 1 registers (for `step`)
+ reg s1_step;
+ reg s1_cmp_gt; // pow_mid > pow_thr
+ reg [X_WIDTH-1:0] s1_mid;
+ reg [X_WIDTH-1:0] s1_lo, s1_hi;
+ reg s1_converged;
+
+ // The "raise lo" decision summary table:
+ // raise_lo = polarity_peak ?
+ // (side_left ? !cmp_gt : cmp_gt) // peak
+ // :
+ // (side_left ? cmp_gt : !cmp_gt); // dip
+ // raise_lo == 1 -> lo<=mid; else hi<=mid.
+
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ lo_o <= 0;
+ hi_o <= 0;
+ mid_next <= 0;
+ converged_o <= 1'b0;
+ valid_o <= 1'b0;
+ side_left_r <= 1'b0;
+ polarity_peak_r <= 1'b0;
+ tol_r <= 0;
+ s1_step <= 1'b0;
+ s1_cmp_gt <= 1'b0;
+ s1_mid <= 0;
+ s1_lo <= 0;
+ s1_hi <= 0;
+ s1_converged <= 1'b0;
+ end else begin
+ valid_o <= 1'b0;
+ s1_step <= 1'b0;
+
+ // Init takes precedence: arms the controller with the initial
+ // interval and resets convergence. No "step" should arrive on
+ // the same cycle as init.
+ if (init) begin
+ lo_o <= lo_init;
+ hi_o <= hi_init;
+ mid_next <= (lo_init + hi_init) >> 1;
+ converged_o <= 1'b0;
+ side_left_r <= side_left;
+ polarity_peak_r <= polarity_peak;
+ tol_r <= tol_in;
+ end
+ else if (step && !converged_o) begin
+ // Stage 1: compute mid, compare, snapshot interval
+ s1_step <= 1'b1;
+ s1_cmp_gt <= (pow_mid > pow_thr);
+ s1_mid <= mid_next; // current midpoint that was probed
+ s1_lo <= lo_o;
+ s1_hi <= hi_o;
+ s1_converged <= ((hi_o - lo_o) < tol_r);
+ end
+
+ // Stage 2: apply decision
+ if (s1_step) begin : apply_decision
+ reg raise_lo;
+ raise_lo = polarity_peak_r
+ ? (side_left_r ? ~s1_cmp_gt : s1_cmp_gt)
+ : (side_left_r ? s1_cmp_gt : ~s1_cmp_gt);
+ if (raise_lo) begin
+ lo_o <= s1_mid;
+ mid_next <= (s1_mid + s1_hi) >> 1;
+ end else begin
+ hi_o <= s1_mid;
+ mid_next <= (s1_lo + s1_mid) >> 1;
+ end
+ converged_o <= s1_converged;
+ valid_o <= 1'b1;
+ end
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/iq_power.v b/firmware/ip/adaptive_sweep/src/iq_power.v
new file mode 100644
index 000000000..6807f68af
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/iq_power.v
@@ -0,0 +1,68 @@
+`timescale 1ns / 1ps
+//
+// iq_power.v
+//
+// Computes exact magnitude squared: power_o = i_in*i_in + q_in*q_in
+// Two DSP48E2 multipliers (one per channel) plus a 32-bit add.
+// Fully pipelined, 3-cycle latency, 1 sample/cycle throughput.
+//
+// Range:
+// Worst case I, Q = -2^(IQ_WIDTH-1) -> i^2 = q^2 = 2^(2*IQ_WIDTH-2)
+// For IQ_WIDTH=16: i^2 + q^2 <= 2^31, fits in POW_WIDTH=32 unsigned.
+//
+// Pipeline (target c_clk = 200 MHz on RFSoC 4x2):
+// P0 i_in, q_in -> i_r, q_r (DSP A reg, 1 LUT level)
+// P1 i_sq <= i_r * i_r; q_sq <= q_r * q_r (DSP M reg, 16x16 mul ~1.5 ns)
+// P2 power_o <= i_sq + q_sq (32-bit add or DSP P)
+//
+
+module iq_power #(
+ parameter integer IQ_WIDTH = 16,
+ parameter integer POW_WIDTH = 32
+)(
+ input wire clk,
+ input wire rst_n,
+
+ input wire signed [IQ_WIDTH-1:0] i_in,
+ input wire signed [IQ_WIDTH-1:0] q_in,
+ input wire valid_in,
+
+ output reg [POW_WIDTH-1:0] power_o,
+ output reg valid_o
+);
+
+ // P0: input regs
+ reg signed [IQ_WIDTH-1:0] i_r, q_r;
+ reg vld_r0;
+
+ // P1: squared
+ (* use_dsp = "yes" *) reg [2*IQ_WIDTH-1:0] i_sq;
+ (* use_dsp = "yes" *) reg [2*IQ_WIDTH-1:0] q_sq;
+ reg vld_r1;
+
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ i_r <= {IQ_WIDTH{1'b0}};
+ q_r <= {IQ_WIDTH{1'b0}};
+ i_sq <= {(2*IQ_WIDTH){1'b0}};
+ q_sq <= {(2*IQ_WIDTH){1'b0}};
+ power_o <= {POW_WIDTH{1'b0}};
+ vld_r0 <= 1'b0;
+ vld_r1 <= 1'b0;
+ valid_o <= 1'b0;
+ end else begin
+ // P0
+ i_r <= i_in;
+ q_r <= q_in;
+ vld_r0 <= valid_in;
+ // P1: signed * signed -> non-negative
+ i_sq <= $signed(i_r) * $signed(i_r);
+ q_sq <= $signed(q_r) * $signed(q_r);
+ vld_r1 <= vld_r0;
+ // P2
+ power_o <= i_sq + q_sq;
+ valid_o <= vld_r1;
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/kw_steps.v b/firmware/ip/adaptive_sweep/src/kw_steps.v
new file mode 100644
index 000000000..1a7bea790
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/kw_steps.v
@@ -0,0 +1,179 @@
+`timescale 1ns / 1ps
+//
+// kw_steps.v
+//
+// LUT-driven Kiefer-Wolfowitz step generator.
+//
+// The ARM (PS) precomputes a step magnitude schedule -- typically the
+// Section 9 _ak_s9(k) function or any other custom decay -- and writes it
+// into the on-chip BRAM through {lut_we, lut_addr, lut_din}.
+//
+// On a step_trigger pulse the module:
+// 1. Reads LUT[k_idx] (sync BRAM read)
+// 2. Determines the step direction from sign(dp_signed):
+// dp > 0 -> step = +LUT[k_idx] (move x toward higher response)
+// dp < 0 -> step = -LUT[k_idx]
+// dp = 0 -> step = 0
+// 3. x_sum = x_in + step
+// 4. x_out = clamp(x_sum, x_min, x_max)
+// 5. conv_flag asserted if |step| < KW_TOL (caller-provided tol param)
+//
+// 6-stage pipeline. No multipliers, one BRAM18. Critical path: 32-bit
+// add followed by clamp compare in stage K5; if synthesis flags slack,
+// move clamp into a separate stage K6.
+//
+
+module kw_steps #(
+ parameter integer X_WIDTH = 32,
+ parameter integer LUT_DEPTH = 256,
+ parameter integer LUT_AW = 8, // log2(LUT_DEPTH)
+ parameter [X_WIDTH-1:0] KW_TOL = 32'h0000_07D0 // ~2000 in fixed-point
+)(
+ input wire clk,
+ input wire rst_n,
+
+ // LUT write port (from adaptive_sweep_control on KW_LUT_WE opcode)
+ input wire lut_we,
+ input wire [LUT_AW-1:0] lut_addr,
+ input wire signed [X_WIDTH-1:0] lut_din,
+
+ // Step request
+ input wire step_trigger,
+ input wire signed [X_WIDTH-1:0] dp_signed, // = y_plus - y_minus
+ input wire [LUT_AW-1:0] k_idx,
+ input wire signed [X_WIDTH-1:0] x_in,
+ input wire signed [X_WIDTH-1:0] x_min,
+ input wire signed [X_WIDTH-1:0] x_max,
+
+ // Step result
+ output reg signed [X_WIDTH-1:0] x_out,
+ output reg conv_flag,
+ output reg valid_o
+);
+
+ // -------------------- LUT (256 x 32, BRAM) --------------------
+ (* ram_style = "block" *) reg signed [X_WIDTH-1:0] lut [0:LUT_DEPTH-1];
+ reg signed [X_WIDTH-1:0] lut_q;
+
+ always @(posedge clk) begin
+ if (lut_we)
+ lut[lut_addr] <= lut_din;
+ // Port B: synchronous read on every step trigger.
+ // For Vivado BRAM inference we drive the read every cycle.
+ lut_q <= lut[k_idx];
+ end
+
+ // -------------------- Pipeline registers --------------------
+ // K0 (sample): inputs latched directly into K1 below
+ reg k1_trig;
+ reg k1_sign_pos;
+ reg k1_is_zero;
+ reg signed [X_WIDTH-1:0] k1_x_in;
+ reg signed [X_WIDTH-1:0] k1_x_min, k1_x_max;
+ reg [LUT_AW-1:0] k1_idx;
+
+ // K2: lut_q valid here (BRAM 1-cycle latency)
+ reg k2_trig;
+ reg k2_sign_pos;
+ reg k2_is_zero;
+ reg signed [X_WIDTH-1:0] k2_x_in;
+ reg signed [X_WIDTH-1:0] k2_x_min, k2_x_max;
+
+ // K3: step computed
+ reg k3_trig;
+ reg signed [X_WIDTH-1:0] k3_step;
+ reg signed [X_WIDTH-1:0] k3_x_in;
+ reg signed [X_WIDTH-1:0] k3_x_min, k3_x_max;
+
+ // K4: x_sum
+ reg k4_trig;
+ reg signed [X_WIDTH-1:0] k4_x_sum;
+ reg signed [X_WIDTH-1:0] k4_x_min, k4_x_max;
+ reg signed [X_WIDTH-1:0] k4_step;
+
+ // K5: clamp + conv flag (output stage)
+
+ // -------------------- Stages --------------------
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ k1_trig <= 1'b0;
+ k1_sign_pos<= 1'b0;
+ k1_is_zero <= 1'b0;
+ k1_x_in <= 0;
+ k1_x_min <= 0;
+ k1_x_max <= 0;
+ k1_idx <= 0;
+
+ k2_trig <= 1'b0;
+ k2_sign_pos<= 1'b0;
+ k2_is_zero <= 1'b0;
+ k2_x_in <= 0;
+ k2_x_min <= 0;
+ k2_x_max <= 0;
+
+ k3_trig <= 1'b0;
+ k3_step <= 0;
+ k3_x_in <= 0;
+ k3_x_min <= 0;
+ k3_x_max <= 0;
+
+ k4_trig <= 1'b0;
+ k4_x_sum <= 0;
+ k4_x_min <= 0;
+ k4_x_max <= 0;
+ k4_step <= 0;
+
+ x_out <= 0;
+ conv_flag <= 1'b0;
+ valid_o <= 1'b0;
+ end else begin
+ // K1: latch inputs and compute sign / is_zero
+ k1_trig <= step_trigger;
+ k1_sign_pos <= ~dp_signed[X_WIDTH-1]; // 1 if non-negative
+ k1_is_zero <= (dp_signed == {X_WIDTH{1'b0}});
+ k1_x_in <= x_in;
+ k1_x_min <= x_min;
+ k1_x_max <= x_max;
+ k1_idx <= k_idx;
+
+ // K2: lut_q is now valid (BRAM read completed this cycle)
+ k2_trig <= k1_trig;
+ k2_sign_pos <= k1_sign_pos;
+ k2_is_zero <= k1_is_zero;
+ k2_x_in <= k1_x_in;
+ k2_x_min <= k1_x_min;
+ k2_x_max <= k1_x_max;
+
+ // K3: pick signed step or zero
+ k3_trig <= k2_trig;
+ k3_x_in <= k2_x_in;
+ k3_x_min <= k2_x_min;
+ k3_x_max <= k2_x_max;
+ if (k2_is_zero)
+ k3_step <= 0;
+ else if (k2_sign_pos)
+ k3_step <= lut_q;
+ else
+ k3_step <= -lut_q;
+
+ // K4: x_sum = x_in + step
+ k4_trig <= k3_trig;
+ k4_x_sum <= k3_x_in + k3_step;
+ k4_x_min <= k3_x_min;
+ k4_x_max <= k3_x_max;
+ k4_step <= k3_step;
+
+ // K5: clamp + conv flag + output valid
+ valid_o <= k4_trig;
+ if (k4_x_sum < k4_x_min) x_out <= k4_x_min;
+ else if (k4_x_sum > k4_x_max) x_out <= k4_x_max;
+ else x_out <= k4_x_sum;
+ // conv flag uses absolute value of step
+ if ((k4_step >= 0 ? k4_step : -k4_step) < KW_TOL)
+ conv_flag <= 1'b1;
+ else
+ conv_flag <= 1'b0;
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/polyak_averager.v b/firmware/ip/adaptive_sweep/src/polyak_averager.v
new file mode 100644
index 000000000..2bf99015d
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/polyak_averager.v
@@ -0,0 +1,158 @@
+`timescale 1ns / 1ps
+//
+// polyak_averager.v
+//
+// Chunked Polyak / running averager built around a single reciprocal-multiply
+// "divider". The ARM precomputes RECIPROCAL = ceil(2^32 / n_avg) and writes
+// it through reciprocal_in. Every 2^chunk_size_log2 valid samples the module
+// fires: xbar = (sum * reciprocal) >>> 32.
+//
+// One instance is used per channel (e.g. one for I and one for Q). When
+// chunk_size_log2 is chosen so that 2^chunk_size_log2 == n_avg the module
+// behaves as a one-shot averager (drop a soft_reset between measurements);
+// when chunks are smaller than the total measurement length it behaves as a
+// running chunked Polyak average and exposes xbar_delta_o for convergence
+// detection.
+//
+// Datapath / timing (target c_clk = 200 MHz on RFSoC 4x2 ZU48DR)
+// H0 sample_in -> sign-extended sample_ext (1 LUT level)
+// H1 sum <= sum + sample_ext (48-bit add)
+// C0 on chunk close: latch sum_chunk, reciprocal (DSP A reg)
+// C1 mul_p1 <= sum_chunk * reciprocal (DSP M reg)
+// C2 mul_p2 <= mul_p1 (DSP P reg)
+// C3 xbar_next = mul_p2 >>> 32 (wire)
+// C4 xbar_o, xbar_delta_o, valid_o (output regs)
+//
+// Synchronous active-low reset only (project policy commit b4f6bcc9).
+//
+
+module polyak_averager #(
+ parameter integer SAMPLE_WIDTH = 16, // signed input width
+ parameter integer SUM_WIDTH = 48, // signed accumulator
+ parameter integer AVG_WIDTH = 32, // signed average output
+ parameter integer RECIP_WIDTH = 32, // unsigned reciprocal
+ parameter integer COUNT_WIDTH = 16 // total sample counter
+)(
+ input wire clk,
+ input wire rst_n,
+
+ // Sample input
+ input wire signed [SAMPLE_WIDTH-1:0] sample_in,
+ input wire sample_valid,
+
+ // Configuration
+ input wire [RECIP_WIDTH-1:0] reciprocal_in,
+ input wire [3:0] chunk_size_log2, // 1..8
+
+ // Control
+ input wire soft_reset, // clear sum/count/xbar
+
+ // Outputs
+ output reg signed [AVG_WIDTH-1:0] xbar_o,
+ output reg [AVG_WIDTH-1:0] xbar_delta_o,
+ output reg [COUNT_WIDTH-1:0] count_o,
+ output reg valid_o // pulses 1 cycle on chunk close
+);
+
+ // -----------------------------------------------------------
+ // Hot path: accumulate samples and detect chunk close
+ // -----------------------------------------------------------
+ reg signed [SUM_WIDTH-1:0] sum;
+ reg signed [SUM_WIDTH-1:0] sum_chunk; // snapshot of sum at chunk close
+ reg [COUNT_WIDTH-1:0] in_chunk_count; // counts 0..(2^k - 1)
+ reg chunk_close_r;
+ reg [RECIP_WIDTH-1:0] reciprocal_r;
+
+ wire signed [SUM_WIDTH-1:0] sample_ext =
+ {{(SUM_WIDTH-SAMPLE_WIDTH){sample_in[SAMPLE_WIDTH-1]}}, sample_in};
+
+ // chunk_size_log2 acts as a comparator threshold against in_chunk_count.
+ // 1..8 supported -> chunk lengths 2..256.
+ wire [COUNT_WIDTH-1:0] chunk_len_minus1 =
+ ({{(COUNT_WIDTH-1){1'b0}}, 1'b1} << chunk_size_log2) - 1'b1;
+
+ always @(posedge clk) begin
+ if (!rst_n || soft_reset) begin
+ sum <= {SUM_WIDTH{1'b0}};
+ sum_chunk <= {SUM_WIDTH{1'b0}};
+ in_chunk_count <= {COUNT_WIDTH{1'b0}};
+ count_o <= {COUNT_WIDTH{1'b0}};
+ chunk_close_r <= 1'b0;
+ reciprocal_r <= {RECIP_WIDTH{1'b0}};
+ end else begin
+ chunk_close_r <= 1'b0;
+ // reciprocal latches every cycle so the ARM can update it between chunks
+ reciprocal_r <= reciprocal_in;
+
+ if (sample_valid) begin
+ sum <= sum + sample_ext;
+ count_o <= count_o + 1'b1;
+
+ if (in_chunk_count == chunk_len_minus1) begin
+ // This is the last sample of the chunk: snapshot the
+ // running sum (including this sample) and pulse chunk_close.
+ in_chunk_count <= {COUNT_WIDTH{1'b0}};
+ sum_chunk <= sum + sample_ext;
+ chunk_close_r <= 1'b1;
+ end else begin
+ in_chunk_count <= in_chunk_count + 1'b1;
+ end
+ end
+ end
+ end
+
+ // -----------------------------------------------------------
+ // Cold path: sum_chunk * reciprocal -> xbar (multi-cycle)
+ // 4-stage DSP pipeline; result valid 4 cycles after chunk_close_r.
+ // -----------------------------------------------------------
+ reg signed [SUM_WIDTH-1:0] mul_a_r;
+ reg signed [RECIP_WIDTH:0] mul_b_r; // sign-extend unsigned to keep signed mul
+ (* use_dsp = "yes" *)
+ reg signed [SUM_WIDTH+RECIP_WIDTH:0] mul_p1; // 1st stage of DSP
+ reg signed [SUM_WIDTH+RECIP_WIDTH:0] mul_p2; // 2nd stage of DSP
+ reg signed [AVG_WIDTH-1:0] xbar_next;
+ reg signed [AVG_WIDTH-1:0] xbar_prev;
+ reg [3:0] pipe_valid; // shift register tracking valid
+
+ always @(posedge clk) begin
+ if (!rst_n || soft_reset) begin
+ mul_a_r <= {SUM_WIDTH{1'b0}};
+ mul_b_r <= {(RECIP_WIDTH+1){1'b0}};
+ mul_p1 <= {(SUM_WIDTH+RECIP_WIDTH+1){1'b0}};
+ mul_p2 <= {(SUM_WIDTH+RECIP_WIDTH+1){1'b0}};
+ xbar_next <= {AVG_WIDTH{1'b0}};
+ xbar_prev <= {AVG_WIDTH{1'b0}};
+ xbar_o <= {AVG_WIDTH{1'b0}};
+ xbar_delta_o <= {AVG_WIDTH{1'b0}};
+ valid_o <= 1'b0;
+ pipe_valid <= 4'b0;
+ end else begin
+ // Stage 0 -> 1
+ mul_a_r <= sum_chunk;
+ mul_b_r <= {1'b0, reciprocal_r}; // unsigned -> 33b signed positive
+ // Stage 1 -> 2
+ mul_p1 <= $signed(mul_a_r) * $signed(mul_b_r);
+ // Stage 2 -> 3
+ mul_p2 <= mul_p1;
+ // Stage 3 -> 4: arithmetic right-shift by 32 then truncate to AVG_WIDTH.
+ // product = sum_chunk * reciprocal (signed, SUM_WIDTH+RECIP_WIDTH+1 bits)
+ // xbar = product >>> 32 (lower AVG_WIDTH bits of that = product[31+AVG_WIDTH:32])
+ xbar_next <= mul_p2[32 +: AVG_WIDTH];
+ // Stage 4: register xbar, compute |delta|
+ if (pipe_valid[3]) begin
+ xbar_o <= xbar_next;
+ xbar_prev <= xbar_next;
+ xbar_delta_o <= (xbar_next >= xbar_prev) ?
+ (xbar_next - xbar_prev) :
+ (xbar_prev - xbar_next);
+ valid_o <= 1'b1;
+ end else begin
+ valid_o <= 1'b0;
+ end
+
+ // Pipeline valid shift register
+ pipe_valid <= {pipe_valid[2:0], chunk_close_r};
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/readout_capture.v b/firmware/ip/adaptive_sweep/src/readout_capture.v
new file mode 100644
index 000000000..c7a4c097c
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/readout_capture.v
@@ -0,0 +1,235 @@
+`timescale 1ns / 1ps
+//
+// readout_capture.v
+//
+// Snoops the m1_axis output of axis_dyn_readout_v1 (32-bit packed I/Q on
+// ro_clk = 307.2 MHz), gates by an external trigger, optionally counts a
+// fixed window of N samples, and surfaces decoded I/Q on the c_clk domain
+// (200 MHz) through an asynchronous BRAM FIFO.
+//
+// Snoop semantics: drives s_ro_axis_tready=1 always. This means the
+// upstream writer (the readout) is never back-pressured by us, so the
+// existing avg_buffer consumer is unaffected. The price is that if our
+// FIFO ever fills up we silently drop samples -- size the FIFO so this
+// can't happen for the configured n_samples.
+//
+// Two CDC paths:
+// arm_pulse : c_clk -> ro_clk (level toggled into a Gray bit then
+// synced; we synthesize a 1-cycle ro_clk pulse from a
+// rising edge).
+// capture_done : ro_clk -> c_clk (synced level then edge-detected).
+//
+// FIFO: xpm_fifo_async, 32-bit data, 64 deep, FWFT. ~1 BRAM18.
+//
+
+module readout_capture #(
+ parameter integer IQ_WIDTH = 16,
+ parameter integer FIFO_DEPTH_LOG2 = 6, // 2^6 = 64
+ parameter integer COUNT_WIDTH = 16
+)(
+ // ----------- c_clk domain -----------
+ input wire clk,
+ input wire rst_n,
+
+ // Capture control (from adaptive_sweep_control)
+ input wire arm_pulse, // 1-cycle pulse to start a window
+ input wire [COUNT_WIDTH-1:0] n_samples, // window length
+ output reg capture_done_o, // sticky high until next arm
+
+ // Decoded sample stream consumed by polyak_averager + iq_power
+ output wire signed [IQ_WIDTH-1:0] i_out,
+ output wire signed [IQ_WIDTH-1:0] q_out,
+ output wire iq_valid,
+ input wire iq_ready, // back-pressure to consumers
+ output wire [COUNT_WIDTH-1:0] samples_remaining,
+
+ // ----------- ro_clk domain -----------
+ input wire s_ro_axis_aclk,
+ input wire s_ro_axis_aresetn,
+ input wire [2*IQ_WIDTH-1:0] s_ro_axis_tdata, // {Q[15:0], I[15:0]}
+ input wire s_ro_axis_tvalid,
+ output wire s_ro_axis_tready, // tied to 1
+ input wire trigger_i // external trigger (ro_clk async)
+);
+
+ // ----------------------------------------------------------------
+ // c_clk -> ro_clk : arm_pulse to ro_clk-domain "armed" enable
+ // ----------------------------------------------------------------
+ // Implement as a toggle FF in c_clk; synchronize the toggle into
+ // ro_clk; edge-detect the synchronized toggle into a 1-cycle ro_clk
+ // pulse. Standard XPM_CDC_PULSE pattern done by hand to keep the
+ // module portable.
+ reg arm_toggle_c;
+ always @(posedge clk) begin
+ if (!rst_n) arm_toggle_c <= 1'b0;
+ else if (arm_pulse) arm_toggle_c <= ~arm_toggle_c;
+ end
+
+ (* ASYNC_REG = "TRUE" *) reg arm_tog_sync_0, arm_tog_sync_1, arm_tog_sync_2;
+ always @(posedge s_ro_axis_aclk) begin
+ if (!s_ro_axis_aresetn) begin
+ arm_tog_sync_0 <= 1'b0;
+ arm_tog_sync_1 <= 1'b0;
+ arm_tog_sync_2 <= 1'b0;
+ end else begin
+ arm_tog_sync_0 <= arm_toggle_c;
+ arm_tog_sync_1 <= arm_tog_sync_0;
+ arm_tog_sync_2 <= arm_tog_sync_1;
+ end
+ end
+ wire arm_pulse_ro = arm_tog_sync_1 ^ arm_tog_sync_2;
+
+ // ----------------------------------------------------------------
+ // c_clk -> ro_clk : n_samples (slow-changing config) -- 2-FF sync
+ // Safe to sync as a multibit because the value is only consumed
+ // when arm_pulse_ro fires, and arm_pulse_ro is at least 3 ro_clk
+ // cycles after n_samples is stable in c_clk.
+ // ----------------------------------------------------------------
+ (* ASYNC_REG = "TRUE" *) reg [COUNT_WIDTH-1:0] n_samples_sync_0, n_samples_sync_1;
+ always @(posedge s_ro_axis_aclk) begin
+ if (!s_ro_axis_aresetn) begin
+ n_samples_sync_0 <= 0;
+ n_samples_sync_1 <= 0;
+ end else begin
+ n_samples_sync_0 <= n_samples;
+ n_samples_sync_1 <= n_samples_sync_0;
+ end
+ end
+
+ // ----------------------------------------------------------------
+ // ro_clk side: trigger gate, sample counter, FIFO writes
+ // ----------------------------------------------------------------
+ reg armed_ro;
+ reg [COUNT_WIDTH-1:0] remaining_ro;
+ reg trigger_d;
+ wire trigger_rise = trigger_i & ~trigger_d;
+
+ wire fifo_full;
+ wire fifo_wr_en;
+
+ // Write enable: armed AND tvalid AND not full. If full, drop sample
+ // (simulation will assert).
+ assign fifo_wr_en = armed_ro & s_ro_axis_tvalid & ~fifo_full;
+ assign s_ro_axis_tready = 1'b1; // snoop never stalls writer
+
+ always @(posedge s_ro_axis_aclk) begin
+ if (!s_ro_axis_aresetn) begin
+ armed_ro <= 1'b0;
+ remaining_ro <= 0;
+ trigger_d <= 1'b0;
+ end else begin
+ trigger_d <= trigger_i;
+
+ // arm_pulse_ro loads the counter and arms (waits for trigger)
+ if (arm_pulse_ro) begin
+ armed_ro <= 1'b0; // not yet capturing
+ remaining_ro <= n_samples_sync_1;
+ end
+
+ // Trigger starts capture only if a window is loaded
+ if (trigger_rise && remaining_ro != 0) begin
+ armed_ro <= 1'b1;
+ end
+
+ // While capturing, decrement on each accepted write
+ if (armed_ro && fifo_wr_en) begin
+ if (remaining_ro == 1) begin
+ armed_ro <= 1'b0; // last sample
+ remaining_ro <= 0;
+ end else begin
+ remaining_ro <= remaining_ro - 1'b1;
+ end
+ end
+ end
+ end
+
+ // capture_done_ro: pulse-toggle into c_clk for capture_done_o
+ reg capture_done_tog_ro;
+ always @(posedge s_ro_axis_aclk) begin
+ if (!s_ro_axis_aresetn)
+ capture_done_tog_ro <= 1'b0;
+ else if (armed_ro && fifo_wr_en && remaining_ro == 1)
+ capture_done_tog_ro <= ~capture_done_tog_ro;
+ end
+
+ (* ASYNC_REG = "TRUE" *) reg cap_done_sync_0, cap_done_sync_1, cap_done_sync_2;
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ cap_done_sync_0 <= 1'b0;
+ cap_done_sync_1 <= 1'b0;
+ cap_done_sync_2 <= 1'b0;
+ capture_done_o <= 1'b0;
+ end else begin
+ cap_done_sync_0 <= capture_done_tog_ro;
+ cap_done_sync_1 <= cap_done_sync_0;
+ cap_done_sync_2 <= cap_done_sync_1;
+ // arm_pulse clears the sticky done flag
+ if (arm_pulse) capture_done_o <= 1'b0;
+ else if (cap_done_sync_1 ^ cap_done_sync_2) capture_done_o <= 1'b1;
+ end
+ end
+
+ // ----------------------------------------------------------------
+ // Async FIFO (xpm_fifo_async, 32 wide, 64 deep, FWFT)
+ // ----------------------------------------------------------------
+ wire [2*IQ_WIDTH-1:0] fifo_dout;
+ wire fifo_empty;
+ wire fifo_rd_en;
+
+ assign fifo_rd_en = ~fifo_empty & iq_ready;
+
+ xpm_fifo_async #(
+ .CDC_SYNC_STAGES (2),
+ .DOUT_RESET_VALUE ("0"),
+ .ECC_MODE ("no_ecc"),
+ .FIFO_MEMORY_TYPE ("block"),
+ .FIFO_READ_LATENCY (0), // FWFT
+ .FIFO_WRITE_DEPTH (1 << FIFO_DEPTH_LOG2),
+ .FULL_RESET_VALUE (0),
+ .READ_DATA_WIDTH (2*IQ_WIDTH),
+ .READ_MODE ("fwft"),
+ .RELATED_CLOCKS (0),
+ .USE_ADV_FEATURES ("0000"),
+ .WAKEUP_TIME (0),
+ .WRITE_DATA_WIDTH (2*IQ_WIDTH),
+ .WR_DATA_COUNT_WIDTH(1)
+ ) u_fifo (
+ .rst (~s_ro_axis_aresetn), // active high
+ .wr_clk (s_ro_axis_aclk),
+ .wr_en (fifo_wr_en),
+ .din (s_ro_axis_tdata),
+ .full (fifo_full),
+ .rd_clk (clk),
+ .rd_en (fifo_rd_en),
+ .dout (fifo_dout),
+ .empty (fifo_empty),
+ // Unused
+ .injectdbiterr(1'b0),
+ .injectsbiterr(1'b0),
+ .sleep (1'b0),
+ .almost_empty (), .almost_full (), .data_valid (),
+ .dbiterr (), .overflow (), .prog_empty (),
+ .prog_full (), .rd_data_count(), .rd_rst_busy(),
+ .sbiterr (), .underflow (), .wr_data_count(),
+ .wr_rst_busy ()
+ );
+
+ assign i_out = fifo_dout[IQ_WIDTH-1:0];
+ assign q_out = fifo_dout[2*IQ_WIDTH-1:IQ_WIDTH];
+ assign iq_valid = ~fifo_empty;
+
+ // c_clk-side samples_remaining mirror (lossy view, for tProc status reads).
+ // Snapshot at arm_pulse, decrement when sample is consumed downstream.
+ reg [COUNT_WIDTH-1:0] remaining_c;
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ remaining_c <= 0;
+ end else begin
+ if (arm_pulse) remaining_c <= n_samples;
+ else if (fifo_rd_en && remaining_c != 0)
+ remaining_c <= remaining_c - 1'b1;
+ end
+ end
+ assign samples_remaining = remaining_c;
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/tb/tb_adaptive_sweep.sv b/firmware/ip/adaptive_sweep/src/tb/tb_adaptive_sweep.sv
new file mode 100644
index 000000000..f8a69e4b0
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/tb/tb_adaptive_sweep.sv
@@ -0,0 +1,290 @@
+`timescale 1ns / 1ps
+//
+// tb_adaptive_sweep.sv
+//
+// Top-level integration testbench for the adaptive_sweep IP. Emulates a
+// tProc on the QP2 (qtag_*) interface and a readout on the AXIS snoop
+// interface, walks through a representative opcode sequence, and checks
+// the major datapaths.
+//
+// Sequence:
+// 1. Reset, configure (SET_NAVG, SET_CHUNK_LOG2, SET_BOUNDS, SET_X)
+// 2. Load a small KW LUT (8 entries used for this test)
+// 3. ARM_CAPTURE(16), then drive 16 synthetic I/Q samples on ro_clk
+// and pulse the trigger; wait for capture_done
+// 4. GET_IQ_AVG -> compare to expected mean
+// 5. GET_POWER -> compare to I_avg^2 + Q_avg^2
+// 6. KW_STEP with dp>0 -> verify x increases by LUT[k_idx]
+// 7. BISECT_INIT + BISECT_STEP loop on a synthetic peak curve
+//
+
+module tb_adaptive_sweep;
+
+ // ---------------- Parameters ----------------
+ localparam int IQ_WIDTH = 16;
+ localparam int X_WIDTH = 32;
+ localparam int LUT_AW = 8;
+ localparam int COUNT_WIDTH = 16;
+ localparam int N_AVG = 16;
+ localparam int CHUNK_LOG2 = 4;
+ // ceil(2^32 / 16) = 268_435_456
+ localparam logic [31:0] RECIP_16 = 32'd268435456;
+
+ // ---------------- Clocks ----------------
+ logic clk; // c_clk = 200 MHz
+ logic ro_clk; // ro_clk = 307.2 MHz
+ initial clk = 0;
+ initial ro_clk = 0;
+ always #2.5 clk = ~clk;
+ always #1.6275 ro_clk = ~ro_clk;
+
+ // ---------------- Resets ----------------
+ logic rst_n;
+ logic ro_aresetn;
+
+ // ---------------- DUT ports ----------------
+ logic qtag_en;
+ logic [4:0] qtag_op;
+ logic [31:0] qtag_dt1, qtag_dt2, qtag_dt3, qtag_dt4;
+ logic qtag_rdy;
+ logic [31:0] qtag_dt1_o, qtag_dt2_o;
+ logic qtag_vld;
+
+ logic [2*IQ_WIDTH-1:0] ro_tdata;
+ logic ro_tvalid;
+ logic ro_tready;
+ logic trigger;
+
+ int errors = 0, passes = 0;
+
+ // ---------------- DUT ----------------
+ adaptive_sweep #(
+ .LUT_DEPTH (256),
+ .LUT_AW (LUT_AW),
+ .X_WIDTH (X_WIDTH),
+ .IQ_WIDTH (IQ_WIDTH),
+ .SUM_WIDTH (48),
+ .POW_WIDTH (32),
+ .COUNT_WIDTH (COUNT_WIDTH),
+ .RO_FIFO_DEPTH_LOG2(6),
+ .KW_TOL (32'h0000_07D0)
+ ) dut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .qtag_en_i (qtag_en),
+ .qtag_op_i (qtag_op),
+ .qtag_dt1_i (qtag_dt1),
+ .qtag_dt2_i (qtag_dt2),
+ .qtag_dt3_i (qtag_dt3),
+ .qtag_dt4_i (qtag_dt4),
+ .qtag_rdy_o (qtag_rdy),
+ .qtag_dt1_o (qtag_dt1_o),
+ .qtag_dt2_o (qtag_dt2_o),
+ .qtag_vld_o (qtag_vld),
+ .s_ro_axis_aclk (ro_clk),
+ .s_ro_axis_aresetn (ro_aresetn),
+ .s_ro_axis_tdata (ro_tdata),
+ .s_ro_axis_tvalid (ro_tvalid),
+ .s_ro_axis_tready (ro_tready),
+ .trigger_i (trigger)
+ );
+
+ // ---------------- QP2 driver ----------------
+ task automatic qp2_op(input [4:0] op,
+ input [31:0] d1, input [31:0] d2,
+ input [31:0] d3, input [31:0] d4,
+ output [31:0] r1, output [31:0] r2);
+ int t;
+ @(posedge clk);
+ qtag_op <= op;
+ qtag_dt1 <= d1;
+ qtag_dt2 <= d2;
+ qtag_dt3 <= d3;
+ qtag_dt4 <= d4;
+ qtag_en <= 1'b1;
+ @(posedge clk);
+ qtag_en <= 1'b0;
+ // wait for qtag_vld
+ t = 0;
+ while (!qtag_vld && t < 200) begin @(posedge clk); t++; end
+ if (!qtag_vld) begin
+ $display("[%0t] ERROR: qp2_op(0x%02h) timeout", $time, op);
+ errors++;
+ r1 = 0; r2 = 0;
+ end else begin
+ r1 = qtag_dt1_o;
+ r2 = qtag_dt2_o;
+ end
+ endtask
+
+ task automatic check_int(input string n, input int got, input int exp,
+ input int tol = 1);
+ int diff;
+ diff = (got > exp) ? (got - exp) : (exp - got);
+ if (diff <= tol) begin
+ $display("[%0t] PASS %s: got=%0d exp=%0d", $time, n, got, exp);
+ passes++;
+ end else begin
+ $display("[%0t] FAIL %s: got=%0d exp=%0d (tol=%0d)",
+ $time, n, got, exp, tol);
+ errors++;
+ end
+ endtask
+
+ // ---------------- ro_clk stream feeder ----------------
+ // Sends `n` samples with constant (i_val, q_val) on ro_clk after `wait_cycles`.
+ task automatic ro_stream_constant(input int n,
+ input signed [IQ_WIDTH-1:0] i_val,
+ input signed [IQ_WIDTH-1:0] q_val,
+ input int wait_cycles);
+ int sent;
+ @(posedge ro_clk);
+ repeat (wait_cycles) @(posedge ro_clk);
+ sent = 0;
+ ro_tvalid <= 1'b1;
+ while (sent < n) begin
+ ro_tdata <= {q_val, i_val};
+ @(posedge ro_clk);
+ sent++;
+ end
+ ro_tvalid <= 1'b0;
+ endtask
+
+ // Trigger pulse on ro_clk
+ task automatic ro_trigger();
+ @(posedge ro_clk);
+ trigger <= 1;
+ @(posedge ro_clk);
+ trigger <= 0;
+ endtask
+
+ // ---------------- Stimulus ----------------
+ logic [31:0] r1, r2;
+
+ initial begin
+ // Init
+ rst_n = 0;
+ ro_aresetn = 0;
+ qtag_en = 0;
+ qtag_op = 0;
+ qtag_dt1 = 0;
+ qtag_dt2 = 0;
+ qtag_dt3 = 0;
+ qtag_dt4 = 0;
+ ro_tdata = 0;
+ ro_tvalid = 0;
+ trigger = 0;
+ repeat (20) @(posedge clk);
+ rst_n = 1;
+ ro_aresetn = 1;
+ repeat (20) @(posedge clk);
+
+ // 1. Configure
+ $display("---- 1. Configure ----");
+ qp2_op(5'h01, 0, 0, 0, 0, r1, r2); // RESET_ALL
+ qp2_op(5'h02, N_AVG, RECIP_16, 0, 0, r1, r2); // SET_NAVG
+ qp2_op(5'h03, CHUNK_LOG2, 0, 0, 0, r1, r2); // SET_CHUNK_LOG2
+ qp2_op(5'h05, 32'h0, 32'h0010_0000, 0, 0, r1, r2); // SET_BOUNDS [0, 1M]
+ qp2_op(5'h04, 32'h0001_0000, 0, 0, 0, r1, r2); // SET_X = 65536
+
+ // 2. Load a small KW LUT (k=0..7 -> 1000)
+ $display("---- 2. Load KW LUT ----");
+ for (int k = 0; k < 8; k++) begin
+ qp2_op(5'h09, k, 32'sd5000, 0, 0, r1, r2); // KW_LUT_WE
+ end
+
+ // 3. ARM and stream constant samples 100/200
+ $display("---- 3. ARM_CAPTURE + stream ----");
+ qp2_op(5'h06, N_AVG, 0, 0, 0, r1, r2); // ARM_CAPTURE(16)
+ // start ro stream a few cycles after arm + trigger
+ fork
+ ro_stream_constant(N_AVG, 16'sd100, 16'sd200, 4);
+ begin
+ repeat (8) @(posedge ro_clk);
+ ro_trigger();
+ end
+ join
+
+ // Poll GET_STATUS until capture_done
+ begin
+ int t;
+ t = 0;
+ while (t < 100) begin
+ qp2_op(5'h10, 0, 0, 0, 0, r1, r2);
+ if (r2[1]) begin
+ $display("[%0t] capture_done observed (samples_remaining=%0d)",
+ $time, r1);
+ break;
+ end
+ t++;
+ end
+ if (t >= 100) begin
+ $display("[%0t] FAIL: capture_done never observed", $time);
+ errors++;
+ end
+ end
+
+ // 4. GET_IQ_AVG -> expect (100, 200)
+ $display("---- 4. GET_IQ_AVG ----");
+ qp2_op(5'h07, 0, 0, 0, 0, r1, r2);
+ check_int("I_avg", $signed(r1), 32'sd100, 1);
+ check_int("Q_avg", $signed(r2), 32'sd200, 1);
+
+ // 5. GET_POWER -> expect 100^2 + 200^2 = 50000
+ $display("---- 5. GET_POWER ----");
+ qp2_op(5'h08, 0, 0, 0, 0, r1, r2);
+ check_int("power", r1, 50000, 2);
+
+ // 6. KW_STEP with dp>0, k=0 -> x: 65536 -> 70536 (step=+5000)
+ $display("---- 6. KW_STEP (dp>0) ----");
+ qp2_op(5'h0A, 32'sd1000, 32'd0, 0, 0, r1, r2);
+ check_int("x_new", $signed(r1), 32'sd70536, 1);
+
+ // 6b. GET_X
+ qp2_op(5'h0B, 0, 0, 0, 0, r1, r2);
+ check_int("x_after_step", $signed(r1), 32'sd70536, 1);
+
+ // 7. BISECT_INIT + BISECT_STEP loop: peak / left at edge=400
+ $display("---- 7. BISECT (peak/left, edge~400) ----");
+ // dt4: bit0=side_left=1, bit1=polarity_peak=1 -> dt4=2'b11
+ qp2_op(5'h0D, 32'd0, 32'd1024, 32'd4, 32'd3, r1, r2); // BISECT_INIT
+ for (int it = 0; it < 16; it++) begin
+ int x_mid;
+ int dx;
+ int p;
+ // Read mid_next
+ qp2_op(5'h0F, 0, 0, 0, 0, r1, r2); // GET_BISECT
+ x_mid = (r1 + r2) >> 1;
+ dx = (x_mid > 512) ? (x_mid - 512) : (512 - x_mid);
+ p = 32768 - dx*64; if (p < 0) p = 0;
+ qp2_op(5'h0E, p, 32'd16000, 0, 0, r1, r2); // BISECT_STEP
+ if (r2[0]) begin
+ $display("[%0t] bisect converged at iter %0d", $time, it);
+ break;
+ end
+ end
+ qp2_op(5'h0F, 0, 0, 0, 0, r1, r2);
+ if (r1 <= 32'd400 && 32'd400 <= r2) begin
+ $display("[%0t] PASS bisect.range: [%0d, %0d] contains 400",
+ $time, r1, r2);
+ passes++;
+ end else begin
+ $display("[%0t] FAIL bisect.range: [%0d, %0d] does not contain 400",
+ $time, r1, r2);
+ errors++;
+ end
+
+ $display("==== tb_adaptive_sweep done: %0d passes, %0d errors ====",
+ passes, errors);
+ if (errors == 0) $display("RESULT: ALL PASS");
+ else $display("RESULT: %0d FAIL", errors);
+ $finish;
+ end
+
+ initial begin
+ #2000000;
+ $display("[%0t] WATCHDOG: simulation timeout", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/tb/tb_bisect_control.sv b/firmware/ip/adaptive_sweep/src/tb/tb_bisect_control.sv
new file mode 100644
index 000000000..41e3634ea
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/tb/tb_bisect_control.sv
@@ -0,0 +1,165 @@
+`timescale 1ns / 1ps
+//
+// tb_bisect_control.sv
+//
+// Unit testbench for bisect_control.v. Verifies that on a synthetic peak
+// curve the bisection narrows to within `tol` in the expected number of
+// steps for all four (polarity, side) corners.
+//
+
+module tb_bisect_control;
+
+ localparam int X_WIDTH = 32;
+ localparam [X_WIDTH-1:0] LO0 = 32'd0;
+ localparam [X_WIDTH-1:0] HI0 = 32'd1024;
+ localparam [X_WIDTH-1:0] TOL = 32'd4;
+ localparam [X_WIDTH-1:0] EDGE = 32'd400; // synthetic edge location
+
+ logic clk, rst_n;
+ logic init, step;
+ logic [X_WIDTH-1:0] lo_init, hi_init, tol_in;
+ logic side_left, polarity_peak;
+ logic [X_WIDTH-1:0] pow_mid, pow_thr;
+ logic [X_WIDTH-1:0] mid_next, lo_o, hi_o;
+ logic converged_o, valid_o;
+
+ int errors = 0, passes = 0;
+
+ initial clk = 0;
+ always #5 clk = ~clk;
+
+ bisect_control #(.X_WIDTH(X_WIDTH)) dut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .init (init),
+ .lo_init (lo_init),
+ .hi_init (hi_init),
+ .side_left (side_left),
+ .polarity_peak(polarity_peak),
+ .tol_in (tol_in),
+ .step (step),
+ .pow_mid (pow_mid),
+ .pow_thr (pow_thr),
+ .mid_next (mid_next),
+ .lo_o (lo_o),
+ .hi_o (hi_o),
+ .converged_o (converged_o),
+ .valid_o (valid_o)
+ );
+
+ // Synthetic peak power curve, peak at x=512:
+ // pow(x) = max(0, 32768 - |x-512|*64)
+ // Threshold 16000 -> left edge at x=512-(32768-16000)/64=512-262=250
+ // right edge at x=512+262=774
+ function automatic [31:0] pow_peak(input [31:0] x);
+ int dx;
+ int p;
+ dx = (x > 512) ? (x - 512) : (512 - x);
+ p = 32768 - dx * 64;
+ if (p < 0) p = 0;
+ return p;
+ endfunction
+
+ function automatic [31:0] pow_dip(input [31:0] x);
+ int dx;
+ int p;
+ dx = (x > 512) ? (x - 512) : (512 - x);
+ p = dx * 64;
+ if (p > 32768) p = 32768;
+ return p;
+ endfunction
+
+ task automatic do_init(input [X_WIDTH-1:0] lo, input [X_WIDTH-1:0] hi,
+ input s_left, input p_peak,
+ input [X_WIDTH-1:0] tol);
+ @(posedge clk);
+ init <= 1;
+ lo_init <= lo;
+ hi_init <= hi;
+ side_left <= s_left;
+ polarity_peak <= p_peak;
+ tol_in <= tol;
+ @(posedge clk);
+ init <= 0;
+ endtask
+
+ task automatic do_step(input [X_WIDTH-1:0] mid_x,
+ input bit peak);
+ int t;
+ @(posedge clk);
+ pow_mid <= peak ? pow_peak(mid_x) : pow_dip(mid_x);
+ pow_thr <= 32'd16000;
+ step <= 1;
+ @(posedge clk);
+ step <= 0;
+ t = 0;
+ while (!valid_o && t < 16) begin @(posedge clk); t++; end
+ endtask
+
+ task automatic check_range(input string n,
+ input [X_WIDTH-1:0] lo,
+ input [X_WIDTH-1:0] hi,
+ input [X_WIDTH-1:0] target);
+ if (lo <= target && target <= hi) begin
+ $display("[%0t] PASS %s: [%0d, %0d] contains %0d",
+ $time, n, lo, hi, target);
+ passes++;
+ end else begin
+ $display("[%0t] FAIL %s: [%0d, %0d] does NOT contain %0d",
+ $time, n, lo, hi, target);
+ errors++;
+ end
+ endtask
+
+ task automatic run_bisect(input bit s_left, input bit p_peak,
+ input [X_WIDTH-1:0] target_edge);
+ do_init(LO0, HI0, s_left, p_peak, TOL);
+ repeat (3) @(posedge clk);
+ for (int i = 0; i < 20; i++) begin
+ if (converged_o) break;
+ do_step(mid_next, p_peak);
+ end
+ check_range($sformatf("polarity=%0d side_left=%0d", p_peak, s_left),
+ lo_o, hi_o, target_edge);
+ endtask
+
+ initial begin
+ rst_n = 0;
+ init = 0; step = 0;
+ lo_init = 0; hi_init = 0; tol_in = 0;
+ side_left = 0; polarity_peak = 0;
+ pow_mid = 0; pow_thr = 0;
+ repeat (5) @(posedge clk);
+ rst_n = 1;
+ repeat (3) @(posedge clk);
+
+ // peak / left edge -> ~250
+ $display("---- run peak/left ----");
+ run_bisect(1'b1, 1'b1, 32'd250);
+
+ // peak / right edge -> ~774
+ $display("---- run peak/right ----");
+ run_bisect(1'b0, 1'b1, 32'd774);
+
+ // dip / left edge -> ~250
+ $display("---- run dip/left ----");
+ run_bisect(1'b1, 1'b0, 32'd250);
+
+ // dip / right edge -> ~774
+ $display("---- run dip/right ----");
+ run_bisect(1'b0, 1'b0, 32'd774);
+
+ $display("==== tb_bisect_control done: %0d passes, %0d errors ====",
+ passes, errors);
+ if (errors == 0) $display("RESULT: ALL PASS");
+ else $display("RESULT: %0d FAIL", errors);
+ $finish;
+ end
+
+ initial begin
+ #200000;
+ $display("[%0t] WATCHDOG: simulation timeout", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/tb/tb_iq_power.sv b/firmware/ip/adaptive_sweep/src/tb/tb_iq_power.sv
new file mode 100644
index 000000000..cefa8bb14
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/tb/tb_iq_power.sv
@@ -0,0 +1,139 @@
+`timescale 1ns / 1ps
+//
+// tb_iq_power.sv
+//
+// Unit testbench for iq_power.v. Streams a small set of (I, Q) corner
+// vectors and checks power_o == I*I + Q*Q for each, with the documented
+// 3-cycle latency.
+//
+
+module tb_iq_power;
+
+ localparam int IQ_WIDTH = 16;
+ localparam int POW_WIDTH = 32;
+ localparam int LAT = 3; // pipeline latency in cycles
+
+ logic clk;
+ logic rst_n;
+ logic signed [IQ_WIDTH-1:0] i_in, q_in;
+ logic valid_in;
+ logic [POW_WIDTH-1:0] power_o;
+ logic valid_o;
+
+ // Reference shift register so we can compare delayed input to current output
+ logic signed [IQ_WIDTH-1:0] i_pipe [0:LAT-1];
+ logic signed [IQ_WIDTH-1:0] q_pipe [0:LAT-1];
+ logic v_pipe [0:LAT-1];
+
+ int errors = 0;
+ int passes = 0;
+
+ initial clk = 0;
+ always #5 clk = ~clk;
+
+ iq_power #(
+ .IQ_WIDTH (IQ_WIDTH),
+ .POW_WIDTH(POW_WIDTH)
+ ) dut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .i_in (i_in),
+ .q_in (q_in),
+ .valid_in(valid_in),
+ .power_o (power_o),
+ .valid_o (valid_o)
+ );
+
+ // shift the pipeline every cycle
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ for (int k = 0; k < LAT; k++) begin
+ i_pipe[k] <= '0;
+ q_pipe[k] <= '0;
+ v_pipe[k] <= 1'b0;
+ end
+ end else begin
+ i_pipe[0] <= i_in;
+ q_pipe[0] <= q_in;
+ v_pipe[0] <= valid_in;
+ for (int k = 1; k < LAT; k++) begin
+ i_pipe[k] <= i_pipe[k-1];
+ q_pipe[k] <= q_pipe[k-1];
+ v_pipe[k] <= v_pipe[k-1];
+ end
+ end
+ end
+
+ // Continuous self-check: when valid_o goes high, power_o must equal
+ // (i_pipe[LAT-1])^2 + (q_pipe[LAT-1])^2
+ always @(posedge clk) begin
+ if (rst_n && valid_o) begin
+ automatic logic [POW_WIDTH-1:0] expected =
+ $signed(i_pipe[LAT-1]) * $signed(i_pipe[LAT-1]) +
+ $signed(q_pipe[LAT-1]) * $signed(q_pipe[LAT-1]);
+ if (power_o === expected) begin
+ passes++;
+ end else begin
+ $display("[%0t] FAIL: I=%0d Q=%0d -> got=%0d exp=%0d",
+ $time, i_pipe[LAT-1], q_pipe[LAT-1],
+ power_o, expected);
+ errors++;
+ end
+ end
+ end
+
+ task automatic drive(input signed [IQ_WIDTH-1:0] iv,
+ input signed [IQ_WIDTH-1:0] qv);
+ @(posedge clk);
+ i_in <= iv;
+ q_in <= qv;
+ valid_in <= 1'b1;
+ @(posedge clk);
+ valid_in <= 1'b0;
+ i_in <= '0;
+ q_in <= '0;
+ endtask
+
+ initial begin
+ rst_n = 0;
+ i_in = 0;
+ q_in = 0;
+ valid_in = 0;
+ repeat (5) @(posedge clk);
+ rst_n = 1;
+ repeat (3) @(posedge clk);
+
+ // Corner cases
+ drive( 0, 0);
+ drive( 16'sh7FFF, 0); // max positive I
+ drive( 0, 16'sh7FFF); // max positive Q
+ drive(-16'sh8000, 0); // max negative I
+ drive( 0, -16'sh8000); // max negative Q
+ drive( 16'sh7FFF, 16'sh7FFF); // both max positive
+ drive(-16'sh8000, -16'sh8000); // both max negative
+ drive( 16'sd100, 16'sd200); // small values
+ drive(-16'sd100, 16'sd200); // mixed signs
+ drive( 16'sd1234, -16'sd5678);
+
+ // Random walk
+ for (int n = 0; n < 64; n++) begin
+ drive($random, $random);
+ end
+
+ // Drain pipeline
+ repeat (LAT + 5) @(posedge clk);
+
+ $display("==== tb_iq_power done: %0d passes, %0d errors ====",
+ passes, errors);
+ if (errors == 0) $display("RESULT: ALL PASS");
+ else $display("RESULT: %0d FAIL", errors);
+ $finish;
+ end
+
+ initial begin
+ #20000;
+ $display("[%0t] WATCHDOG: simulation timeout", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/tb/tb_kw_steps.sv b/firmware/ip/adaptive_sweep/src/tb/tb_kw_steps.sv
new file mode 100644
index 000000000..407c265de
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/tb/tb_kw_steps.sv
@@ -0,0 +1,214 @@
+`timescale 1ns / 1ps
+//
+// tb_kw_steps.sv
+//
+// Unit testbench for kw_steps.v. Exercises:
+// T1: load LUT with halve-every-16 schedule (AK0=1000)
+// T2: dp_signed > 0 -> x increases by LUT[k]
+// T3: dp_signed < 0 -> x decreases by LUT[k]
+// T4: dp_signed = 0 -> x unchanged, conv_flag=1
+// T5: x_sum below x_min -> clamp to x_min
+// T6: x_sum above x_max -> clamp to x_max
+// T7: conv_flag asserts when |LUT[k]| < KW_TOL
+//
+
+module tb_kw_steps;
+
+ localparam int X_WIDTH = 32;
+ localparam int LUT_DEPTH = 256;
+ localparam int LUT_AW = 8;
+ localparam [X_WIDTH-1:0] KW_TOL = 32'h0000_07D0; // 2000
+
+ localparam int LAT = 5; // step_trigger -> valid_o latency
+
+ logic clk;
+ logic rst_n;
+ logic lut_we;
+ logic [LUT_AW-1:0] lut_addr;
+ logic signed [X_WIDTH-1:0] lut_din;
+ logic step_trigger;
+ logic signed [X_WIDTH-1:0] dp_signed;
+ logic [LUT_AW-1:0] k_idx;
+ logic signed [X_WIDTH-1:0] x_in, x_min, x_max;
+ logic signed [X_WIDTH-1:0] x_out;
+ logic conv_flag;
+ logic valid_o;
+
+ int errors = 0, passes = 0;
+
+ initial clk = 0;
+ always #5 clk = ~clk;
+
+ kw_steps #(
+ .X_WIDTH (X_WIDTH),
+ .LUT_DEPTH(LUT_DEPTH),
+ .LUT_AW (LUT_AW),
+ .KW_TOL (KW_TOL)
+ ) dut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .lut_we (lut_we),
+ .lut_addr (lut_addr),
+ .lut_din (lut_din),
+ .step_trigger(step_trigger),
+ .dp_signed (dp_signed),
+ .k_idx (k_idx),
+ .x_in (x_in),
+ .x_min (x_min),
+ .x_max (x_max),
+ .x_out (x_out),
+ .conv_flag (conv_flag),
+ .valid_o (valid_o)
+ );
+
+ // ---------------- Helpers ----------------
+ task automatic load_lut(input [LUT_AW-1:0] addr,
+ input signed [X_WIDTH-1:0] val);
+ @(posedge clk);
+ lut_we <= 1'b1;
+ lut_addr <= addr;
+ lut_din <= val;
+ @(posedge clk);
+ lut_we <= 1'b0;
+ endtask
+
+ task automatic do_step(input signed [X_WIDTH-1:0] dp,
+ input [LUT_AW-1:0] kk,
+ input signed [X_WIDTH-1:0] xi,
+ input signed [X_WIDTH-1:0] xmn,
+ input signed [X_WIDTH-1:0] xmx,
+ output signed [X_WIDTH-1:0] xo,
+ output cf);
+ int t;
+ @(posedge clk);
+ dp_signed <= dp;
+ k_idx <= kk;
+ x_in <= xi;
+ x_min <= xmn;
+ x_max <= xmx;
+ step_trigger <= 1'b1;
+ @(posedge clk);
+ step_trigger <= 1'b0;
+ // wait for valid_o
+ t = 0;
+ while (!valid_o && t < 32) begin
+ @(posedge clk);
+ t++;
+ end
+ if (!valid_o) begin
+ $display("[%0t] ERROR: timeout waiting for valid_o", $time);
+ errors++;
+ xo = 0; cf = 0;
+ end else begin
+ xo = x_out;
+ cf = conv_flag;
+ end
+ endtask
+
+ task automatic check_int(input string n,
+ input signed [X_WIDTH-1:0] got,
+ input signed [X_WIDTH-1:0] exp);
+ if (got === exp) begin
+ $display("[%0t] PASS %s: %0d", $time, n, got);
+ passes++;
+ end else begin
+ $display("[%0t] FAIL %s: got=%0d exp=%0d", $time, n, got, exp);
+ errors++;
+ end
+ endtask
+
+ task automatic check_bit(input string n, input got, input exp);
+ if (got === exp) begin
+ $display("[%0t] PASS %s: %0b", $time, n, got);
+ passes++;
+ end else begin
+ $display("[%0t] FAIL %s: got=%0b exp=%0b", $time, n, got, exp);
+ errors++;
+ end
+ endtask
+
+ // ---------------- Stimulus ----------------
+ signed [X_WIDTH-1:0] xo;
+ bit cf;
+
+ initial begin
+ rst_n = 0;
+ lut_we = 0;
+ lut_addr = 0;
+ lut_din = 0;
+ step_trigger = 0;
+ dp_signed = 0;
+ k_idx = 0;
+ x_in = 0;
+ x_min = 0;
+ x_max = 0;
+ repeat (5) @(posedge clk);
+ rst_n = 1;
+ repeat (3) @(posedge clk);
+
+ // T1: load LUT with halve-every-16 schedule (AK0=1000)
+ $display("---- T1: load LUT ----");
+ for (int k = 0; k < 256; k++) begin
+ int sh;
+ sh = k / 16; // halve every 16
+ load_lut(k[LUT_AW-1:0], 32'sd1000 >>> sh);
+ end
+
+ // T2: dp > 0, k=0 -> step = +1000, x: 5000 -> 6000.
+ // |step|=1000 < KW_TOL=2000 -> conv=1.
+ $display("---- T2: dp>0 ----");
+ do_step(32'sd100, 8'd0, 32'sd5000, -32'sd1000000, 32'sd1000000, xo, cf);
+ check_int("T2.x_out", xo, 32'sd6000);
+ check_bit("T2.conv_flag", cf, 1'b1);
+
+ // T3: dp<0, k=0 -> step = -1000, x: 5000 -> 4000
+ $display("---- T3: dp<0 ----");
+ do_step(-32'sd100, 8'd0, 32'sd5000, -32'sd1000000, 32'sd1000000, xo, cf);
+ check_int("T3.x_out", xo, 32'sd4000);
+
+ // T4: dp=0 -> step=0, x unchanged, conv=1
+ $display("---- T4: dp=0 ----");
+ do_step(32'sd0, 8'd0, 32'sd5000, -32'sd1000000, 32'sd1000000, xo, cf);
+ check_int("T4.x_out", xo, 32'sd5000);
+ check_bit("T4.conv_flag", cf, 1'b1);
+
+ // T5: clamp to x_min
+ $display("---- T5: clamp to x_min ----");
+ do_step(-32'sd1, 8'd0, 32'sd100, 32'sd0, 32'sd1000000, xo, cf);
+ // step = -1000, x_in = 100, x_sum = -900, clamp to x_min=0
+ check_int("T5.x_out", xo, 32'sd0);
+
+ // T6: clamp to x_max
+ $display("---- T6: clamp to x_max ----");
+ do_step(32'sd1, 8'd0, 32'sd999900, 32'sd0, 32'sd1000000, xo, cf);
+ // step = +1000, x_in = 999900, x_sum = 1000900, clamp to x_max=1000000
+ check_int("T6.x_out", xo, 32'sd1000000);
+
+ // T7: conv flag for |step| sh=5 -> step=1000>>5=31, conv=1)
+ $display("---- T7: conv_flag asserts ----");
+ do_step(32'sd1, 8'd80, 32'sd5000, -32'sd1000000, 32'sd1000000, xo, cf);
+ check_bit("T7.conv_flag", cf, 1'b1);
+
+ // Conv flag does NOT assert for k=0 since 1000<2000? actually 1000<2000 IS true,
+ // so conv=1 at k=0 too. Use a smaller tol or larger LUT entries to test the
+ // "not converged" branch:
+ load_lut(8'd5, 32'sd5000); // bigger than KW_TOL=2000
+ $display("---- T7b: conv_flag negates ----");
+ do_step(32'sd1, 8'd5, 32'sd5000, -32'sd1000000, 32'sd1000000, xo, cf);
+ check_int("T7b.x_out", xo, 32'sd10000);
+ check_bit("T7b.conv_flag", cf, 1'b0); // |5000|>=2000 -> not converged
+
+ $display("==== tb_kw_steps done: %0d passes, %0d errors ====",
+ passes, errors);
+ if (errors == 0) $display("RESULT: ALL PASS");
+ else $display("RESULT: %0d FAIL", errors);
+ $finish;
+ end
+
+ initial begin
+ #100000;
+ $display("[%0t] WATCHDOG: simulation timeout", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/tb/tb_polyak_avg.sv b/firmware/ip/adaptive_sweep/src/tb/tb_polyak_avg.sv
new file mode 100644
index 000000000..b7a2d1be6
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/tb/tb_polyak_avg.sv
@@ -0,0 +1,212 @@
+`timescale 1ns / 1ps
+//
+// tb_polyak_avg.sv
+//
+// Unit testbench for polyak_averager.v. Exercises:
+// T1: 16 constant samples (positive) -> xbar == sample
+// T2: 16 ramp samples 1..16 -> xbar == 8 (floor of 8.5)
+// T3: 16 negative samples -> xbar == sample (signed)
+// T4: two back-to-back chunks -> chunk_close fires twice,
+// xbar_delta_o tracks change
+// T5: soft_reset clears state -> next chunk starts fresh
+//
+// Pass criterion: every assertion holds (counted) and $finish reached.
+// 100 MHz clock (10 ns) — exact value irrelevant for behavior, RFSoC
+// timing closure is checked in synthesis, not simulation.
+//
+
+module tb_polyak_avg;
+
+ // ----------------- Parameters -----------------
+ localparam integer SAMPLE_WIDTH = 16;
+ localparam integer SUM_WIDTH = 48;
+ localparam integer AVG_WIDTH = 32;
+ localparam integer RECIP_WIDTH = 32;
+ localparam integer COUNT_WIDTH = 16;
+
+ // For n_avg = 16: reciprocal = ceil(2^32 / 16) = 268_435_456
+ localparam logic [RECIP_WIDTH-1:0] RECIP_16 = 32'd268435456;
+ localparam logic [3:0] CHUNK_LOG2_16 = 4'd4;
+
+ // ----------------- DUT signals -----------------
+ logic clk;
+ logic rst_n;
+ logic signed [SAMPLE_WIDTH-1:0] sample_in;
+ logic sample_valid;
+ logic [RECIP_WIDTH-1:0] reciprocal_in;
+ logic [3:0] chunk_size_log2;
+ logic soft_reset;
+ logic signed [AVG_WIDTH-1:0] xbar_o;
+ logic [AVG_WIDTH-1:0] xbar_delta_o;
+ logic [COUNT_WIDTH-1:0] count_o;
+ logic valid_o;
+
+ // ----------------- Bookkeeping -----------------
+ int errors = 0;
+ int passes = 0;
+
+ // ----------------- Clock -----------------
+ initial clk = 0;
+ always #5 clk = ~clk; // 100 MHz
+
+ // ----------------- DUT -----------------
+ polyak_averager #(
+ .SAMPLE_WIDTH (SAMPLE_WIDTH),
+ .SUM_WIDTH (SUM_WIDTH),
+ .AVG_WIDTH (AVG_WIDTH),
+ .RECIP_WIDTH (RECIP_WIDTH),
+ .COUNT_WIDTH (COUNT_WIDTH)
+ ) dut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .sample_in (sample_in),
+ .sample_valid (sample_valid),
+ .reciprocal_in (reciprocal_in),
+ .chunk_size_log2 (chunk_size_log2),
+ .soft_reset (soft_reset),
+ .xbar_o (xbar_o),
+ .xbar_delta_o (xbar_delta_o),
+ .count_o (count_o),
+ .valid_o (valid_o)
+ );
+
+ // ----------------- Tasks -----------------
+ task automatic feed_sample(input signed [SAMPLE_WIDTH-1:0] v);
+ @(posedge clk);
+ sample_in <= v;
+ sample_valid <= 1'b1;
+ @(posedge clk);
+ sample_valid <= 1'b0;
+ endtask
+
+ // wait until valid_o pulses (1 cycle pulse), capture xbar
+ task automatic wait_for_valid(output signed [AVG_WIDTH-1:0] xbar_captured,
+ output [AVG_WIDTH-1:0] delta_captured);
+ int timeout;
+ timeout = 0;
+ while (!valid_o && timeout < 200) begin
+ @(posedge clk);
+ timeout++;
+ end
+ if (!valid_o) begin
+ $display("[%0t] ERROR: timeout waiting for valid_o", $time);
+ errors++;
+ end else begin
+ xbar_captured = xbar_o;
+ delta_captured = xbar_delta_o;
+ end
+ @(posedge clk);
+ endtask
+
+ task automatic check(input string name,
+ input signed [AVG_WIDTH-1:0] got,
+ input signed [AVG_WIDTH-1:0] exp,
+ input integer tol);
+ if (got > exp ? (got - exp) : (exp - got) <= tol) begin
+ $display("[%0t] PASS %s: got=%0d exp=%0d (tol=%0d)",
+ $time, name, got, exp, tol);
+ passes++;
+ end else begin
+ $display("[%0t] FAIL %s: got=%0d exp=%0d (tol=%0d)",
+ $time, name, got, exp, tol);
+ errors++;
+ end
+ endtask
+
+ task automatic do_soft_reset();
+ @(posedge clk);
+ soft_reset <= 1'b1;
+ @(posedge clk);
+ soft_reset <= 1'b0;
+ endtask
+
+ // ----------------- Stimulus -----------------
+ signed [AVG_WIDTH-1:0] xbar_cap;
+ [AVG_WIDTH-1:0] delta_cap;
+
+ initial begin
+ // Init
+ rst_n = 0;
+ sample_in = 0;
+ sample_valid = 0;
+ reciprocal_in = RECIP_16;
+ chunk_size_log2 = CHUNK_LOG2_16;
+ soft_reset = 0;
+ repeat (5) @(posedge clk);
+ rst_n = 1;
+ repeat (3) @(posedge clk);
+
+ // -----------------------------------------
+ // T1: 16 constant samples == 100 -> xbar==100
+ // -----------------------------------------
+ $display("---- T1: constant 100 ----");
+ for (int i = 0; i < 16; i++) feed_sample(16'sd100);
+ wait_for_valid(xbar_cap, delta_cap);
+ check("T1.xbar", xbar_cap, 32'sd100, 1);
+
+ // -----------------------------------------
+ // T2: ramp 1..16 -> sum=136, xbar=floor(136/16)=8
+ // -----------------------------------------
+ $display("---- T2: ramp 1..16 ----");
+ do_soft_reset();
+ for (int i = 1; i <= 16; i++) feed_sample(i);
+ wait_for_valid(xbar_cap, delta_cap);
+ check("T2.xbar", xbar_cap, 32'sd8, 1);
+
+ // -----------------------------------------
+ // T3: 16 samples == -250 -> xbar == -250
+ // -----------------------------------------
+ $display("---- T3: constant -250 ----");
+ do_soft_reset();
+ for (int i = 0; i < 16; i++) feed_sample(-16'sd250);
+ wait_for_valid(xbar_cap, delta_cap);
+ check("T3.xbar", xbar_cap, -32'sd250, 1);
+
+ // -----------------------------------------
+ // T4: two back-to-back chunks, second chunk has different value
+ // -----------------------------------------
+ $display("---- T4: two chunks 100 then 200 ----");
+ do_soft_reset();
+ for (int i = 0; i < 16; i++) feed_sample(16'sd100);
+ wait_for_valid(xbar_cap, delta_cap);
+ check("T4.first.xbar", xbar_cap, 32'sd100, 1);
+ for (int i = 0; i < 16; i++) feed_sample(16'sd200);
+ wait_for_valid(xbar_cap, delta_cap);
+ // Cumulative average across 32 samples: (16*100 + 16*200)/32 = 150
+ // BUT this module averages PER chunk (sum reset implicitly between chunks?).
+ // Our implementation lets `sum` accumulate across chunks, so second-chunk
+ // sum = 16*100 + 16*200 = 4800; xbar = 4800 * recip / 2^32.
+ // recip is for n=16, so xbar ~= 4800 / 16 = 300 (not 150).
+ // The "running average" interpretation would need the ARM to update recip.
+ // For this TB we verify the documented behavior: sum carries over.
+ check("T4.second.xbar(carried-sum)", xbar_cap, 32'sd300, 2);
+ // delta vs first xbar (100) -> ~200
+ check("T4.delta", $signed(delta_cap), 32'sd200, 2);
+
+ // -----------------------------------------
+ // T5: soft_reset clears state, third chunk all 50 -> xbar=50
+ // -----------------------------------------
+ $display("---- T5: soft_reset then constant 50 ----");
+ do_soft_reset();
+ for (int i = 0; i < 16; i++) feed_sample(16'sd50);
+ wait_for_valid(xbar_cap, delta_cap);
+ check("T5.xbar", xbar_cap, 32'sd50, 1);
+
+ // -----------------------------------------
+ // Summary
+ // -----------------------------------------
+ $display("==== tb_polyak_avg done: %0d passes, %0d errors ====",
+ passes, errors);
+ if (errors == 0) $display("RESULT: ALL PASS");
+ else $display("RESULT: %0d FAIL", errors);
+ $finish;
+ end
+
+ // ----------------- Watchdog -----------------
+ initial begin
+ #50000;
+ $display("[%0t] WATCHDOG: simulation timeout", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/src/tb/tb_readout_capture.sv b/firmware/ip/adaptive_sweep/src/tb/tb_readout_capture.sv
new file mode 100644
index 000000000..19cb516bb
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/src/tb/tb_readout_capture.sv
@@ -0,0 +1,169 @@
+`timescale 1ns / 1ps
+//
+// tb_readout_capture.sv
+//
+// Unit testbench for readout_capture.v. Generates ro_clk = 307.2 MHz and
+// c_clk = 200 MHz, drives a stream of indexed I/Q samples on the ro_clk
+// AXIS slave port, fires a trigger mid-stream, and verifies that exactly
+// n_samples samples cross to the c_clk side in order.
+//
+
+module tb_readout_capture;
+
+ localparam int IQ_WIDTH = 16;
+ localparam int FIFO_DEPTH_LOG2 = 6;
+ localparam int COUNT_WIDTH = 16;
+ localparam int N_SAMPLES = 16;
+
+ // Clocks
+ logic clk;
+ logic ro_clk;
+ initial clk = 0;
+ initial ro_clk = 0;
+ always #2.5 clk = ~clk; // 200 MHz
+ always #1.6275 ro_clk = ~ro_clk; // ~307.2 MHz
+
+ // Resets
+ logic rst_n;
+ logic ro_aresetn;
+
+ // c_clk control
+ logic arm_pulse;
+ logic [COUNT_WIDTH-1:0] n_samples;
+ logic capture_done;
+ logic signed [IQ_WIDTH-1:0] i_out, q_out;
+ logic iq_valid;
+ logic iq_ready;
+ logic [COUNT_WIDTH-1:0] samples_remaining;
+
+ // ro_clk AXIS
+ logic [2*IQ_WIDTH-1:0] ro_tdata;
+ logic ro_tvalid;
+ logic ro_tready;
+ logic trigger;
+
+ int errors = 0, passes = 0;
+
+ readout_capture #(
+ .IQ_WIDTH (IQ_WIDTH),
+ .FIFO_DEPTH_LOG2(FIFO_DEPTH_LOG2),
+ .COUNT_WIDTH (COUNT_WIDTH)
+ ) dut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .arm_pulse (arm_pulse),
+ .n_samples (n_samples),
+ .capture_done_o (capture_done),
+ .i_out (i_out),
+ .q_out (q_out),
+ .iq_valid (iq_valid),
+ .iq_ready (iq_ready),
+ .samples_remaining(samples_remaining),
+
+ .s_ro_axis_aclk (ro_clk),
+ .s_ro_axis_aresetn (ro_aresetn),
+ .s_ro_axis_tdata (ro_tdata),
+ .s_ro_axis_tvalid (ro_tvalid),
+ .s_ro_axis_tready (ro_tready),
+ .trigger_i (trigger)
+ );
+
+ // Continuous I/Q stream on ro_clk. i = counter, q = -counter.
+ int sample_cnt;
+ always @(posedge ro_clk) begin
+ if (!ro_aresetn) begin
+ sample_cnt <= 0;
+ ro_tdata <= '0;
+ ro_tvalid <= 1'b0;
+ end else begin
+ ro_tvalid <= 1'b1;
+ // Q in upper, I in lower
+ ro_tdata <= {(-sample_cnt[IQ_WIDTH-1:0]), sample_cnt[IQ_WIDTH-1:0]};
+ sample_cnt <= sample_cnt + 1;
+ end
+ end
+
+ // Drain the FIFO at full rate so we observe every captured sample
+ assign iq_ready = 1'b1;
+
+ // Capture observed samples for checking
+ int observed = 0;
+ int first_i = -1;
+ always @(posedge clk) begin
+ if (rst_n && iq_valid && iq_ready) begin
+ if (first_i == -1) first_i = i_out;
+ observed <= observed + 1;
+ end
+ end
+
+ initial begin
+ rst_n = 0;
+ ro_aresetn = 0;
+ arm_pulse = 0;
+ n_samples = N_SAMPLES;
+ trigger = 0;
+ observed = 0;
+ first_i = -1;
+ repeat (10) @(posedge clk);
+ rst_n = 1;
+ ro_aresetn = 1;
+ repeat (20) @(posedge clk);
+
+ // Arm capture
+ @(posedge clk);
+ arm_pulse <= 1;
+ @(posedge clk);
+ arm_pulse <= 0;
+
+ // Wait some ro_clk cycles, then fire trigger
+ repeat (50) @(posedge ro_clk);
+ @(posedge ro_clk);
+ trigger <= 1;
+ @(posedge ro_clk);
+ trigger <= 0;
+
+ // Wait for capture_done
+ begin
+ int t;
+ t = 0;
+ while (!capture_done && t < 5000) begin
+ @(posedge clk);
+ t++;
+ end
+ if (!capture_done) begin
+ $display("[%0t] FAIL: capture_done never asserted", $time);
+ errors++;
+ end else begin
+ $display("[%0t] PASS: capture_done asserted", $time);
+ passes++;
+ end
+ end
+
+ // Drain FIFO
+ repeat (200) @(posedge clk);
+
+ // Check exactly N_SAMPLES were observed
+ if (observed === N_SAMPLES) begin
+ $display("[%0t] PASS: observed=%0d == N_SAMPLES=%0d",
+ $time, observed, N_SAMPLES);
+ passes++;
+ end else begin
+ $display("[%0t] FAIL: observed=%0d != N_SAMPLES=%0d",
+ $time, observed, N_SAMPLES);
+ errors++;
+ end
+
+ $display("==== tb_readout_capture done: %0d passes, %0d errors ====",
+ passes, errors);
+ if (errors == 0) $display("RESULT: ALL PASS");
+ else $display("RESULT: %0d FAIL", errors);
+ $finish;
+ end
+
+ initial begin
+ #1000000;
+ $display("[%0t] WATCHDOG: simulation timeout", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/adaptive_sweep/xgui/adaptive_sweep_v1_0.tcl b/firmware/ip/adaptive_sweep/xgui/adaptive_sweep_v1_0.tcl
new file mode 100644
index 000000000..25a1ee5d1
--- /dev/null
+++ b/firmware/ip/adaptive_sweep/xgui/adaptive_sweep_v1_0.tcl
@@ -0,0 +1,136 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+proc update_PARAM_VALUE.COUNT_WIDTH { PARAM_VALUE.COUNT_WIDTH } {
+ # Procedure called to update COUNT_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.COUNT_WIDTH { PARAM_VALUE.COUNT_WIDTH } {
+ # Procedure called to validate COUNT_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.IQ_WIDTH { PARAM_VALUE.IQ_WIDTH } {
+ # Procedure called to update IQ_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.IQ_WIDTH { PARAM_VALUE.IQ_WIDTH } {
+ # Procedure called to validate IQ_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.KW_TOL { PARAM_VALUE.KW_TOL } {
+ # Procedure called to update KW_TOL when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.KW_TOL { PARAM_VALUE.KW_TOL } {
+ # Procedure called to validate KW_TOL
+ return true
+}
+
+proc update_PARAM_VALUE.LUT_AW { PARAM_VALUE.LUT_AW } {
+ # Procedure called to update LUT_AW when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.LUT_AW { PARAM_VALUE.LUT_AW } {
+ # Procedure called to validate LUT_AW
+ return true
+}
+
+proc update_PARAM_VALUE.LUT_DEPTH { PARAM_VALUE.LUT_DEPTH } {
+ # Procedure called to update LUT_DEPTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.LUT_DEPTH { PARAM_VALUE.LUT_DEPTH } {
+ # Procedure called to validate LUT_DEPTH
+ return true
+}
+
+proc update_PARAM_VALUE.POW_WIDTH { PARAM_VALUE.POW_WIDTH } {
+ # Procedure called to update POW_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.POW_WIDTH { PARAM_VALUE.POW_WIDTH } {
+ # Procedure called to validate POW_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.RO_FIFO_DEPTH_LOG2 { PARAM_VALUE.RO_FIFO_DEPTH_LOG2 } {
+ # Procedure called to update RO_FIFO_DEPTH_LOG2 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.RO_FIFO_DEPTH_LOG2 { PARAM_VALUE.RO_FIFO_DEPTH_LOG2 } {
+ # Procedure called to validate RO_FIFO_DEPTH_LOG2
+ return true
+}
+
+proc update_PARAM_VALUE.SUM_WIDTH { PARAM_VALUE.SUM_WIDTH } {
+ # Procedure called to update SUM_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SUM_WIDTH { PARAM_VALUE.SUM_WIDTH } {
+ # Procedure called to validate SUM_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.X_WIDTH { PARAM_VALUE.X_WIDTH } {
+ # Procedure called to update X_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.X_WIDTH { PARAM_VALUE.X_WIDTH } {
+ # Procedure called to validate X_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.LUT_DEPTH { MODELPARAM_VALUE.LUT_DEPTH PARAM_VALUE.LUT_DEPTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.LUT_DEPTH}] ${MODELPARAM_VALUE.LUT_DEPTH}
+}
+
+proc update_MODELPARAM_VALUE.LUT_AW { MODELPARAM_VALUE.LUT_AW PARAM_VALUE.LUT_AW } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.LUT_AW}] ${MODELPARAM_VALUE.LUT_AW}
+}
+
+proc update_MODELPARAM_VALUE.X_WIDTH { MODELPARAM_VALUE.X_WIDTH PARAM_VALUE.X_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.X_WIDTH}] ${MODELPARAM_VALUE.X_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.IQ_WIDTH { MODELPARAM_VALUE.IQ_WIDTH PARAM_VALUE.IQ_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.IQ_WIDTH}] ${MODELPARAM_VALUE.IQ_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.SUM_WIDTH { MODELPARAM_VALUE.SUM_WIDTH PARAM_VALUE.SUM_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.SUM_WIDTH}] ${MODELPARAM_VALUE.SUM_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.POW_WIDTH { MODELPARAM_VALUE.POW_WIDTH PARAM_VALUE.POW_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.POW_WIDTH}] ${MODELPARAM_VALUE.POW_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.COUNT_WIDTH { MODELPARAM_VALUE.COUNT_WIDTH PARAM_VALUE.COUNT_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.COUNT_WIDTH}] ${MODELPARAM_VALUE.COUNT_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.RO_FIFO_DEPTH_LOG2 { MODELPARAM_VALUE.RO_FIFO_DEPTH_LOG2 PARAM_VALUE.RO_FIFO_DEPTH_LOG2 } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.RO_FIFO_DEPTH_LOG2}] ${MODELPARAM_VALUE.RO_FIFO_DEPTH_LOG2}
+}
+
+proc update_MODELPARAM_VALUE.KW_TOL { MODELPARAM_VALUE.KW_TOL PARAM_VALUE.KW_TOL } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.KW_TOL}] ${MODELPARAM_VALUE.KW_TOL}
+}
+
diff --git a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci
index 350ae6412..2c16196a6 100644
--- a/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_avg_buffer/src/axi_mst_0/axi_mst_0.xci
@@ -64,7 +64,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/ip/axis_buffer_ddr/src/tb/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_buffer_ddr/src/tb/axi_mst_0/axi_mst_0.xci
index 88ccced05..59d2d41ac 100644
--- a/firmware/ip/axis_buffer_ddr/src/tb/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_buffer_ddr/src/tb/axi_mst_0/axi_mst_0.xci
@@ -64,7 +64,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/ip/axis_buffer_ddr/src/tb/axi_slv_0/axi_slv_0.xci b/firmware/ip/axis_buffer_ddr/src/tb/axi_slv_0/axi_slv_0.xci
index 3a16abf68..59254a729 100644
--- a/firmware/ip/axis_buffer_ddr/src/tb/axi_slv_0/axi_slv_0.xci
+++ b/firmware/ip/axis_buffer_ddr/src/tb/axi_slv_0/axi_slv_0.xci
@@ -64,7 +64,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci
index 3c5321ff6..5bd551ba8 100644
--- a/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci
+++ b/firmware/ip/axis_dyn_readout_v1/src/dds_compiler_0/dds_compiler_0.xci
@@ -163,7 +163,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
@@ -183,7 +183,7 @@
"OUTPUTDIR": [ { "value": "../../../../projects/qick_tprocv2_216_demo/top/top.tmp/axis_dyn_readout_v1_v1_0_project/axis_dyn_readout_v1_v1_0_project.gen/sources_1/ip/dds_compiler_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
- "SWVERSION": [ { "value": "2022.1" } ],
+ "SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
diff --git a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci
index b157ab253..59ca585ff 100644
--- a/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci
+++ b/firmware/ip/axis_dyn_readout_v1/src/fir_compiler_0/fir_compiler_0.xci
@@ -163,7 +163,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
@@ -348,4 +348,4 @@
}
}
}
-}
+}
\ No newline at end of file
diff --git a/firmware/ip/axis_kidsim_v3/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_kidsim_v3/src/axi_mst_0/axi_mst_0.xci
index 88ccced05..59d2d41ac 100644
--- a/firmware/ip/axis_kidsim_v3/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_kidsim_v3/src/axi_mst_0/axi_mst_0.xci
@@ -64,7 +64,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/ip/axis_kidsim_v3/src/dds/dds_0/dds_0.xci b/firmware/ip/axis_kidsim_v3/src/dds/dds_0/dds_0.xci
index fd8e3b87e..335e185fa 100644
--- a/firmware/ip/axis_kidsim_v3/src/dds/dds_0/dds_0.xci
+++ b/firmware/ip/axis_kidsim_v3/src/dds/dds_0/dds_0.xci
@@ -163,7 +163,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci
index ac9cf042c..08cc24e40 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/axi_mst_0/axi_mst_0.xci
@@ -130,7 +130,7 @@
0
0
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci
index f65db0d9d..ab024c5f6 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/dds_0/dds_0.xci
@@ -226,7 +226,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_0/fir_0.xci
index 64b9287c7..21c26f0c4 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_0/fir_0.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_0/fir_0.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci
index 1db52de13..a09790f9b 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_1/fir_1.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci
index 0f0a644b8..f73be1298 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_2/fir_2.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci
index d0fd7e8ec..00b43c08c 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_3/fir_3.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci
index 48cef3abb..beec0de16 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_4/fir_4.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci
index be396b4ba..081c8e050 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_5/fir_5.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci
index fb143ce18..c3bad38d2 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_6/fir_6.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci
index bcf4c7433..c8d216e9b 100644
--- a/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci
+++ b/firmware/ip/axis_pfb_readout_v2/src/fir/fir_7/fir_7.xci
@@ -226,7 +226,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci
index 88ccced05..59d2d41ac 100644
--- a/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_pfb_readout_v3/src/axi_mst_0/axi_mst_0.xci
@@ -64,7 +64,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci
index b6e5eac13..a9330cc07 100644
--- a/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci
+++ b/firmware/ip/axis_pfb_readout_v3/src/dds/dds_0/dds_0.xci
@@ -227,7 +227,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci
index 6ef4c7e10..8f5cddc28 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/dds/dds_0/dds_0.xci
@@ -227,7 +227,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci
index d3704deda..d2c321f12 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_0/fir_0.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci
index 09d60320e..b765f36ca 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_1/fir_1.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci
index 6c6b57bf4..b45c6cc1a 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_2/fir_2.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci
index 578e4d745..911d75062 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_3/fir_3.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci
index a711e889a..175dbc4f0 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_4/fir_4.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci
index 7a66fd719..2fd8c149d 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_5/fir_5.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci
index c5d236249..a31722ef1 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_6/fir_6.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci
index f3d90963c..ac48ef057 100644
--- a/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci
+++ b/firmware/ip/axis_pfb_readout_v4/src/pfb/fir/fir_7/fir_7.xci
@@ -227,7 +227,7 @@
0.5
2
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci
index ac9cf042c..08cc24e40 100644
--- a/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_pfba_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci
@@ -130,7 +130,7 @@
0
0
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci
index ac9cf042c..08cc24e40 100644
--- a/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_pfbs_pr_4x256_v1/src/axi_mst_0/axi_mst_0.xci
@@ -130,7 +130,7 @@
0
0
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci
index ac9cf042c..08cc24e40 100644
--- a/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_readout_v2/src/axi_mst_0/axi_mst_0.xci
@@ -130,7 +130,7 @@
0
0
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci
index ac9cf042c..08cc24e40 100644
--- a/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_sg_int4_v1/src/axi_mst_0/axi_mst_0.xci
@@ -130,7 +130,7 @@
0
0
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci
index 562a7638f..a17fb5799 100644
--- a/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci
+++ b/firmware/ip/axis_sg_int4_v1/src/dds_compiler_0/dds_compiler_0.xci
@@ -226,7 +226,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci
index e6289ddc3..708c11914 100644
--- a/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci
+++ b/firmware/ip/axis_sg_int4_v1/src/fir_0/fir_0.xci
@@ -226,7 +226,7 @@
0.5
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci
index 274be99b6..f41a49ad6 100644
--- a/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci
+++ b/firmware/ip/axis_sg_mux4_v1/src/dds_compiler_0/dds_compiler_0.xci
@@ -226,7 +226,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci
index ac9cf042c..08cc24e40 100644
--- a/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_sg_mux4_v2/src/axi_mst_0/axi_mst_0.xci
@@ -130,7 +130,7 @@
0
0
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci
index 6ae4d1670..3215c139e 100644
--- a/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci
+++ b/firmware/ip/axis_sg_mux4_v2/src/dds_compiler_0/dds_compiler_0.xci
@@ -226,7 +226,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci
index 3d3cffbbd..60a49cb87 100644
--- a/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci
+++ b/firmware/ip/axis_sg_mux4_v3/src/dds_compiler_0/dds_compiler_0.xci
@@ -227,7 +227,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci
index ac9cf042c..08cc24e40 100644
--- a/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/axis_signal_gen_v5/src/axi_mst_0/axi_mst_0.xci
@@ -130,7 +130,7 @@
0
0
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci
index 825c3173c..1c6aa12c9 100644
--- a/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci
+++ b/firmware/ip/axis_signal_gen_v5/src/dds_compiler_0/dds_compiler_0.xci
@@ -226,7 +226,7 @@
false
1
zynquplusRFSOC
- xilinx.com:zcu216:part0:2.0
+ realdigital.org:rfsoc4x2:part0:1.0
xczu49dr
ffvf1760
diff --git a/firmware/ip/fine_tuning_sweep/component.xml b/firmware/ip/fine_tuning_sweep/component.xml
new file mode 100644
index 000000000..7b3c98e6f
--- /dev/null
+++ b/firmware/ip/fine_tuning_sweep/component.xml
@@ -0,0 +1,584 @@
+
+
+ emrhnozdemir
+ QICK
+ fine_tuning_sweep
+ 1.0
+
+
+ s_axis
+
+
+
+
+
+
+ TDATA
+
+
+ s_axis_tdata
+
+
+
+
+ TVALID
+
+
+ s_axis_tvalid
+
+
+
+
+ TREADY
+
+
+ s_axis_tready
+
+
+
+
+
+ rst_n
+
+
+
+
+
+
+ RST
+
+
+ rst_n
+
+
+
+
+
+ POLARITY
+ ACTIVE_LOW
+
+
+
+
+ clk
+
+
+
+
+
+
+ CLK
+
+
+ clk
+
+
+
+
+
+ ASSOCIATED_BUSIF
+ qick_peripheral:s_axis
+
+
+ ASSOCIATED_RESET
+ rst_n
+
+
+
+
+ qick_peripheral
+
+
+
+
+
+
+ Enable
+
+
+ qtag_en_i
+
+
+
+
+ Operation
+
+
+ qtag_op_i
+
+
+
+
+ a_dt
+
+
+ qtag_dt1_i
+
+
+
+
+ b_dt
+
+
+ qtag_dt2_i
+
+
+
+
+ c_dt
+
+
+ qtag_dt3_i
+
+
+
+
+ d_dt
+
+
+ qtag_dt4_i
+
+
+
+
+ rdy
+
+
+ qtag_rdy_o
+
+
+
+
+ dt_in_1
+
+
+ qtag_dt1_o
+
+
+
+
+ dt_in_2
+
+
+ qtag_dt2_o
+
+
+
+
+ dt_valid
+
+
+ qtag_vld_o
+
+
+
+
+
+ NUM_READ_OUTSTANDING
+
+
+
+ NUM_WRITE_OUTSTANDING
+
+
+
+
+
+
+
+
+ xilinx_anylanguagesynthesis
+ Synthesis
+ :vivado.xilinx.com:synthesis
+ Verilog
+ fine_tuning_sweep
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+
+
+ viewChecksum
+ 4b193fb0
+
+
+
+
+ xilinx_anylanguagebehavioralsimulation
+ Simulation
+ :vivado.xilinx.com:simulation
+ Verilog
+ fine_tuning_sweep
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+
+
+ viewChecksum
+ 4b193fb0
+
+
+
+
+ xilinx_testbench
+ Test Bench
+ :vivado.xilinx.com:simulation.testbench
+ tb_fine_tuning_sweep
+
+ xilinx_testbench_view_fileset
+
+
+
+ viewChecksum
+ 4102393e
+
+
+
+
+ xilinx_xpgui
+ UI Layout
+ :vivado.xilinx.com:xgui.ui
+
+ xilinx_xpgui_view_fileset
+
+
+
+ viewChecksum
+ ebd328eb
+
+
+
+
+
+
+ clk
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ rst_n
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_en_i
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_op_i
+
+ in
+
+ 4
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt1_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt2_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt3_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt4_i
+
+ in
+
+ 31
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_rdy_o
+
+ out
+
+
+ reg
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt1_o
+
+ out
+
+ 31
+ 0
+
+
+
+ reg
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_dt2_o
+
+ out
+
+ 31
+ 0
+
+
+
+ reg
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ qtag_vld_o
+
+ out
+
+
+ reg
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tvalid
+
+ in
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tready
+
+ out
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+
+
+ s_axis_tdata
+
+ in
+
+ 63
+ 0
+
+
+
+ wire
+ xilinx_anylanguagesynthesis
+ xilinx_anylanguagebehavioralsimulation
+
+
+
+ 0
+
+
+
+
+
+
+
+ choice_list_9d8b0d81
+ ACTIVE_HIGH
+ ACTIVE_LOW
+
+
+
+
+ xilinx_anylanguagesynthesis_view_fileset
+
+ src/amplitude_calculator.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ src/peak_finder.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ src/fine_tuning_sweep.v
+ verilogSource
+ CHECKSUM_3b2fa475
+ IMPORTED_FILE
+
+
+
+ xilinx_anylanguagebehavioralsimulation_view_fileset
+
+ src/amplitude_calculator.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ src/peak_finder.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ src/fine_tuning_sweep.v
+ verilogSource
+ IMPORTED_FILE
+
+
+
+ xilinx_testbench_view_fileset
+
+ src/tb_fine_tuning_sweep.sv
+ systemVerilogSource
+ IMPORTED_FILE
+ USED_IN_simulation
+ USED_IN_testbench
+
+
+
+ xilinx_xpgui_view_fileset
+
+ xgui/fine_tuning_sweep_v1_0.tcl
+ tclSource
+ CHECKSUM_b7d7cb27
+ XGUI_VERSION_2
+
+
+
+ fine_tuning_sweep_v1_0
+
+
+ Component_Name
+ fine_tuning_sweep_v1_0
+
+
+
+
+
+ artix7
+ artix7l
+ aartix7
+ qartix7
+ zynq
+ qzynq
+ azynq
+ zynquplus
+
+
+ /UserIP
+
+ fine_tuning_sweep_v1_0
+ package_project
+ 38
+ 2026-07-15T14:33:00Z
+
+
+ 2023.1
+
+
+
+
+
+
+
diff --git a/firmware/ip/fine_tuning_sweep/src/amplitude_calculator.v b/firmware/ip/fine_tuning_sweep/src/amplitude_calculator.v
new file mode 100644
index 000000000..fd470ecaa
--- /dev/null
+++ b/firmware/ip/fine_tuning_sweep/src/amplitude_calculator.v
@@ -0,0 +1,189 @@
+`timescale 1ns / 1ps
+
+module amplitude_calculator (
+ input wire clk,
+ input wire rst_n,
+
+ input wire s_axis_tvalid,
+ input wire s_axis_tready,
+ input wire [63:0] s_axis_tdata,
+
+ input wire arm,
+ input wire [31:0] averager_value,
+ input wire [31:0] nsamp,
+
+ (* mark_debug = "true" *) output reg [35:0] m_axis_tdata,
+ (* mark_debug = "true" *) output reg m_axis_tvalid
+);
+
+ function [4:0] flog2;
+ input [31:0] v;
+ integer k;
+ begin
+ flog2 = 5'd0;
+ for (k = 1; k <= 31; k = k + 1) begin
+ if (v[k])
+ flog2 = k[4:0];
+ end
+ end
+ endfunction
+
+ (* mark_debug = "true" *) reg signed [31:0] i_in, q_in;
+ (* mark_debug = "true" *) reg v_in, r_in;
+
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ i_in <= 0;
+ q_in <= 0;
+ v_in <= 0;
+ r_in <= 0;
+ end else begin
+ i_in <= s_axis_tdata[31:0];
+ q_in <= s_axis_tdata[63:32];
+ v_in <= s_axis_tvalid;
+ r_in <= s_axis_tready;
+ end
+ end
+
+ (* mark_debug = "true" *) reg armed;
+ (* mark_debug = "true" *) reg [31:0] shot_cnt;
+ (* mark_debug = "true" *) reg [31:0] avg_m1;
+ (* mark_debug = "true" *) reg [4:0] s1_r, s2_r;
+ (* mark_debug = "true" *) reg signed [45:0] i_acc, q_acc;
+ (* mark_debug = "true" *) reg signed [17:0] point_mean_i, point_mean_q;
+
+ wire signed [32:0] i_in_ext = {{1{i_in[31]}}, i_in};
+ wire signed [32:0] q_in_ext = {{1{q_in[31]}}, q_in};
+ wire signed [32:0] round1 = (s1_r == 5'd0) ? {33{1'b0}} : ({{32{1'b0}}, 1'b1} <<< (s1_r - 5'd1));
+ wire signed [32:0] i_shifted1 = (i_in_ext + round1) >>> s1_r;
+ wire signed [32:0] q_shifted1 = (q_in_ext + round1) >>> s1_r;
+ wire signed [16:0] shot_mean_i = i_shifted1[16:0];
+ wire signed [16:0] shot_mean_q = q_shifted1[16:0];
+
+ wire signed [45:0] i_acc_next = i_acc + {{29{shot_mean_i[16]}}, shot_mean_i};
+ wire signed [45:0] q_acc_next = q_acc + {{29{shot_mean_q[16]}}, shot_mean_q};
+
+ wire acc_en = armed & v_in & r_in;
+ wire is_last = (shot_cnt == avg_m1);
+ wire emit_now = acc_en & is_last;
+
+ wire signed [45:0] round2 = (s2_r == 5'd0) ? {46{1'b0}} : ({{45{1'b0}}, 1'b1} <<< (s2_r - 5'd1));
+ wire signed [45:0] i_acc_round = i_acc_next + round2;
+ wire signed [45:0] q_acc_round = q_acc_next + round2;
+ wire signed [45:0] i_acc_shifted = i_acc_round >>> s2_r;
+ wire signed [45:0] q_acc_shifted = q_acc_round >>> s2_r;
+ wire signed [17:0] point_mean_i_next = i_acc_shifted[17:0];
+ wire signed [17:0] point_mean_q_next = q_acc_shifted[17:0];
+
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ armed <= 1'b0;
+ shot_cnt <= 32'd0;
+ avg_m1 <= 32'd0;
+ s1_r <= 5'd0;
+ s2_r <= 5'd0;
+ i_acc <= {46{1'b0}};
+ q_acc <= {46{1'b0}};
+ point_mean_i <= {18{1'b0}};
+ point_mean_q <= {18{1'b0}};
+ end else begin
+ if (arm) begin
+ armed <= 1'b1;
+ shot_cnt <= 32'd0;
+ avg_m1 <= (averager_value == 32'd0) ? 32'd0 : averager_value - 32'd1;
+ s1_r <= flog2(nsamp);
+ s2_r <= flog2(averager_value);
+ i_acc <= {46{1'b0}};
+ q_acc <= {46{1'b0}};
+ point_mean_i <= point_mean_i;
+ point_mean_q <= point_mean_q;
+ end else if (acc_en) begin
+ avg_m1 <= avg_m1;
+ s1_r <= s1_r;
+ s2_r <= s2_r;
+ if (is_last) begin
+ armed <= 1'b0;
+ shot_cnt <= 32'd0;
+ i_acc <= {46{1'b0}};
+ q_acc <= {46{1'b0}};
+ point_mean_i <= point_mean_i_next;
+ point_mean_q <= point_mean_q_next;
+ end else begin
+ armed <= 1'b1;
+ shot_cnt <= shot_cnt + 32'd1;
+ i_acc <= i_acc_next;
+ q_acc <= q_acc_next;
+ point_mean_i <= point_mean_i;
+ point_mean_q <= point_mean_q;
+ end
+ end else begin
+ armed <= armed;
+ shot_cnt <= shot_cnt;
+ avg_m1 <= avg_m1;
+ s1_r <= s1_r;
+ s2_r <= s2_r;
+ i_acc <= i_acc;
+ q_acc <= q_acc;
+ point_mean_i <= point_mean_i;
+ point_mean_q <= point_mean_q;
+ end
+ end
+ end
+
+ (* mark_debug = "true" *) reg fin_v0, fin_v1, fin_v2;
+ reg signed [17:0] sq_operand;
+ (* mark_debug = "true" *) reg [35:0] power_acc;
+
+ wire signed [35:0] point_mean_i_sq = point_mean_i * point_mean_i;
+ wire signed [35:0] sq_operand_sq = sq_operand * sq_operand;
+
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ fin_v0 <= 1'b0;
+ fin_v1 <= 1'b0;
+ fin_v2 <= 1'b0;
+ sq_operand <= {18{1'b0}};
+ power_acc <= {36{1'b0}};
+ m_axis_tdata <= {36{1'b0}};
+ m_axis_tvalid <= 1'b0;
+ end else begin
+ fin_v0 <= emit_now;
+ if (fin_v0) begin
+ power_acc <= point_mean_i_sq;
+ sq_operand <= point_mean_q;
+ end else if (fin_v1) begin
+ power_acc <= power_acc + sq_operand_sq;
+ sq_operand <= sq_operand;
+ end else begin
+ power_acc <= power_acc;
+ sq_operand <= sq_operand;
+ end
+ fin_v1 <= fin_v0;
+ fin_v2 <= fin_v1;
+ m_axis_tvalid <= fin_v2;
+ m_axis_tdata <= power_acc;
+ end
+ end
+
+ (* mark_debug = "true" *) reg s_axis_tvalid_dbg;
+ (* mark_debug = "true" *) reg [63:0] s_axis_tdata_dbg;
+ (* mark_debug = "true" *) reg arm_dbg;
+ (* mark_debug = "true" *) reg acc_en_dbg;
+ (* mark_debug = "true" *) reg emit_now_dbg;
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ s_axis_tvalid_dbg <= 1'b0;
+ s_axis_tdata_dbg <= 64'd0;
+ arm_dbg <= 1'b0;
+ acc_en_dbg <= 1'b0;
+ emit_now_dbg <= 1'b0;
+ end else begin
+ s_axis_tvalid_dbg <= s_axis_tvalid;
+ s_axis_tdata_dbg <= s_axis_tdata;
+ arm_dbg <= arm;
+ acc_en_dbg <= acc_en;
+ emit_now_dbg <= emit_now;
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/fine_tuning_sweep/src/fine_tuning_sweep.v b/firmware/ip/fine_tuning_sweep/src/fine_tuning_sweep.v
new file mode 100644
index 000000000..11ab4cb0a
--- /dev/null
+++ b/firmware/ip/fine_tuning_sweep/src/fine_tuning_sweep.v
@@ -0,0 +1,175 @@
+`timescale 1ns / 1ps
+
+module fine_tuning_sweep (
+ input wire clk,
+ input wire rst_n,
+
+ input wire qtag_en_i,
+ input wire [4:0] qtag_op_i,
+ input wire [31:0] qtag_dt1_i,
+ input wire [31:0] qtag_dt2_i,
+ input wire [31:0] qtag_dt3_i,
+ input wire [31:0] qtag_dt4_i,
+ (* mark_debug = "true" *) output reg qtag_rdy_o,
+ (* mark_debug = "true" *) output reg [31:0] qtag_dt1_o,
+ output reg [31:0] qtag_dt2_o,
+ (* mark_debug = "true" *) output reg qtag_vld_o,
+
+ input wire s_axis_tvalid,
+ output wire s_axis_tready,
+ input wire [63:0] s_axis_tdata
+);
+
+ assign s_axis_tready = 1'b1;
+
+ reg en_d;
+ wire en_rise = qtag_en_i & ~en_d;
+
+ always @(posedge clk) begin
+ if (!rst_n)
+ en_d <= 1'b0;
+ else
+ en_d <= qtag_en_i;
+ end
+
+ wire start_now = en_rise & (qtag_op_i == 5'd1);
+
+ (* mark_debug = "true" *) reg [31:0] reg_start;
+ (* mark_debug = "true" *) reg [31:0] reg_step;
+ (* mark_debug = "true" *) reg [31:0] reg_npoints;
+ (* mark_debug = "true" *) reg [31:0] reg_avg;
+ (* mark_debug = "true" *) reg [31:0] reg_nsamp;
+ (* mark_debug = "true" *) reg reg_mode;
+
+ wire [31:0] pf_freq_word;
+ wire pf_freq_valid;
+ wire pf_finish;
+ wire [35:0] max_amplitude;
+ wire [31:0] freq_at_max;
+
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ reg_start <= 32'd0;
+ reg_step <= 32'd0;
+ reg_npoints <= 32'd0;
+ reg_avg <= 32'd0;
+ reg_nsamp <= 32'd0;
+ reg_mode <= 1'b0;
+ end else if (en_rise & (qtag_op_i == 5'd0)) begin
+ reg_start <= qtag_dt1_i;
+ reg_step <= qtag_dt2_i;
+ reg_npoints <= qtag_dt3_i;
+ reg_avg <= qtag_dt4_i;
+ reg_nsamp <= reg_nsamp;
+ reg_mode <= reg_mode;
+ end else if (en_rise & (qtag_op_i == 5'd2)) begin
+ reg_start <= reg_start;
+ reg_step <= reg_step;
+ reg_npoints <= reg_npoints;
+ reg_avg <= reg_avg;
+ reg_nsamp <= qtag_dt1_i;
+ reg_mode <= qtag_dt2_i[0];
+ end else begin
+ reg_start <= reg_start;
+ reg_step <= reg_step;
+ reg_npoints <= reg_npoints;
+ reg_avg <= reg_avg;
+ reg_nsamp <= reg_nsamp;
+ reg_mode <= reg_mode;
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ qtag_dt1_o <= 32'd0;
+ qtag_dt2_o <= 32'd0;
+ qtag_vld_o <= 1'b0;
+ end else if (start_now) begin
+ qtag_dt1_o <= 32'd0;
+ qtag_dt2_o <= 32'd0;
+ qtag_vld_o <= 1'b0;
+ end else if (pf_finish) begin
+ qtag_dt1_o <= pf_freq_word;
+ qtag_dt2_o <= 32'd0;
+ qtag_vld_o <= 1'b1;
+ end else begin
+ qtag_dt1_o <= qtag_dt1_o;
+ qtag_dt2_o <= qtag_dt2_o;
+ qtag_vld_o <= qtag_vld_o;
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!rst_n)
+ qtag_rdy_o <= 1'b1;
+ else if (start_now)
+ qtag_rdy_o <= 1'b0;
+ else if (pf_finish)
+ qtag_rdy_o <= 1'b1;
+ else
+ qtag_rdy_o <= qtag_rdy_o;
+ end
+
+ wire point_arm = start_now | pf_freq_valid;
+
+ wire [35:0] amp_data_c;
+ wire amp_valid_c;
+
+ amplitude_calculator u_amplitude_calculator (
+ .clk (clk),
+ .rst_n (rst_n),
+ .s_axis_tvalid (s_axis_tvalid),
+ .s_axis_tready (s_axis_tready),
+ .s_axis_tdata (s_axis_tdata),
+ .arm (point_arm),
+ .averager_value (reg_avg),
+ .nsamp (reg_nsamp),
+ .m_axis_tdata (amp_data_c),
+ .m_axis_tvalid (amp_valid_c)
+ );
+
+ peak_finder u_peak_finder_v2 (
+ .clk (clk),
+ .rstn (rst_n),
+ .start (start_now),
+ .start_freq (reg_start),
+ .step (reg_step),
+ .n_points (reg_npoints),
+ .mode (reg_mode),
+ .amp_valid (amp_valid_c),
+ .amp_data (amp_data_c),
+ .freq_word (pf_freq_word),
+ .freq_valid (pf_freq_valid),
+ .finish (pf_finish),
+ .max_amplitude (max_amplitude),
+ .freq_at_max (freq_at_max)
+ );
+
+ (* mark_debug = "true" *) reg s_axis_tvalid_dbg;
+ (* mark_debug = "true" *) reg s_axis_tready_dbg;
+ (* mark_debug = "true" *) reg [63:0] s_axis_tdata_dbg;
+ (* mark_debug = "true" *) reg amp_valid_c_dbg;
+ (* mark_debug = "true" *) reg [35:0] amp_data_c_dbg;
+ (* mark_debug = "true" *) reg qtag_en_dbg;
+ (* mark_debug = "true" *) reg [4:0] qtag_op_dbg;
+ always @(posedge clk) begin
+ if (!rst_n) begin
+ s_axis_tvalid_dbg <= 1'b0;
+ s_axis_tready_dbg <= 1'b0;
+ s_axis_tdata_dbg <= 64'd0;
+ amp_valid_c_dbg <= 1'b0;
+ amp_data_c_dbg <= {36{1'b0}};
+ qtag_en_dbg <= 1'b0;
+ qtag_op_dbg <= 5'd0;
+ end else begin
+ s_axis_tvalid_dbg <= s_axis_tvalid;
+ s_axis_tready_dbg <= s_axis_tready;
+ s_axis_tdata_dbg <= s_axis_tdata;
+ amp_valid_c_dbg <= amp_valid_c;
+ amp_data_c_dbg <= amp_data_c;
+ qtag_en_dbg <= qtag_en_i;
+ qtag_op_dbg <= qtag_op_i;
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/fine_tuning_sweep/src/peak_finder.v b/firmware/ip/fine_tuning_sweep/src/peak_finder.v
new file mode 100644
index 000000000..2d183df26
--- /dev/null
+++ b/firmware/ip/fine_tuning_sweep/src/peak_finder.v
@@ -0,0 +1,184 @@
+`timescale 1ns / 1ps
+
+module peak_finder (
+ input wire clk,
+ input wire rstn,
+
+ input wire start,
+ input wire [31:0] start_freq,
+ input wire [31:0] step,
+ input wire [31:0] n_points,
+ input wire mode,
+
+ input wire amp_valid,
+ input wire [35:0] amp_data,
+
+ (* mark_debug = "true" *) output reg [31:0] freq_word,
+ (* mark_debug = "true" *) output reg freq_valid,
+ (* mark_debug = "true" *) output reg finish,
+
+ (* mark_debug = "true" *) output reg [35:0] max_amplitude,
+ (* mark_debug = "true" *) output reg [31:0] freq_at_max
+);
+
+ localparam [1:0] IDLE = 2'd0, SEND_FREQ = 2'd1, WAIT_MEAS = 2'd2;
+
+ (* mark_debug = "true" *) reg [1:0] state;
+ reg [1:0] next_state;
+ (* mark_debug = "true" *) reg [31:0] cur_freq, cur_step, n_pts, point_idx;
+
+ (* mark_debug = "true" *) reg last_point_r;
+ (* mark_debug = "true" *) reg mode_r;
+
+ wire is_better = mode_r ? (amp_data < max_amplitude) : (amp_data > max_amplitude);
+
+
+ always @(posedge clk) begin
+ if (!rstn)
+ state <= IDLE;
+ else
+ state <= next_state;
+ end
+
+ always @(*) begin
+ case (state)
+ IDLE:
+ next_state = start ? SEND_FREQ : IDLE;
+
+ SEND_FREQ:
+ next_state = WAIT_MEAS;
+
+ WAIT_MEAS: begin
+ if (amp_valid)
+ next_state = last_point_r ? IDLE : SEND_FREQ;
+ else
+ next_state = WAIT_MEAS;
+ end
+
+ default:
+ next_state = IDLE;
+ endcase
+ end
+
+ always @(posedge clk) begin
+ if (!rstn) begin
+ freq_word <= 32'd0;
+ freq_valid <= 1'b0;
+ finish <= 1'b0;
+ max_amplitude <= {36{1'b0}};
+ freq_at_max <= 32'd0;
+ cur_freq <= 32'd0;
+ cur_step <= 32'd0;
+ n_pts <= 32'd0;
+ point_idx <= 32'd0;
+ last_point_r <= 1'b0;
+ mode_r <= 1'b0;
+ end else begin
+ case (state)
+ IDLE: begin
+ freq_word <= freq_word;
+ freq_valid <= 1'b0;
+ finish <= 1'b0;
+ if (start) begin
+ cur_freq <= start_freq;
+ cur_step <= step;
+ n_pts <= n_points;
+ point_idx <= 32'd0;
+ last_point_r <= (32'd1 >= n_points);
+ mode_r <= mode;
+ max_amplitude <= mode ? {36{1'b1}} : {36{1'b0}};
+ freq_at_max <= 32'd0;
+ end else begin
+ cur_freq <= cur_freq;
+ cur_step <= cur_step;
+ n_pts <= n_pts;
+ point_idx <= point_idx;
+ last_point_r <= last_point_r;
+ mode_r <= mode_r;
+ max_amplitude <= max_amplitude;
+ freq_at_max <= freq_at_max;
+ end
+ end
+
+ SEND_FREQ: begin
+ freq_word <= cur_freq;
+ freq_valid <= 1'b1;
+ finish <= 1'b0;
+ max_amplitude <= max_amplitude;
+ freq_at_max <= freq_at_max;
+ cur_freq <= cur_freq;
+ cur_step <= cur_step;
+ n_pts <= n_pts;
+ point_idx <= point_idx;
+ last_point_r <= last_point_r;
+ mode_r <= mode_r;
+ end
+
+ WAIT_MEAS: begin
+ freq_valid <= 1'b0;
+ cur_step <= cur_step;
+ n_pts <= n_pts;
+ mode_r <= mode_r;
+ if (amp_valid) begin
+ if (is_better) begin
+ max_amplitude <= amp_data;
+ freq_at_max <= cur_freq;
+ end else begin
+ max_amplitude <= max_amplitude;
+ freq_at_max <= freq_at_max;
+ end
+
+ if (last_point_r) begin
+ freq_word <= is_better ? cur_freq : freq_at_max;
+ finish <= 1'b1;
+ cur_freq <= cur_freq;
+ point_idx <= point_idx;
+ last_point_r <= last_point_r;
+ end else begin
+ freq_word <= freq_word;
+ finish <= 1'b0;
+ cur_freq <= cur_freq + cur_step;
+ point_idx <= point_idx + 32'd1;
+ last_point_r <= (point_idx + 32'd2 >= n_pts);
+ end
+ end else begin
+ freq_word <= freq_word;
+ finish <= 1'b0;
+ max_amplitude <= max_amplitude;
+ freq_at_max <= freq_at_max;
+ cur_freq <= cur_freq;
+ point_idx <= point_idx;
+ last_point_r <= last_point_r;
+ end
+ end
+
+ default: begin
+ freq_word <= freq_word;
+ freq_valid <= 1'b0;
+ finish <= 1'b0;
+ max_amplitude <= max_amplitude;
+ freq_at_max <= freq_at_max;
+ cur_freq <= cur_freq;
+ cur_step <= cur_step;
+ n_pts <= n_pts;
+ point_idx <= point_idx;
+ last_point_r <= last_point_r;
+ mode_r <= mode_r;
+ end
+ endcase
+ end
+ end
+
+ (* mark_debug = "true" *) reg rstn_dbg;
+ (* mark_debug = "true" *) reg start_dbg;
+ always @(posedge clk) begin
+ if (!rstn) begin
+ rstn_dbg <= 1'b0;
+ start_dbg <= 1'b0;
+ end else begin
+ rstn_dbg <= rstn;
+ start_dbg <= start;
+ end
+ end
+
+endmodule
diff --git a/firmware/ip/fine_tuning_sweep/src/tb_amplitude_calculator.sv b/firmware/ip/fine_tuning_sweep/src/tb_amplitude_calculator.sv
new file mode 100644
index 000000000..0ca3f1389
--- /dev/null
+++ b/firmware/ip/fine_tuning_sweep/src/tb_amplitude_calculator.sv
@@ -0,0 +1,358 @@
+`timescale 1ns / 1ps
+//------------------------------------------------------------------------------
+// tb_amplitude_calculator -- self-checking unit sim for the two-stage
+// accumulate-and-shift power calculator.
+//
+// Golden model mirrors the RTL's exact round-half-up + floor-log2-shift
+// algorithm (see CLAUDE.md: I1-I4) using 64-bit integer math -- DUT power
+// must match the golden model EXACTLY for every case below.
+//
+// N2 (avg) is tested up to 4096 (2^12) shots per point, not the design's
+// documented max of 2^29 -- simulating 2^29 shots is not tractable in
+// xsim. The 46-bit accumulator width for N2<=2^29 is a closed-form proof
+// (see plan / CLAUDE.md), not exhaustively simulated here; this TB
+// exercises the SAME shift/round logic at a power-of-two and non-power-of-
+// two N2 to validate the algorithm, and separately asserts the proven
+// tight numeric bounds on shot_mean/point_mean every cycle regardless of
+// N2 used.
+//------------------------------------------------------------------------------
+
+module tb_amplitude_calculator();
+
+ reg clk;
+ reg rst_n;
+ always #5 clk = ~clk;
+
+ reg s_axis_tvalid;
+ reg s_axis_tready;
+ reg [63:0] s_axis_tdata;
+ reg arm;
+ reg [31:0] averager_value;
+ reg [31:0] nsamp;
+ wire [35:0] m_axis_tdata;
+ wire m_axis_tvalid;
+
+ amplitude_calculator dut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .s_axis_tvalid (s_axis_tvalid),
+ .s_axis_tready (s_axis_tready),
+ .s_axis_tdata (s_axis_tdata),
+ .arm (arm),
+ .averager_value (averager_value),
+ .nsamp (nsamp),
+ .m_axis_tdata (m_axis_tdata),
+ .m_axis_tvalid (m_axis_tvalid)
+ );
+
+ integer pass_count, fail_count;
+
+ function automatic int flog2_g(input int unsigned v);
+ int r;
+ int k;
+ begin
+ r = 0;
+ for (k = 1; k <= 31; k = k + 1) begin
+ if (v[k])
+ r = k;
+ end
+ flog2_g = r;
+ end
+ endfunction
+
+ function automatic longint round_shift_g(input longint val, input int s);
+ longint rnd;
+ begin
+ rnd = (s == 0) ? 0 : (64'sd1 <<< (s - 1));
+ round_shift_g = (val + rnd) >>> s;
+ end
+ endfunction
+
+ function automatic longint golden_power(
+ input longint isums[],
+ input longint qsums[],
+ input int unsigned nsamp_v,
+ input int unsigned avg_v
+ );
+ int s1, s2;
+ longint iacc, qacc, ipm, qpm;
+ int k;
+ begin
+ s1 = flog2_g(nsamp_v);
+ s2 = flog2_g(avg_v);
+ iacc = 0;
+ qacc = 0;
+ for (k = 0; k < isums.size(); k = k + 1) begin
+ iacc = iacc + round_shift_g(isums[k], s1);
+ qacc = qacc + round_shift_g(qsums[k], s1);
+ end
+ ipm = round_shift_g(iacc, s2);
+ qpm = round_shift_g(qacc, s2);
+ golden_power = ipm * ipm + qpm * qpm;
+ end
+ endfunction
+
+ function automatic real true_power(
+ input longint isums[],
+ input longint qsums[],
+ input int unsigned nsamp_v,
+ input int unsigned avg_v
+ );
+ longint isum, qsum;
+ real denom, mean_i, mean_q;
+ int k, s1, s2;
+ begin
+ isum = 0;
+ qsum = 0;
+ for (k = 0; k < isums.size(); k = k + 1) begin
+ isum = isum + isums[k];
+ qsum = qsum + qsums[k];
+ end
+ // exact (UNROUNDED) two-stage mean using the SAME 2^s1 * 2^s2
+ // divisor the RTL uses -- not exact n1*avg. Dividing by the
+ // nearest power-of-two-below-n1 (not n1 itself) is an
+ // intentional, systematic scale factor of the design (same for
+ // every point in a pass, so argmax-irrelevant); this function
+ // isolates the ROUNDING error on top of that, which is the
+ // quantity the near-tie/quantization bound documents.
+ s1 = flog2_g(nsamp_v);
+ s2 = flog2_g(avg_v);
+ denom = real'(longint'(1) <<< (s1 + s2));
+ mean_i = real'(isum) / denom;
+ mean_q = real'(qsum) / denom;
+ true_power = mean_i * mean_i + mean_q * mean_q;
+ end
+ endfunction
+
+ task automatic do_reset;
+ begin
+ rst_n = 1'b0;
+ s_axis_tvalid = 1'b0;
+ s_axis_tready = 1'b1;
+ s_axis_tdata = 64'd0;
+ arm = 1'b0;
+ averager_value = 32'd0;
+ nsamp = 32'd0;
+ pass_count = 0;
+ fail_count = 0;
+ repeat (5) @(posedge clk);
+ #1;
+ rst_n = 1'b1;
+ repeat (5) @(posedge clk);
+ end
+ endtask
+
+ task automatic pulse_arm(input int unsigned nsamp_v, input int unsigned avg_v);
+ begin
+ @(posedge clk); #1;
+ nsamp = nsamp_v;
+ averager_value = avg_v;
+ arm = 1'b1;
+ @(posedge clk); #1;
+ arm = 1'b0;
+ end
+ endtask
+
+ task automatic fire_shot(input longint isum, input longint qsum);
+ begin
+ @(posedge clk); #1;
+ s_axis_tdata = {qsum[31:0], isum[31:0]};
+ s_axis_tvalid = 1'b1;
+ @(posedge clk); #1;
+ s_axis_tvalid = 1'b0;
+ s_axis_tdata = 64'd0;
+ end
+ endtask
+
+ task automatic wait_result(output longint got_power);
+ begin
+ while (!m_axis_tvalid) @(posedge clk);
+ got_power = {28'd0, m_axis_tdata};
+ @(posedge clk);
+ end
+ endtask
+
+ task automatic run_point(
+ input int unsigned nsamp_v,
+ input int unsigned avg_v,
+ input longint isums[],
+ input longint qsums[],
+ input string tag
+ );
+ longint golden, got;
+ int k;
+ begin
+ pulse_arm(nsamp_v, avg_v);
+ for (k = 0; k < isums.size(); k = k + 1)
+ fire_shot(isums[k], qsums[k]);
+ wait_result(got);
+ golden = golden_power(isums, qsums, nsamp_v, avg_v);
+ if (got == golden) begin
+ pass_count = pass_count + 1;
+ $display("[%0t] PASS %s: power=%0d", $time, tag, got);
+ end else begin
+ fail_count = fail_count + 1;
+ $display("[%0t] FAIL %s: got=%0d golden=%0d", $time, tag, got, golden);
+ end
+ end
+ endtask
+
+ task automatic run_bound_check(
+ input int unsigned nsamp_v,
+ input int unsigned avg_v,
+ input longint isums[],
+ input longint qsums[],
+ input real rel_bound,
+ input string tag
+ );
+ longint got;
+ real truep, relerr;
+ int k;
+ begin
+ pulse_arm(nsamp_v, avg_v);
+ for (k = 0; k < isums.size(); k = k + 1)
+ fire_shot(isums[k], qsums[k]);
+ wait_result(got);
+ truep = true_power(isums, qsums, nsamp_v, avg_v);
+ relerr = (truep == 0.0) ? 0.0 : (real'(got) - truep) / truep;
+ if (relerr < 0.0)
+ relerr = -relerr;
+ if (relerr <= rel_bound) begin
+ pass_count = pass_count + 1;
+ $display("[%0t] PASS %s: quantized=%0d true=%.3e relerr=%.3e (bound %.3e)",
+ $time, tag, got, truep, relerr, rel_bound);
+ end else begin
+ fail_count = fail_count + 1;
+ $display("[%0t] FAIL %s: quantized=%0d true=%.3e relerr=%.3e EXCEEDS bound %.3e",
+ $time, tag, got, truep, relerr, rel_bound);
+ end
+ end
+ endtask
+
+ always @(posedge clk) begin
+ if (rst_n && dut.acc_en) begin
+ if (dut.shot_mean_i > 17'sd65534 || dut.shot_mean_i < -17'sd65535) begin
+ $display("[%0t] BOUND FAIL: shot_mean_i=%0d outside proven [-65535,65534]", $time, dut.shot_mean_i);
+ fail_count = fail_count + 1;
+ end
+ if (dut.shot_mean_q > 17'sd65534 || dut.shot_mean_q < -17'sd65535) begin
+ $display("[%0t] BOUND FAIL: shot_mean_q=%0d outside proven [-65535,65534]", $time, dut.shot_mean_q);
+ fail_count = fail_count + 1;
+ end
+ if (dut.is_last) begin
+ if (dut.point_mean_i_next > 18'sd131070 || dut.point_mean_i_next < -18'sd131072) begin
+ $display("[%0t] BOUND FAIL: point_mean_i_next=%0d outside proven [-131072,131070]", $time, dut.point_mean_i_next);
+ fail_count = fail_count + 1;
+ end
+ if (dut.point_mean_q_next > 18'sd131070 || dut.point_mean_q_next < -18'sd131072) begin
+ $display("[%0t] BOUND FAIL: point_mean_q_next=%0d outside proven [-131072,131070]", $time, dut.point_mean_q_next);
+ fail_count = fail_count + 1;
+ end
+ end
+ end
+ end
+
+ longint isums_a[], qsums_a[];
+ int k;
+
+ initial begin
+ clk = 0;
+ do_reset();
+
+ // 1. Full-scale: n1=2^16 (avg_buffer's own overflow ceiling), positive
+ // extreme, N2=4096 (power-of-two stand-in for "N2 at max", see header)
+ isums_a = new[4096];
+ qsums_a = new[4096];
+ for (k = 0; k < 4096; k = k + 1) begin
+ isums_a[k] = 65536 * 32767;
+ qsums_a[k] = 65536 * 32767;
+ end
+ run_point(65536, 4096, isums_a, qsums_a, "fullscale_pos_pow2");
+
+ // 1b. Full-scale negative extreme -- exact int32 min shot sum
+ for (k = 0; k < 4096; k = k + 1) begin
+ isums_a[k] = -65536 * 32768;
+ qsums_a[k] = -65536 * 32768;
+ end
+ run_point(65536, 4096, isums_a, qsums_a, "fullscale_neg_pow2");
+
+ // 2. Worst non-power n1 AND N2 simultaneously
+ isums_a = new[1000];
+ qsums_a = new[1000];
+ for (k = 0; k < 1000; k = k + 1) begin
+ isums_a[k] = 1000 * 20000 - k;
+ qsums_a[k] = -1000 * 15000 + 2 * k;
+ end
+ run_point(1000, 1000, isums_a, qsums_a, "n1_1000_avg_1000_nonpow2");
+
+ // 2b. Small worst non-power n1=3, N2=3
+ isums_a = new[3];
+ qsums_a = new[3];
+ isums_a[0] = 3 * 100; qsums_a[0] = 3 * (-200);
+ isums_a[1] = 3 * (-50); qsums_a[1] = 3 * 300;
+ isums_a[2] = 3 * 400; qsums_a[2] = 3 * (-10);
+ run_point(3, 3, isums_a, qsums_a, "n1_3_avg_3");
+
+ // 2c. 2^k+1 non-power cases: n1=1025, N2=65
+ isums_a = new[65];
+ qsums_a = new[65];
+ for (k = 0; k < 65; k = k + 1) begin
+ isums_a[k] = 1025 * (1000 + k);
+ qsums_a[k] = 1025 * (-2000 + 3 * k);
+ end
+ run_point(1025, 65, isums_a, qsums_a, "n1_1025_avg_65_2kplus1");
+
+ // 3. n1=1, N2=1 -- s1=0 and s2=0, zero round constant, identity path
+ isums_a = new[1];
+ qsums_a = new[1];
+ isums_a[0] = 12345;
+ qsums_a[0] = -6789;
+ run_point(1, 1, isums_a, qsums_a, "n1_1_avg_1_identity");
+
+ // 3b. n1=1, N2=60 -- s1=0 mixed with s2>0
+ isums_a = new[60];
+ qsums_a = new[60];
+ for (k = 0; k < 60; k = k + 1) begin
+ isums_a[k] = 1000 - 2 * k;
+ qsums_a[k] = -500 + 3 * k;
+ end
+ run_point(1, 60, isums_a, qsums_a, "n1_1_avg_60");
+
+ // 4. Sign stress: I+/Q-, both-, alternating, n1=1000, N2=4
+ isums_a = new[4];
+ qsums_a = new[4];
+ isums_a[0] = 1000 * 1000; qsums_a[0] = 1000 * (-2000);
+ isums_a[1] = 1000 * (-1500); qsums_a[1] = 1000 * 800;
+ isums_a[2] = 1000 * (-3000); qsums_a[2] = 1000 * (-3000);
+ isums_a[3] = 1000 * 500; qsums_a[3] = 1000 * 500;
+ run_point(1000, 4, isums_a, qsums_a, "sign_stress");
+
+ // 6. Quantization error bound (near-tie floor): moderate n1/N2, verify
+ // the DUT's rounded power sits within the documented ~2^-17 relative
+ // bound of the TRUE (unrounded) sum-then-square power.
+ isums_a = new[500];
+ qsums_a = new[500];
+ for (k = 0; k < 500; k = k + 1) begin
+ isums_a[k] = 1000 * (7000 + (k % 37) - 18);
+ qsums_a[k] = 1000 * (-4000 + (k % 23) - 11);
+ end
+ run_bound_check(1000, 500, isums_a, qsums_a, 0.0001, "quantization_bound");
+
+ $display("------------------------------------------------");
+ $display("[%0t] SUMMARY: %0d PASS, %0d FAIL", $time, pass_count, fail_count);
+ if (fail_count == 0)
+ $display("[%0t] ALL PASS", $time);
+ else
+ $display("[%0t] FAILURES PRESENT", $time);
+
+ #200;
+ $finish;
+ end
+
+ initial begin
+ #5000000;
+ $display("[%0t] TIMEOUT", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/fine_tuning_sweep/src/tb_fine_tuning_sweep.sv b/firmware/ip/fine_tuning_sweep/src/tb_fine_tuning_sweep.sv
new file mode 100644
index 000000000..b694bde9a
--- /dev/null
+++ b/firmware/ip/fine_tuning_sweep/src/tb_fine_tuning_sweep.sv
@@ -0,0 +1,197 @@
+`timescale 1ns / 1ps
+//------------------------------------------------------------------------------
+// tb_fine_tuning_sweep -- self-checking sim for the single-clock sweep FSM.
+//
+// Models the tProc + DUT loop against the avg_buffer-m2 front end, with NO
+// read opcode: the IP presents freq_word on qtag_dt1_o + raises qtag_vld_o /
+// qtag_rdy_o on finish, and the tProc reads the result directly.
+// * OP2 loads nsamp (n1, for the amplitude_calculator's stage-1 shift)
+// and the peak/dip comparison mode
+// * OP0 loads the sweep config (start/step/n_points/avg)
+// * OP1 starts the sweep; the tProc then waits for qtag_rdy_o to drop (WSTART)
+// * per point: while armed, "retune" the synthetic readout to cur_freq and
+// present AVG accumulated m2 words (one 64-bit {Q,I} per shot) as tready/
+// tvalid beats; the accumulator disarms when it has its AVG shots
+// * finish: qtag_rdy_o rises (WDONE) -> read freq_at_max from qtag_dt1_o
+// The synthetic readout is a triangular peak (mode=0) or notch (mode=1)
+// centred on PEAK_FREQ, so freq_at_max must land on the grid point nearest
+// PEAK_FREQ in both modes. NSAMP_TEST=8 (s1=3 nonzero) exercises the
+// stage-1 shift; stimulus is pre-scaled by NSAMP_TEST so the recovered
+// shot_mean lands in the same numeric range as before the two-stage
+// rearchitecture, preserving the argmax/argmin behavior. Single clock: the
+// real BD brings s_axis into the core clock via axis_clock_converter.
+//------------------------------------------------------------------------------
+
+module tb_fine_tuning_sweep();
+
+ reg clk;
+ reg rst_n;
+ always #5 clk = ~clk;
+
+ reg qtag_en_i;
+ reg [4:0] qtag_op_i;
+ reg [31:0] qtag_dt1_i, qtag_dt2_i, qtag_dt3_i, qtag_dt4_i;
+ wire qtag_rdy_o;
+ wire [31:0] qtag_dt1_o, qtag_dt2_o;
+ wire qtag_vld_o;
+
+ reg [63:0] s_axis_tdata;
+ reg s_axis_tvalid;
+ wire s_axis_tready;
+
+ fine_tuning_sweep uut (
+ .clk (clk),
+ .rst_n (rst_n),
+ .qtag_en_i (qtag_en_i),
+ .qtag_op_i (qtag_op_i),
+ .qtag_dt1_i (qtag_dt1_i),
+ .qtag_dt2_i (qtag_dt2_i),
+ .qtag_dt3_i (qtag_dt3_i),
+ .qtag_dt4_i (qtag_dt4_i),
+ .qtag_rdy_o (qtag_rdy_o),
+ .qtag_dt1_o (qtag_dt1_o),
+ .qtag_dt2_o (qtag_dt2_o),
+ .qtag_vld_o (qtag_vld_o),
+ .s_axis_tvalid (s_axis_tvalid),
+ .s_axis_tready (s_axis_tready),
+ .s_axis_tdata (s_axis_tdata)
+ );
+
+ localparam [31:0] START_FREQ = 32'd6000000;
+ localparam [31:0] STEP = 32'd1000000;
+ localparam [31:0] NPOINTS = 32'd100;
+ localparam [31:0] AVG = 32'd3;
+ localparam [31:0] NSAMP_TEST = 32'd8;
+
+ localparam [31:0] PEAK_FREQ = 32'd18000000;
+ localparam [31:0] PEAK_WIDTH = 32'd4000000;
+
+ reg [31:0] tuned_freq;
+ reg [15:0] adc_amp;
+ reg test_mode;
+
+ always @(*) begin : amp_model
+ integer diff;
+ integer bump;
+ diff = tuned_freq - PEAK_FREQ;
+ if (diff < 0) diff = -diff;
+ if (diff < PEAK_WIDTH)
+ bump = 30000 - ((diff * 29000) / PEAK_WIDTH);
+ else
+ bump = 1000;
+ adc_amp = test_mode ? (31000 - bump) : bump;
+ end
+
+ task qp2_send(input [4:0] op,
+ input [31:0] d1, input [31:0] d2,
+ input [31:0] d3, input [31:0] d4);
+ begin
+ @(posedge clk); #1;
+ qtag_en_i = 1'b1; qtag_op_i = op;
+ qtag_dt1_i = d1; qtag_dt2_i = d2; qtag_dt3_i = d3; qtag_dt4_i = d4;
+ @(posedge clk); #1;
+ qtag_en_i = 1'b0;
+ @(posedge clk);
+ end
+ endtask
+
+ // present one avg_buffer m2 word: {Q,I} accumulated for this shot, as a
+ // single tvalid/tready beat. Pre-scaled by NSAMP_TEST so the stage-1
+ // shift (s1=3 at NSAMP_TEST=8) recovers a shot_mean tracking adc_amp --
+ // bigger amplitude -> bigger point_mean^2*2 after stage 2.
+ task fire_shot;
+ reg [31:0] scaled;
+ begin
+ scaled = adc_amp * NSAMP_TEST;
+ @(posedge clk); #1;
+ s_axis_tvalid = 1'b1;
+ s_axis_tdata = {scaled, scaled};
+ @(posedge clk); #1;
+ s_axis_tvalid = 1'b0;
+ s_axis_tdata = 64'd0;
+ @(posedge clk);
+ end
+ endtask
+
+ reg [31:0] rd_freq;
+ integer step_i, a;
+ integer fail_count;
+
+ task run_sweep_test(input mode_v, input [31:0] tag);
+ begin
+ test_mode = mode_v;
+ tuned_freq = 0;
+
+ qp2_send(5'd2, NSAMP_TEST, {31'd0, mode_v}, 0, 0);
+ $display("[%0t] %s CONFIG: nsamp=%0d mode=%0d", $time, tag, NSAMP_TEST, mode_v);
+
+ qp2_send(5'd0, START_FREQ, STEP, NPOINTS, AVG);
+ $display("[%0t] %s CONFIG: start=%0d step=%0d N=%0d avg=%0d",
+ $time, tag, START_FREQ, STEP, NPOINTS, AVG);
+
+ qp2_send(5'd1, 0, 0, 0, 0);
+ while (qtag_rdy_o) @(posedge clk);
+ $display("[%0t] %s SWEEP STARTED (target @ %0d)", $time, tag, PEAK_FREQ);
+
+ step_i = 0;
+ while (!qtag_rdy_o) begin
+ @(posedge clk); #1;
+ if (uut.u_amplitude_calculator.armed) begin
+ tuned_freq = uut.u_peak_finder_v2.cur_freq;
+ #1;
+ step_i = step_i + 1;
+ for (a = 0; a < AVG; a = a + 1) fire_shot;
+ while (uut.u_amplitude_calculator.armed) @(posedge clk);
+ end
+ end
+
+ rd_freq = qtag_dt1_o;
+ $display("------------------------------------------------");
+ $display("[%0t] %s FINISH. freq_at_max = %0d Hz (vld=%0b)",
+ $time, tag, rd_freq, qtag_vld_o);
+
+ if (rd_freq == PEAK_FREQ)
+ $display("[%0t] %s PASS: freq_at_max (%0d) == expected (%0d)",
+ $time, tag, rd_freq, PEAK_FREQ);
+ else begin
+ $display("[%0t] %s FAIL: freq_at_max (%0d) != expected (%0d)",
+ $time, tag, rd_freq, PEAK_FREQ);
+ fail_count = fail_count + 1;
+ end
+ $display("[%0t] %s SWEPT %0d points", $time, tag, step_i);
+ end
+ endtask
+
+ initial begin
+ clk = 0; rst_n = 0;
+ qtag_en_i = 0; qtag_op_i = 0;
+ qtag_dt1_i = 0; qtag_dt2_i = 0; qtag_dt3_i = 0; qtag_dt4_i = 0;
+ tuned_freq = 0;
+ test_mode = 1'b0;
+ fail_count = 0;
+ s_axis_tvalid = 1'b0; s_axis_tdata = 64'd0;
+
+ #100; rst_n = 1; #100;
+ $display("[%0t] RESET DONE", $time);
+
+ run_sweep_test(1'b0, "PEAK");
+ run_sweep_test(1'b1, "DIP ");
+
+ $display("------------------------------------------------");
+ if (fail_count == 0)
+ $display("[%0t] ALL PASS", $time);
+ else
+ $display("[%0t] %0d FAILURE(S)", $time, fail_count);
+
+ #500;
+ $display("[%0t] SIM COMPLETE", $time);
+ $finish;
+ end
+
+ initial begin
+ #10000000;
+ $display("[%0t] TIMEOUT -- sweep never finished", $time);
+ $finish;
+ end
+
+endmodule
diff --git a/firmware/ip/fine_tuning_sweep/xgui/fine_tuning_sweep_v1_0.tcl b/firmware/ip/fine_tuning_sweep/xgui/fine_tuning_sweep_v1_0.tcl
new file mode 100644
index 000000000..04eb794dd
--- /dev/null
+++ b/firmware/ip/fine_tuning_sweep/xgui/fine_tuning_sweep_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "ACC_WIDTH" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.ACC_WIDTH { PARAM_VALUE.ACC_WIDTH } {
+ # Procedure called to update ACC_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ACC_WIDTH { PARAM_VALUE.ACC_WIDTH } {
+ # Procedure called to validate ACC_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.ACC_WIDTH { MODELPARAM_VALUE.ACC_WIDTH PARAM_VALUE.ACC_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.ACC_WIDTH}] ${MODELPARAM_VALUE.ACC_WIDTH}
+}
+
diff --git a/firmware/ip/qick_processor/src/dsp_macro_0/dsp_macro_0.xci b/firmware/ip/qick_processor/src/dsp_macro_0/dsp_macro_0.xci
index 30bd7cf38..5ec9f3345 100644
--- a/firmware/ip/qick_processor/src/dsp_macro_0/dsp_macro_0.xci
+++ b/firmware/ip/qick_processor/src/dsp_macro_0/dsp_macro_0.xci
@@ -154,7 +154,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/ip/qick_processor/src/qick_processor.sv b/firmware/ip/qick_processor/src/qick_processor.sv
index a21d1971d..56036f965 100644
--- a/firmware/ip/qick_processor/src/qick_processor.sv
+++ b/firmware/ip/qick_processor/src/qick_processor.sv
@@ -306,10 +306,10 @@ always_ff @(posedge c_clk_i) begin
qp1_dt_r <= qp1_dt_i ;
end else if ( qp1_clr ) qp1_dt_new <= 0 ;
// Q-PERIPHERAL 2 Control
- if ( qp2_vld_i ) begin
+ if ( qp2_vld_i ) begin
qp2_dt_new <= 1 ;
qp2_dt_r <= qp2_dt_i ;
- end else if ( qp1_clr ) qp2_dt_new <= 0 ;
+ end else if ( qp2_clr ) qp2_dt_new <= 0 ;
end
end
diff --git a/firmware/ip/qick_time_tagger/src/axi_mst_0/axi_mst_0.xci b/firmware/ip/qick_time_tagger/src/axi_mst_0/axi_mst_0.xci
index 350ae6412..2c16196a6 100644
--- a/firmware/ip/qick_time_tagger/src/axi_mst_0/axi_mst_0.xci
+++ b/firmware/ip/qick_time_tagger/src/axi_mst_0/axi_mst_0.xci
@@ -64,7 +64,7 @@
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
- "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
+ "BASE_BOARD_PART": [ { "value": "realdigital.org:rfsoc4x2:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu49dr" } ],
"PACKAGE": [ { "value": "ffvf1760" } ],
diff --git a/firmware/projects/qick_tprocv1_111_rfbv1_standard/bd_2020-2.tcl b/firmware/projects/qick_tprocv1_111_rfbv1_standard/bd_2020-2.tcl
deleted file mode 100644
index a13a5df40..000000000
--- a/firmware/projects/qick_tprocv1_111_rfbv1_standard/bd_2020-2.tcl
+++ /dev/null
@@ -1,2698 +0,0 @@
-
-################################################################
-# This is a generated script based on design: d_1
-#
-# Though there are limitations about the generated script,
-# the main purpose of this utility is to make learning
-# IP Integrator Tcl commands easier.
-################################################################
-
-namespace eval _tcl {
-proc get_script_folder {} {
- set script_path [file normalize [info script]]
- set script_folder [file dirname $script_path]
- return $script_folder
-}
-}
-variable script_folder
-set script_folder [_tcl::get_script_folder]
-
-################################################################
-# Check if script is running in correct Vivado version.
-################################################################
-set scripts_vivado_version 2020.2
-set current_vivado_version [version -short]
-
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
- puts ""
- catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
-
- return 1
-}
-
-################################################################
-# START
-################################################################
-
-# To test this script, run the following commands from Vivado Tcl console:
-# source d_1_script.tcl
-
-
-# The design that will be created by this Tcl script contains the following
-# module references:
-# lo_spi_mux, vect2bits_16
-
-# Please add the sources of those modules before sourcing this Tcl script.
-
-# If there is no project opened, this script will create a
-# project, but make sure you do not have an existing project
-# <./myproj/project_1.xpr> in the current working folder.
-
-set list_projs [get_projects -quiet]
-if { $list_projs eq "" } {
- create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
- set_property BOARD_PART xilinx.com:zcu111:part0:1.4 [current_project]
-}
-
-
-# CHANGE DESIGN NAME HERE
-variable design_name
-set design_name d_1
-
-# If you do not already have an existing IP Integrator design open,
-# you can create a design using the following command:
-# create_bd_design $design_name
-
-# Creating design if needed
-set errMsg ""
-set nRet 0
-
-set cur_design [current_bd_design -quiet]
-set list_cells [get_bd_cells -quiet]
-
-if { ${design_name} eq "" } {
- # USE CASES:
- # 1) Design_name not set
-
- set errMsg "Please set the variable to a non-empty value."
- set nRet 1
-
-} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
- # USE CASES:
- # 2): Current design opened AND is empty AND names same.
- # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
- # 4): Current design opened AND is empty AND names diff; design_name exists in project.
-
- if { $cur_design ne $design_name } {
- common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty."
- set design_name [get_property NAME $cur_design]
- }
- common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
-
-} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
- # USE CASES:
- # 5) Current design opened AND has components AND same names.
-
- set errMsg "Design <$design_name> already exists in your project, please set the variable to another value."
- set nRet 1
-} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
- # USE CASES:
- # 6) Current opened design, has components, but diff names, design_name exists in project.
- # 7) No opened design, design_name exists in project.
-
- set errMsg "Design <$design_name> already exists in your project, please set the variable to another value."
- set nRet 2
-
-} else {
- # USE CASES:
- # 8) No opened design, design_name not in project.
- # 9) Current opened design, has components, but diff names, design_name not in project.
-
- common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
-
- create_bd_design $design_name
-
- common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
- current_bd_design $design_name
-
-}
-
-common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"."
-
-if { $nRet != 0 } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
- return $nRet
-}
-
-set bCheckIPsPassed 1
-##################################################################
-# CHECK IPs
-##################################################################
-set bCheckIPs 1
-if { $bCheckIPs == 1 } {
- set list_check_ips "\
-xilinx.com:ip:axi_quad_spi:3.2\
-xilinx.com:ip:axi_bram_ctrl:4.1\
-xilinx.com:ip:blk_mem_gen:8.4\
-xilinx.com:ip:axi_dma:7.1\
-xilinx.com:ip:smartconnect:1.0\
-QICK:QICK:axis_avg_buffer:1.2\
-xilinx.com:ip:axis_clock_converter:1.1\
-QICK:QICK:axis_constant:1.0\
-QICK:QICK:axis_readout_v2:1.0\
-xilinx.com:ip:axis_register_slice:1.1\
-QICK:QICK:axis_set_reg:1.0\
-QICK:QICK:axis_signal_gen_v6:1.0\
-xilinx.com:ip:axis_switch:1.1\
-QICK:QICK:axis_terminator:1.0\
-QICK:QICK:axis_tproc64x32_x8:1.0\
-xilinx.com:ip:xlconstant:1.1\
-xilinx.com:ip:clk_wiz:6.0\
-xilinx.com:ip:proc_sys_reset:5.0\
-xilinx.com:ip:system_ila:1.1\
-xilinx.com:ip:usp_rf_data_converter:2.4\
-xilinx.com:ip:zynq_ultra_ps_e:3.3\
-"
-
- set list_ips_missing ""
- common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
-
- foreach ip_vlnv $list_check_ips {
- set ip_obj [get_ipdefs -all $ip_vlnv]
- if { $ip_obj eq "" } {
- lappend list_ips_missing $ip_vlnv
- }
- }
-
- if { $list_ips_missing ne "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
- set bCheckIPsPassed 0
- }
-
-}
-
-##################################################################
-# CHECK Modules
-##################################################################
-set bCheckModules 1
-if { $bCheckModules == 1 } {
- set list_check_mods "\
-lo_spi_mux\
-vect2bits_16\
-"
-
- set list_mods_missing ""
- common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
-
- foreach mod_vlnv $list_check_mods {
- if { [can_resolve_reference $mod_vlnv] == 0 } {
- lappend list_mods_missing $mod_vlnv
- }
- }
-
- if { $list_mods_missing ne "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
- common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
- set bCheckIPsPassed 0
- }
-}
-
-if { $bCheckIPsPassed != 1 } {
- common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
- return 3
-}
-
-##################################################################
-# DESIGN PROCs
-##################################################################
-
-
-
-# Procedure to create entire design; Provide argument to make
-# procedure reusable. If parentCell is "", will use root.
-proc create_root_design { parentCell } {
-
- variable script_folder
- variable design_name
-
- if { $parentCell eq "" } {
- set parentCell [get_bd_cells /]
- }
-
- # Get object for parentCell
- set parentObj [get_bd_cells $parentCell]
- if { $parentObj == "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
- return
- }
-
- # Make sure parentObj is hier blk
- set parentType [get_property TYPE $parentObj]
- if { $parentType ne "hier" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
- return
- }
-
- # Save current instance; Restore later
- set oldCurInst [current_bd_instance .]
-
- # Set parent object as current
- current_bd_instance $parentObj
-
-
- # Create interface ports
- set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ]
-
- set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ]
-
- set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ]
-
- set sysref_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_in ]
-
- set vin0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin0 ]
-
- set vin1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vin1 ]
-
- set vout0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout0 ]
-
- set vout1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout1 ]
-
- set vout2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout2 ]
-
- set vout3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout3 ]
-
- set vout4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout4 ]
-
- set vout5 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout5 ]
-
- set vout6 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vout6 ]
-
-
- # Create ports
- set ATTN_CLK [ create_bd_port -dir O ATTN_CLK ]
- set ATTN_LE [ create_bd_port -dir O -from 2 -to 0 ATTN_LE ]
- set ATTN_SI [ create_bd_port -dir O ATTN_SI ]
- set BIAS_CE [ create_bd_port -dir O -from 0 -to 0 BIAS_CE ]
- set BIAS_CLR [ create_bd_port -dir O -from 0 -to 0 BIAS_CLR ]
- set BIAS_RESET [ create_bd_port -dir O -from 0 -to 0 BIAS_RESET ]
- set BIAS_S [ create_bd_port -dir O -from 3 -to 0 BIAS_S ]
- set BIAS_SCLK [ create_bd_port -dir O BIAS_SCLK ]
- set BIAS_SDI [ create_bd_port -dir O BIAS_SDI ]
- set BIAS_SDO [ create_bd_port -dir I BIAS_SDO ]
- set LO_CS0 [ create_bd_port -dir O LO_CS0 ]
- set LO_CS1 [ create_bd_port -dir O LO_CS1 ]
- set LO_MISO0 [ create_bd_port -dir I LO_MISO0 ]
- set LO_MISO1 [ create_bd_port -dir I LO_MISO1 ]
- set LO_MOSI [ create_bd_port -dir O LO_MOSI ]
- set LO_SCLK [ create_bd_port -dir O LO_SCLK ]
- set PMOD0_0_LS [ create_bd_port -dir O PMOD0_0_LS ]
- set PMOD0_1_LS [ create_bd_port -dir O PMOD0_1_LS ]
- set PMOD0_2_LS [ create_bd_port -dir O PMOD0_2_LS ]
- set PMOD0_3_LS [ create_bd_port -dir O PMOD0_3_LS ]
- set PMOD0_4_LS [ create_bd_port -dir O PMOD0_4_LS ]
- set PMOD0_5_LS [ create_bd_port -dir O PMOD0_5_LS ]
- set PMOD0_6_LS [ create_bd_port -dir O PMOD0_6_LS ]
- set PMOD0_7_LS [ create_bd_port -dir O PMOD0_7_LS ]
- set PMOD1_0_LS [ create_bd_port -dir I PMOD1_0_LS ]
- set PWR_SYNC [ create_bd_port -dir O -from 0 -to 0 PWR_SYNC ]
- set RST_5VEN [ create_bd_port -dir O -from 0 -to 0 RST_5VEN ]
- set S [ create_bd_port -dir O -from 3 -to 0 S ]
- set SCLK [ create_bd_port -dir O SCLK ]
- set SDI [ create_bd_port -dir O SDI ]
- set SDO [ create_bd_port -dir I SDO ]
-
- # Create instance: attn_spi, and set properties
- set attn_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 attn_spi ]
- set_property -dict [ list \
- CONFIG.C_NUM_SS_BITS {3} \
- CONFIG.C_NUM_TRANSFER_BITS {16} \
- ] $attn_spi
-
- # Create instance: axi_bram_ctrl_0, and set properties
- set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {64} \
- CONFIG.ECC_TYPE {0} \
- CONFIG.SINGLE_PORT_BRAM {1} \
- ] $axi_bram_ctrl_0
-
- # Create instance: axi_bram_ctrl_0_bram, and set properties
- set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ]
- set_property -dict [ list \
- CONFIG.EN_SAFETY_CKT {false} \
- CONFIG.Enable_B {Use_ENB_Pin} \
- CONFIG.Memory_Type {True_Dual_Port_RAM} \
- CONFIG.Port_B_Clock {100} \
- CONFIG.Port_B_Enable_Rate {100} \
- CONFIG.Port_B_Write_Rate {50} \
- CONFIG.Read_Width_B {64} \
- CONFIG.Use_RSTB_Pin {true} \
- CONFIG.Write_Width_B {64} \
- ] $axi_bram_ctrl_0_bram
-
- # Create instance: axi_dma_avg, and set properties
- set axi_dma_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_avg ]
- set_property -dict [ list \
- CONFIG.c_include_mm2s {0} \
- CONFIG.c_include_sg {0} \
- CONFIG.c_sg_include_stscntrl_strm {0} \
- CONFIG.c_sg_length_width {26} \
- ] $axi_dma_avg
-
- # Create instance: axi_dma_buf, and set properties
- set axi_dma_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_buf ]
- set_property -dict [ list \
- CONFIG.c_include_mm2s {0} \
- CONFIG.c_include_sg {0} \
- CONFIG.c_sg_include_stscntrl_strm {0} \
- CONFIG.c_sg_length_width {26} \
- ] $axi_dma_buf
-
- # Create instance: axi_dma_gen, and set properties
- set axi_dma_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_gen ]
- set_property -dict [ list \
- CONFIG.c_include_mm2s {1} \
- CONFIG.c_include_s2mm {0} \
- CONFIG.c_include_sg {0} \
- CONFIG.c_sg_include_stscntrl_strm {0} \
- CONFIG.c_sg_length_width {26} \
- ] $axi_dma_gen
-
- # Create instance: axi_dma_tproc, and set properties
- set axi_dma_tproc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_tproc ]
- set_property -dict [ list \
- CONFIG.c_include_sg {0} \
- CONFIG.c_sg_include_stscntrl_strm {0} \
- CONFIG.c_sg_length_width {26} \
- ] $axi_dma_tproc
-
- # Create instance: axi_smc, and set properties
- set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
- set_property -dict [ list \
- CONFIG.NUM_SI {5} \
- ] $axi_smc
-
- # Create instance: axis_avg_buffer_0, and set properties
- set axis_avg_buffer_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_avg_buffer:1.2 axis_avg_buffer_0 ]
- set_property -dict [ list \
- CONFIG.N_AVG {14} \
- ] $axis_avg_buffer_0
-
- # Create instance: axis_avg_buffer_1, and set properties
- set axis_avg_buffer_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_avg_buffer:1.2 axis_avg_buffer_1 ]
- set_property -dict [ list \
- CONFIG.N_AVG {14} \
- ] $axis_avg_buffer_1
-
- # Create instance: axis_clk_cnvrt_avg_0, and set properties
- set axis_clk_cnvrt_avg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_0 ]
-
- # Create instance: axis_clk_cnvrt_avg_1, and set properties
- set axis_clk_cnvrt_avg_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_avg_1 ]
-
- # Create instance: axis_clk_cnvrt_gen_3, and set properties
- set axis_clk_cnvrt_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_3 ]
-
- # Create instance: axis_clk_cnvrt_gen_4, and set properties
- set axis_clk_cnvrt_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_4 ]
-
- # Create instance: axis_clk_cnvrt_gen_5, and set properties
- set axis_clk_cnvrt_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_5 ]
-
- # Create instance: axis_clk_cnvrt_gen_6, and set properties
- set axis_clk_cnvrt_gen_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clk_cnvrt_gen_6 ]
-
- # Create instance: axis_constant_0, and set properties
- set axis_constant_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_constant:1.0 axis_constant_0 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {64} \
- ] $axis_constant_0
-
- # Create instance: axis_constant_1, and set properties
- set axis_constant_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_constant:1.0 axis_constant_1 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {64} \
- ] $axis_constant_1
-
- # Create instance: axis_readout_v2_0, and set properties
- set axis_readout_v2_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_readout_v2:1.0 axis_readout_v2_0 ]
-
- # Create instance: axis_readout_v2_1, and set properties
- set axis_readout_v2_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_readout_v2:1.0 axis_readout_v2_1 ]
-
- # Create instance: axis_register_slice_0, and set properties
- set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ]
-
- # Create instance: axis_register_slice_1, and set properties
- set axis_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_1 ]
-
- # Create instance: axis_set_reg_0, and set properties
- set axis_set_reg_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_set_reg:1.0 axis_set_reg_0 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {160} \
- ] $axis_set_reg_0
-
- # Create instance: axis_signal_gen_v6_0, and set properties
- set axis_signal_gen_v6_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_0 ]
-
- # Create instance: axis_signal_gen_v6_1, and set properties
- set axis_signal_gen_v6_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_1 ]
-
- # Create instance: axis_signal_gen_v6_2, and set properties
- set axis_signal_gen_v6_2 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_2 ]
-
- # Create instance: axis_signal_gen_v6_3, and set properties
- set axis_signal_gen_v6_3 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_3 ]
-
- # Create instance: axis_signal_gen_v6_4, and set properties
- set axis_signal_gen_v6_4 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_4 ]
-
- # Create instance: axis_signal_gen_v6_5, and set properties
- set axis_signal_gen_v6_5 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_5 ]
-
- # Create instance: axis_signal_gen_v6_6, and set properties
- set axis_signal_gen_v6_6 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_signal_gen_v6:1.0 axis_signal_gen_v6_6 ]
-
- # Create instance: axis_switch_avg, and set properties
- set axis_switch_avg [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_avg ]
- set_property -dict [ list \
- CONFIG.ROUTING_MODE {1} \
- ] $axis_switch_avg
-
- # Create instance: axis_switch_buf, and set properties
- set axis_switch_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_buf ]
- set_property -dict [ list \
- CONFIG.ROUTING_MODE {1} \
- ] $axis_switch_buf
-
- # Create instance: axis_switch_gen, and set properties
- set axis_switch_gen [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_gen ]
- set_property -dict [ list \
- CONFIG.DECODER_REG {1} \
- CONFIG.NUM_MI {7} \
- CONFIG.NUM_SI {1} \
- CONFIG.ROUTING_MODE {1} \
- ] $axis_switch_gen
-
- # Create instance: axis_terminator_0, and set properties
- set axis_terminator_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_terminator:1.0 axis_terminator_0 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {256} \
- ] $axis_terminator_0
-
- # Create instance: axis_terminator_1, and set properties
- set axis_terminator_1 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_terminator:1.0 axis_terminator_1 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {256} \
- ] $axis_terminator_1
-
- # Create instance: axis_tproc64x32_x8_0, and set properties
- set axis_tproc64x32_x8_0 [ create_bd_cell -type ip -vlnv QICK:QICK:axis_tproc64x32_x8:1.0 axis_tproc64x32_x8_0 ]
- set_property -dict [ list \
- CONFIG.DMEM_N {12} \
- CONFIG.PMEM_N {20} \
- ] $axis_tproc64x32_x8_0
-
- # Create instance: bias_constant_0, and set properties
- set bias_constant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 bias_constant_0 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $bias_constant_0
-
- # Create instance: bias_constant_1, and set properties
- set bias_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 bias_constant_1 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {1} \
- ] $bias_constant_1
-
- # Create instance: clk_adc0_x2, and set properties
- set clk_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_adc0_x2 ]
- set_property -dict [ list \
- CONFIG.CLKIN1_JITTER_PS {52.08} \
- CONFIG.CLKOUT1_JITTER {81.938} \
- CONFIG.CLKOUT1_PHASE_ERROR {82.655} \
- CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {384} \
- CONFIG.MMCM_CLKFBOUT_MULT_F {6.250} \
- CONFIG.MMCM_CLKIN1_PERIOD {5.208} \
- CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
- CONFIG.MMCM_CLKOUT0_DIVIDE_F {3.125} \
- ] $clk_adc0_x2
-
- # Create instance: dac_bias_spi, and set properties
- set dac_bias_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 dac_bias_spi ]
- set_property -dict [ list \
- CONFIG.C_NUM_SS_BITS {4} \
- CONFIG.C_NUM_TRANSFER_BITS {8} \
- ] $dac_bias_spi
-
- # Create instance: dig_lconstant_1, and set properties
- set dig_lconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 dig_lconstant_1 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {1} \
- ] $dig_lconstant_1
-
- # Create instance: lo_spi, and set properties
- set lo_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 lo_spi ]
- set_property -dict [ list \
- CONFIG.C_NUM_SS_BITS {2} \
- CONFIG.C_NUM_TRANSFER_BITS {8} \
- ] $lo_spi
-
- # Create instance: lo_spi_mux_0, and set properties
- set block_name lo_spi_mux
- set block_cell_name lo_spi_mux_0
- if { [catch {set lo_spi_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
- return 1
- } elseif { $lo_spi_mux_0 eq "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
- return 1
- }
-
- # Create instance: ps8_0_axi_periph, and set properties
- set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
- set_property -dict [ list \
- CONFIG.NUM_MI {26} \
- ] $ps8_0_axi_periph
-
- # Create instance: psf_spi, and set properties
- set psf_spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 psf_spi ]
- set_property -dict [ list \
- CONFIG.C_NUM_SS_BITS {4} \
- CONFIG.C_NUM_TRANSFER_BITS {8} \
- ] $psf_spi
-
- # Create instance: rst_100, and set properties
- set rst_100 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_100 ]
-
- # Create instance: rst_adc0, and set properties
- set rst_adc0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0 ]
-
- # Create instance: rst_adc0_x2, and set properties
- set rst_adc0_x2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_adc0_x2 ]
-
- # Create instance: rst_dac0, and set properties
- set rst_dac0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac0 ]
-
- # Create instance: rst_dac1, and set properties
- set rst_dac1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_dac1 ]
-
- # Create instance: system_ila_0, and set properties
- set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
- set_property -dict [ list \
- CONFIG.C_BRAM_CNT {6} \
- CONFIG.C_MON_TYPE {MIX} \
- CONFIG.C_NUM_MONITOR_SLOTS {1} \
- CONFIG.C_SLOT {0} \
- CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- ] $system_ila_0
-
- # Create instance: system_ila_1, and set properties
- set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ]
- set_property -dict [ list \
- CONFIG.C_BRAM_CNT {6} \
- CONFIG.C_MON_TYPE {MIX} \
- CONFIG.C_NUM_MONITOR_SLOTS {1} \
- CONFIG.C_SLOT {0} \
- CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
- ] $system_ila_1
-
- # Create instance: usp_rf_data_converter_0, and set properties
- set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.4 usp_rf_data_converter_0 ]
- set_property -dict [ list \
- CONFIG.ADC0_Enable {1} \
- CONFIG.ADC0_Fabric_Freq {384.000} \
- CONFIG.ADC0_Outclk_Freq {192.000} \
- CONFIG.ADC0_PLL_Enable {true} \
- CONFIG.ADC0_Refclk_Freq {204.800} \
- CONFIG.ADC0_Sampling_Rate {3.072} \
- CONFIG.ADC_Decimation_Mode00 {1} \
- CONFIG.ADC_Decimation_Mode01 {1} \
- CONFIG.ADC_Decimation_Mode02 {1} \
- CONFIG.ADC_Decimation_Mode03 {1} \
- CONFIG.ADC_Mixer_Type00 {0} \
- CONFIG.ADC_Mixer_Type01 {0} \
- CONFIG.ADC_Mixer_Type02 {0} \
- CONFIG.ADC_Mixer_Type03 {0} \
- CONFIG.ADC_Slice00_Enable {true} \
- CONFIG.ADC_Slice01_Enable {true} \
- CONFIG.ADC_Slice02_Enable {true} \
- CONFIG.ADC_Slice03_Enable {true} \
- CONFIG.DAC0_Enable {1} \
- CONFIG.DAC0_Fabric_Freq {384.000} \
- CONFIG.DAC0_Outclk_Freq {384.000} \
- CONFIG.DAC0_PLL_Enable {true} \
- CONFIG.DAC0_Refclk_Freq {204.800} \
- CONFIG.DAC0_Sampling_Rate {6.144} \
- CONFIG.DAC1_Enable {1} \
- CONFIG.DAC1_Fabric_Freq {384.000} \
- CONFIG.DAC1_Outclk_Freq {384.000} \
- CONFIG.DAC1_PLL_Enable {true} \
- CONFIG.DAC1_Refclk_Freq {204.800} \
- CONFIG.DAC1_Sampling_Rate {6.144} \
- CONFIG.DAC_Interpolation_Mode00 {1} \
- CONFIG.DAC_Interpolation_Mode01 {1} \
- CONFIG.DAC_Interpolation_Mode02 {1} \
- CONFIG.DAC_Interpolation_Mode10 {1} \
- CONFIG.DAC_Interpolation_Mode11 {1} \
- CONFIG.DAC_Interpolation_Mode12 {1} \
- CONFIG.DAC_Interpolation_Mode13 {1} \
- CONFIG.DAC_Mixer_Type00 {0} \
- CONFIG.DAC_Mixer_Type01 {0} \
- CONFIG.DAC_Mixer_Type02 {0} \
- CONFIG.DAC_Mixer_Type10 {0} \
- CONFIG.DAC_Mixer_Type11 {0} \
- CONFIG.DAC_Mixer_Type12 {0} \
- CONFIG.DAC_Mixer_Type13 {0} \
- CONFIG.DAC_Slice00_Enable {true} \
- CONFIG.DAC_Slice01_Enable {true} \
- CONFIG.DAC_Slice02_Enable {true} \
- CONFIG.DAC_Slice10_Enable {true} \
- CONFIG.DAC_Slice11_Enable {true} \
- CONFIG.DAC_Slice12_Enable {true} \
- CONFIG.DAC_Slice13_Enable {true} \
- ] $usp_rf_data_converter_0
-
- # Create instance: vect2bits_16_0, and set properties
- set block_name vect2bits_16
- set block_cell_name vect2bits_16_0
- if { [catch {set vect2bits_16_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
- return 1
- } elseif { $vect2bits_16_0 eq "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
- return 1
- }
-
- # Create instance: xlconstant_0, and set properties
- set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {64} \
- ] $xlconstant_0
-
- # Create instance: xlconstant_1, and set properties
- set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
- set_property -dict [ list \
- CONFIG.CONST_WIDTH {1} \
- ] $xlconstant_1
-
- # Create instance: xlconstant_2, and set properties
- set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {1} \
- ] $xlconstant_2
-
- # Create instance: xlconstant_3, and set properties
- set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {8} \
- ] $xlconstant_3
-
- # Create instance: zynq_ultra_ps_e_0, and set properties
- set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
- set_property -dict [ list \
- CONFIG.CAN0_BOARD_INTERFACE {custom} \
- CONFIG.CAN1_BOARD_INTERFACE {custom} \
- CONFIG.CSU_BOARD_INTERFACE {custom} \
- CONFIG.DP_BOARD_INTERFACE {custom} \
- CONFIG.GEM0_BOARD_INTERFACE {custom} \
- CONFIG.GEM1_BOARD_INTERFACE {custom} \
- CONFIG.GEM2_BOARD_INTERFACE {custom} \
- CONFIG.GEM3_BOARD_INTERFACE {custom} \
- CONFIG.GPIO_BOARD_INTERFACE {custom} \
- CONFIG.IIC0_BOARD_INTERFACE {custom} \
- CONFIG.IIC1_BOARD_INTERFACE {custom} \
- CONFIG.NAND_BOARD_INTERFACE {custom} \
- CONFIG.PCIE_BOARD_INTERFACE {custom} \
- CONFIG.PJTAG_BOARD_INTERFACE {custom} \
- CONFIG.PMU_BOARD_INTERFACE {custom} \
- CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
- CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
- CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
- CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
- CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
- CONFIG.PSU_IMPORT_BOARD_PRESET {} \
- CONFIG.PSU_MIO_0_DIRECTION {out} \
- CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_0_POLARITY {Default} \
- CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_0_SLEW {fast} \
- CONFIG.PSU_MIO_10_DIRECTION {inout} \
- CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_10_POLARITY {Default} \
- CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_10_SLEW {fast} \
- CONFIG.PSU_MIO_11_DIRECTION {inout} \
- CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_11_POLARITY {Default} \
- CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_11_SLEW {fast} \
- CONFIG.PSU_MIO_12_DIRECTION {out} \
- CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_12_POLARITY {Default} \
- CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_12_SLEW {fast} \
- CONFIG.PSU_MIO_13_DIRECTION {inout} \
- CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_13_POLARITY {Default} \
- CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_13_SLEW {fast} \
- CONFIG.PSU_MIO_14_DIRECTION {inout} \
- CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_14_POLARITY {Default} \
- CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_14_SLEW {fast} \
- CONFIG.PSU_MIO_15_DIRECTION {inout} \
- CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_15_POLARITY {Default} \
- CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_15_SLEW {fast} \
- CONFIG.PSU_MIO_16_DIRECTION {inout} \
- CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_16_POLARITY {Default} \
- CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_16_SLEW {fast} \
- CONFIG.PSU_MIO_17_DIRECTION {inout} \
- CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_17_POLARITY {Default} \
- CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_17_SLEW {fast} \
- CONFIG.PSU_MIO_18_DIRECTION {in} \
- CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_18_POLARITY {Default} \
- CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_18_SLEW {fast} \
- CONFIG.PSU_MIO_19_DIRECTION {out} \
- CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_19_POLARITY {Default} \
- CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_19_SLEW {fast} \
- CONFIG.PSU_MIO_1_DIRECTION {inout} \
- CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_1_POLARITY {Default} \
- CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_1_SLEW {fast} \
- CONFIG.PSU_MIO_20_DIRECTION {inout} \
- CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_20_POLARITY {Default} \
- CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_20_SLEW {fast} \
- CONFIG.PSU_MIO_21_DIRECTION {inout} \
- CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_21_POLARITY {Default} \
- CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_21_SLEW {fast} \
- CONFIG.PSU_MIO_22_DIRECTION {inout} \
- CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_22_POLARITY {Default} \
- CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_22_SLEW {fast} \
- CONFIG.PSU_MIO_23_DIRECTION {inout} \
- CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_23_POLARITY {Default} \
- CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_23_SLEW {fast} \
- CONFIG.PSU_MIO_24_DIRECTION {inout} \
- CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_24_POLARITY {Default} \
- CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_24_SLEW {fast} \
- CONFIG.PSU_MIO_25_DIRECTION {inout} \
- CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_25_POLARITY {Default} \
- CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_25_SLEW {fast} \
- CONFIG.PSU_MIO_26_DIRECTION {inout} \
- CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_26_POLARITY {Default} \
- CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_26_SLEW {fast} \
- CONFIG.PSU_MIO_27_DIRECTION {out} \
- CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_27_POLARITY {Default} \
- CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_27_SLEW {fast} \
- CONFIG.PSU_MIO_28_DIRECTION {in} \
- CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_28_POLARITY {Default} \
- CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_28_SLEW {fast} \
- CONFIG.PSU_MIO_29_DIRECTION {out} \
- CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_29_POLARITY {Default} \
- CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_29_SLEW {fast} \
- CONFIG.PSU_MIO_2_DIRECTION {inout} \
- CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_2_POLARITY {Default} \
- CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_2_SLEW {fast} \
- CONFIG.PSU_MIO_30_DIRECTION {in} \
- CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_30_POLARITY {Default} \
- CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_30_SLEW {fast} \
- CONFIG.PSU_MIO_31_DIRECTION {inout} \
- CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_31_POLARITY {Default} \
- CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_31_SLEW {fast} \
- CONFIG.PSU_MIO_32_DIRECTION {out} \
- CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_32_POLARITY {Default} \
- CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_32_SLEW {fast} \
- CONFIG.PSU_MIO_33_DIRECTION {out} \
- CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_33_POLARITY {Default} \
- CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_33_SLEW {fast} \
- CONFIG.PSU_MIO_34_DIRECTION {out} \
- CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_34_POLARITY {Default} \
- CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_34_SLEW {fast} \
- CONFIG.PSU_MIO_35_DIRECTION {out} \
- CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_35_POLARITY {Default} \
- CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_35_SLEW {fast} \
- CONFIG.PSU_MIO_36_DIRECTION {out} \
- CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_36_POLARITY {Default} \
- CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_36_SLEW {fast} \
- CONFIG.PSU_MIO_37_DIRECTION {out} \
- CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_37_POLARITY {Default} \
- CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_37_SLEW {fast} \
- CONFIG.PSU_MIO_38_DIRECTION {inout} \
- CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_38_POLARITY {Default} \
- CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_38_SLEW {fast} \
- CONFIG.PSU_MIO_39_DIRECTION {inout} \
- CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_39_POLARITY {Default} \
- CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_39_SLEW {fast} \
- CONFIG.PSU_MIO_3_DIRECTION {inout} \
- CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_3_POLARITY {Default} \
- CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_3_SLEW {fast} \
- CONFIG.PSU_MIO_40_DIRECTION {inout} \
- CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_40_POLARITY {Default} \
- CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_40_SLEW {fast} \
- CONFIG.PSU_MIO_41_DIRECTION {inout} \
- CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_41_POLARITY {Default} \
- CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_41_SLEW {fast} \
- CONFIG.PSU_MIO_42_DIRECTION {inout} \
- CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_42_POLARITY {Default} \
- CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_42_SLEW {fast} \
- CONFIG.PSU_MIO_43_DIRECTION {inout} \
- CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_43_POLARITY {Default} \
- CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_43_SLEW {fast} \
- CONFIG.PSU_MIO_44_DIRECTION {inout} \
- CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_44_POLARITY {Default} \
- CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_44_SLEW {fast} \
- CONFIG.PSU_MIO_45_DIRECTION {in} \
- CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_45_POLARITY {Default} \
- CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_45_SLEW {fast} \
- CONFIG.PSU_MIO_46_DIRECTION {inout} \
- CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_46_POLARITY {Default} \
- CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_46_SLEW {fast} \
- CONFIG.PSU_MIO_47_DIRECTION {inout} \
- CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_47_POLARITY {Default} \
- CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_47_SLEW {fast} \
- CONFIG.PSU_MIO_48_DIRECTION {inout} \
- CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_48_POLARITY {Default} \
- CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_48_SLEW {fast} \
- CONFIG.PSU_MIO_49_DIRECTION {inout} \
- CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_49_POLARITY {Default} \
- CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_49_SLEW {fast} \
- CONFIG.PSU_MIO_4_DIRECTION {inout} \
- CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_4_POLARITY {Default} \
- CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_4_SLEW {fast} \
- CONFIG.PSU_MIO_50_DIRECTION {inout} \
- CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_50_POLARITY {Default} \
- CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_50_SLEW {fast} \
- CONFIG.PSU_MIO_51_DIRECTION {out} \
- CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_51_POLARITY {Default} \
- CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_51_SLEW {fast} \
- CONFIG.PSU_MIO_52_DIRECTION {in} \
- CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_52_POLARITY {Default} \
- CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_52_SLEW {fast} \
- CONFIG.PSU_MIO_53_DIRECTION {in} \
- CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_53_POLARITY {Default} \
- CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_53_SLEW {fast} \
- CONFIG.PSU_MIO_54_DIRECTION {inout} \
- CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_54_POLARITY {Default} \
- CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_54_SLEW {fast} \
- CONFIG.PSU_MIO_55_DIRECTION {in} \
- CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_55_POLARITY {Default} \
- CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_55_SLEW {fast} \
- CONFIG.PSU_MIO_56_DIRECTION {inout} \
- CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_56_POLARITY {Default} \
- CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_56_SLEW {fast} \
- CONFIG.PSU_MIO_57_DIRECTION {inout} \
- CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_57_POLARITY {Default} \
- CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_57_SLEW {fast} \
- CONFIG.PSU_MIO_58_DIRECTION {out} \
- CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_58_POLARITY {Default} \
- CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_58_SLEW {fast} \
- CONFIG.PSU_MIO_59_DIRECTION {inout} \
- CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_59_POLARITY {Default} \
- CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_59_SLEW {fast} \
- CONFIG.PSU_MIO_5_DIRECTION {out} \
- CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_5_POLARITY {Default} \
- CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_5_SLEW {fast} \
- CONFIG.PSU_MIO_60_DIRECTION {inout} \
- CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_60_POLARITY {Default} \
- CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_60_SLEW {fast} \
- CONFIG.PSU_MIO_61_DIRECTION {inout} \
- CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_61_POLARITY {Default} \
- CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_61_SLEW {fast} \
- CONFIG.PSU_MIO_62_DIRECTION {inout} \
- CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_62_POLARITY {Default} \
- CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_62_SLEW {fast} \
- CONFIG.PSU_MIO_63_DIRECTION {inout} \
- CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_63_POLARITY {Default} \
- CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_63_SLEW {fast} \
- CONFIG.PSU_MIO_64_DIRECTION {out} \
- CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_64_POLARITY {Default} \
- CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_64_SLEW {fast} \
- CONFIG.PSU_MIO_65_DIRECTION {out} \
- CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_65_POLARITY {Default} \
- CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_65_SLEW {fast} \
- CONFIG.PSU_MIO_66_DIRECTION {out} \
- CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_66_POLARITY {Default} \
- CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_66_SLEW {fast} \
- CONFIG.PSU_MIO_67_DIRECTION {out} \
- CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_67_POLARITY {Default} \
- CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_67_SLEW {fast} \
- CONFIG.PSU_MIO_68_DIRECTION {out} \
- CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_68_POLARITY {Default} \
- CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_68_SLEW {fast} \
- CONFIG.PSU_MIO_69_DIRECTION {out} \
- CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_69_POLARITY {Default} \
- CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_69_SLEW {fast} \
- CONFIG.PSU_MIO_6_DIRECTION {out} \
- CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_6_POLARITY {Default} \
- CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_6_SLEW {fast} \
- CONFIG.PSU_MIO_70_DIRECTION {in} \
- CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_70_POLARITY {Default} \
- CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_70_SLEW {fast} \
- CONFIG.PSU_MIO_71_DIRECTION {in} \
- CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_71_POLARITY {Default} \
- CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_71_SLEW {fast} \
- CONFIG.PSU_MIO_72_DIRECTION {in} \
- CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_72_POLARITY {Default} \
- CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_72_SLEW {fast} \
- CONFIG.PSU_MIO_73_DIRECTION {in} \
- CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_73_POLARITY {Default} \
- CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_73_SLEW {fast} \
- CONFIG.PSU_MIO_74_DIRECTION {in} \
- CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_74_POLARITY {Default} \
- CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_74_SLEW {fast} \
- CONFIG.PSU_MIO_75_DIRECTION {in} \
- CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_75_POLARITY {Default} \
- CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_75_SLEW {fast} \
- CONFIG.PSU_MIO_76_DIRECTION {out} \
- CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_76_POLARITY {Default} \
- CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_76_SLEW {fast} \
- CONFIG.PSU_MIO_77_DIRECTION {inout} \
- CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_77_POLARITY {Default} \
- CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_77_SLEW {fast} \
- CONFIG.PSU_MIO_7_DIRECTION {out} \
- CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_7_POLARITY {Default} \
- CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_7_SLEW {fast} \
- CONFIG.PSU_MIO_8_DIRECTION {inout} \
- CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_8_POLARITY {Default} \
- CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_8_SLEW {fast} \
- CONFIG.PSU_MIO_9_DIRECTION {inout} \
- CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_9_POLARITY {Default} \
- CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_9_SLEW {fast} \
- CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
- CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
- CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
- CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
- CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \
- CONFIG.PSU_SMC_CYCLE_T0 {NA} \
- CONFIG.PSU_SMC_CYCLE_T1 {NA} \
- CONFIG.PSU_SMC_CYCLE_T2 {NA} \
- CONFIG.PSU_SMC_CYCLE_T3 {NA} \
- CONFIG.PSU_SMC_CYCLE_T4 {NA} \
- CONFIG.PSU_SMC_CYCLE_T5 {NA} \
- CONFIG.PSU_SMC_CYCLE_T6 {NA} \
- CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
- CONFIG.PSU_VALUE_SILVERSION {3} \
- CONFIG.PSU__ACPU0__POWER__ON {1} \
- CONFIG.PSU__ACPU1__POWER__ON {1} \
- CONFIG.PSU__ACPU2__POWER__ON {1} \
- CONFIG.PSU__ACPU3__POWER__ON {1} \
- CONFIG.PSU__ACTUAL__IP {1} \
- CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \
- CONFIG.PSU__AFI0_COHERENCY {0} \
- CONFIG.PSU__AFI1_COHERENCY {0} \
- CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
- CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
- CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {1.999980} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {50} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {15} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {2} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
- CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
- CONFIG.PSU__CSU_COHERENCY {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__AL {0} \
- CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
- CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
- CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
- CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
- CONFIG.PSU__DDRC__CL {15} \
- CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
- CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
- CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \
- CONFIG.PSU__DDRC__CWL {14} \
- CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
- CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
- CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
- CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
- CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \
- CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
- CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
- CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
- CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
- CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
- CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
- CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
- CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
- CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
- CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
- CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
- CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
- CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
- CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
- CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
- CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
- CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
- CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
- CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
- CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
- CONFIG.PSU__DDRC__ECC {Disabled} \
- CONFIG.PSU__DDRC__ECC_SCRUB {0} \
- CONFIG.PSU__DDRC__ENABLE {1} \
- CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
- CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
- CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
- CONFIG.PSU__DDRC__FGRM {1X} \
- CONFIG.PSU__DDRC__FREQ_MHZ {1} \
- CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
- CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LP_ASR {manual normal} \
- CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
- CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
- CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
- CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
- CONFIG.PSU__DDRC__PLL_BYPASS {0} \
- CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
- CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
- CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
- CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
- CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
- CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
- CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
- CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
- CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
- CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
- CONFIG.PSU__DDRC__T_FAW {30.0} \
- CONFIG.PSU__DDRC__T_RAS_MIN {33} \
- CONFIG.PSU__DDRC__T_RC {47.06} \
- CONFIG.PSU__DDRC__T_RCD {15} \
- CONFIG.PSU__DDRC__T_RP {15} \
- CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
- CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
- CONFIG.PSU__DDRC__VREF {1} \
- CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
- CONFIG.PSU__DDR_QOS_ENABLE {0} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
- CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
- CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
- CONFIG.PSU__DEVICE_TYPE {RFSOC} \
- CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
- CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DLL__ISUSED {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
- CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
- CONFIG.PSU__DP__REF_CLK_FREQ {27} \
- CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
- CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
- CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET0__PTP__ENABLE {0} \
- CONFIG.PSU__ENET0__TSU__ENABLE {0} \
- CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET1__PTP__ENABLE {0} \
- CONFIG.PSU__ENET1__TSU__ENABLE {0} \
- CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET2__PTP__ENABLE {0} \
- CONFIG.PSU__ENET2__TSU__ENABLE {0} \
- CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
- CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
- CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
- CONFIG.PSU__ENET3__PTP__ENABLE {0} \
- CONFIG.PSU__ENET3__TSU__ENABLE {0} \
- CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
- CONFIG.PSU__EN_EMIO_TRACE {0} \
- CONFIG.PSU__EP__IP {0} \
- CONFIG.PSU__EXPAND__CORESIGHT {0} \
- CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
- CONFIG.PSU__EXPAND__GIC {0} \
- CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
- CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
- CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
- CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \
- CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \
- CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__FPGA_PL0_ENABLE {1} \
- CONFIG.PSU__FPGA_PL1_ENABLE {1} \
- CONFIG.PSU__FPGA_PL2_ENABLE {0} \
- CONFIG.PSU__FPGA_PL3_ENABLE {0} \
- CONFIG.PSU__FP__POWER__ON {1} \
- CONFIG.PSU__FTM__CTI_IN_0 {0} \
- CONFIG.PSU__FTM__CTI_IN_1 {0} \
- CONFIG.PSU__FTM__CTI_IN_2 {0} \
- CONFIG.PSU__FTM__CTI_IN_3 {0} \
- CONFIG.PSU__FTM__CTI_OUT_0 {0} \
- CONFIG.PSU__FTM__CTI_OUT_1 {0} \
- CONFIG.PSU__FTM__CTI_OUT_2 {0} \
- CONFIG.PSU__FTM__CTI_OUT_3 {0} \
- CONFIG.PSU__FTM__GPI {0} \
- CONFIG.PSU__FTM__GPO {0} \
- CONFIG.PSU__GEM0_COHERENCY {0} \
- CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM1_COHERENCY {0} \
- CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM2_COHERENCY {0} \
- CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM3_COHERENCY {0} \
- CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM__TSU__ENABLE {0} \
- CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
- CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
- CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
- CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
- CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
- CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
- CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
- CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {