ports/qemu: Update port.

Signed-off-by: iabdalkader <[email protected]>

Author: iabdalkader

ports/qemu/Dockerfile.riscv

@@ -0,0 +1,39 @@
+# This file is part of the MicroPython project, https://micropython.org/
+#
+# The MIT License (MIT)
+#
+# Copyright (c) 2025 Alessandro Gatti
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+FROM ubuntu:24.04
+
+RUN apt-get update && \
+    apt-get install -y \
+        gcc-riscv64-unknown-elf \
+        picolibc-riscv64-unknown-elf \
+        python3 \
+        python3-pip \
+        python3-platformdirs \
+        python3-pyelftools \
+        python3-serial \
+        qemu-system && \
+    pip3 install ar --break-system-packages
+
+WORKDIR /micropython

ports/qemu/Makefile

@@ -35,6 +35,12 @@ ifeq ($(QEMU_ARCH),riscv32)
 MICROPY_HEAP_SIZE ?= 143360
 FROZEN_MANIFEST ?= "require('unittest'); freeze('test-frzmpy', ('frozen_asm_rv32.py', 'frozen_const.py', 'frozen_viper.py', 'native_frozen_align.py'))"
 endif
+ifeq ($(QEMU_ARCH),riscv64)
+MICROPY_HEAP_SIZE ?= 204800
+FROZEN_MANIFEST ?= "require('unittest'); freeze('test-frzmpy', ('frozen_const.py',))"
+endif
+
+MICROPY_FLOAT_IMPL ?= float
 
 # include py core make definitions
 include $(TOP)/py/py.mk
@@ -44,6 +50,20 @@ GIT_SUBMODULES += lib/berkeley-db-1.xx
 
 CFLAGS += -DMICROPY_HEAP_SIZE=$(MICROPY_HEAP_SIZE)
 
+ifeq ($(MICROPY_FLOAT_IMPL),double)
+CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_DOUBLE
+else ifeq ($(MICROPY_FLOAT_IMPL),float)
+CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_FLOAT -fsingle-precision-constant
+else
+CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_NONE
+endif
+
+ifeq ($(SUPPORTS_HARDWARE_FP_SINGLE),1)
+CFLAGS += -DMICROPY_HW_FPU=1
+else ifeq ($(SUPPORTS_HARDWARE_FP_DOUBLE),1)
+CFLAGS += -DMICROPY_HW_FPU=1
+endif
+
 ################################################################################
 # ARM specific settings
 
@@ -57,6 +77,7 @@ LIBS = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
 SRC_C += \
 	mcu/arm/errorhandler.c \
 	mcu/arm/startup.c \
+	mcu/arm/systick.c \
 	shared/runtime/semihosting_arm.c \
 
 endif
@@ -94,6 +115,39 @@ SRC_BOARD_O += mcu/rv32/entrypoint.o
 
 endif
 
+################################################################################
+# RISC-V 64-bit specific settings
+
+ifeq ($(QEMU_ARCH),riscv64)
+
+CROSS_COMPILE ?= riscv64-unknown-elf-
+
+GCC_VERSION = $(word 1, $(subst ., , $(shell $(CC) -dumpversion)))
+
+RV64_ABI = lp64
+
+QEMU_ARGS += -bios none
+
+# GCC 10 and lower do not recognise the Zicsr extension in the architecture name.
+ifeq ($(shell test $(GCC_VERSION) -le 10; echo $$?),0)
+RV64_ARCH ?= rv64imac
+else
+# Recent GCC versions explicitly require to declare extensions.
+RV64_ARCH ?= rv64imac_zicsr
+endif
+
+AFLAGS += -mabi=$(RV64_ABI) -march=$(RV64_ARCH)
+CFLAGS += $(AFLAGS) -mcmodel=medany
+LDFLAGS += -mabi=$(RV64_ABI) -march=$(RV64_ARCH) -Wl,-EL -mcmodel=medany
+
+SRC_C += \
+	mcu/rv64/interrupts.c \
+	mcu/rv64/startup.c \
+
+SRC_BOARD_O += mcu/rv64/entrypoint.o
+
+endif
+
 ################################################################################
 # Project specific settings and compiler/linker flags
 
@@ -140,7 +194,7 @@ CFLAGS += $(SPECS_FRAGMENT)
 LDFLAGS += $(SPECS_FRAGMENT)
 endif
 
-RUN_TESTS_FULL_ARGS = -t execpty:"$(QEMU_SYSTEM) $(QEMU_ARGS) -serial pty -kernel ../ports/qemu/$<" $(RUN_TESTS_ARGS)
+RUN_TESTS_FULL_ARGS = -t execpty:"$(QEMU_SYSTEM) $(QEMU_ARGS) -serial pty -kernel ../ports/qemu/$<" --mpy-cross-flags='$(MPY_CROSS_FLAGS)' $(RUN_TESTS_ARGS)
 
 ################################################################################
 # Source files and libraries
@@ -156,21 +210,34 @@ SRC_C += \
 	shared/runtime/stdout_helpers.c \
 	shared/runtime/sys_stdio_mphal.c \
 
-LIB_SRC_C += $(SRC_LIB_LIBM_C)
-LIB_SRC_C += $(SRC_LIB_LIBM_SQRT_SW_C)
+ifeq ($(MICROPY_FLOAT_IMPL),double)
+LIBM_SRC_C += $(SRC_LIB_LIBM_DBL_C)
+ifeq ($(SUPPORTS_HARDWARE_FP_DOUBLE),1)
+LIBM_SRC_C += $(SRC_LIB_LIBM_DBL_SQRT_HW_C)
+else
+LIBM_SRC_C += $(SRC_LIB_LIBM_DBL_SQRT_SW_C)
+endif
+else
+LIBM_SRC_C += $(SRC_LIB_LIBM_C)
+ifeq ($(SUPPORTS_HARDWARE_FP_SINGLE),1)
+LIBM_SRC_C += $(SRC_LIB_LIBM_SQRT_HW_C)
+else
+LIBM_SRC_C += $(SRC_LIB_LIBM_SQRT_SW_C)
+endif
+endif
 
 OBJ += $(PY_O)
 OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(SRC_BOARD_O))
-OBJ += $(addprefix $(BUILD)/, $(LIB_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(LIBM_SRC_C:.c=.o))
 
 # List of sources for qstr extraction
-SRC_QSTR += $(SRC_C) $(LIB_SRC_C)
+SRC_QSTR += $(SRC_C) $(LIBM_SRC_C)
 
 ################################################################################
 # Main targets
 
-all: $(BUILD)/firmware.elf
+all: $(OBJ)
 
 .PHONY: repl
 repl: $(BUILD)/firmware.elf
@@ -196,7 +263,7 @@ test_natmod: $(BUILD)/firmware.elf
 	$(eval DIRNAME=ports/$(notdir $(CURDIR)))
 	cd $(TOP)/tests && \
 		for natmod in btree deflate framebuf heapq random_basic re; do \
-		./run-natmodtests.py -p -d execpty:"$(QEMU_SYSTEM) $(QEMU_ARGS) -serial pty -kernel ../$(DIRNAME)/$<" $(RUN_TESTS_EXTRA) extmod/$$natmod*.py; \
+		./run-natmodtests.py -t execpty:"$(QEMU_SYSTEM) $(QEMU_ARGS) -serial pty -kernel ../$(DIRNAME)/$<" $(RUN_TESTS_EXTRA) extmod/$$natmod*.py; \
 		done
 
 $(BUILD)/firmware.elf: $(LDSCRIPT) $(OBJ)

ports/qemu/README.md

@@ -1,8 +1,8 @@
 MicroPython port to qemu
 ========================
 
-This is experimental, community-supported port for Cortex-M and RISC-V RV32IMC
-emulation as provided by QEMU (http://qemu.org).
+This is experimental, community-supported port for Cortex-M and RISC-V
+RV32IMC/RV64IMC emulation as provided by QEMU (http://qemu.org).
 
 The purposes of this port are to enable:
 
@@ -26,9 +26,9 @@ Dependencies
 For ARM-based boards the build requires a bare-metal ARM toolchain, such as
 `arm-none-eabi-gcc`.
 
-### RISC-V
+### RISC-V 32
 
-For RISC-V-based boards the build requires a bare metal RISC-V toolchain with GCC 10
+For RV32-based boards the build requires a bare metal RISC-V toolchain with GCC 10
 or later, either with multilib support or 32 bits specific (M, C, and Zicsr
 extensions must be supported, along with ilp32 ABI).  Both newlib and picolibc are
 supported, with the latter having precedence if found.
@@ -37,6 +37,47 @@ Most pre-built toolchains should work out of the box, either coming from your
 Linux distribution's package manager, or independently packaged ones like
 [xPack](https://xpack.github.io/dev-tools/riscv-none-elf-gcc/).
 
+### RISC-V 64
+
+For RV64-based boards the build requires a bare metal RISC-V toolchain with GCC 10
+or later, either with multilib support or 64 bits specific (M, C, and Zicsr
+extensions must be supported, along with lp64 ABI).  In other words, if your
+compiler can build a binary that's compliant to any ratified RVA profiles,
+you *might* be good to go: if you run your cross-compiler `gcc` binary with `-v` as
+its only argument and you don't see mentions of `-mcmodel=medany`, your
+toolchain is probably not going to work for this situation (more later).  Both newlib
+and picolibc are supported, with the latter having precedence if found.
+
+RISC-V 64 toolchains are a bit more temperamental.  Some toolchains have their `libc`,
+`libm`, and `libgcc` libraries built in a way that they cannot be used with code
+placed at an offset beyond 0x7FFFF7FF.  QEMU's `VIRT_RV64` board code address space
+starts at 0x80000000, making those toolchains not viable if code from those libraries
+is brought in by the build process.  A lot of readily available RISC-V toolchains are
+unfortunately broken from this point of view.
+
+However, to work around this, a Docker container file is provided to be able to run
+tests using a known working compiler (the same one running MicroPython's RV32 and RV64
+CI jobs).
+
+To build the provided toolchain image you can use the following commands:
+
+```bash
+cd $MICROPYTHON_SOURCE_ROOT/ports/qemu
+docker build -t micropython/mpy-qemu-riscv -f Dockerfile.riscv .
+```
+
+and then tests can be run with:
+
+```bash
+cd $MICROPYTHON_SOURCE_ROOT
+docker container run -v .:/micropython --rm -it micropython/mpy-qemu-riscv make -C ports/qemu -- BOARD=VIRT_RV64 test
+```
+
+(If you use Podman, you can replace `docker` with `podman` in the commands above).
+
+Also, if you replace `VIRT_RV64` with `VIRT_RV32` you should be able to run
+32-bits tests as well!
+
 Build instructions
 ------------------
 
@@ -59,9 +100,11 @@ Available boards are:
 | ----------------- | ------------ | ------------------------ |
 | `MICROBIT`        | `arm`        | `microbit`               |
 | `MPS2_AN385`      | `arm`        | `mps2-an385`             |
+| `MPS2_AN500`      | `arm`        | `mps2-an500`             |
 | `NETDUINO2`       | `arm`        | `netduino2`              |
 | `SABRELITE`       | `arm`        | `sabrelite`              |
 | `VIRT_RV32`       | `riscv32`    | `virt`                   |
+| `VIRT_RV64`       | `riscv64`    | `virt`                   |
 
 Running
 -------
@@ -99,8 +142,8 @@ tests against the serial device, for example:
     $ ./run-tests.py -t /dev/pts/1
 
 Selected native modules that come as examples with the MicroPython source tree
-can also be tested with this command (this is currently supported only for the
-`VIRT_RV32` board):
+can also be tested with this command (this is currently not supported for the
+`VIRT_RV64` board):
 
     $ make test_natmod
 

ports/qemu/boards/MPS2_AN500/mpconfigboard.mk

@@ -0,0 +1,16 @@
+QEMU_ARCH = arm
+QEMU_MACHINE = mps2-an500
+
+CFLAGS += -mthumb -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16
+CFLAGS += -DQEMU_SOC_MPS2
+CFLAGS += -DMICROPY_HW_MCU_NAME='"Cortex-M7"'
+CFLAGS += -DCPU_FREQ_HZ=25000000
+
+LDSCRIPT = mcu/arm/mps2.ld
+
+SRC_BOARD_O = shared/runtime/gchelper_native.o shared/runtime/gchelper_thumb2.o
+
+MPY_CROSS_FLAGS += -march=armv7emdp
+
+MICROPY_FLOAT_IMPL = double
+SUPPORTS_HARDWARE_FP_DOUBLE = 1

ports/qemu/boards/MPS3_AN547/mpconfigboard.mk

@@ -0,0 +1,16 @@
+QEMU_ARCH = arm
+QEMU_MACHINE = mps3-an547
+
+CFLAGS += -mthumb -mcpu=cortex-m55 -mfloat-abi=hard -mfpu=fpv5-d16
+CFLAGS += -DQEMU_SOC_MPS3
+CFLAGS += -DMICROPY_HW_MCU_NAME='"Cortex-M55"'
+CFLAGS += -DCPU_FREQ_HZ=32000000
+
+LDSCRIPT = mcu/arm/mps3.ld
+
+SRC_BOARD_O = shared/runtime/gchelper_generic.o
+
+MPY_CROSS_FLAGS += -march=armv7emdp
+
+MICROPY_FLOAT_IMPL ?= double
+SUPPORTS_HARDWARE_FP_DOUBLE ?= 1

ports/qemu/boards/VIRT_RV32/mpconfigboard.mk

@@ -8,4 +8,4 @@ LDSCRIPT = mcu/rv32/virt.ld
 
 SRC_BOARD_O += shared/runtime/gchelper_native.o shared/runtime/gchelper_rv32i.o
 
-MPY_CROSS_FLAGS += -march=rv32imc
+MPY_CROSS_FLAGS += -march=rv32imc -march-flags=zba

ports/qemu/boards/VIRT_RV64/mpconfigboard.mk

@@ -0,0 +1,11 @@
+QEMU_ARCH = riscv64
+QEMU_MACHINE = virt
+
+CFLAGS += -DQEMU_SOC_VIRT
+CFLAGS += -DMICROPY_HW_MCU_NAME='"$(RV64_ARCH)"'
+
+LDSCRIPT = mcu/rv64/virt.ld
+
+SRC_BOARD_O += shared/runtime/gchelper_native.o shared/runtime/gchelper_rv64i.o
+
+MPY_CROSS_FLAGS += -march=rv64imc

ports/qemu/main.c

@@ -28,7 +28,6 @@
 
 #include "py/compile.h"
 #include "py/runtime.h"
-#include "py/stackctrl.h"
 #include "py/gc.h"
 #include "py/mperrno.h"
 #include "shared/runtime/gchelper.h"
@@ -41,8 +40,7 @@
 static uint32_t gc_heap[MICROPY_HEAP_SIZE / sizeof(uint32_t)];
 
 int main(int argc, char **argv) {
-    mp_stack_ctrl_init();
-    mp_stack_set_limit(10240);
+    mp_cstack_init_with_sp_here(10240);
     gc_init(gc_heap, (char *)gc_heap + MICROPY_HEAP_SIZE);
 
     for (;;) {

ports/qemu/mcu/arm/errorhandler.c

@@ -63,6 +63,8 @@ static const char *EXCEPTION_NAMES_TABLE[] = {
 // R0-R15, PSR, Kind
 uintptr_t registers_copy[18] = { 0 };
 
+#define BIT(v, b) (((v) & (1U << (b))) != 0)
+
 __attribute__((naked)) MP_NORETURN void exception_handler(uintptr_t kind) {
     // Save registers
     __asm volatile (
@@ -127,13 +129,33 @@ __attribute__((naked)) MP_NORETURN void exception_handler(uintptr_t kind) {
             }
             break;
     }
-    printf(" exception caught:\n");
+    printf(" exception caught:\n\n");
+    printf("CPU registers:\n");
     printf("R0:   %08X R1:   %08X R2:   %08X R3:   %08X\n", registers_copy[0], registers_copy[1], registers_copy[2], registers_copy[3]);
     printf("R4:   %08X R5:   %08X R6:   %08X R7:   %08X\n", registers_copy[4], registers_copy[5], registers_copy[6], registers_copy[7]);
     printf("R8:   %08X R9:   %08X R10:  %08X R11:  %08X\n", registers_copy[8], registers_copy[9], registers_copy[10], registers_copy[11]);
     printf("R12:  %08X R13:  %08X R14:  %08X R15:  %08X\n", registers_copy[12], registers_copy[13], registers_copy[14], registers_copy[15]);
     printf("xPSR: %08X\n", registers_copy[16]);
 
+    #if __ARM_ARCH == 7
+    uint32_t cfsr = *(volatile uint32_t *)0xE000ED28;
+    uint32_t hfsr = *(volatile uint32_t *)0xE000ED2C;
+    uint32_t dfsr = *(volatile uint32_t *)0xE000ED30;
+    uint32_t mmfar = *(volatile uint32_t *)0xE000ED34;
+    uint32_t bfar = *(volatile uint32_t *)0xE000ED38;
+
+    printf("\nDebug registers:\n");
+    printf("CFSR: %08lX HFSR: %08lX DFSR: %08lX MMFAR: %08lX BFAR: %08lX\n", cfsr, hfsr, dfsr, mmfar, bfar);
+    printf("CFSR.IACCVIOL:    %d CFSR.DACCVIOL:   %d CFSR.MUNSTKERR: %d CFSR.MSTKERR:   %d\n", BIT(cfsr, 0), BIT(cfsr, 1), BIT(cfsr, 3), BIT(cfsr, 4));
+    printf("CFSR.MLSPERR:     %d CFSR.MMARVALID:  %d CFSR.IBUSERR:   %d CFSR.PRECISERR: %d\n", BIT(cfsr, 5), BIT(cfsr, 7), BIT(cfsr, 8), BIT(cfsr, 9));
+    printf("CFSR.IMPRECISERR: %d CFSR.UNSTKERR:   %d CFSR.STKERR:    %d CFSR.LSPERR:    %d\n", BIT(cfsr, 10), BIT(cfsr, 11), BIT(cfsr, 12), BIT(cfsr, 13));
+    printf("CFSR.BFARVALID:   %d CFSR.UNDEFINSTR: %d CFSR.INVSTATE:  %d CFSR.INVPC:     %d\n", BIT(cfsr, 15), BIT(cfsr, 16), BIT(cfsr, 17), BIT(cfsr, 18));
+    printf("CFSR.NOCP:        %d CFSR.UNALIGNED:  %d CFSR.DIVBYZERO: %d\n", BIT(cfsr, 19), BIT(cfsr, 24), BIT(cfsr, 25));
+    printf("HFSR.VECTTBL:     %d HFSR.FORCED:     %d HFSR.DEBUGEVT:  %d\n", BIT(hfsr, 1), BIT(hfsr, 30), BIT(hfsr, 31));
+    printf("DFSR.HALTED:      %d DFSR.BKPT:       %d DFSR.DWTTRAP:   %d DFSR.VCATCH:    %d\n", BIT(dfsr, 0), BIT(dfsr, 1), BIT(dfsr, 2), BIT(dfsr, 3));
+    printf("DFSR.EXTERNAL:    %d\n", BIT(dfsr, 4));
+    #endif
+
     for (;;) {}
 }
 
@@ -169,7 +191,7 @@ __attribute__((naked)) MP_NORETURN void PendSV_Handler(void) {
     exception_handler(PENDING_SV);
 }
 
-__attribute__((naked)) MP_NORETURN void SysTick_Handler(void) {
+__attribute__((naked, weak)) MP_NORETURN void SysTick_Handler(void) {
     exception_handler(SYSTEM_TICK);
 }