diff --git a/.gitignore b/.gitignore
index b61f4bf0ba..04789a6786 100644
--- a/.gitignore
+++ b/.gitignore
@@ -26,7 +26,7 @@ build/
 *.o
 uart
 work-ver/*
-fpga/work-fpga
+corev_apu/fpga/work-fpga
 stdout/
 work-dpi/
 tb/riscv-isa-sim/
diff --git a/Makefile b/Makefile
index 002c22c032..8f23d25464 100644
--- a/Makefile
+++ b/Makefile
@@ -36,13 +36,7 @@ root-dir := $(dir $(mkfile_path))
 
 support_verilator_4 := $(shell ($(verilator) --version | grep '4\.') > /dev/null 2>&1 ; echo $$?)
 ifeq ($(support_verilator_4), 0)
-	ifndef verilator_threads
-		ifeq ($(shell test `nproc` -ge 4; echo $$?),0)
-			verilator_threads := 4
-		else ifeq ($(shell test `nproc` -ge 2; echo $$?),0)
 			verilator_threads := 2
-		endif
-	endif
 endif
 
 ifndef RISCV
@@ -79,15 +73,22 @@ endif
 
 # Sources
 # Package files -> compile first
-ariane_pkg := core/include/riscv_pkg.sv                              \
+ifeq ($(findstring 32, $(variant)),32)
+    ariane_pkg := core/include/cv32a6_imac_sv0_config_pkg.sv
+else
+    ariane_pkg := core/include/cv64a6_imacfd_sv39_config_pkg.sv
+endif
+ariane_pkg += core/include/riscv_pkg.sv                              \
               corev_apu/riscv-dbg/src/dm_pkg.sv                      \
               core/include/ariane_pkg.sv                             \
+              core/include/ariane_rvfi_pkg.sv                        \
               core/include/std_cache_pkg.sv                          \
               core/include/wt_cache_pkg.sv                           \
               corev_apu/axi/src/axi_pkg.sv                           \
               corev_apu/register_interface/src/reg_intf.sv           \
               corev_apu/register_interface/src/reg_intf_pkg.sv       \
               core/include/axi_intf.sv                               \
+              corev_apu/tb/rvfi_pkg.sv                               \
               corev_apu/tb/ariane_soc_pkg.sv                         \
               corev_apu/tb/ariane_axi_soc_pkg.sv                     \
               core/include/ariane_axi_pkg.sv                         \
@@ -96,12 +97,12 @@ ariane_pkg := core/include/riscv_pkg.sv                              \
 ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
 
 # utility modules
-util := include/instr_tracer_pkg.sv                         \
-        src/util/instr_tracer_if.sv                         \
-        src/util/instr_tracer.sv                            \
-        src/tech_cells_generic/src/cluster_clock_gating.sv  \
-        tb/common/mock_uart.sv                              \
-        src/util/sram.sv
+util := core/include/instr_tracer_pkg.sv                              \
+        common/local/util/instr_tracer_if.sv                          \
+        common/local/util/instr_tracer.sv                             \
+        corev_apu/src/tech_cells_generic/src/cluster_clock_gating.sv  \
+        corev_apu/tb/common/mock_uart.sv                              \
+        common/local/util/sram.sv
 
 ifdef spike-tandem
     util += tb/common/spike.sv
@@ -113,7 +114,7 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
 			$(wildcard tb/test/*/*_pkg.sv*)
 
 # DPI
-dpi := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc))
+dpi := $(patsubst corev_apu/tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard corev_apu/tb/dpi/*.cc))
 
 # filter spike stuff if tandem is not activated
 ifndef spike-tandem
@@ -125,9 +126,10 @@ ifndef DROMAJO
     dpi := $(filter-out ${dpi-library}/dromajo_cosim_dpi.o, $(dpi))
 endif
 
-dpi_hdr := $(wildcard tb/dpi/*.h)
+dpi_hdr := $(wildcard corev_apu/tb/dpi/*.h)
 dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
 CFLAGS := -I$(QUESTASIM_HOME)/include         \
+          -I$(VCS_HOME)/include \
           -I$(RISCV)/include                  \
           -I$(SPIKE_ROOT)/include             \
           $(if $(DROMAJO), -I../corev_apu/tb/dromajo/src,) \
@@ -143,6 +145,7 @@ ifdef spike-tandem
     CFLAGS += -Itb/riscv-isa-sim/install/include/spike
 endif
 
+
 # this list contains the standalone components
 src :=  $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))                  \
         $(filter-out core/fpu/src/fpnew_pkg.sv, $(wildcard core/fpu/src/*.sv))       \
@@ -217,20 +220,21 @@ src :=  $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
         corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv                      \
         corev_apu/tb/ariane_testharness.sv                                           \
         corev_apu/tb/ariane_peripherals.sv                                           \
+        corev_apu/tb/rvfi_tracer.sv                                                      \
         corev_apu/tb/common/uart.sv                                                  \
         corev_apu/tb/common/SimDTM.sv                                                \
         corev_apu/tb/common/SimJTAG.sv
 
 src := $(addprefix $(root-dir), $(src))
 
-uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
+uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
 uart_src := $(addprefix $(root-dir), $(uart_src))
 
-fpga_src :=  $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
+fpga_src :=  $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv)
 fpga_src := $(addprefix $(root-dir), $(fpga_src))
 
 # look for testbenches
-tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
+tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv
 # RISCV asm tests and benchmark setup (used for CI)
 # there is a definesd test-list with selected CI tests
 riscv-test-dir            := tmp/riscv-tests/build/isa/
@@ -290,6 +294,18 @@ else
 	questa-cmd += +jtag_rbb_enable=0
 endif
 
+vcs_build: $(dpi-library)/ariane_dpi.so
+	vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2
+	vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+WT_CACHE +define+RVFI_TRACE $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi
+	vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+WT_CACHE +define+RVFI_TRACE $(filter %.sv,$(util)) +incdir+common/local/util+core/include/+src/util/+$(VCS_HOME)/etc/uvm-1.2/dpi
+	vhdlan -full64 $(filter %.vhd,$(uart_src))
+	vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 -assert svaext +define+WT_CACHE +define+RVFI_TRACE $(filter %.sv,$(src)) +incdir+core/include/+common/submodules/common_cells/include/+common/local/util/+$(VCS_HOME)/etc/uvm-1.2/dpi
+	vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+RVFI_TRACE
+	vcs -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb
+
+vcs: vcs_build
+	./simv +permissive -sv_lib work-dpi/ariane_dpi +permissive-off ++$(elf-bin) | tee vcs.log
+
 # Build the TB and module using QuestaSim
 build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
 	# Optimize top level
@@ -299,24 +315,24 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari
 $(library)/.build-srcs: $(util) $(library)
 	vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
 	# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
-	vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
+	vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
 	# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
 	vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
 	# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
-	vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
+	vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
 	touch $(library)/.build-srcs
 
 # build TBs
 $(library)/.build-tb: $(dpi)
 	# Compile top level
-	vlog$(questa_version) $(compile_flag) -sv $(tbs) -work $(library)
+	vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -sv $(tbs) -work $(library)
 	touch $(library)/.build-tb
 
 $(library):
 	vlib${questa_version} $(library)
 
 # compile DPIs
-$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr)
+$(dpi-library)/%.o: corev_apu/tb/dpi/%.cc $(dpi_hdr)
 	mkdir -p $(dpi-library)
 	$(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@
 
@@ -328,12 +344,7 @@ $(dpi-library)/ariane_dpi.so: $(dpi)
 # single test runs on Questa can be started by calling make <testname>, e.g. make towers.riscv
 # the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
 # if you want to run in batch mode, use make <testname> batch-mode=1
-# alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary		
- 
-generate-trace-vsim:
-	make sim preload=$(preload) elf-bin= batch-mode=1
-	make generate-trace
-
+# alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary
 sim: build
 	vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
 	+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi  \
@@ -409,7 +420,7 @@ CVA6_HOME	   ?= $(realpath -s $(root-dir))
 XRUN_INCDIR :=+incdir+$(CVA6_HOME)/src/axi_node 	\
 	+incdir+$(CVA6_HOME)/src/common_cells/include 	\
 	+incdir+$(CVA6_HOME)/src/util
-XRUN_TB := $(addprefix $(CVA6_HOME)/, tb/ariane_tb.sv)
+XRUN_TB := $(addprefix $(CVA6_HOME)/, corev_apu/tb/ariane_tb.sv)
 
 XRUN_COMP_FLAGS  ?= -64bit -disable_sem2009 -access +rwc 			\
 		    -sv -v93 -uvm -uvmhome $(XRUN_UVMHOME_ARG) 			\
@@ -541,7 +552,7 @@ xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchma
 verilate_command := $(verilator)                                                                                 \
                     $(filter-out %.vhd, $(ariane_pkg))                                                           \
                     $(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src)))                                  \
-                    +define+$(defines)                                                                           \
+                    +define+$(defines) -DRVFI_TRACE=1                                                            \
                     common/local/util/sram.sv                                                                    \
                     corev_apu/tb/common/mock_uart.sv                                                             \
                     +incdir+corev_apu/axi_node                                                                   \
@@ -557,6 +568,7 @@ verilate_command := $(verilator)
                     -Wno-UNOPTFLAT                                                                               \
                     -Wno-BLKANDNBLK                                                                              \
                     -Wno-style                                                                                   \
+                    $(if ($(PRELOAD)!=""), -DPRELOAD=1,)                                                         \
                     $(if $(DROMAJO), -DDROMAJO=1,)                                                               \
                     $(if $(PROFILE),--stats --stats-vars --profile-cfuncs,)                                      \
                     $(if $(DEBUG),--trace --trace-structs,)                                                      \
@@ -714,22 +726,22 @@ check-torture:
 	grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
 	diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
 
-fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
-fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv)
+fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv)
+fpga_filter += $(addprefix $(root-dir), core/include/instr_tracer_pkg.sv)
 fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
 fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
-fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv)
-fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv)
+fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer_if.sv)
+fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
 
 fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
 	@echo "[FPGA] Generate sources"
-	@echo read_vhdl        {$(uart_src)}    > fpga/scripts/add_sources.tcl
-	@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
-	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))}     >> fpga/scripts/add_sources.tcl
-	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} 	   >> fpga/scripts/add_sources.tcl
-	@echo read_verilog -sv {$(fpga_src)}   >> fpga/scripts/add_sources.tcl
+	@echo read_vhdl        {$(uart_src)}    > corev_apu/fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))}     >> corev_apu/fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} 	   >> corev_apu/fpga/scripts/add_sources.tcl
+	@echo read_verilog -sv {$(fpga_src)}   >> corev_apu/fpga/scripts/add_sources.tcl
 	@echo "[FPGA] Generate Bitstream"
-	cd fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
+	cd corev_apu/fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
 
 .PHONY: fpga
 
diff --git a/core/example_tb/Flist.cva6 b/core/Flist.cv32a6_imac_sv0
similarity index 89%
rename from core/example_tb/Flist.cva6
rename to core/Flist.cv32a6_imac_sv0
index 8d3424580c..43159df0a9 100644
--- a/core/example_tb/Flist.cva6
+++ b/core/Flist.cv32a6_imac_sv0
@@ -31,17 +31,22 @@
 +incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
 +incdir+${CVA6_REPO_DIR}/common/local/util/
 
+${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
 // Broken (?) dependencies in packages:
 //    - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
 //      (ariane should not depend on debug-module)
 //    - The core RTL is dependent on tb/ariane_soc_pkg.sv
 //      (RTL should not depend on TB code)
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
-${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv   // TODO: should not be needed.
+// TODO: should not be needed.
+${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
 ${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
-${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv      // TODO: should not be needed.
-${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv        // TODO: ariane_axi_pkg is dependent on this.
+// TODO: should not be needed.
+${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv
+// TODO: ariane_axi_pkg is dependent on this.
+${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
 ${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
+${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
 
 // Packages
 ${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
@@ -82,9 +87,11 @@ ${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
 ${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
 
 // Top-level source files (not necessarily instantiated at the top of the cva6).
+${CVA6_REPO_DIR}/core/ariane_wrapper.sv
 ${CVA6_REPO_DIR}/core/ariane.sv
 ${CVA6_REPO_DIR}/core/alu.sv
-${CVA6_REPO_DIR}/core/fpu_wrap.sv  // Note: depends on fpnew_pkg, above
+// Note: depends on fpnew_pkg, above
+${CVA6_REPO_DIR}/core/fpu_wrap.sv
 ${CVA6_REPO_DIR}/core/branch_unit.sv
 ${CVA6_REPO_DIR}/core/compressed_decoder.sv
 ${CVA6_REPO_DIR}/core/controller.sv
@@ -106,7 +113,8 @@ ${CVA6_REPO_DIR}/core/perf_counters.sv
 ${CVA6_REPO_DIR}/core/ptw.sv
 ${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
 ${CVA6_REPO_DIR}/core/re_name.sv
-${CVA6_REPO_DIR}/core/scoreboard.sv // NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
+// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/scoreboard.sv
 ${CVA6_REPO_DIR}/core/store_buffer.sv
 ${CVA6_REPO_DIR}/core/amo_buffer.sv
 ${CVA6_REPO_DIR}/core/store_unit.sv
@@ -133,7 +141,8 @@ ${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
 
 // Physical Memory Protection
-${CVA6_REPO_DIR}/core/pmp/src/pmp.sv // NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
+// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
 ${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
 
 // Tracer (behavioral code, not RTL)
diff --git a/core/Flist.cv64a6_imafdc_sv39 b/core/Flist.cv64a6_imafdc_sv39
new file mode 100644
index 0000000000..42a64c7164
--- /dev/null
+++ b/core/Flist.cv64a6_imafdc_sv39
@@ -0,0 +1,153 @@
+//////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2021 OpenHW Group
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// Manifest for the CVA6 CORE RTL model.
+//   - This is a CORE-ONLY manifest.
+//   - Relevent synthesis and simulation scripts/Makefiles must set the shell
+//     ENV variable CVA6_REPO_DIR.
+//
+///////////////////////////////////////////////////////////////////////////////
+
++define+WT_DCACHE
+
++incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/include/
++incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
++incdir+${CVA6_REPO_DIR}/common/local/util/
+
+${CVA6_REPO_DIR}/core/include/cv64a6_imacfd_sv39_config_pkg.sv
+// Broken (?) dependencies in packages:
+//    - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
+//      (ariane should not depend on debug-module)
+//    - The core RTL is dependent on tb/ariane_soc_pkg.sv
+//      (RTL should not depend on TB code)
+${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
+// TODO: should not be needed.
+${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
+${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
+// TODO: should not be needed.
+${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv
+// TODO: ariane_axi_pkg is dependent on this.
+${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
+${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
+${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
+
+// Packages
+${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
+${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
+${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
+${CVA6_REPO_DIR}/core/include/axi_intf.sv
+${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
+
+// Common Cells
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/fifo_v3.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/lfsr_8bit.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/lzc.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/rr_arb_tree.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/shift_reg.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/unread.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/popcount.sv
+${CVA6_REPO_DIR}/common/submodules/common_cells/src/exp_backoff.sv
+
+// Floating point unit
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_pkg.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_cast_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_classifier.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_divsqrt_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma_multi.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_noncomp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_block.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_fmt_slice.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_multifmt_slice.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_rounding.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpnew_top.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
+${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
+
+// Top-level source files (not necessarily instantiated at the top of the cva6).
+${CVA6_REPO_DIR}/core/ariane_wrapper.sv
+${CVA6_REPO_DIR}/core/ariane.sv
+${CVA6_REPO_DIR}/core/alu.sv
+// Note: depends on fpnew_pkg, above
+${CVA6_REPO_DIR}/core/fpu_wrap.sv
+${CVA6_REPO_DIR}/core/branch_unit.sv
+${CVA6_REPO_DIR}/core/compressed_decoder.sv
+${CVA6_REPO_DIR}/core/controller.sv
+${CVA6_REPO_DIR}/core/csr_buffer.sv
+${CVA6_REPO_DIR}/core/csr_regfile.sv
+${CVA6_REPO_DIR}/core/decoder.sv
+${CVA6_REPO_DIR}/core/ex_stage.sv
+${CVA6_REPO_DIR}/core/instr_realign.sv
+${CVA6_REPO_DIR}/core/id_stage.sv
+${CVA6_REPO_DIR}/core/issue_read_operands.sv
+${CVA6_REPO_DIR}/core/issue_stage.sv
+${CVA6_REPO_DIR}/core/load_unit.sv
+${CVA6_REPO_DIR}/core/load_store_unit.sv
+${CVA6_REPO_DIR}/core/mmu.sv
+${CVA6_REPO_DIR}/core/mult.sv
+${CVA6_REPO_DIR}/core/multiplier.sv
+${CVA6_REPO_DIR}/core/serdiv.sv
+${CVA6_REPO_DIR}/core/perf_counters.sv
+${CVA6_REPO_DIR}/core/ptw.sv
+${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
+${CVA6_REPO_DIR}/core/re_name.sv
+// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/scoreboard.sv
+${CVA6_REPO_DIR}/core/store_buffer.sv
+${CVA6_REPO_DIR}/core/amo_buffer.sv
+${CVA6_REPO_DIR}/core/store_unit.sv
+${CVA6_REPO_DIR}/core/tlb.sv
+${CVA6_REPO_DIR}/core/commit_stage.sv
+${CVA6_REPO_DIR}/core/axi_shim.sv
+
+// What is "frontend"?
+${CVA6_REPO_DIR}/core/frontend/btb.sv
+${CVA6_REPO_DIR}/core/frontend/bht.sv
+${CVA6_REPO_DIR}/core/frontend/ras.sv
+${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
+${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
+${CVA6_REPO_DIR}/core/frontend/frontend.sv
+
+// Cache subsystem
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
+${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
+
+// Physical Memory Protection
+// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
+${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
+${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
+
+// Tracer (behavioral code, not RTL)
+${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
+${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
+${CVA6_REPO_DIR}/common/local/util/sram.sv
+
+// end of manifest
diff --git a/core/ariane.sv b/core/ariane.sv
index 5668e60699..6217c7fd99 100644
--- a/core/ariane.sv
+++ b/core/ariane.sv
@@ -42,6 +42,11 @@ module ariane import ariane_pkg::*; #(
   // firesim trace port
   output traced_instr_pkg::trace_port_t trace_o,
 `endif
+`ifdef RVFI_TRACE
+  // RISC-V formal interface port (`rvfi`):
+  // Can be left open when formal tracing is not needed.
+  output ariane_rvfi_pkg::rvfi_port_t  rvfi_o,
+`endif
 `ifdef PITON_ARIANE
   // L15 (memory side)
   output wt_cache_pkg::l15_req_t       l15_req_o,
@@ -894,4 +899,38 @@ module ariane import ariane_pkg::*; #(
 `endif // VERILATOR
 //pragma translate_on
 
+`ifdef RVFI_TRACE
+  always_comb
+    for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
+      logic exception, mem_exception;
+      exception = commit_instr_id_commit[i].valid && commit_instr_id_commit[i].ex.valid && ex_commit.valid;
+      mem_exception = exception &&
+        (commit_instr_id_commit[i].ex.cause == riscv::INSTR_ADDR_MISALIGNED ||
+         commit_instr_id_commit[i].ex.cause == riscv::INSTR_ACCESS_FAULT ||
+         commit_instr_id_commit[i].ex.cause == riscv::ILLEGAL_INSTR ||
+         commit_instr_id_commit[i].ex.cause == riscv::LD_ADDR_MISALIGNED ||
+         commit_instr_id_commit[i].ex.cause == riscv::LD_ACCESS_FAULT ||
+         commit_instr_id_commit[i].ex.cause == riscv::ST_ADDR_MISALIGNED ||
+         commit_instr_id_commit[i].ex.cause == riscv::ST_ACCESS_FAULT ||
+         commit_instr_id_commit[i].ex.cause == riscv::INSTR_PAGE_FAULT ||
+         commit_instr_id_commit[i].ex.cause == riscv::LOAD_PAGE_FAULT ||
+         commit_instr_id_commit[i].ex.cause == riscv::STORE_PAGE_FAULT);
+      // when rvfi_valid, the instruction is executed
+      rvfi_o[i].valid    = (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) ||
+        (exception && (commit_instr_id_commit[i].ex.cause == riscv::ENV_CALL_MMODE ||
+                  commit_instr_id_commit[i].ex.cause == riscv::ENV_CALL_SMODE ||
+                  commit_instr_id_commit[i].ex.cause == riscv::ENV_CALL_UMODE));
+      rvfi_o[i].insn     = commit_instr_id_commit[i].ex.tval[31:0];
+      // when trap, the instruction is not executed
+      rvfi_o[i].trap     = mem_exception;
+      rvfi_o[i].mode     = debug_mode ? 2'b10 : priv_lvl;
+      rvfi_o[i].ixl      = riscv::XLEN == 64 ? 2 : 1;
+      rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1;
+      rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2;
+      rvfi_o[i].rd_addr  = commit_instr_id_commit[i].rd;
+      rvfi_o[i].rd_wdata = ariane_pkg::is_rd_fpr(commit_instr_id_commit[i].op) == 0 ? wdata_commit_id[i] : commit_instr_id_commit[i].result;
+      rvfi_o[i].pc_rdata = commit_instr_id_commit[i].pc;
+    end
+`endif
+
 endmodule // ariane
diff --git a/core/ariane_wrapper.sv b/core/ariane_wrapper.sv
new file mode 100644
index 0000000000..a430cb647c
--- /dev/null
+++ b/core/ariane_wrapper.sv
@@ -0,0 +1,237 @@
+// Copyright 2021 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
+
+module ariane_wrapper import ariane_pkg::*; #(
+  parameter ariane_pkg::ariane_cfg_t ArianeCfg     = ariane_pkg::ArianeDefaultConfig
+) (
+  input  logic                         clk_i,
+  input  logic                         rst_ni,
+  // Core ID, Cluster ID and boot address are considered more or less static
+  input  logic [63:0]                  boot_addr_i,  // reset boot address
+  input  logic [63:0]                  hart_id_i,    // hart id in a multicore environment (reflected in a CSR)
+
+  // Interrupt inputs
+  input  logic [1:0]                   irq_i,        // level sensitive IR lines, mip & sip (async)
+  input  logic                         ipi_i,        // inter-processor interrupts (async)
+  // Timer facilities
+  input  logic                         time_irq_i,   // timer interrupt in (async)
+  input  logic                         debug_req_i,  // debug request (async)
+`ifdef FIRESIM_TRACE
+  // firesim trace port
+  output traced_instr_pkg::trace_port_t trace_o,
+`endif
+  // RISC-V formal interface port (`rvfi`):
+  // Can be left open when formal tracing is not needed.
+  output logic                         rvfi_valid_1,
+  output logic[63:0]                   rvfi_order_1,
+  output logic[31:0]                   rvfi_insn_1,
+  output logic                         rvfi_trap_1,
+  output logic                         rvfi_halt_1,
+  output logic                         rvfi_intr_1,
+  output logic[2:0]                    rvfi_mode_1,
+  output logic[2:0]                    rvfi_ixl_1,
+  output logic[4:0]                    rvfi_rs1_addr_1,
+  output logic[4:0]                    rvfi_rs2_addr_1,
+  output logic[riscv::XLEN-1:0]        rvfi_rs1_rdata_1,
+  output logic[riscv::XLEN-1:0]        rvfi_rs2_rdata_1,
+  output logic[4:0]                    rvfi_rd_addr_1,
+  output logic[riscv::XLEN-1:0]        rvfi_rd_wdata_1,
+  output logic[riscv::XLEN-1:0]        rvfi_pc_rdata_1,
+  output logic[riscv::XLEN-1:0]        rvfi_pc_wdata_1,
+  output logic[riscv::XLEN-1:0]        rvfi_mem_addr_1,
+  output logic[(riscv::XLEN)/8-1:0]    rvfi_mem_rmask_1,
+  output logic[(riscv::XLEN)/8-1:0]    rvfi_mem_wmask_1,
+  output logic[riscv::XLEN-1:0]        rvfi_mem_rdata_1,
+  output logic[riscv::XLEN-1:0]        rvfi_mem_wdata_1,
+  output logic                         rvfi_valid_0,
+  output logic[63:0]                   rvfi_order_0,
+  output logic[31:0]                   rvfi_insn_0,
+  output logic                         rvfi_trap_0,
+  output logic                         rvfi_halt_0,
+  output logic                         rvfi_intr_0,
+  output logic[2:0]                    rvfi_mode_0,
+  output logic[2:0]                    rvfi_ixl_0,
+  output logic[4:0]                    rvfi_rs1_addr_0,
+  output logic[4:0]                    rvfi_rs2_addr_0,
+  output logic[riscv::XLEN-1:0]        rvfi_rs1_rdata_0,
+  output logic[riscv::XLEN-1:0]        rvfi_rs2_rdata_0,
+  output logic[4:0]                    rvfi_rd_addr_0,
+  output logic[riscv::XLEN-1:0]        rvfi_rd_wdata_0,
+  output logic[riscv::XLEN-1:0]        rvfi_pc_rdata_0,
+  output logic[riscv::XLEN-1:0]        rvfi_pc_wdata_0,
+  output logic[riscv::XLEN-1:0]        rvfi_mem_addr_0,
+  output logic[(riscv::XLEN)/8-1:0]    rvfi_mem_rmask_0,
+  output logic[(riscv::XLEN)/8-1:0]    rvfi_mem_wmask_0,
+  output logic[riscv::XLEN-1:0]        rvfi_mem_rdata_0,
+  output logic[riscv::XLEN-1:0]        rvfi_mem_wdata_0,
+`ifdef PITON_ARIANE
+  // L15 (memory side)
+  output wt_cache_pkg::l15_req_t       l15_req_o,
+  input  wt_cache_pkg::l15_rtrn_t      l15_rtrn_i
+`else
+  // memory side, AXI Master
+  output ariane_axi::id_t              aw_id_o,
+  output ariane_axi::addr_t            aw_addr_o,
+  output axi_pkg::len_t                aw_len_o,
+  output axi_pkg::size_t               aw_size_o,
+  output axi_pkg::burst_t              aw_burst_o,
+  output logic                         aw_lock_o,
+  output axi_pkg::cache_t              aw_cache_o,
+  output axi_pkg::prot_t               aw_prot_o,
+  output axi_pkg::qos_t                aw_qos_o,
+  output axi_pkg::region_t             aw_region_o,
+  output axi_pkg::atop_t               aw_atop_o,
+  output ariane_axi::user_t            aw_user_o,
+  output logic                         aw_valid_o,
+  output ariane_axi::data_t            w_data_o,
+  output ariane_axi::strb_t            w_strb_o,
+  output logic                         w_last_o,
+  output ariane_axi::user_t            w_user_o,
+  output logic                         w_valid_o,
+  output logic                         b_ready_o,
+  output ariane_axi::id_t              ar_id_o,
+  output ariane_axi::addr_t            ar_addr_o,
+  output axi_pkg::len_t                ar_len_o,
+  output axi_pkg::size_t               ar_size_o,
+  output axi_pkg::burst_t              ar_burst_o,
+  output logic                         ar_lock_o,
+  output axi_pkg::cache_t              ar_cache_o,
+  output axi_pkg::prot_t               ar_prot_o,
+  output axi_pkg::qos_t                ar_qos_o,
+  output axi_pkg::region_t             ar_region_o,
+  output ariane_axi::user_t            ar_user_o,
+  output logic                         ar_valid_o,
+  output logic                         r_ready_o,
+  input  logic                         aw_ready_i,
+  input  logic                         ar_ready_i,
+  input  logic                         w_ready_i,
+  input  logic                         b_valid_i,
+  input  ariane_axi::id_t              b_id_i,
+  input  axi_pkg::resp_t               b_resp_i,
+  input  ariane_axi::user_t            b_user_i,
+  input  logic                         r_valid_i,
+  input  ariane_axi::id_t              r_id_i,
+  input  ariane_axi::data_t            r_data_i,
+  input  axi_pkg::resp_t               r_resp_i,
+  input  logic                         r_last_i,
+  input  ariane_axi::user_t            r_user_i
+`endif
+);
+
+  ariane_axi::req_t               axi_ariane_req;
+  ariane_axi::resp_t              axi_ariane_resp;
+  ariane_rvfi_pkg::rvfi_port_t    rvfi;
+
+  assign aw_id_o                  = axi_ariane_req.aw.id;
+  assign aw_addr_o                = axi_ariane_req.aw.addr;
+  assign aw_len_o                 = axi_ariane_req.aw.len;
+  assign aw_size_o                = axi_ariane_req.aw.size;
+  assign aw_burst_o               = axi_ariane_req.aw.burst;
+  assign aw_lock_o                = axi_ariane_req.aw.lock;
+  assign aw_cache_o               = axi_ariane_req.aw.cache;
+  assign aw_prot_o                = axi_ariane_req.aw.prot;
+  assign aw_qos_o                 = axi_ariane_req.aw.qos;
+  assign aw_region_o              = axi_ariane_req.aw.region;
+  assign aw_atop_o                = axi_ariane_req.aw.atop;
+  assign aw_user_o                = axi_ariane_req.aw.user;
+  assign aw_valid_o               = axi_ariane_req.aw_valid;
+  assign w_data_o                 = axi_ariane_req.w.data;
+  assign w_strb_o                 = axi_ariane_req.w.strb;
+  assign w_last_o                 = axi_ariane_req.w.last;
+  assign w_user_o                 = axi_ariane_req.w.user;
+  assign w_valid_o                = axi_ariane_req.w_valid;
+  assign b_ready_o                = axi_ariane_req.b_ready;
+  assign ar_id_o                  = axi_ariane_req.ar.id;
+  assign ar_addr_o                = axi_ariane_req.ar.addr;
+  assign ar_len_o                 = axi_ariane_req.ar.len;
+  assign ar_size_o                = axi_ariane_req.ar.size;
+  assign ar_burst_o               = axi_ariane_req.ar.burst;
+  assign ar_lock_o                = axi_ariane_req.ar.lock;
+  assign ar_cache_o               = axi_ariane_req.ar.cache;
+  assign ar_prot_o                = axi_ariane_req.ar.prot;
+  assign ar_qos_o                 = axi_ariane_req.ar.qos;
+  assign ar_region_o              = axi_ariane_req.ar.region;
+  assign ar_user_o                = axi_ariane_req.ar.user;
+  assign ar_valid_o               = axi_ariane_req.ar_valid;
+  assign r_ready_o                = axi_ariane_req.r_ready;
+
+  assign axi_ariane_resp.aw_ready = aw_ready_i;
+  assign axi_ariane_resp.ar_ready = ar_ready_i;
+  assign axi_ariane_resp.w_ready  = w_ready_i;
+  assign axi_ariane_resp.b_valid  = b_valid_i;
+  assign axi_ariane_resp.b.id     = b_id_i;
+  assign axi_ariane_resp.b.resp   = b_resp_i;
+  assign axi_ariane_resp.b.user   = b_user_i;
+  assign axi_ariane_resp.r_valid  = r_valid_i;
+  assign axi_ariane_resp.r.id     = r_id_i;
+  assign axi_ariane_resp.r.data   = r_data_i;
+  assign axi_ariane_resp.r.resp   = r_resp_i;
+  assign axi_ariane_resp.r.last   = r_last_i;
+  assign axi_ariane_resp.r.user   = r_user_i;
+
+  assign rvfi_valid_1             = rvfi[1].valid;
+  assign rvfi_order_1             = rvfi[1].order;
+  assign rvfi_insn_1              = rvfi[1].insn;
+  assign rvfi_trap_1              = rvfi[1].trap;
+  assign rvfi_halt_1              = rvfi[1].halt;
+  assign rvfi_intr_1              = rvfi[1].intr;
+  assign rvfi_mode_1              = rvfi[1].mode;
+  assign rvfi_ixl_1               = rvfi[1].ixl;
+  assign rvfi_rs1_addr_1          = rvfi[1].rs1_addr;
+  assign rvfi_rs2_addr_1          = rvfi[1].rs2_addr;
+  assign rvfi_rs1_rdata_1         = rvfi[1].rs1_rdata;
+  assign rvfi_rs2_rdata_1         = rvfi[1].rs2_rdata;
+  assign rvfi_rd_addr_1           = rvfi[1].rd_addr;
+  assign rvfi_rd_wdata_1          = rvfi[1].rd_wdata;
+  assign rvfi_pc_rdata_1          = rvfi[1].pc_rdata;
+  assign rvfi_pc_wdata_1          = rvfi[1].pc_wdata;
+  assign rvfi_mem_addr_1          = rvfi[1].mem_addr;
+  assign rvfi_mem_rmask_1         = rvfi[1].mem_rmask;
+  assign rvfi_mem_wmask_1         = rvfi[1].mem_wmask;
+  assign rvfi_mem_rdata_1         = rvfi[1].mem_rdata;
+  assign rvfi_mem_wdata_1         = rvfi[1].mem_wdata;
+  assign rvfi_valid_0             = rvfi[0].valid;
+  assign rvfi_order_0             = rvfi[0].order;
+  assign rvfi_insn_0              = rvfi[0].insn;
+  assign rvfi_trap_0              = rvfi[0].trap;
+  assign rvfi_halt_0              = rvfi[0].halt;
+  assign rvfi_intr_0              = rvfi[0].intr;
+  assign rvfi_mode_0              = rvfi[0].mode;
+  assign rvfi_ixl_0               = rvfi[0].ixl;
+  assign rvfi_rs1_addr_0          = rvfi[0].rs1_addr;
+  assign rvfi_rs2_addr_0          = rvfi[0].rs2_addr;
+  assign rvfi_rs1_rdata_0         = rvfi[0].rs1_rdata;
+  assign rvfi_rs2_rdata_0         = rvfi[0].rs2_rdata;
+  assign rvfi_rd_addr_0           = rvfi[0].rd_addr;
+  assign rvfi_rd_wdata_0          = rvfi[0].rd_wdata;
+  assign rvfi_pc_rdata_0          = rvfi[0].pc_rdata;
+  assign rvfi_pc_wdata_0          = rvfi[0].pc_wdata;
+  assign rvfi_mem_addr_0          = rvfi[0].mem_addr;
+  assign rvfi_mem_rmask_0         = rvfi[0].mem_rmask;
+  assign rvfi_mem_wmask_0         = rvfi[0].mem_wmask;
+  assign rvfi_mem_rdata_0         = rvfi[0].mem_rdata;
+  assign rvfi_mem_wdata_0         = rvfi[0].mem_wdata;
+
+  ariane #(
+    .ArianeCfg  ( ariane_soc::ArianeSocCfg )
+  ) i_ariane (
+    .clk_i                ( clk_i           ),
+    .rst_ni               ( rst_ni          ),
+    .boot_addr_i          ( boot_addr_i     ),
+    .hart_id_i            ( hart_id_i       ),
+    .irq_i                ( irq_i           ),
+    .ipi_i                ( ipi_i           ),
+    .time_irq_i           ( time_irq_i      ),
+    .rvfi_o               ( rvfi            ),
+    .debug_req_i          ( debug_req_i     ),
+    .axi_req_o            ( axi_ariane_req  ),
+    .axi_resp_i           ( axi_ariane_resp )
+  );
+
+endmodule // ariane_wrapper
diff --git a/core/example_tb/.gitignore b/core/example_tb/.gitignore
deleted file mode 100644
index 0ad1458b42..0000000000
--- a/core/example_tb/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-verilator_results
-verilator_work
-dsim_results
diff --git a/core/example_tb/Flist.cva6_tb b/core/example_tb/Flist.cva6_tb
deleted file mode 100644
index a6292a34d4..0000000000
--- a/core/example_tb/Flist.cva6_tb
+++ /dev/null
@@ -1,34 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-//
-// Copyright 2021 OpenHW Group
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     https://solderpad.org/licenses/
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-//
-///////////////////////////////////////////////////////////////////////////////
-//
-// Manifest for the CVA6 TB.
-//   - This is a CORE-ONLY testbench.
-//   - Relevent simulation scripts/Makefiles must set the shell ENV variable
-//     CVA6_TB_DIR as required.
-//
-///////////////////////////////////////////////////////////////////////////////
-
-// These need to be moved
-${CVA6_REPO_DIR}/corev_apu/axi_mem_if/src/axi2mem.sv
-${CVA6_REPO_DIR}/common/local/util/axi_master_connect.sv
-${CVA6_REPO_DIR}/corev_apu/tb/ariane_axi_soc_pkg.sv
-
-${CVA6_TB_DIR}/tb_components/cva6_core_tb_sram.sv
-${CVA6_TB_DIR}/cva6_tb.sv
diff --git a/core/example_tb/Makefile b/core/example_tb/Makefile
deleted file mode 100644
index 52c4da2d32..0000000000
--- a/core/example_tb/Makefile
+++ /dev/null
@@ -1,202 +0,0 @@
-###############################################################################
-#
-# Copyright 2021 OpenHW Group
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     https://solderpad.org/licenses/
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-#
-###############################################################################
-#
-# Makefile for the CVA6 "core_only" testbench.
-#
-###############################################################################
-
-mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
-root-dir    := $(dir $(mkfile_path))
-
-ifndef CVA6_REPO_DIR
-$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...)
-export CVA6_REPO_DIR = $(abspath $(root-dir)../..)
-export CVA6_TB_DIR   = $(root-dir)
-endif
-
-.DEFAULT_GOAL := help
-
-###############################################################################
-# Cadence Xcelium specific commands, variables
-###############################################################################
-XRUN                   ?= xrun
-XRUN_COMP_FLAGS        ?= -sv -64bit -disable_sem2009 -access +rwc -timescale 1ns/1ps
-XRUN_ACC_FLAGS         ?= 
-XRUN_DISABLED_WARNINGS ?= -nowarn UEXPSC
-XRUN_UVMHOME_ARG       ?= -uvm -uvmhome CDNS-1.2-ML
-XRUN_COMPL_LOG         ?= xrun_compl.log
-XRUN_RUN_LOG           ?= xrun_run.log
-XRUN_RESULTS_DIR       ?= xrun_results
-
-XRUN_COMP = $(XRUN_COMP_FLAGS) \
-            $(XRUN_ACC_FLAGS) \
-            $(XRUN_DISABLED_WARNINGS) \
-            $(XRUN_UVMHOME_ARG) \
-            -l $(XRUN_COMPL_LOG) \
-            -f $(CVA6_TB_DIR)/Flist.cva6 \
-            -f $(CVA6_TB_DIR)/Flist.cva6_tb \
-            -top cva6_core_only_tb \
-            -elaborate
-
-xrun_comp:
-	@echo "[XRUN] Building Model"
-	mkdir -p $(XRUN_RESULTS_DIR)
-	cd $(XRUN_RESULTS_DIR) && \
-	$(XRUN) $(XRUN_COMP)
-
-xrun_run: xrun_comp
-	@echo "[XRUN] Running Model"
-	cd $(XRUN_RESULTS_DIR) && \
-	$(XRUN) -R -xmlibdirname ./xcelium.d -l $(XRUN_RUN_LOG)
-
-xrun_clean_all:
-	@echo "[XRUN] Cleanup (entire xrun_results dir)"
-	rm -rf $(XRUN_RESULTS_DIR)
-
-###############################################################################
-# dsim-specific commands, variables
-###############################################################################
-DSIM               ?= dsim
-DSIM_HOME          ?= /tools/Metrics/dsim
-DSIM_CMP_FLAGS     ?= $(TIMESCALE) -top worklib.$(top_level) -pli_lib
-DSIM_WORK_DIR      ?= dsim_work
-DSIM_RESULTS_DIR   ?= dsim_results
-DSIM_UVMHOME_ARG   ?= +incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm_pkg.sv
-DSIM_COMPL_LOG     ?= dsim_compl.log
-DSIM_RUN_LOG       ?= dsim_run.log
-DSIM_IMAGE         ?= dsim.out
-DSIM_ACC_FLAGS     ?= +acc
-DSIM_DMP_FILE      ?= dsim.fst
-DSIM_DMP_FLAGS     ?= -waves $(DSIM_DMP_FILE)
-
-DSIM_COMP = $(DSIM_COMP_FLAGS) \
-            $(DSIM_ACC_FLAGS) \
-            $(DSIM_DISABLED_WARNINGS) \
-            $(DSIM_UVMHOME_ARG) \
-            -l $(DSIM_COMPL_LOG) \
-            -genimage $(DSIM_IMAGE) \
-            -f $(CVA6_TB_DIR)/Flist.cva6 \
-            -f $(CVA6_TB_DIR)/Flist.cva6_tb
-
-dsim_comp:
-	@echo "[DSIM] Building Model"
-	mkdir -p $(DSIM_RESULTS_DIR)
-	cd $(DSIM_RESULTS_DIR) && \
-	$(DSIM) $(DSIM_COMP)
-
-dsim_run: dsim_comp
-	@echo "[DSIM] Running Model"
-	cd $(DSIM_RESULTS_DIR) && \
-	$(DSIM) \
-		$(DSIM_RUN_FLAGS) \
-		$(DSIM_DMP_FLAGS) \
-		-l $(DSIM_RUN_LOG) \
-		-image $(DSIM_IMAGE) \
-		-sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so
-
-dsim_clean:
-	@echo "[DSIM] Cleanup (select contents of dsim_results dir)"
-	cd $(DSIM_RESULTS_DIR) && \
-	rm -rf $(DSIM_RESULTS_DIR) && \
-	rm -rf $(DSIM_WORK_DIR) && \
-	rm -f $(DSIM_IMAGE) && \
-	rm -f $(DSIM_COMPL_LOG) && \
-	rm -f $(DSIM_RUN_LOG) && \
-	rm -f dsim.env && \
-	rm -f metrics.db && \
-	rm -f metrics_history.db && \
-	rm -f trace_hart*.log && \
-	rm -f $(DSIM_DMP_FILE) && \
-	rm -f $(DSIM_DMP_FILE).hier
-
-dsim_clean_all:
-	@echo "[DSIM] Cleanup (entire dsim_results dir)"
-	rm -rf $(DSIM_RESULTS_DIR)
-
-###############################################################################
-# Verilator
-###############################################################################
-
-VERILATOR             ?= verilator
-VERILATOR_FLAGS       ?= 
-VERILATOR_WORK_DIR    ?= verilator_work
-VERILATOR_RESULTS_DIR ?= verilator_results
-
-verilate:
-	@echo "[VERILATOR] Building Model"
-	$(VERILATOR) \
-		-Werror-PINMISSING \
-		-Werror-IMPLICIT \
-		-Wno-fatal \
-		-Wno-PINCONNECTEMPTY \
-		-Wno-ASSIGNDLY \
-		-Wno-DECLFILENAME \
-		-Wno-UNUSED \
-		-Wno-UNOPTFLAT \
-		-Wno-BLKANDNBLK \
-		-Wno-style \
-		-Wall --cc  --vpi --exe \
-		--top-module cva6_core_only_tb \
-		--Mdir $(VERILATOR_WORK_DIR) -O3 \
-		-f $(CVA6_TB_DIR)/Flist.cva6 \
-		-f $(CVA6_TB_DIR)/Flist.cva6_tb \
-		$(CVA6_TB_DIR)/cva6_tb_verilator.cpp
-
-veri_comp: verilate
-	@echo "[VERILATOR] Compiling Model"
-	$(MAKE) -C $(VERILATOR_WORK_DIR) -f Vcva6_core_only_tb.mk
-
-veri_run: veri_comp
-	@echo "[VERILATOR] Running Model"
-	mkdir -p $(VERILATOR_RESULTS_DIR) && \
-	cp $(VERILATOR_WORK_DIR)/Vcva6_core_only_tb $(VERILATOR_RESULTS_DIR)
-	cd $(VERILATOR_RESULTS_DIR) && \
-		./Vcva6_core_only_tb $(VERILATOR_FLAGS)
-
-veri_clean_all:
-	@echo "[VERILATOR] Cleanup (both work and results dirs)"
-	rm -rf $(VERILATOR_WORK_DIR)
-	rm -rf $(VERILATOR_RESULTS_DIR)
-
-###############################################################################
-# Common targets and rules
-###############################################################################
-
-clean_all: xrun_clean_all dsim_clean_all veri_clean_all
-
-
-help:
-	@echo "Shell environment:"
-	@echo "   CVA6_REPO_DIR  : $(CVA6_REPO_DIR)"
-	@echo "   CVA6_TB_DIR    : $(CVA6_TB_DIR)"
-	@echo "Verilator targets:"
-	@echo "   make verilate  : Builds verilator"
-	@echo "   make veri_comp : Builds and compiles verilator"
-	@echo "   make veri_run  : Builds, compiles and runs"
-	@echo "DSIM targets:"
-	@echo "   make dsim_comp : Compiles with DSIM"
-	@echo "   make dsim_run  : Compiles and runs with DSIM"
-	@echo "XRUN targets:"
-	@echo "   make xrun_comp : Compiles with XRUN"
-	@echo "   make xrun_run  : Compiles and runs with XRUN"
-	@echo "Clean-up targets:"
-	@echo "   make clean_all : Deletes ALL generated files"
-	@echo "Support for other simulators on the ToDo list..."
-
diff --git a/core/example_tb/Mem_init.txt b/core/example_tb/Mem_init.txt
deleted file mode 100755
index ed46991e61..0000000000
--- a/core/example_tb/Mem_init.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-@0000000
-35 A8 01 00 73 2F 20 34 A1 4F 63 04 FF 03 A5 4F 
-63 01 FF 03 AD 4F 63 0E FF 01 13 0F 00 00 63 03 
-0F 00 02 8F 73 2F 20 34 63 53 0F 00 09 A0 93 E1 
-91 53 17 1F 00 00 23 27 3F FC E5 BF 81 40 01 41 
-81 41 01 42 81 42 01 43 81 43 01 44 81 44 01 45 
-81 45 01 46 81 46 01 47 81 47 01 48 81 48 01 49 
-81 49 01 4A 81 4A 01 4B 81 4B 01 4C 81 4C 01 4D 
-81 4D 01 4E 81 4E 01 4F 81 4F 73 25 40 F1 01 E1 
-97 02 00 00 93 82 02 01 73 90 52 30 73 50 00 18 
-97 02 00 00 93 82 02 02 73 90 52 30 9B 02 10 00 
-D6 12 FD 12 73 90 02 3B FD 42 73 90 02 3A 01 00 
-97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 
-73 50 30 30 73 50 40 30 81 41 97 02 00 00 93 82 
-A2 F3 73 90 52 30 05 45 7E 05 63 5A 05 00 0F 00 
-F0 0F 85 41 93 08 D0 05 01 45 73 00 00 00 93 02 
-00 00 63 89 02 00 73 90 52 10 AD 62 9B 82 92 10 
-73 90 22 30 73 50 00 30 97 02 00 00 93 82 42 01 
-73 90 12 34 73 25 40 F1 73 00 20 30 81 40 01 41 
-33 87 20 00 81 43 89 41 63 1B 77 34 85 40 05 41 
-33 87 20 00 89 43 8D 41 63 13 77 34 8D 40 1D 41 
-33 87 20 00 A9 43 91 41 63 1B 77 32 81 40 37 81 
-FF FF 33 87 20 00 E1 73 95 41 63 12 77 32 B7 00 
-00 80 01 41 33 87 20 00 B7 03 00 80 99 41 63 18 
-77 30 B7 00 00 80 37 81 FF FF 33 87 20 00 C1 73 
-FD 33 BE 03 9D 41 63 1C 77 2E 81 40 37 81 00 00 
-7D 31 33 87 20 00 A1 63 FD 33 A1 41 63 11 77 2E 
-B7 00 00 80 FD 30 01 41 33 87 20 00 B7 03 00 80 
-FD 33 A5 41 63 15 77 2C B7 00 00 80 FD 30 37 81 
-00 00 7D 31 33 87 20 00 C1 63 85 23 BE 03 F9 13 
-A9 41 63 16 77 2A B7 00 00 80 37 81 00 00 7D 31 
-33 87 20 00 B7 83 00 80 FD 33 AD 41 63 19 77 28 
-B7 00 00 80 FD 30 37 81 FF FF 33 87 20 00 B7 83 
-FF 7F FD 33 B1 41 63 1C 77 26 81 40 7D 51 33 87 
-20 00 FD 53 B5 41 63 14 77 26 FD 50 05 41 33 87 
-20 00 81 43 B9 41 63 1C 77 24 FD 50 7D 51 33 87 
-20 00 F9 53 BD 41 63 14 77 24 85 40 37 01 00 80 
-7D 31 33 87 20 00 9B 03 10 00 FE 03 C1 41 63 18 
-77 22 B5 40 2D 41 8A 90 E1 43 C5 41 63 91 70 22 
-B9 40 2D 41 06 91 E5 43 C9 41 63 1A 71 20 B5 40 
-86 90 E9 43 CD 41 63 94 70 20 01 42 B5 40 2D 41 
-33 87 20 00 13 03 07 00 05 02 89 42 E3 18 52 FE 
-E1 43 D1 41 63 15 73 1E 01 42 B9 40 2D 41 33 87 
-20 00 01 00 13 03 07 00 05 02 89 42 E3 17 52 FE 
-E5 43 D5 41 63 15 73 1C 01 42 BD 40 2D 41 33 87 
-20 00 01 00 01 00 13 03 07 00 05 02 89 42 E3 16 
-52 FE E9 43 D9 41 63 14 73 1A 01 42 B5 40 2D 41 
-33 87 20 00 05 02 89 42 E3 1A 52 FE E1 43 DD 41 
-63 17 77 18 01 42 B9 40 2D 41 01 00 33 87 20 00 
-05 02 89 42 E3 19 52 FE E5 43 E1 41 63 19 77 16 
-01 42 BD 40 2D 41 01 00 01 00 33 87 20 00 05 02 
-89 42 E3 18 52 FE E9 43 E5 41 63 1A 77 14 01 42 
-B5 40 01 00 2D 41 33 87 20 00 05 02 89 42 E3 19 
-52 FE E1 43 E9 41 63 1C 77 12 01 42 B9 40 01 00 
-2D 41 01 00 33 87 20 00 05 02 89 42 E3 18 52 FE 
-E5 43 ED 41 63 1D 77 10 01 42 BD 40 01 00 01 00 
-2D 41 33 87 20 00 05 02 89 42 E3 18 52 FE E9 43 
-F1 41 63 1E 77 0E 01 42 2D 41 B5 40 33 87 20 00 
-05 02 89 42 E3 1A 52 FE E1 43 F5 41 63 11 77 0E 
-01 42 2D 41 B9 40 01 00 33 87 20 00 05 02 89 42 
-E3 19 52 FE E5 43 F9 41 63 13 77 0C 01 42 2D 41 
-BD 40 01 00 01 00 33 87 20 00 05 02 89 42 E3 18 
-52 FE E9 43 FD 41 63 14 77 0A 01 42 2D 41 01 00 
-B5 40 33 87 20 00 05 02 89 42 E3 19 52 FE E1 43 
-93 01 00 02 63 15 77 08 01 42 2D 41 01 00 B9 40 
-01 00 33 87 20 00 05 02 89 42 E3 18 52 FE E5 43 
-93 01 10 02 63 15 77 06 01 42 2D 41 01 00 01 00 
-BD 40 33 87 20 00 05 02 89 42 E3 18 52 FE E9 43 
-93 01 20 02 63 15 77 04 BD 40 06 81 BD 43 93 01 
-30 02 63 1E 71 02 93 00 00 02 33 81 00 00 93 03 
-00 02 93 01 40 02 63 14 71 02 B3 00 00 00 81 43 
-93 01 50 02 63 9D 70 00 C1 40 79 41 33 80 20 00 
-81 43 93 01 60 02 63 14 70 00 63 1F 30 00 0F 00 
-F0 0F 63 80 01 00 86 01 93 E1 11 00 93 08 D0 05 
-13 85 01 00 73 00 00 00 0F 00 F0 0F 85 41 93 08 
-D0 05 01 45 73 00 00 00 00 00 00 00 00 00 00 00 
-00 00 00 00 00 00 
-@0001000
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
-00 00 00 00 00 00 00 00 
diff --git a/core/example_tb/README.md b/core/example_tb/README.md
deleted file mode 100644
index eb3c4f63b1..0000000000
--- a/core/example_tb/README.md
+++ /dev/null
@@ -1,11 +0,0 @@
-## Experimental Stand-alone testbench for the CVA6
-This do-nothing TB supports experiments with the CVA6 to develop a standalone testbenech for the CVA6.
-It uses a "core-only" manifest file `Flist.cva6`.
-
-### Current status:
-Compiles and runs without errors for a few thousand clock cycles under either Verilator, Metrics DSIM or Cadence Xcelium (xrun).
-
-### Give it a try:
-```
-$ make help
-```
diff --git a/core/example_tb/bootrom/.gen_rom.py.swp b/core/example_tb/bootrom/.gen_rom.py.swp
deleted file mode 100644
index f0e667b110..0000000000
Binary files a/core/example_tb/bootrom/.gen_rom.py.swp and /dev/null differ
diff --git a/core/example_tb/bootrom/.gitignore b/core/example_tb/bootrom/.gitignore
deleted file mode 100644
index b553ec26ea..0000000000
--- a/core/example_tb/bootrom/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-*.elf
-*.img
-*.dtb
diff --git a/core/example_tb/bootrom/Makefile b/core/example_tb/bootrom/Makefile
deleted file mode 100644
index 86708317c8..0000000000
--- a/core/example_tb/bootrom/Makefile
+++ /dev/null
@@ -1,53 +0,0 @@
-###############################################################################
-#    $@ is the file being generated.
-#    $< is first prerequiste.
-#    $^ is all prerequistes.
-#    $* is file_name (w/o extension) of target
-
-DTB ?= cva6.dtb
-LCS ?= linker.ld
-
-# Tools yer gonna need
-RISCV_EXE_PREFIX ?= riscv64-unknown-elf
-RISCV_GCC        ?= $(RISCV_EXE_PREFIX)-gcc
-RISCV_OBJCOPY    ?= $(RISCV_EXE_PREFIX)-objcopy
-RISCV_READELF    ?= $(RISCV_EXE_PREFIX)-readelf
-RISCV_OBJDUMP    ?= $(RISCV_EXE_PREFIX)-objdump
-PYTHON           ?= python3
-DTC              ?= dtc
-DD               ?= dd
-
-.PRECIOUS : %.elf
-
-%.dtb: %.dts
-	$(DTC) -I dts $< -O dtb -o $@
-
-%.elf: %.S $(LCS) $(DTB)
-	$(RISCV_GCC) -T$(LCS) -march=rv32i -mabi=ilp32 $< -nostdlib -static -Wl,--no-gc-sections -o $@
-
-%.hex: %.elf
-	$(RISCV_OBJCOPY) -O verilog $< $@
-
-%.readelf: %.elf
-	$(RISCV_READELF) -a $< > $@
-
-%.objdump: %.elf
-	$(RISCV_OBJDUMP) -D -S $< > $@
-
-clean:
-	rm -f $(bootrom_img) $(DTB) *.elf *.hex *.readelf *.objdump
-
-###############################################################################
-# Deprecated variables and targets
-
-#bootrom_img    = bootrom.img bootrom.sv
-
-#%.sv: %.img
-#	$(PYTHON) ./gen_rom.py $<
-
-#%.img: %.bin
-#	$(DD) if=$< of=$@ bs=128
-
-#%.bin: %.elf
-#	$(RISCV_OBJCOPY) -O binary $< $@
-
diff --git a/core/example_tb/bootrom/bootrom.S b/core/example_tb/bootrom/bootrom.S
deleted file mode 100644
index e8089b552e..0000000000
--- a/core/example_tb/bootrom/bootrom.S
+++ /dev/null
@@ -1,27 +0,0 @@
-.section .text.start, "ax", @progbits
-.globl _start
-_start:
-# bootrom.sv need to be functional in 64 and 32 bits,
-# li s0, DRAM_BASE creates instructions not compatible with both
-# versions. That's why we have replaced it by li and slli instructions
-# to generates code compatible with both versions.
-  li s0, 1
-  slli s0, s0, 31
-  csrr a0, mhartid
-  la a1, _dtb
-  jr s0
-
-.section .text.hang, "ax", @progbits
-.globl _hang
-_hang:
-  csrr a0, mhartid
-  la a1, _dtb
-1:
-  wfi
-  j 1b
-
-.section .rodata.dtb, "a", @progbits
-.globl _dtb
-.align 5, 0
-_dtb:
-.incbin "cva6.dtb"
diff --git a/core/example_tb/bootrom/bootrom.h b/core/example_tb/bootrom/bootrom.h
deleted file mode 100644
index e1419e65b1..0000000000
--- a/core/example_tb/bootrom/bootrom.h
+++ /dev/null
@@ -1,408 +0,0 @@
-// Auto-generated code
-
-const int reset_vec_size = 402;
-
-uint32_t reset_vec[reset_vec_size] = {
-    0x00100413,
-    0x01f41413,
-    0xf1402573,
-    0x00000597,
-    0x07458593,
-    0x00040067,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0xf1402573,
-    0x00000597,
-    0x03c58593,
-    0x10500073,
-    0xffdff06f,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0xedfe0dd0,
-    0xc2050000,
-    0x38000000,
-    0xbc040000,
-    0x28000000,
-    0x11000000,
-    0x10000000,
-    0x00000000,
-    0x06010000,
-    0x84040000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x01000000,
-    0x00000000,
-    0x03000000,
-    0x04000000,
-    0x00000000,
-    0x02000000,
-    0x03000000,
-    0x04000000,
-    0x0f000000,
-    0x02000000,
-    0x03000000,
-    0x14000000,
-    0x1b000000,
-    0x2c687465,
-    0x61697261,
-    0x622d656e,
-    0x2d657261,
-    0x00766564,
-    0x03000000,
-    0x10000000,
-    0x26000000,
-    0x2c687465,
-    0x61697261,
-    0x622d656e,
-    0x00657261,
-    0x01000000,
-    0x73757063,
-    0x00000000,
-    0x03000000,
-    0x04000000,
-    0x00000000,
-    0x01000000,
-    0x03000000,
-    0x04000000,
-    0x0f000000,
-    0x00000000,
-    0x03000000,
-    0x04000000,
-    0x2c000000,
-    0x00800000,
-    0x01000000,
-    0x40757063,
-    0x00000030,
-    0x03000000,
-    0x04000000,
-    0x3f000000,
-    0x80f0fa02,
-    0x03000000,
-    0x04000000,
-    0x4f000000,
-    0x00757063,
-    0x03000000,
-    0x04000000,
-    0x5b000000,
-    0x00000000,
-    0x03000000,
-    0x05000000,
-    0x5f000000,
-    0x79616b6f,
-    0x00000000,
-    0x03000000,
-    0x12000000,
-    0x1b000000,
-    0x2c687465,
-    0x69726120,
-    0x00656e61,
-    0x63736972,
-    0x00000076,
-    0x03000000,
-    0x0b000000,
-    0x66000000,
-    0x34367672,
-    0x66616d69,
-    0x00006364,
-    0x03000000,
-    0x0b000000,
-    0x70000000,
-    0x63736972,
-    0x76732c76,
-    0x00003933,
-    0x03000000,
-    0x00000000,
-    0x79000000,
-    0x01000000,
-    0x65746e69,
-    0x70757272,
-    0x6f632d74,
-    0x6f72746e,
-    0x72656c6c,
-    0x00000000,
-    0x03000000,
-    0x04000000,
-    0x83000000,
-    0x01000000,
-    0x03000000,
-    0x00000000,
-    0x94000000,
-    0x03000000,
-    0x0f000000,
-    0x1b000000,
-    0x63736972,
-    0x70632c76,
-    0x6e692d75,
-    0x00006374,
-    0x03000000,
-    0x04000000,
-    0xa9000000,
-    0x01000000,
-    0x02000000,
-    0x02000000,
-    0x02000000,
-    0x01000000,
-    0x6f6d656d,
-    0x38407972,
-    0x30303030,
-    0x00303030,
-    0x03000000,
-    0x07000000,
-    0x4f000000,
-    0x6f6d656d,
-    0x00007972,
-    0x03000000,
-    0x10000000,
-    0x5b000000,
-    0x00000000,
-    0x00000080,
-    0x00000000,
-    0x00000010,
-    0x02000000,
-    0x01000000,
-    0x00636f73,
-    0x03000000,
-    0x04000000,
-    0x00000000,
-    0x02000000,
-    0x03000000,
-    0x04000000,
-    0x0f000000,
-    0x02000000,
-    0x03000000,
-    0x1f000000,
-    0x1b000000,
-    0x2c687465,
-    0x61697261,
-    0x622d656e,
-    0x2d657261,
-    0x00636f73,
-    0x706d6973,
-    0x622d656c,
-    0x00007375,
-    0x03000000,
-    0x00000000,
-    0xb1000000,
-    0x01000000,
-    0x6e696c63,
-    0x30324074,
-    0x30303030,
-    0x00000030,
-    0x03000000,
-    0x0d000000,
-    0x1b000000,
-    0x63736972,
-    0x6c632c76,
-    0x30746e69,
-    0x00000000,
-    0x03000000,
-    0x10000000,
-    0xb8000000,
-    0x01000000,
-    0x03000000,
-    0x01000000,
-    0x07000000,
-    0x03000000,
-    0x10000000,
-    0x5b000000,
-    0x00000000,
-    0x00000002,
-    0x00000000,
-    0x00000c00,
-    0x03000000,
-    0x08000000,
-    0xcc000000,
-    0x746e6f63,
-    0x006c6f72,
-    0x02000000,
-    0x01000000,
-    0x75626564,
-    0x6f632d67,
-    0x6f72746e,
-    0x72656c6c,
-    0x00003040,
-    0x03000000,
-    0x10000000,
-    0x1b000000,
-    0x63736972,
-    0x65642c76,
-    0x2d677562,
-    0x00333130,
-    0x03000000,
-    0x08000000,
-    0xb8000000,
-    0x01000000,
-    0xffff0000,
-    0x03000000,
-    0x10000000,
-    0x5b000000,
-    0x00000000,
-    0x00000000,
-    0x00000000,
-    0x00100000,
-    0x03000000,
-    0x08000000,
-    0xcc000000,
-    0x746e6f63,
-    0x006c6f72,
-    0x02000000,
-    0x01000000,
-    0x74726175,
-    0x30303140,
-    0x30303030,
-    0x00000030,
-    0x03000000,
-    0x08000000,
-    0x1b000000,
-    0x3631736e,
-    0x00303537,
-    0x03000000,
-    0x10000000,
-    0x5b000000,
-    0x00000000,
-    0x00000010,
-    0x00000000,
-    0x00100000,
-    0x03000000,
-    0x04000000,
-    0x3f000000,
-    0x80f0fa02,
-    0x03000000,
-    0x04000000,
-    0xd6000000,
-    0x00c20100,
-    0x03000000,
-    0x04000000,
-    0xe4000000,
-    0x01000000,
-    0x03000000,
-    0x04000000,
-    0xef000000,
-    0x02000000,
-    0x03000000,
-    0x04000000,
-    0xf9000000,
-    0x04000000,
-    0x02000000,
-    0x01000000,
-    0x656d6974,
-    0x38314072,
-    0x30303030,
-    0x00003030,
-    0x03000000,
-    0x0f000000,
-    0x1b000000,
-    0x706c7570,
-    0x6270612c,
-    0x6d69745f,
-    0x00007265,
-    0x03000000,
-    0x10000000,
-    0xe4000000,
-    0x04000000,
-    0x05000000,
-    0x06000000,
-    0x07000000,
-    0x03000000,
-    0x10000000,
-    0x5b000000,
-    0x00000000,
-    0x00000018,
-    0x00000000,
-    0x00100000,
-    0x03000000,
-    0x08000000,
-    0xcc000000,
-    0x746e6f63,
-    0x006c6f72,
-    0x02000000,
-    0x02000000,
-    0x02000000,
-    0x09000000,
-    0x64646123,
-    0x73736572,
-    0x6c65632d,
-    0x2300736c,
-    0x657a6973,
-    0x6c65632d,
-    0x6300736c,
-    0x61706d6f,
-    0x6c626974,
-    0x6f6d0065,
-    0x006c6564,
-    0x656d6974,
-    0x65736162,
-    0x6572662d,
-    0x6e657571,
-    0x63007963,
-    0x6b636f6c,
-    0x6572662d,
-    0x6e657571,
-    0x64007963,
-    0x63697665,
-    0x79745f65,
-    0x72006570,
-    0x73006765,
-    0x75746174,
-    0x69720073,
-    0x2c766373,
-    0x00617369,
-    0x2d756d6d,
-    0x65707974,
-    0x626c7400,
-    0x6c70732d,
-    0x23007469,
-    0x65746e69,
-    0x70757272,
-    0x65632d74,
-    0x00736c6c,
-    0x65746e69,
-    0x70757272,
-    0x6f632d74,
-    0x6f72746e,
-    0x72656c6c,
-    0x61687000,
-    0x656c646e,
-    0x6e617200,
-    0x00736567,
-    0x65746e69,
-    0x70757272,
-    0x652d7374,
-    0x6e657478,
-    0x00646564,
-    0x2d676572,
-    0x656d616e,
-    0x75630073,
-    0x6e657272,
-    0x70732d74,
-    0x00646565,
-    0x65746e69,
-    0x70757272,
-    0x72007374,
-    0x732d6765,
-    0x74666968,
-    0x67657200,
-    0x2d6f692d,
-    0x74646977,
-    0x00000068,
-    0x00000000
-};
diff --git a/core/example_tb/bootrom/cva6.dts b/core/example_tb/bootrom/cva6.dts
deleted file mode 100644
index e54da14e61..0000000000
--- a/core/example_tb/bootrom/cva6.dts
+++ /dev/null
@@ -1,68 +0,0 @@
-/dts-v1/;
-
-/ {
-  #address-cells = <2>;
-  #size-cells = <2>;
-  compatible = "eth,cva6-bare-dev";
-  model = "eth,cva6-bare";
-  cpus {
-    #address-cells = <1>;
-    #size-cells = <0>;
-    timebase-frequency = <32768>; // 32.768 kHz
-    CPU0: cpu@0 {
-      clock-frequency = <50000000>; // 50 MHz
-      device_type = "cpu";
-      reg = <0>;
-      status = "okay";
-      compatible = "eth, cva6", "riscv";
-      riscv,isa = "rv64imafdc";
-      mmu-type = "riscv,sv39";
-      tlb-split;
-      // HLIC - hart local interrupt controller
-      CPU0_intc: interrupt-controller {
-        #interrupt-cells = <1>;
-        interrupt-controller;
-        compatible = "riscv,cpu-intc";
-      };
-    };
-  };
-  memory@80000000 {
-    device_type = "memory";
-    reg = <0x0 0x80000000 0x0 0x10000000>;
-  };
-  soc {
-    #address-cells = <2>;
-    #size-cells = <2>;
-    compatible = "eth,cva6-bare-soc", "simple-bus";
-    ranges;
-    clint@2000000 {
-      compatible = "riscv,clint0";
-      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
-      reg = <0x0 0x2000000 0x0 0xc0000>;
-      reg-names = "control";
-    };
-    debug-controller@0 {
-      compatible = "riscv,debug-013";
-      interrupts-extended = <&CPU0_intc 65535>;
-      reg = <0x0 0x0 0x0 0x1000>;
-      reg-names = "control";
-    };
-    uart@10000000 {
-      compatible = "ns16750";
-      reg = <0x0 0x10000000 0x0 0x1000>;
-      clock-frequency = <50000000>;
-      current-speed = <115200>;
-      // interrupt-parent = <&PLIC0>;
-      interrupts = <1>;
-      reg-shift = <2>; // regs are spaced on 32 bit boundary
-      reg-io-width = <4>; // only 32-bit access are supported
-    };
-    timer@18000000 {
-      compatible = "pulp,apb_timer";
-      interrupts = <0x00000004 0x00000005 0x00000006 0x00000007>;
-      reg = <0x00000000 0x18000000 0x00000000 0x00001000>;
-      // interrupt-parent = <&PLIC0>;
-      reg-names = "control";
-    };
-  };
-};
diff --git a/core/example_tb/bootrom/encoding.h b/core/example_tb/bootrom/encoding.h
deleted file mode 100644
index f5a40afdad..0000000000
--- a/core/example_tb/bootrom/encoding.h
+++ /dev/null
@@ -1,1475 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef RISCV_CSR_ENCODING_H
-#define RISCV_CSR_ENCODING_H
-
-#define MSTATUS_UIE         0x00000001
-#define MSTATUS_SIE         0x00000002
-#define MSTATUS_HIE         0x00000004
-#define MSTATUS_MIE         0x00000008
-#define MSTATUS_UPIE        0x00000010
-#define MSTATUS_SPIE        0x00000020
-#define MSTATUS_HPIE        0x00000040
-#define MSTATUS_MPIE        0x00000080
-#define MSTATUS_SPP         0x00000100
-#define MSTATUS_HPP         0x00000600
-#define MSTATUS_MPP         0x00001800
-#define MSTATUS_FS          0x00006000
-#define MSTATUS_XS          0x00018000
-#define MSTATUS_MPRV        0x00020000
-#define MSTATUS_SUM         0x00040000
-#define MSTATUS_MXR         0x00080000
-#define MSTATUS_TVM         0x00100000
-#define MSTATUS_TW          0x00200000
-#define MSTATUS_TSR         0x00400000
-#define MSTATUS32_SD        0x80000000
-#define MSTATUS_UXL         0x0000000300000000
-#define MSTATUS_SXL         0x0000000C00000000
-#define MSTATUS64_SD        0x8000000000000000
-
-#define SSTATUS_UIE         0x00000001
-#define SSTATUS_SIE         0x00000002
-#define SSTATUS_UPIE        0x00000010
-#define SSTATUS_SPIE        0x00000020
-#define SSTATUS_SPP         0x00000100
-#define SSTATUS_FS          0x00006000
-#define SSTATUS_XS          0x00018000
-#define SSTATUS_SUM         0x00040000
-#define SSTATUS_MXR         0x00080000
-#define SSTATUS32_SD        0x80000000
-#define SSTATUS_UXL         0x0000000300000000
-#define SSTATUS64_SD        0x8000000000000000
-
-#define DCSR_XDEBUGVER      (3U<<30)
-#define DCSR_NDRESET        (1<<29)
-#define DCSR_FULLRESET      (1<<28)
-#define DCSR_EBREAKM        (1<<15)
-#define DCSR_EBREAKH        (1<<14)
-#define DCSR_EBREAKS        (1<<13)
-#define DCSR_EBREAKU        (1<<12)
-#define DCSR_STOPCYCLE      (1<<10)
-#define DCSR_STOPTIME       (1<<9)
-#define DCSR_CAUSE          (7<<6)
-#define DCSR_DEBUGINT       (1<<5)
-#define DCSR_HALT           (1<<3)
-#define DCSR_STEP           (1<<2)
-#define DCSR_PRV            (3<<0)
-
-#define DCSR_CAUSE_NONE     0
-#define DCSR_CAUSE_SWBP     1
-#define DCSR_CAUSE_HWBP     2
-#define DCSR_CAUSE_DEBUGINT 3
-#define DCSR_CAUSE_STEP     4
-#define DCSR_CAUSE_HALT     5
-
-#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
-#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
-#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
-
-#define MCONTROL_SELECT     (1<<19)
-#define MCONTROL_TIMING     (1<<18)
-#define MCONTROL_ACTION     (0x3f<<12)
-#define MCONTROL_CHAIN      (1<<11)
-#define MCONTROL_MATCH      (0xf<<7)
-#define MCONTROL_M          (1<<6)
-#define MCONTROL_H          (1<<5)
-#define MCONTROL_S          (1<<4)
-#define MCONTROL_U          (1<<3)
-#define MCONTROL_EXECUTE    (1<<2)
-#define MCONTROL_STORE      (1<<1)
-#define MCONTROL_LOAD       (1<<0)
-
-#define MCONTROL_TYPE_NONE      0
-#define MCONTROL_TYPE_MATCH     2
-
-#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
-#define MCONTROL_ACTION_DEBUG_MODE        1
-#define MCONTROL_ACTION_TRACE_START       2
-#define MCONTROL_ACTION_TRACE_STOP        3
-#define MCONTROL_ACTION_TRACE_EMIT        4
-
-#define MCONTROL_MATCH_EQUAL     0
-#define MCONTROL_MATCH_NAPOT     1
-#define MCONTROL_MATCH_GE        2
-#define MCONTROL_MATCH_LT        3
-#define MCONTROL_MATCH_MASK_LOW  4
-#define MCONTROL_MATCH_MASK_HIGH 5
-
-#define MIP_SSIP            (1 << IRQ_S_SOFT)
-#define MIP_HSIP            (1 << IRQ_H_SOFT)
-#define MIP_MSIP            (1 << IRQ_M_SOFT)
-#define MIP_STIP            (1 << IRQ_S_TIMER)
-#define MIP_HTIP            (1 << IRQ_H_TIMER)
-#define MIP_MTIP            (1 << IRQ_M_TIMER)
-#define MIP_SEIP            (1 << IRQ_S_EXT)
-#define MIP_HEIP            (1 << IRQ_H_EXT)
-#define MIP_MEIP            (1 << IRQ_M_EXT)
-
-#define SIP_SSIP MIP_SSIP
-#define SIP_STIP MIP_STIP
-
-#define PRV_U 0
-#define PRV_S 1
-#define PRV_H 2
-#define PRV_M 3
-
-#define SATP32_MODE 0x80000000
-#define SATP32_ASID 0x7FC00000
-#define SATP32_PPN  0x003FFFFF
-#define SATP64_MODE 0xF000000000000000
-#define SATP64_ASID 0x0FFFF00000000000
-#define SATP64_PPN  0x00000FFFFFFFFFFF
-
-#define SATP_MODE_OFF  0
-#define SATP_MODE_SV32 1
-#define SATP_MODE_SV39 8
-#define SATP_MODE_SV48 9
-#define SATP_MODE_SV57 10
-#define SATP_MODE_SV64 11
-
-#define PMP_R     0x01
-#define PMP_W     0x02
-#define PMP_X     0x04
-#define PMP_A     0x18
-#define PMP_L     0x80
-#define PMP_SHIFT 2
-
-#define PMP_TOR   0x08
-#define PMP_NA4   0x10
-#define PMP_NAPOT 0x18
-
-#define IRQ_S_SOFT   1
-#define IRQ_H_SOFT   2
-#define IRQ_M_SOFT   3
-#define IRQ_S_TIMER  5
-#define IRQ_H_TIMER  6
-#define IRQ_M_TIMER  7
-#define IRQ_S_EXT    9
-#define IRQ_H_EXT    10
-#define IRQ_M_EXT    11
-#define IRQ_COP      12
-#define IRQ_HOST     13
-
-#define DEFAULT_RSTVEC     0x00001000
-#define CLINT_BASE         0x02000000
-#define CLINT_SIZE         0x000c0000
-#define EXT_IO_BASE        0x40000000
-#define DRAM_BASE          0x80000000
-
-// page table entry (PTE) fields
-#define PTE_V     0x001 // Valid
-#define PTE_R     0x002 // Read
-#define PTE_W     0x004 // Write
-#define PTE_X     0x008 // Execute
-#define PTE_U     0x010 // User
-#define PTE_G     0x020 // Global
-#define PTE_A     0x040 // Accessed
-#define PTE_D     0x080 // Dirty
-#define PTE_SOFT  0x300 // Reserved for Software
-
-#define PTE_PPN_SHIFT 10
-
-#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
-
-#ifdef __riscv
-
-#if __riscv_xlen == 64
-# define MSTATUS_SD MSTATUS64_SD
-# define SSTATUS_SD SSTATUS64_SD
-# define RISCV_PGLEVEL_BITS 9
-# define SATP_MODE SATP64_MODE
-#else
-# define MSTATUS_SD MSTATUS32_SD
-# define SSTATUS_SD SSTATUS32_SD
-# define RISCV_PGLEVEL_BITS 10
-# define SATP_MODE SATP32_MODE
-#endif
-#define RISCV_PGSHIFT 12
-#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
-
-#ifndef __ASSEMBLER__
-
-#ifdef __GNUC__
-
-#define read_csr(reg) ({ unsigned long __tmp; \
-  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
-  __tmp; })
-
-#define write_csr(reg, val) ({ \
-  asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
-
-#define swap_csr(reg, val) ({ unsigned long __tmp; \
-  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
-  __tmp; })
-
-#define set_csr(reg, bit) ({ unsigned long __tmp; \
-  asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
-  __tmp; })
-
-#define clear_csr(reg, bit) ({ unsigned long __tmp; \
-  asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
-  __tmp; })
-
-#define rdtime() read_csr(time)
-#define rdcycle() read_csr(cycle)
-#define rdinstret() read_csr(instret)
-
-#endif
-
-#endif
-
-#endif
-
-#endif
-/* Automatically generated by parse-opcodes.  */
-#ifndef RISCV_ENCODING_H
-#define RISCV_ENCODING_H
-#define MATCH_BEQ 0x63
-#define MASK_BEQ  0x707f
-#define MATCH_BNE 0x1063
-#define MASK_BNE  0x707f
-#define MATCH_BLT 0x4063
-#define MASK_BLT  0x707f
-#define MATCH_BGE 0x5063
-#define MASK_BGE  0x707f
-#define MATCH_BLTU 0x6063
-#define MASK_BLTU  0x707f
-#define MATCH_BGEU 0x7063
-#define MASK_BGEU  0x707f
-#define MATCH_JALR 0x67
-#define MASK_JALR  0x707f
-#define MATCH_JAL 0x6f
-#define MASK_JAL  0x7f
-#define MATCH_LUI 0x37
-#define MASK_LUI  0x7f
-#define MATCH_AUIPC 0x17
-#define MASK_AUIPC  0x7f
-#define MATCH_ADDI 0x13
-#define MASK_ADDI  0x707f
-#define MATCH_SLLI 0x1013
-#define MASK_SLLI  0xfc00707f
-#define MATCH_SLTI 0x2013
-#define MASK_SLTI  0x707f
-#define MATCH_SLTIU 0x3013
-#define MASK_SLTIU  0x707f
-#define MATCH_XORI 0x4013
-#define MASK_XORI  0x707f
-#define MATCH_SRLI 0x5013
-#define MASK_SRLI  0xfc00707f
-#define MATCH_SRAI 0x40005013
-#define MASK_SRAI  0xfc00707f
-#define MATCH_ORI 0x6013
-#define MASK_ORI  0x707f
-#define MATCH_ANDI 0x7013
-#define MASK_ANDI  0x707f
-#define MATCH_ADD 0x33
-#define MASK_ADD  0xfe00707f
-#define MATCH_SUB 0x40000033
-#define MASK_SUB  0xfe00707f
-#define MATCH_SLL 0x1033
-#define MASK_SLL  0xfe00707f
-#define MATCH_SLT 0x2033
-#define MASK_SLT  0xfe00707f
-#define MATCH_SLTU 0x3033
-#define MASK_SLTU  0xfe00707f
-#define MATCH_XOR 0x4033
-#define MASK_XOR  0xfe00707f
-#define MATCH_SRL 0x5033
-#define MASK_SRL  0xfe00707f
-#define MATCH_SRA 0x40005033
-#define MASK_SRA  0xfe00707f
-#define MATCH_OR 0x6033
-#define MASK_OR  0xfe00707f
-#define MATCH_AND 0x7033
-#define MASK_AND  0xfe00707f
-#define MATCH_ADDIW 0x1b
-#define MASK_ADDIW  0x707f
-#define MATCH_SLLIW 0x101b
-#define MASK_SLLIW  0xfe00707f
-#define MATCH_SRLIW 0x501b
-#define MASK_SRLIW  0xfe00707f
-#define MATCH_SRAIW 0x4000501b
-#define MASK_SRAIW  0xfe00707f
-#define MATCH_ADDW 0x3b
-#define MASK_ADDW  0xfe00707f
-#define MATCH_SUBW 0x4000003b
-#define MASK_SUBW  0xfe00707f
-#define MATCH_SLLW 0x103b
-#define MASK_SLLW  0xfe00707f
-#define MATCH_SRLW 0x503b
-#define MASK_SRLW  0xfe00707f
-#define MATCH_SRAW 0x4000503b
-#define MASK_SRAW  0xfe00707f
-#define MATCH_LB 0x3
-#define MASK_LB  0x707f
-#define MATCH_LH 0x1003
-#define MASK_LH  0x707f
-#define MATCH_LW 0x2003
-#define MASK_LW  0x707f
-#define MATCH_LD 0x3003
-#define MASK_LD  0x707f
-#define MATCH_LBU 0x4003
-#define MASK_LBU  0x707f
-#define MATCH_LHU 0x5003
-#define MASK_LHU  0x707f
-#define MATCH_LWU 0x6003
-#define MASK_LWU  0x707f
-#define MATCH_SB 0x23
-#define MASK_SB  0x707f
-#define MATCH_SH 0x1023
-#define MASK_SH  0x707f
-#define MATCH_SW 0x2023
-#define MASK_SW  0x707f
-#define MATCH_SD 0x3023
-#define MASK_SD  0x707f
-#define MATCH_FENCE 0xf
-#define MASK_FENCE  0x707f
-#define MATCH_FENCE_I 0x100f
-#define MASK_FENCE_I  0x707f
-#define MATCH_MUL 0x2000033
-#define MASK_MUL  0xfe00707f
-#define MATCH_MULH 0x2001033
-#define MASK_MULH  0xfe00707f
-#define MATCH_MULHSU 0x2002033
-#define MASK_MULHSU  0xfe00707f
-#define MATCH_MULHU 0x2003033
-#define MASK_MULHU  0xfe00707f
-#define MATCH_DIV 0x2004033
-#define MASK_DIV  0xfe00707f
-#define MATCH_DIVU 0x2005033
-#define MASK_DIVU  0xfe00707f
-#define MATCH_REM 0x2006033
-#define MASK_REM  0xfe00707f
-#define MATCH_REMU 0x2007033
-#define MASK_REMU  0xfe00707f
-#define MATCH_MULW 0x200003b
-#define MASK_MULW  0xfe00707f
-#define MATCH_DIVW 0x200403b
-#define MASK_DIVW  0xfe00707f
-#define MATCH_DIVUW 0x200503b
-#define MASK_DIVUW  0xfe00707f
-#define MATCH_REMW 0x200603b
-#define MASK_REMW  0xfe00707f
-#define MATCH_REMUW 0x200703b
-#define MASK_REMUW  0xfe00707f
-#define MATCH_AMOADD_W 0x202f
-#define MASK_AMOADD_W  0xf800707f
-#define MATCH_AMOXOR_W 0x2000202f
-#define MASK_AMOXOR_W  0xf800707f
-#define MATCH_AMOOR_W 0x4000202f
-#define MASK_AMOOR_W  0xf800707f
-#define MATCH_AMOAND_W 0x6000202f
-#define MASK_AMOAND_W  0xf800707f
-#define MATCH_AMOMIN_W 0x8000202f
-#define MASK_AMOMIN_W  0xf800707f
-#define MATCH_AMOMAX_W 0xa000202f
-#define MASK_AMOMAX_W  0xf800707f
-#define MATCH_AMOMINU_W 0xc000202f
-#define MASK_AMOMINU_W  0xf800707f
-#define MATCH_AMOMAXU_W 0xe000202f
-#define MASK_AMOMAXU_W  0xf800707f
-#define MATCH_AMOSWAP_W 0x800202f
-#define MASK_AMOSWAP_W  0xf800707f
-#define MATCH_LR_W 0x1000202f
-#define MASK_LR_W  0xf9f0707f
-#define MATCH_SC_W 0x1800202f
-#define MASK_SC_W  0xf800707f
-#define MATCH_AMOADD_D 0x302f
-#define MASK_AMOADD_D  0xf800707f
-#define MATCH_AMOXOR_D 0x2000302f
-#define MASK_AMOXOR_D  0xf800707f
-#define MATCH_AMOOR_D 0x4000302f
-#define MASK_AMOOR_D  0xf800707f
-#define MATCH_AMOAND_D 0x6000302f
-#define MASK_AMOAND_D  0xf800707f
-#define MATCH_AMOMIN_D 0x8000302f
-#define MASK_AMOMIN_D  0xf800707f
-#define MATCH_AMOMAX_D 0xa000302f
-#define MASK_AMOMAX_D  0xf800707f
-#define MATCH_AMOMINU_D 0xc000302f
-#define MASK_AMOMINU_D  0xf800707f
-#define MATCH_AMOMAXU_D 0xe000302f
-#define MASK_AMOMAXU_D  0xf800707f
-#define MATCH_AMOSWAP_D 0x800302f
-#define MASK_AMOSWAP_D  0xf800707f
-#define MATCH_LR_D 0x1000302f
-#define MASK_LR_D  0xf9f0707f
-#define MATCH_SC_D 0x1800302f
-#define MASK_SC_D  0xf800707f
-#define MATCH_ECALL 0x73
-#define MASK_ECALL  0xffffffff
-#define MATCH_EBREAK 0x100073
-#define MASK_EBREAK  0xffffffff
-#define MATCH_URET 0x200073
-#define MASK_URET  0xffffffff
-#define MATCH_SRET 0x10200073
-#define MASK_SRET  0xffffffff
-#define MATCH_MRET 0x30200073
-#define MASK_MRET  0xffffffff
-#define MATCH_DRET 0x7b200073
-#define MASK_DRET  0xffffffff
-#define MATCH_SFENCE_VMA 0x12000073
-#define MASK_SFENCE_VMA  0xfe007fff
-#define MATCH_WFI 0x10500073
-#define MASK_WFI  0xffffffff
-#define MATCH_CSRRW 0x1073
-#define MASK_CSRRW  0x707f
-#define MATCH_CSRRS 0x2073
-#define MASK_CSRRS  0x707f
-#define MATCH_CSRRC 0x3073
-#define MASK_CSRRC  0x707f
-#define MATCH_CSRRWI 0x5073
-#define MASK_CSRRWI  0x707f
-#define MATCH_CSRRSI 0x6073
-#define MASK_CSRRSI  0x707f
-#define MATCH_CSRRCI 0x7073
-#define MASK_CSRRCI  0x707f
-#define MATCH_FADD_S 0x53
-#define MASK_FADD_S  0xfe00007f
-#define MATCH_FSUB_S 0x8000053
-#define MASK_FSUB_S  0xfe00007f
-#define MATCH_FMUL_S 0x10000053
-#define MASK_FMUL_S  0xfe00007f
-#define MATCH_FDIV_S 0x18000053
-#define MASK_FDIV_S  0xfe00007f
-#define MATCH_FSGNJ_S 0x20000053
-#define MASK_FSGNJ_S  0xfe00707f
-#define MATCH_FSGNJN_S 0x20001053
-#define MASK_FSGNJN_S  0xfe00707f
-#define MATCH_FSGNJX_S 0x20002053
-#define MASK_FSGNJX_S  0xfe00707f
-#define MATCH_FMIN_S 0x28000053
-#define MASK_FMIN_S  0xfe00707f
-#define MATCH_FMAX_S 0x28001053
-#define MASK_FMAX_S  0xfe00707f
-#define MATCH_FSQRT_S 0x58000053
-#define MASK_FSQRT_S  0xfff0007f
-#define MATCH_FADD_D 0x2000053
-#define MASK_FADD_D  0xfe00007f
-#define MATCH_FSUB_D 0xa000053
-#define MASK_FSUB_D  0xfe00007f
-#define MATCH_FMUL_D 0x12000053
-#define MASK_FMUL_D  0xfe00007f
-#define MATCH_FDIV_D 0x1a000053
-#define MASK_FDIV_D  0xfe00007f
-#define MATCH_FSGNJ_D 0x22000053
-#define MASK_FSGNJ_D  0xfe00707f
-#define MATCH_FSGNJN_D 0x22001053
-#define MASK_FSGNJN_D  0xfe00707f
-#define MATCH_FSGNJX_D 0x22002053
-#define MASK_FSGNJX_D  0xfe00707f
-#define MATCH_FMIN_D 0x2a000053
-#define MASK_FMIN_D  0xfe00707f
-#define MATCH_FMAX_D 0x2a001053
-#define MASK_FMAX_D  0xfe00707f
-#define MATCH_FCVT_S_D 0x40100053
-#define MASK_FCVT_S_D  0xfff0007f
-#define MATCH_FCVT_D_S 0x42000053
-#define MASK_FCVT_D_S  0xfff0007f
-#define MATCH_FSQRT_D 0x5a000053
-#define MASK_FSQRT_D  0xfff0007f
-#define MATCH_FADD_Q 0x6000053
-#define MASK_FADD_Q  0xfe00007f
-#define MATCH_FSUB_Q 0xe000053
-#define MASK_FSUB_Q  0xfe00007f
-#define MATCH_FMUL_Q 0x16000053
-#define MASK_FMUL_Q  0xfe00007f
-#define MATCH_FDIV_Q 0x1e000053
-#define MASK_FDIV_Q  0xfe00007f
-#define MATCH_FSGNJ_Q 0x26000053
-#define MASK_FSGNJ_Q  0xfe00707f
-#define MATCH_FSGNJN_Q 0x26001053
-#define MASK_FSGNJN_Q  0xfe00707f
-#define MATCH_FSGNJX_Q 0x26002053
-#define MASK_FSGNJX_Q  0xfe00707f
-#define MATCH_FMIN_Q 0x2e000053
-#define MASK_FMIN_Q  0xfe00707f
-#define MATCH_FMAX_Q 0x2e001053
-#define MASK_FMAX_Q  0xfe00707f
-#define MATCH_FCVT_S_Q 0x40300053
-#define MASK_FCVT_S_Q  0xfff0007f
-#define MATCH_FCVT_Q_S 0x46000053
-#define MASK_FCVT_Q_S  0xfff0007f
-#define MATCH_FCVT_D_Q 0x42300053
-#define MASK_FCVT_D_Q  0xfff0007f
-#define MATCH_FCVT_Q_D 0x46100053
-#define MASK_FCVT_Q_D  0xfff0007f
-#define MATCH_FSQRT_Q 0x5e000053
-#define MASK_FSQRT_Q  0xfff0007f
-#define MATCH_FLE_S 0xa0000053
-#define MASK_FLE_S  0xfe00707f
-#define MATCH_FLT_S 0xa0001053
-#define MASK_FLT_S  0xfe00707f
-#define MATCH_FEQ_S 0xa0002053
-#define MASK_FEQ_S  0xfe00707f
-#define MATCH_FLE_D 0xa2000053
-#define MASK_FLE_D  0xfe00707f
-#define MATCH_FLT_D 0xa2001053
-#define MASK_FLT_D  0xfe00707f
-#define MATCH_FEQ_D 0xa2002053
-#define MASK_FEQ_D  0xfe00707f
-#define MATCH_FLE_Q 0xa6000053
-#define MASK_FLE_Q  0xfe00707f
-#define MATCH_FLT_Q 0xa6001053
-#define MASK_FLT_Q  0xfe00707f
-#define MATCH_FEQ_Q 0xa6002053
-#define MASK_FEQ_Q  0xfe00707f
-#define MATCH_FCVT_W_S 0xc0000053
-#define MASK_FCVT_W_S  0xfff0007f
-#define MATCH_FCVT_WU_S 0xc0100053
-#define MASK_FCVT_WU_S  0xfff0007f
-#define MATCH_FCVT_L_S 0xc0200053
-#define MASK_FCVT_L_S  0xfff0007f
-#define MATCH_FCVT_LU_S 0xc0300053
-#define MASK_FCVT_LU_S  0xfff0007f
-#define MATCH_FMV_X_W 0xe0000053
-#define MASK_FMV_X_W  0xfff0707f
-#define MATCH_FCLASS_S 0xe0001053
-#define MASK_FCLASS_S  0xfff0707f
-#define MATCH_FCVT_W_D 0xc2000053
-#define MASK_FCVT_W_D  0xfff0007f
-#define MATCH_FCVT_WU_D 0xc2100053
-#define MASK_FCVT_WU_D  0xfff0007f
-#define MATCH_FCVT_L_D 0xc2200053
-#define MASK_FCVT_L_D  0xfff0007f
-#define MATCH_FCVT_LU_D 0xc2300053
-#define MASK_FCVT_LU_D  0xfff0007f
-#define MATCH_FMV_X_D 0xe2000053
-#define MASK_FMV_X_D  0xfff0707f
-#define MATCH_FCLASS_D 0xe2001053
-#define MASK_FCLASS_D  0xfff0707f
-#define MATCH_FCVT_W_Q 0xc6000053
-#define MASK_FCVT_W_Q  0xfff0007f
-#define MATCH_FCVT_WU_Q 0xc6100053
-#define MASK_FCVT_WU_Q  0xfff0007f
-#define MATCH_FCVT_L_Q 0xc6200053
-#define MASK_FCVT_L_Q  0xfff0007f
-#define MATCH_FCVT_LU_Q 0xc6300053
-#define MASK_FCVT_LU_Q  0xfff0007f
-#define MATCH_FMV_X_Q 0xe6000053
-#define MASK_FMV_X_Q  0xfff0707f
-#define MATCH_FCLASS_Q 0xe6001053
-#define MASK_FCLASS_Q  0xfff0707f
-#define MATCH_FCVT_S_W 0xd0000053
-#define MASK_FCVT_S_W  0xfff0007f
-#define MATCH_FCVT_S_WU 0xd0100053
-#define MASK_FCVT_S_WU  0xfff0007f
-#define MATCH_FCVT_S_L 0xd0200053
-#define MASK_FCVT_S_L  0xfff0007f
-#define MATCH_FCVT_S_LU 0xd0300053
-#define MASK_FCVT_S_LU  0xfff0007f
-#define MATCH_FMV_W_X 0xf0000053
-#define MASK_FMV_W_X  0xfff0707f
-#define MATCH_FCVT_D_W 0xd2000053
-#define MASK_FCVT_D_W  0xfff0007f
-#define MATCH_FCVT_D_WU 0xd2100053
-#define MASK_FCVT_D_WU  0xfff0007f
-#define MATCH_FCVT_D_L 0xd2200053
-#define MASK_FCVT_D_L  0xfff0007f
-#define MATCH_FCVT_D_LU 0xd2300053
-#define MASK_FCVT_D_LU  0xfff0007f
-#define MATCH_FMV_D_X 0xf2000053
-#define MASK_FMV_D_X  0xfff0707f
-#define MATCH_FCVT_Q_W 0xd6000053
-#define MASK_FCVT_Q_W  0xfff0007f
-#define MATCH_FCVT_Q_WU 0xd6100053
-#define MASK_FCVT_Q_WU  0xfff0007f
-#define MATCH_FCVT_Q_L 0xd6200053
-#define MASK_FCVT_Q_L  0xfff0007f
-#define MATCH_FCVT_Q_LU 0xd6300053
-#define MASK_FCVT_Q_LU  0xfff0007f
-#define MATCH_FMV_Q_X 0xf6000053
-#define MASK_FMV_Q_X  0xfff0707f
-#define MATCH_FLW 0x2007
-#define MASK_FLW  0x707f
-#define MATCH_FLD 0x3007
-#define MASK_FLD  0x707f
-#define MATCH_FLQ 0x4007
-#define MASK_FLQ  0x707f
-#define MATCH_FSW 0x2027
-#define MASK_FSW  0x707f
-#define MATCH_FSD 0x3027
-#define MASK_FSD  0x707f
-#define MATCH_FSQ 0x4027
-#define MASK_FSQ  0x707f
-#define MATCH_FMADD_S 0x43
-#define MASK_FMADD_S  0x600007f
-#define MATCH_FMSUB_S 0x47
-#define MASK_FMSUB_S  0x600007f
-#define MATCH_FNMSUB_S 0x4b
-#define MASK_FNMSUB_S  0x600007f
-#define MATCH_FNMADD_S 0x4f
-#define MASK_FNMADD_S  0x600007f
-#define MATCH_FMADD_D 0x2000043
-#define MASK_FMADD_D  0x600007f
-#define MATCH_FMSUB_D 0x2000047
-#define MASK_FMSUB_D  0x600007f
-#define MATCH_FNMSUB_D 0x200004b
-#define MASK_FNMSUB_D  0x600007f
-#define MATCH_FNMADD_D 0x200004f
-#define MASK_FNMADD_D  0x600007f
-#define MATCH_FMADD_Q 0x6000043
-#define MASK_FMADD_Q  0x600007f
-#define MATCH_FMSUB_Q 0x6000047
-#define MASK_FMSUB_Q  0x600007f
-#define MATCH_FNMSUB_Q 0x600004b
-#define MASK_FNMSUB_Q  0x600007f
-#define MATCH_FNMADD_Q 0x600004f
-#define MASK_FNMADD_Q  0x600007f
-#define MATCH_C_NOP 0x1
-#define MASK_C_NOP  0xffff
-#define MATCH_C_ADDI16SP 0x6101
-#define MASK_C_ADDI16SP  0xef83
-#define MATCH_C_JR 0x8002
-#define MASK_C_JR  0xf07f
-#define MATCH_C_JALR 0x9002
-#define MASK_C_JALR  0xf07f
-#define MATCH_C_EBREAK 0x9002
-#define MASK_C_EBREAK  0xffff
-#define MATCH_C_LD 0x6000
-#define MASK_C_LD  0xe003
-#define MATCH_C_SD 0xe000
-#define MASK_C_SD  0xe003
-#define MATCH_C_ADDIW 0x2001
-#define MASK_C_ADDIW  0xe003
-#define MATCH_C_LDSP 0x6002
-#define MASK_C_LDSP  0xe003
-#define MATCH_C_SDSP 0xe002
-#define MASK_C_SDSP  0xe003
-#define MATCH_C_ADDI4SPN 0x0
-#define MASK_C_ADDI4SPN  0xe003
-#define MATCH_C_FLD 0x2000
-#define MASK_C_FLD  0xe003
-#define MATCH_C_LW 0x4000
-#define MASK_C_LW  0xe003
-#define MATCH_C_FLW 0x6000
-#define MASK_C_FLW  0xe003
-#define MATCH_C_FSD 0xa000
-#define MASK_C_FSD  0xe003
-#define MATCH_C_SW 0xc000
-#define MASK_C_SW  0xe003
-#define MATCH_C_FSW 0xe000
-#define MASK_C_FSW  0xe003
-#define MATCH_C_ADDI 0x1
-#define MASK_C_ADDI  0xe003
-#define MATCH_C_JAL 0x2001
-#define MASK_C_JAL  0xe003
-#define MATCH_C_LI 0x4001
-#define MASK_C_LI  0xe003
-#define MATCH_C_LUI 0x6001
-#define MASK_C_LUI  0xe003
-#define MATCH_C_SRLI 0x8001
-#define MASK_C_SRLI  0xec03
-#define MATCH_C_SRAI 0x8401
-#define MASK_C_SRAI  0xec03
-#define MATCH_C_ANDI 0x8801
-#define MASK_C_ANDI  0xec03
-#define MATCH_C_SUB 0x8c01
-#define MASK_C_SUB  0xfc63
-#define MATCH_C_XOR 0x8c21
-#define MASK_C_XOR  0xfc63
-#define MATCH_C_OR 0x8c41
-#define MASK_C_OR  0xfc63
-#define MATCH_C_AND 0x8c61
-#define MASK_C_AND  0xfc63
-#define MATCH_C_SUBW 0x9c01
-#define MASK_C_SUBW  0xfc63
-#define MATCH_C_ADDW 0x9c21
-#define MASK_C_ADDW  0xfc63
-#define MATCH_C_J 0xa001
-#define MASK_C_J  0xe003
-#define MATCH_C_BEQZ 0xc001
-#define MASK_C_BEQZ  0xe003
-#define MATCH_C_BNEZ 0xe001
-#define MASK_C_BNEZ  0xe003
-#define MATCH_C_SLLI 0x2
-#define MASK_C_SLLI  0xe003
-#define MATCH_C_FLDSP 0x2002
-#define MASK_C_FLDSP  0xe003
-#define MATCH_C_LWSP 0x4002
-#define MASK_C_LWSP  0xe003
-#define MATCH_C_FLWSP 0x6002
-#define MASK_C_FLWSP  0xe003
-#define MATCH_C_MV 0x8002
-#define MASK_C_MV  0xf003
-#define MATCH_C_ADD 0x9002
-#define MASK_C_ADD  0xf003
-#define MATCH_C_FSDSP 0xa002
-#define MASK_C_FSDSP  0xe003
-#define MATCH_C_SWSP 0xc002
-#define MASK_C_SWSP  0xe003
-#define MATCH_C_FSWSP 0xe002
-#define MASK_C_FSWSP  0xe003
-#define MATCH_CUSTOM0 0xb
-#define MASK_CUSTOM0  0x707f
-#define MATCH_CUSTOM0_RS1 0x200b
-#define MASK_CUSTOM0_RS1  0x707f
-#define MATCH_CUSTOM0_RS1_RS2 0x300b
-#define MASK_CUSTOM0_RS1_RS2  0x707f
-#define MATCH_CUSTOM0_RD 0x400b
-#define MASK_CUSTOM0_RD  0x707f
-#define MATCH_CUSTOM0_RD_RS1 0x600b
-#define MASK_CUSTOM0_RD_RS1  0x707f
-#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
-#define MATCH_CUSTOM1 0x2b
-#define MASK_CUSTOM1  0x707f
-#define MATCH_CUSTOM1_RS1 0x202b
-#define MASK_CUSTOM1_RS1  0x707f
-#define MATCH_CUSTOM1_RS1_RS2 0x302b
-#define MASK_CUSTOM1_RS1_RS2  0x707f
-#define MATCH_CUSTOM1_RD 0x402b
-#define MASK_CUSTOM1_RD  0x707f
-#define MATCH_CUSTOM1_RD_RS1 0x602b
-#define MASK_CUSTOM1_RD_RS1  0x707f
-#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
-#define MATCH_CUSTOM2 0x5b
-#define MASK_CUSTOM2  0x707f
-#define MATCH_CUSTOM2_RS1 0x205b
-#define MASK_CUSTOM2_RS1  0x707f
-#define MATCH_CUSTOM2_RS1_RS2 0x305b
-#define MASK_CUSTOM2_RS1_RS2  0x707f
-#define MATCH_CUSTOM2_RD 0x405b
-#define MASK_CUSTOM2_RD  0x707f
-#define MATCH_CUSTOM2_RD_RS1 0x605b
-#define MASK_CUSTOM2_RD_RS1  0x707f
-#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
-#define MATCH_CUSTOM3 0x7b
-#define MASK_CUSTOM3  0x707f
-#define MATCH_CUSTOM3_RS1 0x207b
-#define MASK_CUSTOM3_RS1  0x707f
-#define MATCH_CUSTOM3_RS1_RS2 0x307b
-#define MASK_CUSTOM3_RS1_RS2  0x707f
-#define MATCH_CUSTOM3_RD 0x407b
-#define MASK_CUSTOM3_RD  0x707f
-#define MATCH_CUSTOM3_RD_RS1 0x607b
-#define MASK_CUSTOM3_RD_RS1  0x707f
-#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
-#define CSR_FFLAGS 0x1
-#define CSR_FRM 0x2
-#define CSR_FCSR 0x3
-#define CSR_CYCLE 0xc00
-#define CSR_TIME 0xc01
-#define CSR_INSTRET 0xc02
-#define CSR_HPMCOUNTER3 0xc03
-#define CSR_HPMCOUNTER4 0xc04
-#define CSR_HPMCOUNTER5 0xc05
-#define CSR_HPMCOUNTER6 0xc06
-#define CSR_HPMCOUNTER7 0xc07
-#define CSR_HPMCOUNTER8 0xc08
-#define CSR_HPMCOUNTER9 0xc09
-#define CSR_HPMCOUNTER10 0xc0a
-#define CSR_HPMCOUNTER11 0xc0b
-#define CSR_HPMCOUNTER12 0xc0c
-#define CSR_HPMCOUNTER13 0xc0d
-#define CSR_HPMCOUNTER14 0xc0e
-#define CSR_HPMCOUNTER15 0xc0f
-#define CSR_HPMCOUNTER16 0xc10
-#define CSR_HPMCOUNTER17 0xc11
-#define CSR_HPMCOUNTER18 0xc12
-#define CSR_HPMCOUNTER19 0xc13
-#define CSR_HPMCOUNTER20 0xc14
-#define CSR_HPMCOUNTER21 0xc15
-#define CSR_HPMCOUNTER22 0xc16
-#define CSR_HPMCOUNTER23 0xc17
-#define CSR_HPMCOUNTER24 0xc18
-#define CSR_HPMCOUNTER25 0xc19
-#define CSR_HPMCOUNTER26 0xc1a
-#define CSR_HPMCOUNTER27 0xc1b
-#define CSR_HPMCOUNTER28 0xc1c
-#define CSR_HPMCOUNTER29 0xc1d
-#define CSR_HPMCOUNTER30 0xc1e
-#define CSR_HPMCOUNTER31 0xc1f
-#define CSR_SSTATUS 0x100
-#define CSR_SIE 0x104
-#define CSR_STVEC 0x105
-#define CSR_SCOUNTEREN 0x106
-#define CSR_SSCRATCH 0x140
-#define CSR_SEPC 0x141
-#define CSR_SCAUSE 0x142
-#define CSR_STVAL 0x143
-#define CSR_SIP 0x144
-#define CSR_SATP 0x180
-#define CSR_MSTATUS 0x300
-#define CSR_MISA 0x301
-#define CSR_MEDELEG 0x302
-#define CSR_MIDELEG 0x303
-#define CSR_MIE 0x304
-#define CSR_MTVEC 0x305
-#define CSR_MCOUNTEREN 0x306
-#define CSR_MSCRATCH 0x340
-#define CSR_MEPC 0x341
-#define CSR_MCAUSE 0x342
-#define CSR_MTVAL 0x343
-#define CSR_MIP 0x344
-#define CSR_PMPCFG0 0x3a0
-#define CSR_PMPCFG1 0x3a1
-#define CSR_PMPCFG2 0x3a2
-#define CSR_PMPCFG3 0x3a3
-#define CSR_PMPADDR0 0x3b0
-#define CSR_PMPADDR1 0x3b1
-#define CSR_PMPADDR2 0x3b2
-#define CSR_PMPADDR3 0x3b3
-#define CSR_PMPADDR4 0x3b4
-#define CSR_PMPADDR5 0x3b5
-#define CSR_PMPADDR6 0x3b6
-#define CSR_PMPADDR7 0x3b7
-#define CSR_PMPADDR8 0x3b8
-#define CSR_PMPADDR9 0x3b9
-#define CSR_PMPADDR10 0x3ba
-#define CSR_PMPADDR11 0x3bb
-#define CSR_PMPADDR12 0x3bc
-#define CSR_PMPADDR13 0x3bd
-#define CSR_PMPADDR14 0x3be
-#define CSR_PMPADDR15 0x3bf
-#define CSR_TSELECT 0x7a0
-#define CSR_TDATA1 0x7a1
-#define CSR_TDATA2 0x7a2
-#define CSR_TDATA3 0x7a3
-#define CSR_DCSR 0x7b0
-#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
-#define CSR_DSCRATCH0 CSR_DSCRATCH
-#define CSR_DSCRATCH1 0x7b3
-#define CSR_MCYCLE 0xb00
-#define CSR_MINSTRET 0xb02
-#define CSR_MHPMCOUNTER3 0xb03
-#define CSR_MHPMCOUNTER4 0xb04
-#define CSR_MHPMCOUNTER5 0xb05
-#define CSR_MHPMCOUNTER6 0xb06
-#define CSR_MHPMCOUNTER7 0xb07
-#define CSR_MHPMCOUNTER8 0xb08
-#define CSR_MHPMCOUNTER9 0xb09
-#define CSR_MHPMCOUNTER10 0xb0a
-#define CSR_MHPMCOUNTER11 0xb0b
-#define CSR_MHPMCOUNTER12 0xb0c
-#define CSR_MHPMCOUNTER13 0xb0d
-#define CSR_MHPMCOUNTER14 0xb0e
-#define CSR_MHPMCOUNTER15 0xb0f
-#define CSR_MHPMCOUNTER16 0xb10
-#define CSR_MHPMCOUNTER17 0xb11
-#define CSR_MHPMCOUNTER18 0xb12
-#define CSR_MHPMCOUNTER19 0xb13
-#define CSR_MHPMCOUNTER20 0xb14
-#define CSR_MHPMCOUNTER21 0xb15
-#define CSR_MHPMCOUNTER22 0xb16
-#define CSR_MHPMCOUNTER23 0xb17
-#define CSR_MHPMCOUNTER24 0xb18
-#define CSR_MHPMCOUNTER25 0xb19
-#define CSR_MHPMCOUNTER26 0xb1a
-#define CSR_MHPMCOUNTER27 0xb1b
-#define CSR_MHPMCOUNTER28 0xb1c
-#define CSR_MHPMCOUNTER29 0xb1d
-#define CSR_MHPMCOUNTER30 0xb1e
-#define CSR_MHPMCOUNTER31 0xb1f
-#define CSR_MHPMEVENT3 0x323
-#define CSR_MHPMEVENT4 0x324
-#define CSR_MHPMEVENT5 0x325
-#define CSR_MHPMEVENT6 0x326
-#define CSR_MHPMEVENT7 0x327
-#define CSR_MHPMEVENT8 0x328
-#define CSR_MHPMEVENT9 0x329
-#define CSR_MHPMEVENT10 0x32a
-#define CSR_MHPMEVENT11 0x32b
-#define CSR_MHPMEVENT12 0x32c
-#define CSR_MHPMEVENT13 0x32d
-#define CSR_MHPMEVENT14 0x32e
-#define CSR_MHPMEVENT15 0x32f
-#define CSR_MHPMEVENT16 0x330
-#define CSR_MHPMEVENT17 0x331
-#define CSR_MHPMEVENT18 0x332
-#define CSR_MHPMEVENT19 0x333
-#define CSR_MHPMEVENT20 0x334
-#define CSR_MHPMEVENT21 0x335
-#define CSR_MHPMEVENT22 0x336
-#define CSR_MHPMEVENT23 0x337
-#define CSR_MHPMEVENT24 0x338
-#define CSR_MHPMEVENT25 0x339
-#define CSR_MHPMEVENT26 0x33a
-#define CSR_MHPMEVENT27 0x33b
-#define CSR_MHPMEVENT28 0x33c
-#define CSR_MHPMEVENT29 0x33d
-#define CSR_MHPMEVENT30 0x33e
-#define CSR_MHPMEVENT31 0x33f
-#define CSR_MVENDORID 0xf11
-#define CSR_MARCHID 0xf12
-#define CSR_MIMPID 0xf13
-#define CSR_MHARTID 0xf14
-#define CSR_CYCLEH 0xc80
-#define CSR_TIMEH 0xc81
-#define CSR_INSTRETH 0xc82
-#define CSR_HPMCOUNTER3H 0xc83
-#define CSR_HPMCOUNTER4H 0xc84
-#define CSR_HPMCOUNTER5H 0xc85
-#define CSR_HPMCOUNTER6H 0xc86
-#define CSR_HPMCOUNTER7H 0xc87
-#define CSR_HPMCOUNTER8H 0xc88
-#define CSR_HPMCOUNTER9H 0xc89
-#define CSR_HPMCOUNTER10H 0xc8a
-#define CSR_HPMCOUNTER11H 0xc8b
-#define CSR_HPMCOUNTER12H 0xc8c
-#define CSR_HPMCOUNTER13H 0xc8d
-#define CSR_HPMCOUNTER14H 0xc8e
-#define CSR_HPMCOUNTER15H 0xc8f
-#define CSR_HPMCOUNTER16H 0xc90
-#define CSR_HPMCOUNTER17H 0xc91
-#define CSR_HPMCOUNTER18H 0xc92
-#define CSR_HPMCOUNTER19H 0xc93
-#define CSR_HPMCOUNTER20H 0xc94
-#define CSR_HPMCOUNTER21H 0xc95
-#define CSR_HPMCOUNTER22H 0xc96
-#define CSR_HPMCOUNTER23H 0xc97
-#define CSR_HPMCOUNTER24H 0xc98
-#define CSR_HPMCOUNTER25H 0xc99
-#define CSR_HPMCOUNTER26H 0xc9a
-#define CSR_HPMCOUNTER27H 0xc9b
-#define CSR_HPMCOUNTER28H 0xc9c
-#define CSR_HPMCOUNTER29H 0xc9d
-#define CSR_HPMCOUNTER30H 0xc9e
-#define CSR_HPMCOUNTER31H 0xc9f
-#define CSR_MCYCLEH 0xb80
-#define CSR_MINSTRETH 0xb82
-#define CSR_MHPMCOUNTER3H 0xb83
-#define CSR_MHPMCOUNTER4H 0xb84
-#define CSR_MHPMCOUNTER5H 0xb85
-#define CSR_MHPMCOUNTER6H 0xb86
-#define CSR_MHPMCOUNTER7H 0xb87
-#define CSR_MHPMCOUNTER8H 0xb88
-#define CSR_MHPMCOUNTER9H 0xb89
-#define CSR_MHPMCOUNTER10H 0xb8a
-#define CSR_MHPMCOUNTER11H 0xb8b
-#define CSR_MHPMCOUNTER12H 0xb8c
-#define CSR_MHPMCOUNTER13H 0xb8d
-#define CSR_MHPMCOUNTER14H 0xb8e
-#define CSR_MHPMCOUNTER15H 0xb8f
-#define CSR_MHPMCOUNTER16H 0xb90
-#define CSR_MHPMCOUNTER17H 0xb91
-#define CSR_MHPMCOUNTER18H 0xb92
-#define CSR_MHPMCOUNTER19H 0xb93
-#define CSR_MHPMCOUNTER20H 0xb94
-#define CSR_MHPMCOUNTER21H 0xb95
-#define CSR_MHPMCOUNTER22H 0xb96
-#define CSR_MHPMCOUNTER23H 0xb97
-#define CSR_MHPMCOUNTER24H 0xb98
-#define CSR_MHPMCOUNTER25H 0xb99
-#define CSR_MHPMCOUNTER26H 0xb9a
-#define CSR_MHPMCOUNTER27H 0xb9b
-#define CSR_MHPMCOUNTER28H 0xb9c
-#define CSR_MHPMCOUNTER29H 0xb9d
-#define CSR_MHPMCOUNTER30H 0xb9e
-#define CSR_MHPMCOUNTER31H 0xb9f
-#define CAUSE_MISALIGNED_FETCH 0x0
-#define CAUSE_FETCH_ACCESS 0x1
-#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-#define CAUSE_BREAKPOINT 0x3
-#define CAUSE_MISALIGNED_LOAD 0x4
-#define CAUSE_LOAD_ACCESS 0x5
-#define CAUSE_MISALIGNED_STORE 0x6
-#define CAUSE_STORE_ACCESS 0x7
-#define CAUSE_USER_ECALL 0x8
-#define CAUSE_SUPERVISOR_ECALL 0x9
-#define CAUSE_HYPERVISOR_ECALL 0xa
-#define CAUSE_MACHINE_ECALL 0xb
-#define CAUSE_FETCH_PAGE_FAULT 0xc
-#define CAUSE_LOAD_PAGE_FAULT 0xd
-#define CAUSE_STORE_PAGE_FAULT 0xf
-#endif
-#ifdef DECLARE_INSN
-DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
-DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
-DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
-DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
-DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
-DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
-DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
-DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
-DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
-DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
-DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
-DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
-DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
-DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
-DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
-DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
-DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
-DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
-DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
-DECLARE_INSN(or, MATCH_OR, MASK_OR)
-DECLARE_INSN(and, MATCH_AND, MASK_AND)
-DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
-DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
-DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
-DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
-DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
-DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
-DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
-DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
-DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-DECLARE_INSN(lw, MATCH_LW, MASK_LW)
-DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
-DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
-DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
-DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
-DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
-DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
-DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
-DECLARE_INSN(rem, MATCH_REM, MASK_REM)
-DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
-DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
-DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
-DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
-DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
-DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
-DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
-DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
-DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
-DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
-DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
-DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
-DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
-DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
-DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
-DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
-DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
-DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
-DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
-DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
-DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
-DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
-DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
-DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
-DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
-DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
-DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-DECLARE_INSN(uret, MATCH_URET, MASK_URET)
-DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
-DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
-DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
-DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
-DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
-DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
-DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
-DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
-DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
-DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
-DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
-DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
-DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
-DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
-DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
-DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
-DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
-DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
-DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
-DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
-DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
-DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
-DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
-DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
-DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
-DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
-DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
-DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
-DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
-DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
-DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
-DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
-DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
-DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
-DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
-DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
-DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
-DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
-DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
-DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
-DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
-DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
-DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
-DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
-DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
-DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
-DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
-DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
-DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
-DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
-DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
-DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
-DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
-DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
-DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
-DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
-DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
-DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
-DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
-DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
-DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
-DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
-DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
-DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
-DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
-DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
-DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
-DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
-DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
-DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
-DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
-DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
-DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
-DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
-DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
-DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
-DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
-DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
-DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
-DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
-DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
-DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
-DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
-DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
-DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
-DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
-DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
-DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
-DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
-DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
-DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
-DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
-DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
-DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
-DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
-DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
-DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
-DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-#endif
-#ifdef DECLARE_CSR
-DECLARE_CSR(fflags, CSR_FFLAGS)
-DECLARE_CSR(frm, CSR_FRM)
-DECLARE_CSR(fcsr, CSR_FCSR)
-DECLARE_CSR(cycle, CSR_CYCLE)
-DECLARE_CSR(time, CSR_TIME)
-DECLARE_CSR(instret, CSR_INSTRET)
-DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
-DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
-DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
-DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
-DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
-DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
-DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
-DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
-DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
-DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
-DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
-DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
-DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
-DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
-DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
-DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
-DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
-DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
-DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
-DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
-DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
-DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
-DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
-DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
-DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
-DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
-DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
-DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
-DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
-DECLARE_CSR(sstatus, CSR_SSTATUS)
-DECLARE_CSR(sie, CSR_SIE)
-DECLARE_CSR(stvec, CSR_STVEC)
-DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
-DECLARE_CSR(sscratch, CSR_SSCRATCH)
-DECLARE_CSR(sepc, CSR_SEPC)
-DECLARE_CSR(scause, CSR_SCAUSE)
-DECLARE_CSR(stval, CSR_STVAL)
-DECLARE_CSR(sip, CSR_SIP)
-DECLARE_CSR(satp, CSR_SATP)
-DECLARE_CSR(mstatus, CSR_MSTATUS)
-DECLARE_CSR(misa, CSR_MISA)
-DECLARE_CSR(medeleg, CSR_MEDELEG)
-DECLARE_CSR(mideleg, CSR_MIDELEG)
-DECLARE_CSR(mie, CSR_MIE)
-DECLARE_CSR(mtvec, CSR_MTVEC)
-DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
-DECLARE_CSR(mscratch, CSR_MSCRATCH)
-DECLARE_CSR(mepc, CSR_MEPC)
-DECLARE_CSR(mcause, CSR_MCAUSE)
-DECLARE_CSR(mtval, CSR_MTVAL)
-DECLARE_CSR(mip, CSR_MIP)
-DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
-DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
-DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
-DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
-DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
-DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
-DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
-DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
-DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
-DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
-DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
-DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
-DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
-DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
-DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
-DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
-DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
-DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
-DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
-DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
-DECLARE_CSR(tselect, CSR_TSELECT)
-DECLARE_CSR(tdata1, CSR_TDATA1)
-DECLARE_CSR(tdata2, CSR_TDATA2)
-DECLARE_CSR(tdata3, CSR_TDATA3)
-DECLARE_CSR(dcsr, CSR_DCSR)
-DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
-DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
-DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
-DECLARE_CSR(mcycle, CSR_MCYCLE)
-DECLARE_CSR(minstret, CSR_MINSTRET)
-DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
-DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
-DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
-DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
-DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
-DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
-DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
-DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
-DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
-DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
-DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
-DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
-DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
-DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
-DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
-DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
-DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
-DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
-DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
-DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
-DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
-DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
-DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
-DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
-DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
-DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
-DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
-DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
-DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
-DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
-DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
-DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
-DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
-DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
-DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
-DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
-DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
-DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
-DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
-DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
-DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
-DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
-DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
-DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
-DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
-DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
-DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
-DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
-DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
-DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
-DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
-DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
-DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
-DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
-DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
-DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
-DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
-DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
-DECLARE_CSR(mvendorid, CSR_MVENDORID)
-DECLARE_CSR(marchid, CSR_MARCHID)
-DECLARE_CSR(mimpid, CSR_MIMPID)
-DECLARE_CSR(mhartid, CSR_MHARTID)
-DECLARE_CSR(cycleh, CSR_CYCLEH)
-DECLARE_CSR(timeh, CSR_TIMEH)
-DECLARE_CSR(instreth, CSR_INSTRETH)
-DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
-DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
-DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
-DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
-DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
-DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
-DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
-DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
-DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
-DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
-DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
-DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
-DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
-DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
-DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
-DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
-DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
-DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
-DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
-DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
-DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
-DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
-DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
-DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
-DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
-DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
-DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
-DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
-DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
-DECLARE_CSR(mcycleh, CSR_MCYCLEH)
-DECLARE_CSR(minstreth, CSR_MINSTRETH)
-DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
-DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
-DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
-DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
-DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
-DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
-DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
-DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
-DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
-DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
-DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
-DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
-DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
-DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
-DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
-DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
-DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
-DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
-DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
-DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
-DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
-DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
-DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
-DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
-DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
-DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
-DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
-DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
-DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
-#endif
-#ifdef DECLARE_CAUSE
-DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
-DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
-DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
-DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
-DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
-DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
-DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
-DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
-DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
-DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
-DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
-DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
-DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
-DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
-DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
-#endif
diff --git a/core/example_tb/bootrom/gen_rom.py b/core/example_tb/bootrom/gen_rom.py
deleted file mode 100755
index 16e4488461..0000000000
--- a/core/example_tb/bootrom/gen_rom.py
+++ /dev/null
@@ -1,135 +0,0 @@
-#!/usr/bin/env python3
-
-from string import Template
-import argparse
-import os.path
-import sys
-import binascii
-
-
-parser = argparse.ArgumentParser(description='Convert binary file to verilog rom')
-parser.add_argument('filename', metavar='filename', nargs=1,
-                   help='filename of input binary')
-
-args = parser.parse_args()
-file = args.filename[0];
-
-# check that file exists
-if not os.path.isfile(file):
-    print("File {} does not exist.".format(filename))
-    sys.exit(1)
-
-filename = os.path.splitext(file)[0]
-
-license = """\
-/* Copyright 2018 ETH Zurich and University of Bologna.
- * Copyright and related rights are licensed under the Solderpad Hardware
- * License, Version 0.51 (the "License"); you may not use this file except in
- * compliance with the License.  You may obtain a copy of the License at
- * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
- * or agreed to in writing, software, hardware and materials distributed under
- * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
- * CONDITIONS OF ANY KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations under the License.
- *
- * File: $filename.v
- *
- * Description: Auto-generated bootrom
- */
-
-// Auto-generated code
-"""
-
-module = """\
-module $filename (
-   input  logic         clk_i,
-   input  logic         req_i,
-   input  logic [63:0]  addr_i,
-   output logic [63:0]  rdata_o
-);
-    localparam int RomSize = $size;
-
-    const logic [RomSize-1:0][63:0] mem = {
-$content
-    };
-
-    logic [$$clog2(RomSize)-1:0] addr_q;
-
-    always_ff @(posedge clk_i) begin
-        if (req_i) begin
-            addr_q <= addr_i[$$clog2(RomSize)-1+3:3];
-        end
-    end
-
-    // this prevents spurious Xes from propagating into
-    // the speculative fetch stage of the core
-    assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
-endmodule
-"""
-
-c_var = """\
-// Auto-generated code
-
-const int reset_vec_size = $size;
-
-uint32_t reset_vec[reset_vec_size] = {
-$content
-};
-"""
-
-def read_bin():
-
-    numlines=0
-    with open(filename + ".img", 'rb') as f:
-        rom = binascii.hexlify(f.read())
-        #rom = map(''.join, zip(rom[::2], rom[1::2]))
-        zipped = zip(rom[::2], rom[1::2])
-        #print(zipped)
-        numlines = numlines+1
-
-
-    #print (numlines)
-    print (rom)
-    print (len(rom))
-    # align to 64 bit
-    #mylist = list(rom)
-    #align = (int((len(rom) + 7) / 8 )) * 8
-
-    for i in range(len(list(rom)), align):
-        rom.append("00")
-
-    return rom
-
-rom = read_bin()
-
-""" Generate C header file for simulator
-"""
-with open(filename + ".h", "w") as f:
-    rom_str = ""
-    # process in junks of 32 bit (4 byte)
-    for i in range(0, int(len(rom)/4)):
-        rom_str += "    0x" + "".join(rom[i*4:i*4+4][::-1]) + ",\n"
-
-    # remove the trailing comma
-    rom_str = rom_str[:-2]
-
-    s = Template(c_var)
-    f.write(s.substitute(filename=filename, size=int(len(rom)/4), content=rom_str))
-
-    f.close()
-
-""" Generate SystemVerilog bootcode for FPGA and ASIC
-"""
-with open(filename + ".sv", "w") as f:
-    rom_str = ""
-    # process in junks of 64 bit (8 byte)
-    for i in reversed(range(int(len(rom)/8))):
-        rom_str += "        64'h" + "".join(rom[i*8+4:i*8+8][::-1]) + "_" + "".join(rom[i*8:i*8+4][::-1]) + ",\n"
-
-    # remove the trailing comma
-    rom_str = rom_str[:-2]
-
-    f.write(license)
-    s = Template(module)
-    f.write(s.substitute(filename=filename, size=int(len(rom)/8), content=rom_str))
-
diff --git a/core/example_tb/bootrom/linker.ld b/core/example_tb/bootrom/linker.ld
deleted file mode 100644
index 43bc012aa8..0000000000
--- a/core/example_tb/bootrom/linker.ld
+++ /dev/null
@@ -1,11 +0,0 @@
-SECTIONS
-{
-    ROM_BASE = 0x10000; /* ... but actually position independent */
-
-    . = ROM_BASE;
-    .text.start : { *(.text.start) }
-    . = ROM_BASE + 0x40;
-    .text.hang : { *(.text.hang) }
-    . = ROM_BASE + 0x80;
-    .rodata.dtb : { *(.rodata.dtb) }
-}
diff --git a/core/example_tb/bsp/.gitignore b/core/example_tb/bsp/.gitignore
deleted file mode 100644
index c0a1f349c4..0000000000
--- a/core/example_tb/bsp/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-libcv-verif.a
diff --git a/core/example_tb/bsp/Makefile b/core/example_tb/bsp/Makefile
deleted file mode 100644
index 17ead027d0..0000000000
--- a/core/example_tb/bsp/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-CV_SW_TOOLCHAIN  ?= /opt/riscv
-RISCV            ?= $(CV_SW_TOOLCHAIN)
-RISCV_EXE_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf-
-RISCV_GCC = $(RISCV_EXE_PREFIX)gcc
-RISCV_AR = $(RISCV_EXE_PREFIX)ar
-SRC = crt0.S handlers.S syscalls.c vectors.S
-OBJ = crt0.o handlers.o syscalls.o vectors.o
-LIBCV-VERIF = libcv-verif.a 
-CFLAGS ?= -Os -g -static -mabi=ilp32 -march=rv32imc -Wall -pedantic
-
-all: $(LIBCV-VERIF)
-
-$(LIBCV-VERIF): $(OBJ) 
-	$(RISCV_AR) rcs $@ $(OBJ)
-
-%.o : %.c
-	$(RISCV_GCC) $(CFLAGS) -c $< -o $@
-	
-%.o : %.S
-	$(RISCV_GCC) $(CFLAGS) -c $< -o $@
-
-clean:
-	rm -f $(OBJ) $(LIBCV-VERIF)
-
-
-vars:
-	@echo "make bsp variables:"
-	@echo "   CV_SW_TOOLCHAIN  = $(CV_SW_TOOLCHAIN)"
-	@echo "   RISCV            = $(RISCV)"
-	@echo "   RISCV_EXE_PREFIX = $(RISCV_EXE_PREFIX)"
-	@echo "   RISCV_GCC        = $(RISCV_GCC)"
-
diff --git a/core/example_tb/bsp/README.md b/core/example_tb/bsp/README.md
deleted file mode 100644
index 8e6d5d44c6..0000000000
--- a/core/example_tb/bsp/README.md
+++ /dev/null
@@ -1,166 +0,0 @@
-Board Support Package (BSP) for CV32 Verification
-=================================================
-
-This BSP provides the code to support running programs on the CV32 verification
-target. It performs initialization tasks (`crt0.S`), handles
-interrupts/exceptions (`vectors.S`, `handlers.S`), provides syscall
-implementations (`syscalls.c`) and includes a linker script (`link.ld`) to
-control the placement of sections in the binary.
-
-Each file is described in more detail below followed by instructions for
-building and using the BSP.
-
-C Runtime Initialization
-------------------------
-
-The C Runtime file `crt0.S` provides the `_start` function which is the entry
-point of the program and performs the following tasks:
-  * Initialize global and stack pointer.
-  * Store the address of `vector_table` in `mtvec`, setting the lower two bits
-  to `0x2` to select vectored interrupt mode.
-  * Zero the BSS section.
-  * Invoke initialization of C constructors and set destructors to be called on
-  exit.
-  * Zero `argc` and `argv` (the stack is not initialized, so these are zeroed
-  to prevent uninitialized values causing a mismatch against the reference
-  result).
-  * Call `main`.
-  * If `main` returns, call `exit` with its return code.
-
-Interrupt and Exception Handling
---------------------------------
-
-When a RISC-V core traps on an interrupt/exception, the `pc` is stored in `mepc`
-and the reason for the trap is stored in `mcause`. The `MSB` of `mcause`
-is set to `0` for an exception and `1` for an interrupt; the remaining bits
-`mcause[MXLEN-2:0]` contain the exception code. The table of `mcause` values is
-defined in Table 3.6 of the [RISC-V Instruction Set Manual Volume II: Privileged
-Architecture Version 20190608-Priv-MSU-Ratified](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf).
-
-The core jumps to a location in the vector table according to the `BASE` address
-of the vector table stored in `mtvec` and the value of the exception code in
-`mcause`. In vectored mode, all exceptions jump to `BASE` and interrupts jump to
-`BASE+4*mcause[XLEN-2:0]`. Note that because user software interrupts have
-exception code `0`, they jump to the same location as exceptions, therefore the
-user software interrupt handler must also handle exceptions.
-
-The vector table is defined in `vectors.S` and may jump to one of the
-following interrupt request handlers in `handlers.S`:
-  * `u_sw_irq_handler` - handles user software interrupts and all exceptions.
-  Saves all caller saved registers then checks `mcause` and jumps to the
-  appropriate handler as follows:
-    - Breakpoint: jump to `handle_ebreak`.
-    - Illegal instruction: jump to `handle_illegal`.
-    - Environment call from M-mode: jump to `handle_ecall`.
-    - Any other exception or user software interrupt: jump to `handle_unknown`.
-  * `m_software_irq_handler` - handles machine-mode software interrupts
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_timer_irq_handler` - handles machine-mode timer interrupts
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_external_irq_handler` - handles machine-mode external interrupts
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast0_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)  
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast1_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast2_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast3_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast4_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast5_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast6_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast7_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast8_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast9_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast10_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast11_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast12_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast13_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast14_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `m_fast15_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32)
-    - Currently jumps to `__no_irq_handler`.  Behavior to be defined in future commit.
-  * `__no_irq_handler` - loops printing "no exception handler installed".
-
-The following exception handlers may be called from `u_sw_irq_handler`:
-  * `handle_ecall` - calls `handle_syscall` which checks the syscall number and
-  calls the corresponding syscall function.
-  * `handle_ebreak` - currently just prints "ebreak exception handler entered"
-  * `handle_illegal_insn` - prints "illegal instruction exception handler
-  entered"
-  * `unknown_handler` - called when there is no handler for the interrupt/
-  exception. This is the only case where `mepc` is not incremented, because we
-  do not know the appropiate action to take.
-
-Returning from the `u_sw_irq_handler`. All handlers called by `u_sw_irq_handler`
-increment `mepc` before calling `mret`, except for `unknown_handler`. Handlers
-that require `mepc` to be incremented jump to `end_handler_incr_mepc` otherwise
-they jump to `end_handler_ret`. All caller saved registers are restored before
-finally calling `mret`.
-
-Some test cases require the ability to override the default handlers. In future,
-these handlers will be made overridable by defining their labels as `.weak`
-symbols. Test cases can then provide their own handlers where necessary.
-
-System Calls
-------------
-
-On a bare-metal system there is no OS to handle system calls, therefore, we
-define our own system calls in `syscalls.c`. For example, the implementation of
-`_write` outputs a byte at a time to the virtual printer peripheral. Many of the
-functions provide minimal implementations that simply fail gracefully due to
-lack of necessary OS support e.g. no file system.
-
-The [RISC-V Instruction Set Manual Volume I: Unprivileged ISA Version 20191213](
-https://content.riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf) states that
-for an `ecall` the "ABI for the system will define how parameters for the
-environment request are passed". This BSP follows the convention used for RISC-V
-in `newlib`. Parameters are passed in registers `a0` to `a5` and system call ID
-in `a7` (`t0` on RV32E). When handling an `ecall`, `handle_ecall` calls
-`handle_syscall` which then calls the appropriate function that implements the
-system call, passing parameters as necessary.
-
-Linker Script
--------------
-
-The linker script defines the memory layout and controls the mapping of input
-sections from object files to output sections in the output binary.
-
-The `link.ld` script is based on the standard upstream RV32 linker script, with
-some changes required for CV32:
-  * Memory layout is defined as follows:
-    * `ram` start=0x0, length=4MB
-    * `dbg` start=0x1A110800, length=2KB
-  * Changes to output section placement are as follows:
-    - `.vectors` start=ORIGIN(`ram`)
-    - `.init` start=0x80
-    - `.heap` starts at end of data and grows upwards
-    - `.stack` starts at the end of `ram` and grows downwards
-    - `.debugger` start=ORIGIN(`dbg`)
-    - `.debugger_exception` start=0x1A110C00
-    - `.debugger_stack` follows `.debugger_exception`
-
-Building and using the BSP Library
-----------------------------------
-
-The BSP can be built in this directory as follows:
-```
-make
-```
-This produces libcv-verif.a which can then be linked with a test program as
-follows:
-
-```
-gcc test-program.c -nostartfiles -T/path/to/bsp/link.ld -L/path/to/bsp/ -lcv-verif
-```
diff --git a/core/example_tb/bsp/crt0.S b/core/example_tb/bsp/crt0.S
deleted file mode 100644
index 302da07ce3..0000000000
--- a/core/example_tb/bsp/crt0.S
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright (c) 2017  SiFive Inc. All rights reserved.
- * Copyright (c) 2019  ETH Zürich and University of Bologna
- * This copyrighted material is made available to anyone wishing to use,
- * modify, copy, or redistribute it subject to the terms and conditions
- * of the FreeBSD License.   This program is distributed in the hope that
- * it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
- * including the implied warranties of MERCHANTABILITY or FITNESS FOR
- * A PARTICULAR PURPOSE.  A copy of this license is available at
- * http://www.opensource.org/licenses.
- */
-/* Make sure the vector table gets linked into the binary.  */
-.global vector_table
-
-/* Entry point for bare metal programs */
-.section .text.start
-.global _start
-.type _start, @function
-
-_start:
-/* initialize global pointer */
-.option push
-.option norelax
-1:	auipc gp, %pcrel_hi(__global_pointer$)
-	addi  gp, gp, %pcrel_lo(1b)
-.option pop
-
-/* initialize stack pointer */
-	la sp, __stack_end
-
-/* set vector table address */
-	la a0, __vector_start
-	ori a0, a0, 1 /*vector mode = vectored */
-	csrw mtvec, a0
-
-/* clear the bss segment */
-	la a0, _edata
-	la a2, _end
-	sub a2, a2, a0
-	li a1, 0
-	call memset
-
-/* new-style constructors and destructors */
-	la a0, __libc_fini_array
-	call atexit
-	call __libc_init_array
-
-/* call main */
-//	lw a0, 0(sp)                    /* a0 = argc */
-//	addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
-//	li a2, 0                        /* a2 = envp = NULL */
-// Initialize these variables to 0. Cannot use argc or argv
-// since the stack is not initialized
-	li a0, 0
-	li a1, 0
-	li a2, 0
-
-	call main
-	tail exit
-
-.size  _start, .-_start
-
-.global _init
-.type   _init, @function
-.global _fini
-.type   _fini, @function
-_init:
-_fini:
- /* These don't have to do anything since we use init_array/fini_array. Prevent
-    missing symbol error */
-	ret
-.size  _init, .-_init
-.size _fini, .-_fini
diff --git a/core/example_tb/bsp/handlers.S b/core/example_tb/bsp/handlers.S
deleted file mode 100644
index 6068105276..0000000000
--- a/core/example_tb/bsp/handlers.S
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
-* Copyright 2019 ETH Zürich and University of Bologna
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*/
-
-/* Exception codes */
-#define EXCEPTION_ILLEGAL_INSN 2
-#define EXCEPTION_BREAKPOINT 3
-#define EXCEPTION_ECALL_M 11
-
-.section .text.handlers
-.global __no_irq_handler
-.global u_sw_irq_handler
-.global m_software_irq_handler
-.global m_timer_irq_handler
-.global m_external_irq_handler
-.global m_fast0_irq_handler
-.global m_fast1_irq_handler
-.global m_fast2_irq_handler
-.global m_fast3_irq_handler
-.global m_fast4_irq_handler
-.global m_fast5_irq_handler
-.global m_fast6_irq_handler
-.global m_fast7_irq_handler
-.global m_fast8_irq_handler
-.global m_fast9_irq_handler
-.global m_fast10_irq_handler
-.global m_fast11_irq_handler
-.global m_fast12_irq_handler
-.global m_fast13_irq_handler
-.global m_fast14_irq_handler
-.global m_fast15_irq_handler
-
-.weak u_sw_irq_handler
-.weak m_software_irq_handler
-.weak m_timer_irq_handler
-.weak m_external_irq_handler
-.weak m_fast0_irq_handler
-.weak m_fast1_irq_handler
-.weak m_fast2_irq_handler
-.weak m_fast3_irq_handler
-.weak m_fast4_irq_handler
-.weak m_fast5_irq_handler
-.weak m_fast6_irq_handler
-.weak m_fast7_irq_handler
-.weak m_fast8_irq_handler
-.weak m_fast9_irq_handler
-.weak m_fast10_irq_handler
-.weak m_fast11_irq_handler
-.weak m_fast12_irq_handler
-.weak m_fast13_irq_handler
-.weak m_fast14_irq_handler
-.weak m_fast15_irq_handler
-
-
-/* exception handling */
-__no_irq_handler:
-	la a0, no_exception_handler_msg
-	jal ra, puts
-	j __no_irq_handler
-
-m_software_irq_handler:
-	j __no_irq_handler
-
-m_timer_irq_handler:
-	j __no_irq_handler
-
-m_external_irq_handler:
-	j __no_irq_handler
-
-m_fast0_irq_handler:
-	j __no_irq_handler
-
-m_fast1_irq_handler:
-	j __no_irq_handler
-
-m_fast2_irq_handler:
-	j __no_irq_handler
-
-m_fast3_irq_handler:
-	j __no_irq_handler
-
-m_fast4_irq_handler:
-	j __no_irq_handler
-
-m_fast5_irq_handler:
-	j __no_irq_handler
-
-m_fast6_irq_handler:
-	j __no_irq_handler
-
-m_fast7_irq_handler:
-	j __no_irq_handler
-
-m_fast8_irq_handler:
-	j __no_irq_handler
-
-m_fast9_irq_handler:
-	j __no_irq_handler
-
-m_fast10_irq_handler:
-	j __no_irq_handler
-
-m_fast11_irq_handler:
-	j __no_irq_handler
-
-m_fast12_irq_handler:
-	j __no_irq_handler
-
-m_fast13_irq_handler:
-	j __no_irq_handler
-
-m_fast14_irq_handler:
-	j __no_irq_handler
-
-m_fast15_irq_handler:
-	j __no_irq_handler
-
-u_sw_irq_handler:
-	/* While we are still using puts in handlers, save all caller saved
-	   regs.  Eventually, some of these saves could be deferred.  */
-	addi sp,sp,-64
-	sw ra, 0(sp)
-	sw a0, 4(sp)
-	sw a1, 8(sp)
-	sw a2, 12(sp)
-	sw a3, 16(sp)
-	sw a4, 20(sp)
-	sw a5, 24(sp)
-	sw a6, 28(sp)
-	sw a7, 32(sp)
-	sw t0, 36(sp)
-	sw t1, 40(sp)
-	sw t2, 44(sp)
-	sw t3, 48(sp)
-	sw t4, 52(sp)
-	sw t5, 56(sp)
-	sw t6, 60(sp)
-	csrr t0, mcause
-	li t1, EXCEPTION_ILLEGAL_INSN
-	beq t0, t1, handle_illegal_insn
-	li t1, EXCEPTION_ECALL_M
-	beq t0, t1, handle_ecall
-	li t1, EXCEPTION_BREAKPOINT
-	beq t0, t1, handle_ebreak
-	j handle_unknown
-
-handle_ecall:
-	jal ra, handle_syscall
-	j end_handler_incr_mepc
-
-handle_ebreak:
-	/* TODO support debug handling requirements.  */
-	la a0, ebreak_msg
-	jal ra, puts
-	j end_handler_incr_mepc
-
-handle_illegal_insn:
-	la a0, illegal_insn_msg
-	jal ra, puts
-	j end_handler_incr_mepc
-
-handle_unknown:
-	la a0, unknown_msg
-	jal ra, puts
-	/* We don't know what interrupt/exception is being handled, so don't
-	   increment mepc.  */
-	j end_handler_ret
-
-end_handler_incr_mepc:
-	csrr t0, mepc
-	lb t1, 0(t0)
-	li a0, 0x3
-	and t1, t1, a0
-	/* Increment mepc by 2 or 4 depending on whether the instruction at mepc
-	   is compressed or not.  */
-	bne t1, a0, end_handler_incr_mepc2
-	addi t0, t0, 2
-end_handler_incr_mepc2:
-	addi t0, t0, 2
-	csrw mepc, t0
-end_handler_ret:
-	lw ra, 0(sp)
-	lw a0, 4(sp)
-	lw a1, 8(sp)
-	lw a2, 12(sp)
-	lw a3, 16(sp)
-	lw a4, 20(sp)
-	lw a5, 24(sp)
-	lw a6, 28(sp)
-	lw a7, 32(sp)
-	lw t0, 36(sp)
-	lw t1, 40(sp)
-	lw t2, 44(sp)
-	lw t3, 48(sp)
-	lw t4, 52(sp)
-	lw t5, 56(sp)
-	lw t6, 60(sp)
-	addi sp,sp,64
-	mret
-
-.section .rodata
-illegal_insn_msg:
-	.string "CV32E40P BSP: illegal instruction exception handler entered\n"
-ecall_msg:
-	.string "CV32E40P BSP: ecall exception handler entered\n"
-ebreak_msg:
-	.string "CV32E40P BSP: ebreak exception handler entered\n"
-unknown_msg:
-	.string "CV32E40P BSP: unknown exception handler entered\n"
-no_exception_handler_msg:
-	.string "CV32E40P BSP: no exception handler installed\n"
diff --git a/core/example_tb/bsp/link.ld b/core/example_tb/bsp/link.ld
deleted file mode 100644
index 9ea197dbf5..0000000000
--- a/core/example_tb/bsp/link.ld
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Script for -z combreloc */
-/* Copyright (C) 2014-2020 Free Software Foundation, Inc.
-   Copyright (C) 2019 ETH Zürich and University of Bologna
-   Copyright (C) 2020 OpenHW Group
-   Copying and distribution of this script, with or without modification,
-   are permitted in any medium without royalty provided the copyright
-   notice and this notice are preserved.  */
-
-/* This linker script is adapted from the default linker script for upstream
-   RISC-V GCC.  It has been modified for use in verification of CORE-V cores.
-*/
-
-OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
-	      "elf32-littleriscv")
-OUTPUT_ARCH(riscv)
-ENTRY(_start)
-
-/* CORE-V */
-MEMORY
-{
-	/* Our testbench is a bit weird in that we initialize the RAM (thus
-	   allowing initialized sections to be placed there). Infact we dump all
-	   sections to ram. */
-
-	ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000
-	dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000
-}
-
-SECTIONS
-{
-  /* CORE-V Debugger Code: This section address must be the same as the
-     DM_HaltAddress parameter in the RTL */
-  .debugger (ORIGIN(dbg)):
-  {
-    KEEP(*(.debugger));
-  } >dbg
-  .debugger_exception (0x1A111000):
-  {
-    KEEP(*(.debugger_exception));
-  } >dbg
-  /* Debugger Stack*/
-  .debugger_stack         : ALIGN(16)
-  {
-   PROVIDE(__debugger_stack_start = .);
-   . = 0x80;
-  } >dbg
-
-  /* CORE-V: we want a fixed entry point */
-  PROVIDE(__boot_address = 0x80);
-
-  /* CORE-V: interrupt vectors */
-  .vectors (ORIGIN(ram)):
-  {
-    PROVIDE(__vector_start = .);
-    KEEP(*(.vectors));
-  } >ram
-
-  /* CORE-V: crt0 init code */
-  .init (__boot_address):
-  {
-    KEEP (*(SORT_NONE(.init)))
-    KEEP (*(.text.start))
-  } >ram
-
-  /* Read-only sections, merged into text segment: */
-  PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS;
-  .interp         : { *(.interp) } >ram
-  .note.gnu.build-id  : { *(.note.gnu.build-id) } >ram
-  .hash           : { *(.hash) } >ram
-  .gnu.hash       : { *(.gnu.hash) } >ram
-  .dynsym         : { *(.dynsym) } >ram
-  .dynstr         : { *(.dynstr) } >ram
-  .gnu.version    : { *(.gnu.version) } >ram
-  .gnu.version_d  : { *(.gnu.version_d) } >ram
-  .gnu.version_r  : { *(.gnu.version_r) } >ram
-  .rela.dyn       :
-    {
-      *(.rela.init)
-      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
-      *(.rela.fini)
-      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
-      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
-      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
-      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
-      *(.rela.ctors)
-      *(.rela.dtors)
-      *(.rela.got)
-      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
-      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
-      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
-      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
-      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
-      PROVIDE_HIDDEN (__rela_iplt_start = .);
-      *(.rela.iplt)
-      PROVIDE_HIDDEN (__rela_iplt_end = .);
-    } >ram
-  .rela.plt       :
-    {
-      *(.rela.plt)
-    } >ram
-
-  .plt            : { *(.plt) }
-  .iplt           : { *(.iplt) }
-  .text           :
-  {
-    *(.text.unlikely .text.*_unlikely .text.unlikely.*)
-    *(.text.exit .text.exit.*)
-    *(.text.startup .text.startup.*)
-    *(.text.hot .text.hot.*)
-    *(SORT(.text.sorted.*))
-    *(.text .stub .text.* .gnu.linkonce.t.*)
-    /* .gnu.warning sections are handled specially by elf.em.  */
-    *(.gnu.warning)
-  } >ram
-  .fini           :
-  {
-    KEEP (*(SORT_NONE(.fini)))
-  } >ram
-  PROVIDE (__etext = .);
-  PROVIDE (_etext = .);
-  PROVIDE (etext = .);
-  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram
-  .rodata1        : { *(.rodata1) } >ram
-  .sdata2         :
-  {
-    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
-  } >ram
-  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram
-  .eh_frame_hdr   : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >ram
-  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram
-  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >ram
-  .gnu_extab   : ONLY_IF_RO { *(.gnu_extab*) } >ram
-  /* These sections are generated by the Sun/Oracle C++ compiler.  */
-  .exception_ranges   : ONLY_IF_RO { *(.exception_ranges*) }
-  /* Adjust the address for the data segment.  We want to adjust up to
-     the same address within the page on the next page up.  */
-  . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
-  /* Exception handling  */
-  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram
-  .gnu_extab      : ONLY_IF_RW { *(.gnu_extab) } >ram
-  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >ram
-  .exception_ranges   : ONLY_IF_RW { *(.exception_ranges*) } >ram
-  /* Thread Local Storage sections  */
-  .tdata	  :
-   {
-     PROVIDE_HIDDEN (__tdata_start = .);
-     *(.tdata .tdata.* .gnu.linkonce.td.*)
-   } >ram
-  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram
-  .preinit_array    :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >ram
-  .init_array    :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
-    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >ram
-  .fini_array    :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
-    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >ram
-  .ctors          :
-  {
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    /* We don't want to include the .ctor section from
-       the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-  } >ram
-  .dtors          :
-  {
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-  } >ram
-  .jcr            : { KEEP (*(.jcr)) }
-  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
-  .dynamic        : { *(.dynamic) }
-  . = DATA_SEGMENT_RELRO_END (0, .);
-  .data           :
-  {
-    __DATA_BEGIN__ = .;
-    *(.data .data.* .gnu.linkonce.d.*)
-    SORT(CONSTRUCTORS)
-  } >ram
-  .data1          : { *(.data1) } >ram
-  .got            : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata          :
-  {
-    __SDATA_BEGIN__ = .;
-    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  } >ram
-  _edata = .; PROVIDE (edata = .);
-  . = .;
-  __bss_start = .;
-  .sbss           :
-  {
-    *(.dynsbss)
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-  } >ram
-  .bss            :
-  {
-   *(.dynbss)
-   *(.bss .bss.* .gnu.linkonce.b.*)
-   *(COMMON)
-   /* Align here to ensure that the .bss section occupies space up to
-      _end.  Align after .bss to ensure correct alignment even if the
-      .bss section disappears because there are no input sections.
-      FIXME: Why do we need it? When there is no .bss section, we do not
-      pad the .data section.  */
-   . = ALIGN(. != 0 ? 32 / 8 : 1);
-  } >ram
-  . = ALIGN(32 / 8);
-  . = SEGMENT_START("ldata-segment", .);
-  . = ALIGN(32 / 8);
-  __bss_end = .;
-    __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
-		            MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800));
-  _end = .; PROVIDE (end = .);
-  . = DATA_SEGMENT_END (.);
-
-  /* Heap grows upward towards end of ram */
-  .heap                    : ALIGN(16)
-  {
-   PROVIDE(__heap_start = .);
-   /* If end of ram is not 16-byte aligned, align to previous 16-byte
-      boundary */
-   PROVIDE(__heap_end = ALIGN(ORIGIN(ram) + LENGTH(ram) - __heap_start - 15, 16));
-   . = __heap_end;
-  } >ram
-
-  /* Stack grows downward from end of ram */
-  .stack (__heap_start)    : ALIGN(16) /* this is a requirement of the ABI(?) */
-  {
-   PROVIDE(__stack_start = __heap_start);
-   . = __heap_end;
-   PROVIDE(__stack_end = .);
-  } >ram
-
-  /* Stabs debugging sections.  */
-  .stab          0 : { *(.stab) }
-  .stabstr       0 : { *(.stabstr) }
-  .stab.excl     0 : { *(.stab.excl) }
-  .stab.exclstr  0 : { *(.stab.exclstr) }
-  .stab.index    0 : { *(.stab.index) }
-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  .comment       0 : { *(.comment) }
-  .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /* DWARF 3 */
-  .debug_pubtypes 0 : { *(.debug_pubtypes) }
-  .debug_ranges   0 : { *(.debug_ranges) }
-  /* DWARF Extension.  */
-  .debug_macro    0 : { *(.debug_macro) }
-  .debug_addr     0 : { *(.debug_addr) }
-  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
-  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
-}
-
diff --git a/core/example_tb/bsp/syscalls.c b/core/example_tb/bsp/syscalls.c
deleted file mode 100644
index 36ffac37da..0000000000
--- a/core/example_tb/bsp/syscalls.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/* An extremely minimalist syscalls.c for newlib
- * Based on riscv newlib libgloss/riscv/sys_*.c
- *
- * Copyright 2019 Claire Wolf
- * Copyright 2019 ETH Zürich and University of Bologna
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <sys/stat.h>
-#include <sys/timeb.h>
-#include <sys/times.h>
-#include <sys/utime.h>
-#include <newlib.h>
-#include <unistd.h>
-#include <errno.h>
-#include <machine/syscall.h>
-#include <assert.h>
-#undef errno
-extern int errno;
-
-/* write to this reg for outputting strings */
-#define STDOUT_REG 0x10000000
-/* write test result of program to this reg */
-#define RESULT_REG 0x20000000
-/* write exit value of program to this reg */
-#define EXIT_REG 0x20000004
-
-#define STDOUT_FILENO 1
-
-/* It turns out that older newlib versions use different symbol names which goes
- * against newlib recommendations. Anyway this is fixed in later version.
- */
-#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5
-#define _sbrk sbrk
-#define _write write
-#define _close close
-#define _lseek lseek
-#define _read read
-#define _fstat fstat
-#define _isatty isatty
-#endif
-/* Upstream newlib now defines this in libgloss/riscv/internal_syscall.h.  */
-long
-__syscall_error(long a0)
-{
-  errno = -a0;
-  return -1;
-}
-
-void unimplemented_syscall()
-{
-  const char *p = "BSP: Unimplemented system call called!\n";
-  while (*p)
-    *(volatile int *)STDOUT_REG = *(p++);
-}
-
-int nanosleep(const struct timespec *rqtp, struct timespec *rmtp)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _access(const char *file, int mode)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _chdir(const char *path)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _chmod(const char *path, mode_t mode)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _chown(const char *path, uid_t owner, gid_t group)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _close(int file)
-{
-  return -1;
-}
-
-int _execve(const char *name, char *const argv[], char *const env[])
-{
-  errno = ENOMEM;
-  return -1;
-}
-
-void _exit(int exit_status)
-{
-  *(volatile int *)EXIT_REG = exit_status;
-  asm volatile("wfi");
-  /* _exit should not return */
-  while (1) {};
-}
-
-int _faccessat(int dirfd, const char *file, int mode, int flags)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _fork(void)
-{
-  errno = EAGAIN;
-  return -1;
-}
-
-int _fstat(int file, struct stat *st)
-{
-  st->st_mode = S_IFCHR;
-  return 0;
-  // errno = -ENOSYS;
-  // return -1;
-}
-
-int _fstatat(int dirfd, const char *file, struct stat *st, int flags)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _ftime(struct timeb *tp)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-char *_getcwd(char *buf, size_t size)
-{
-  errno = -ENOSYS;
-  return NULL;
-}
-
-int _getpid()
-{
-  return 1;
-}
-
-int _gettimeofday(struct timeval *tp, void *tzp)
-{
-  errno = -ENOSYS;
-  return -1;
-}
-
-int _isatty(int file)
-{
-  return (file == STDOUT_FILENO);
-}
-
-int _kill(int pid, int sig)
-{
-  errno = EINVAL;
-  return -1;
-}
-
-int _link(const char *old_name, const char *new_name)
-{
-  errno = EMLINK;
-  return -1;
-}
-
-off_t _lseek(int file, off_t ptr, int dir)
-{
-  return 0;
-}
-
-int _lstat(const char *file, struct stat *st)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _open(const char *name, int flags, int mode)
-{
-  return -1;
-}
-
-int _openat(int dirfd, const char *name, int flags, int mode)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-ssize_t _read(int file, void *ptr, size_t len)
-{
-  return 0;
-}
-
-int _stat(const char *file, struct stat *st)
-{
-  st->st_mode = S_IFCHR;
-  return 0;
-  // errno = ENOSYS;
-  // return -1;
-}
-
-long _sysconf(int name)
-{
-
-  return -1;
-}
-
-clock_t _times(struct tms *buf)
-{
-  return -1;
-}
-
-int _unlink(const char *name)
-{
-  errno = ENOENT;
-  return -1;
-}
-
-int _utime(const char *path, const struct utimbuf *times)
-{
-  errno = ENOSYS;
-  return -1;
-}
-
-int _wait(int *status)
-{
-  errno = ECHILD;
-  return -1;
-}
-
-ssize_t _write(int file, const void *ptr, size_t len)
-{
-  const char *cptr = (char *)ptr;
-  if (file != STDOUT_FILENO)
-    {
-      errno = ENOSYS;
-      return -1;
-    }
-
-  const void *eptr = cptr + len;
-  while (cptr != eptr)
-    *(volatile int *)STDOUT_REG = *cptr++;
-  return len;
-}
-
-extern char __heap_start[];
-extern char __heap_end[];
-static char *brk = __heap_start;
-
-int _brk(void *addr)
-{
-  brk = addr;
-  return 0;
-}
-
-void *_sbrk(ptrdiff_t incr)
-{
-  char *old_brk = brk;
-  register long sp asm("sp");
-
-  char *new_brk = brk += incr;
-  if (new_brk < (char *) sp && new_brk < __heap_end)
-    {
-      brk = new_brk;
-
-      return old_brk;
-    }
-  else
-    {
-      errno = ENOMEM;
-      return (void *) -1;
-    }
-}
-
-void handle_syscall (long a0,
-		     long a1,
-		     long a2,
-		     long a3,
-		     __attribute__((unused)) long a4,
-		     __attribute__((unused)) long a5,
-		     __attribute__((unused)) long a6,
-		     long a7) {
-  #ifdef __riscv_32e
-    register long syscall_id asm("t0");
-  #else
-    long syscall_id = a7;
-  #endif
-
-  switch (syscall_id) {
-    case SYS_exit:
-      _exit (a0);
-      break;
-    case SYS_read:
-      _read (a0, (void *) a1, a2);
-      break;
-    case SYS_write:
-      _write (a0, (const void *) a1, a2);
-      break;
-    case SYS_getpid:
-      _getpid ();
-      break;
-    case SYS_kill:
-      _kill (a0, a1);
-      break;
-    case SYS_open:
-      _open ((const char *) a0, a1, a2);
-      break;
-    case SYS_openat:
-      _openat (a0, (const char *) a1, a2, a3);
-      break;
-    case SYS_close:
-      _close (a0);
-      break;
-    case SYS_lseek:
-      _lseek (a0, a1, a2);
-      break;
-    case SYS_brk:
-      _brk ((void *) a0);
-      break;
-    case SYS_link:
-      _link ((const char *) a0, (const char *) a1);
-      break;
-    case SYS_unlink:
-      _unlink ((const char *) a0);
-      break;
-    case SYS_chdir:
-      _chdir ((const char *) a0);
-      break;
-    case SYS_getcwd:
-      _getcwd ((char *) a0, a1);
-      break;
-    case SYS_stat:
-      _stat ((const char *) a0, (struct stat *) a1);
-      break;
-    case SYS_fstat:
-      _fstat (a0, (struct stat *) a1);
-      break;
-    case SYS_lstat:
-      _lstat ((const char *) a0, (struct stat *) a1);
-      break;
-    case SYS_fstatat:
-      _fstatat (a0, (const char *) a1, (struct stat *) a2, a3);
-      break;
-    case SYS_access:
-      _access ((const char *) a0, a1);
-      break;
-    case SYS_faccessat:
-      _faccessat (a0, (const char *) a1, a2, a3);
-      break;
-    case SYS_gettimeofday:
-      _gettimeofday ((struct timeval *) a0, (void *) a1);
-      break;
-    case SYS_times:
-      _times ((struct tms *) a0);
-      break;
-    default:
-      unimplemented_syscall ();
-      break;
-  }
-}
diff --git a/core/example_tb/bsp/useful_sites.txt b/core/example_tb/bsp/useful_sites.txt
deleted file mode 100644
index c674db240d..0000000000
--- a/core/example_tb/bsp/useful_sites.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Google "RISC-V startup code"
-https://twilco.github.io/riscv-from-scratch/2019/04/27/riscv-from-scratch-2.html
diff --git a/core/example_tb/bsp/vectors.S b/core/example_tb/bsp/vectors.S
deleted file mode 100644
index 08af4128ae..0000000000
--- a/core/example_tb/bsp/vectors.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
-* Copyright 2019 ETH Zürich and University of Bologna
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*/
-
-.section .vectors, "ax"
-.option norvc
-.global vector_table
-
-vector_table:
-	j u_sw_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j m_software_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j m_timer_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j m_external_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j __no_irq_handler
-	j m_fast0_irq_handler
-	j m_fast1_irq_handler
-	j m_fast2_irq_handler
-	j m_fast3_irq_handler
-	j m_fast4_irq_handler
-	j m_fast5_irq_handler
-	j m_fast6_irq_handler
-	j m_fast7_irq_handler
-	j m_fast8_irq_handler
-	j m_fast9_irq_handler
-	j m_fast10_irq_handler
-	j m_fast11_irq_handler
-	j m_fast12_irq_handler
-	j m_fast13_irq_handler
-	j m_fast14_irq_handler
-	j m_fast15_irq_handler
-
diff --git a/core/example_tb/cva6_tb.sv b/core/example_tb/cva6_tb.sv
deleted file mode 100644
index b60d379b0b..0000000000
--- a/core/example_tb/cva6_tb.sv
+++ /dev/null
@@ -1,190 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// Copyright 2021 OpenHW Group
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//    https://solderpad.org/licenses/
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-//
-///////////////////////////////////////////////////////////////////////////////
-//
-// CVA6 "core_only" testbench.
-//
-///////////////////////////////////////////////////////////////////////////////
-
-module cva6_core_only_tb #(
-  parameter int unsigned AXI_USER_WIDTH    = 1,
-  parameter int unsigned AXI_ADDRESS_WIDTH = 64,
-  parameter int unsigned AXI_DATA_WIDTH    = 64,
-  //parameter int unsigned NUM_WORDS         = 2**25,       // memory size
-  parameter int unsigned NUM_WORDS         = 2**10         // memory size
-) (
-  input  logic verilator_clk_i,
-  input  logic verilator_rstn_i,
-  output wire  tb_exit_o
-);
-
-  localparam CLK_REPORT_COUNT  =  100;
-  localparam CLK_TIMEOUT_COUNT = 1000;
-  localparam CLK_PERIOD        =   10;
-  localparam RESET_ASSERT_TIME = 1234;
-
-  reg     r_tb_clk;
-  reg     r_tb_rstn;
-  reg     r_tb_exit;
-  integer clk_cntr;
-
-  wire    tb_clk;
-  wire    tb_rstn;
-
-  //----------------------------------------------------------------------------
-  // Core:
-  //      The AXI REQ and RESP ports are implemented as structs which are
-  //      defined in two packages:
-  //            - package "ariane_axi_soc" defined in tb/ariane_axi_soc_pkg.sv
-  //            - package "axi_pkg"        defined in src/axi/src/axi_pkg.sv
-  //      TODO: extract these package definitions into a single file that is
-  //            completely independ of the RTL.
-  //----------------------------------------------------------------------------
-  ariane_axi_soc::req_t    axi_ariane_req;
-  ariane_axi_soc::resp_t   axi_ariane_resp;
-
-  ariane #(
-    .ArianeCfg  ( ariane_soc::ArianeSocCfg )
-  ) i_cva6 (
-    .clk_i                ( tb_clk                    ),
-    .rst_ni               ( tb_rstn                   ),
-    .boot_addr_i          ( 64'h0000_0000_0001_0000   ), //ariane_soc::ROMBase
-    .hart_id_i            ( 64'h0000_0000_0000_0000   ), //seriously? 2**64 harts?!?
-    .irq_i                ( 2'b00 /*irqs*/            ),
-    .ipi_i                ( 1'b0  /*ipi*/             ),
-    .time_irq_i           ( 1'b0  /*timer_irq*/       ),
-    .debug_req_i          ( 1'b0                      ),
-    .axi_req_o            ( axi_ariane_req            ),
-    .axi_resp_i           ( axi_ariane_resp           )
-  );
-
-  //----------------------------------------------------------------------------
-  // Memory
-  //----------------------------------------------------------------------------
-
-  logic                         req;
-  logic                         we;
-  logic [AXI_ADDRESS_WIDTH-1:0] addr;
-  logic [AXI_DATA_WIDTH/8-1:0]  be;
-  logic [AXI_DATA_WIDTH-1:0]    wdata;
-  logic [AXI_DATA_WIDTH-1:0]    rdata;
-
-  AXI_BUS #(
-    .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH        ),
-    .AXI_DATA_WIDTH ( AXI_DATA_WIDTH           ),
-    .AXI_ID_WIDTH   ( ariane_soc::IdWidthSlave ),
-    .AXI_USER_WIDTH ( AXI_USER_WIDTH           )
-  ) cva6_axi_bus();
-
-  axi_master_connect #(
-  ) i_axi_master_connect_cva6_to_mem (
-    .axi_req_i  (axi_ariane_req),
-    .axi_resp_o (axi_ariane_resp),
-    .master     (cva6_axi_bus)
-  );
-
-  axi2mem #(
-    .AXI_ID_WIDTH   ( ariane_soc::IdWidthSlave ),
-    .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH        ),
-    .AXI_DATA_WIDTH ( AXI_DATA_WIDTH           ),
-    .AXI_USER_WIDTH ( AXI_USER_WIDTH           )
-  ) i_cva6_axi2mem (
-    .clk_i  ( tb_clk       ),
-    .rst_ni ( tb_rstn      ),
-    .slave  ( cva6_axi_bus ),
-    .req_o  ( req          ),
-    .we_o   ( we           ),
-    .addr_o ( addr         ),
-    .be_o   ( be           ),
-    .data_o ( wdata        ),
-    .data_i ( rdata        )
-  );
-
-  cva6_core_tb_sram #(
-    .DATA_WIDTH ( AXI_DATA_WIDTH ),
-    .NUM_WORDS  ( NUM_WORDS      )
-  ) i_cva6_core_tb_sram (
-    .clk_i      ( tb_clk                                                                      ),
-    .rstn_i     ( tb_rstn                                                                     ),
-    .req_i      ( req                                                                         ),
-    .we_i       ( we                                                                          ),
-    .addr_i     ( addr[$clog2(NUM_WORDS)-1+$clog2(AXI_DATA_WIDTH/8):$clog2(AXI_DATA_WIDTH/8)] ),
-    .wdata_i    ( wdata                                                                       ),
-    .be_i       ( be                                                                          ),
-    .rdata_o    ( rdata                                                                       )
-  );
-
-///////////////////////////////////////////////////////////////////////////////
-//
-// Testbench control:
-//   - clock and reset generation
-//   - wavedumping
-//   - simulator init
-//
-///////////////////////////////////////////////////////////////////////////////
-`ifdef VERILATOR
-  // testbench control for Verilator is handled in cva6_tb_verilator.cpp.
-  assign tb_clk    = verilator_clk_i;
-  assign tb_rstn   = verilator_rstn_i;
-  assign tb_exit_o = 0;
-`else  // VERILATOR
-  assign tb_clk    = r_tb_clk;
-  assign tb_rstn   = r_tb_rstn;
-  assign tb_exit_o = r_tb_exit;
-
-  initial begin
-    // units, precision, suffix-string, minimum-field-width)
-    $timeformat(-9, 3, "ns", 5);
-    //$dumpfile("cva6_tb.vcd");
-    //$dumpvars(0, cva6_tb);
-    r_tb_clk    = 0;
-    r_tb_rstn   = 0;
-    r_tb_exit   = 0;
-    fork
-      begin
-        #RESET_ASSERT_TIME;
-        r_tb_rstn = 1;
-        $display("%m @ %0t: Reset de-asserted", $time);
-      end
-      begin
-        #(CLK_PERIOD/2) r_tb_clk = ~r_tb_clk;
-        $display("%m @ %0t: Clock started", $time);
-        forever #(CLK_PERIOD/2) r_tb_clk = ~r_tb_clk;
-      end
-    join
-  end
-`endif // VERILATOR
-
-  always @(posedge tb_clk) begin
-    if (!tb_rstn) begin
-      clk_cntr  <= 0;
-    end
-    else begin
-      clk_cntr++;
-      if (!(clk_cntr%CLK_REPORT_COUNT)) begin
-        $display("%m @ %0t: %0d clocks", $time, clk_cntr);
-      end
-      if (clk_cntr > (CLK_TIMEOUT_COUNT+2)) begin
-        $display("%m @ %0t: FINISHED", $time);
-        $finish;
-      end
-    end
-  end
-
-endmodule
diff --git a/core/example_tb/cva6_tb_verilator.cpp b/core/example_tb/cva6_tb_verilator.cpp
deleted file mode 100644
index b0ebe688a2..0000000000
--- a/core/example_tb/cva6_tb_verilator.cpp
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- *******************************************************************************
- *
- * Copyright 2021 OpenHW Group
- *
- * Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     https://solderpad.org/licenses/
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
- *
- *******************************************************************************
- *
- * Verilator top for the CVA6 "core_only" testbench.
- * Genrates clock, reset and optionally dumps waves.
- *
- *******************************************************************************
- */
-
-#include "svdpi.h"
-//#include "Vcva6_core_only_tb__Dpi.h"
-#include "Vcva6_core_only_tb.h"
-#include "verilated_vcd_c.h"
-#include "verilated.h"
-
-#include <iostream>
-#include <iomanip>
-#include <fstream>
-#include <exception>
-#include <cstdio>
-#include <cstdint>
-#include <cerrno>
-
-double sc_time_stamp();
-
-static vluint64_t t = 0;
-Vcva6_core_only_tb *top;
-
-int main(int argc, char **argv, char **env)
-{
-
-    Verilated::commandArgs(argc, argv);
-    Verilated::traceEverOn(true);
-    top = new Vcva6_core_only_tb();
-
-    //svSetScope(svGetScopeFromName(
-    //    "TOP.tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i.dp_ram_i"));
-    Verilated::scopesDump();
-
-#ifdef VCD_TRACE
-    VerilatedVcdC *tfp = new VerilatedVcdC;
-    top->trace(tfp, 99);
-    tfp->open("verilator_tb.vcd");
-#endif
-    top->verilator_clk_i  = 0;
-    top->verilator_rstn_i = 0;
-
-    top->eval();
-    //dump_memory();
-
-    while (!Verilated::gotFinish()) {
-        if (t > 40)
-            top->verilator_rstn_i = 1;
-        top->verilator_clk_i = !top->verilator_clk_i;
-        top->eval();
-#ifdef VCD_TRACE
-        tfp->dump(t);
-#endif
-        t += 5;
-    }
-#ifdef VCD_TRACE
-    tfp->close();
-#endif
-    delete top;
-    exit(0);
-}
-
-double sc_time_stamp()
-{
-    return t;
-}
diff --git a/core/example_tb/tb_components/cva6_core_tb_sram.sv b/core/example_tb/tb_components/cva6_core_tb_sram.sv
deleted file mode 100644
index 3e21b0a254..0000000000
--- a/core/example_tb/tb_components/cva6_core_tb_sram.sv
+++ /dev/null
@@ -1,180 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-//
-// Copyright 2021 OpenHW Group
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     https://solderpad.org/licenses/
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-//
-////////////////////////////////////////////////////////////////////////////////
-//
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//
-////////////////////////////////////////////////////////////////////////////////
-// Description: Synchronous single-port synchronous memory model for the CVA6
-//              core testbench. Support byte-wise enables.  Size of memory is
-//              $ceil(DATA_WIDTH%64)-by-NUM_WORDS. (which may be overkill)
-//              Author: Mike Thompson, OpenHW Group
-//
-//              Adapted from FPGA wrapper (requires the fpga-support submodule)
-//              and "SyncSpRamBeNx64" originally developed for the Ariane
-//              testharness by:
-//                Florian Zaruba    <zarubaf@iis.ee.ethz.ch>, ETH Zurich
-//                Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
-//                Date: 15.08.2018
-////////////////////////////////////////////////////////////////////////////////
-
-module cva6_core_tb_sram #(
-    parameter DATA_WIDTH  = 64,
-    parameter NUM_WORDS   = 1024,
-    parameter OUT_REGS    = 0    // enables output registers in FPGA macro (read lat = 2)
-)(
-   input  logic                          clk_i,
-   input  logic                          rstn_i,
-   input  logic                          req_i,
-   input  logic                          we_i,
-   input  logic [$clog2(NUM_WORDS)-1:0]  addr_i,
-   input  logic [DATA_WIDTH-1:0]         wdata_i,
-   input  logic [(DATA_WIDTH+7)/8-1:0]   be_i,
-   output logic [DATA_WIDTH-1:0]         rdata_o
-);
-
-localparam DATA_WIDTH_ALIGNED = ((DATA_WIDTH+63)/64)*64;
-localparam BE_WIDTH_ALIGNED   = (((DATA_WIDTH+7)/8+7)/8)*8;
-
-logic [DATA_WIDTH_ALIGNED-1:0]  wdata_aligned;
-logic [BE_WIDTH_ALIGNED-1:0]    be_aligned;
-logic [DATA_WIDTH_ALIGNED-1:0]  rdata_aligned;
-
-// align to 64 bits for inferrable macro below
-always_comb begin : p_align
-    wdata_aligned                    ='0;
-    be_aligned                       ='0;
-    wdata_aligned[DATA_WIDTH-1:0]    = wdata_i;
-    be_aligned[BE_WIDTH_ALIGNED-1:0] = be_i;
-
-    rdata_o = rdata_aligned[DATA_WIDTH-1:0];
-end
-
-  for (genvar k = 0; k<(DATA_WIDTH+63)/64; k++) begin : gen_cut
-      // unused byte-enable segments (8bits) are culled by the tool
-      sync_sram_nx64 #(
-        .ADDR_WIDTH($clog2(NUM_WORDS)),
-        .DATA_DEPTH(NUM_WORDS),
-        .SIM_INIT (4) // 0: no init, 1: zero init, 2: random init, 3: deadbeef init, 4: init from file
-      ) i_ram (
-          .Clk_CI    ( clk_i                     ),
-          .Rst_RBI   ( rstn_i                    ),
-          .CSel_SI   ( req_i                     ),
-          .WrEn_SI   ( we_i                      ),
-          .BEn_SI    ( be_aligned[k*8 +: 8]      ),
-          .WrData_DI ( wdata_aligned[k*64 +: 64] ),
-          .Addr_DI   ( addr_i                    ),
-          .RdData_DO ( rdata_aligned[k*64 +: 64] )
-      );
-  end
-endmodule : cva6_core_tb_sram
-
-
-////////////////////////////////////////////////////////////////////////////////
-// N-word by 64-bit synchronous SRAM model
-////////////////////////////////////////////////////////////////////////////////
-module sync_sram_nx64
-#(
-  parameter ADDR_WIDTH = 10,
-  parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower
-  parameter SIM_INIT   = 0     // for simulation only, will not be synthesized
-                               // 0: no init, 1: zero init, 2: random init, 3: deadbeef init, 4: init from file
-                               // note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
-)(
-  input  logic                  Clk_CI,
-  input  logic                  Rst_RBI,
-  input  logic                  CSel_SI,
-  input  logic                  WrEn_SI,
-  input  logic [7:0]            BEn_SI,
-  input  logic [63:0]           WrData_DI,
-  input  logic [ADDR_WIDTH-1:0] Addr_DI,
-  output logic [63:0]           RdData_DO
-);
-
-  ////////////////////////////
-  // signals, localparams
-  ////////////////////////////
-
-  localparam DATA_BYTES = 8;
-
-  logic [DATA_BYTES*8-1:0] RdData_DN;
-  logic [DATA_BYTES*8-1:0] RdData_DP;
-
-  logic [DATA_BYTES*8-1:0] Mem_DP[DATA_DEPTH-1:0];
-  logic [7:0] Mem_init[0:'hFFFFFF];
-
-  initial begin
-    $readmemh("../Mem_init.txt", Mem_init);
-  end
-
-  assign RdData_DO = RdData_DP;
-  assign RdData_DP = RdData_DN;
-
-  always_ff @(posedge Clk_CI) begin
-    automatic logic [63:0] val;
-    if(Rst_RBI == 1'b0 && SIM_INIT>0) begin
-      for(int k=0; k<DATA_DEPTH;k++) begin
-        // 0: no init, 1: zero init, 2: random init, 3: deadbeef init, 4: init from file
-        if(SIM_INIT==1) val = '0;
-    `ifndef VERILATOR
-        else if(SIM_INIT==2) void'(randomize(val));
-    `endif
-        else if(SIM_INIT==3) val = 64'hdeadbeefdeadbeef;
-        else val = {Mem_init[8*k+7], Mem_init[8*k+6],
-                    Mem_init[8*k+5], Mem_init[8*k+4],
-                    Mem_init[8*k+3], Mem_init[8*k+2],
-                    Mem_init[8*k+1], Mem_init[8*k+0]};
-        Mem_DP[k] = val;
-        //$write("%m @ %0t: Mem_DP[%0d] = %h\n", $time, k, val);
-      end
-    end
-    else begin
-      if(CSel_SI) begin
-        if(WrEn_SI) begin
-          if(BEn_SI[0]) Mem_DP[Addr_DI][ 7: 0] <= WrData_DI[ 7: 0];
-          if(BEn_SI[1]) Mem_DP[Addr_DI][15: 8] <= WrData_DI[15: 8];
-          if(BEn_SI[2]) Mem_DP[Addr_DI][23:16] <= WrData_DI[23:16];
-          if(BEn_SI[3]) Mem_DP[Addr_DI][31:24] <= WrData_DI[31:24];
-          if(BEn_SI[4]) Mem_DP[Addr_DI][39:32] <= WrData_DI[39:32];
-          if(BEn_SI[5]) Mem_DP[Addr_DI][47:40] <= WrData_DI[47:40];
-          if(BEn_SI[6]) Mem_DP[Addr_DI][55:48] <= WrData_DI[55:48];
-          if(BEn_SI[7]) Mem_DP[Addr_DI][63:56] <= WrData_DI[63:56];
-        end
-        RdData_DN <= Mem_DP[Addr_DI];
-      end
-    end
-  end
-
-  ////////////////////////////
-  // assertions
-  ////////////////////////////
-
-  assert property
-    (@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
-    else $error("depth out of bounds");
-
-endmodule : sync_sram_nx64
diff --git a/core/include/ariane_rvfi_pkg.sv b/core/include/ariane_rvfi_pkg.sv
new file mode 100644
index 0000000000..18a2eed073
--- /dev/null
+++ b/core/include/ariane_rvfi_pkg.sv
@@ -0,0 +1,43 @@
+// Copyright 2020 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
+
+package ariane_rvfi_pkg;
+
+  localparam NRET = 1;
+  localparam ILEN = 32;
+
+  typedef struct packed {
+    logic [NRET-1:0]                 valid;
+    logic [NRET*63:0]                order;
+    logic [NRET*ILEN-1:0]            insn;
+    logic [NRET-1:0]                 trap;
+    logic [NRET-1:0]                 halt;
+    logic [NRET-1:0]                 intr;
+    logic [NRET*2-1:0]               mode;
+    logic [NRET*2-1:0]               ixl;
+    logic [NRET*5-1:0]               rs1_addr;
+    logic [NRET*5-1:0]               rs2_addr;
+    logic [NRET*riscv::XLEN-1:0]     rs1_rdata;
+    logic [NRET*riscv::XLEN-1:0]     rs2_rdata;
+    logic [NRET*5-1:0]               rd_addr;
+    logic [NRET*riscv::XLEN-1:0]     rd_wdata;
+
+    logic [NRET*riscv::XLEN-1:0]     pc_rdata;
+    logic [NRET*riscv::XLEN-1:0]     pc_wdata;
+
+    logic [NRET*riscv::XLEN-1:0]     mem_addr;
+    logic [NRET*(riscv::XLEN/8)-1:0] mem_rmask;
+    logic [NRET*(riscv::XLEN/8)-1:0] mem_wmask;
+    logic [NRET*riscv::XLEN-1:0]     mem_rdata;
+    logic [NRET*riscv::XLEN-1:0]     mem_wdata;
+  } rvfi_instr_t;
+
+  typedef rvfi_instr_t [ariane_pkg::NR_COMMIT_PORTS-1:0] rvfi_port_t;
+
+endpackage
diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv
new file mode 100644
index 0000000000..54f7c5c8cd
--- /dev/null
+++ b/core/include/cv32a6_imac_sv0_config_pkg.sv
@@ -0,0 +1,15 @@
+// Copyright 2021 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
+
+
+package cva6_config_pkg;
+
+    localparam CVA6ConfigXlen = 32;
+
+endpackage
diff --git a/core/include/cv64a6_imacfd_sv39_config_pkg.sv b/core/include/cv64a6_imacfd_sv39_config_pkg.sv
new file mode 100644
index 0000000000..2ce3898f33
--- /dev/null
+++ b/core/include/cv64a6_imacfd_sv39_config_pkg.sv
@@ -0,0 +1,15 @@
+// Copyright 2021 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
+
+
+package cva6_config_pkg;
+
+    localparam CVA6ConfigXlen = 64;
+
+endpackage
diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv
index 10ddf80732..50c4ea58e8 100644
--- a/core/include/riscv_pkg.sv
+++ b/core/include/riscv_pkg.sv
@@ -14,8 +14,14 @@
  *
  * Description: Common RISC-V definitions.
  */
+
 package riscv;
 
+    // ----------------------
+    // Import cva6 config from cva6_config_pkg
+    // ----------------------
+    localparam XLEN = cva6_config_pkg::CVA6ConfigXlen;
+
     // ----------------------
     // Data and Address length
     // ----------------------
@@ -28,8 +34,6 @@ package riscv;
        ModeSv64 = 11
     } vm_mode_t;
 
-    localparam XLEN = 64;
-
     // Warning: When using STD_CACHE, configuration must be PLEN=56 and VLEN=64
     // Warning: VLEN must be superior or equal to PLEN
     localparam VLEN       = (XLEN == 32) ? 32 : 64;    // virtual address length
diff --git a/corev_apu/fpga/scripts/run.tcl b/corev_apu/fpga/scripts/run.tcl
index 53162fa438..d2bfc9268f 100644
--- a/corev_apu/fpga/scripts/run.tcl
+++ b/corev_apu/fpga/scripts/run.tcl
@@ -36,24 +36,24 @@ read_ip { \
 }
 # read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci
 
-set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
+set_property include_dirs { "src/axi_sd_bridge/include" "../../common/submodules/common_cells/include" } [current_fileset]
 
 source scripts/add_sources.tcl
 
 set_property top ${project}_xilinx [current_fileset]
 
 if {$::env(BOARD) eq "genesys2"} {
-    read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh}
+    read_verilog -sv {src/genesysii.svh ../../common/submodules/common_cells/include/common_cells/registers.svh}
     set file "src/genesysii.svh"
-    set registers "../src/common_cells/include/common_cells/registers.svh"
+    set registers "../../common/submodules/common_cells/include/common_cells/registers.svh"
 } elseif {$::env(BOARD) eq "kc705"} {
-      read_verilog -sv {src/kc705.svh ../src/common_cells/include/common_cells/registers.svh}
+      read_verilog -sv {src/kc705.svh ../../common/submodules/common_cells/include/common_cells/registers.svh}
       set file "src/kc705.svh"
-      set registers "../src/common_cells/include/common_cells/registers.svh"
+      set registers "../../common/submodules/common_cells/include/common_cells/registers.svh"
 } elseif {$::env(BOARD) eq "vc707"} {
-      read_verilog -sv {src/vc707.svh ../src/common_cells/include/common_cells/registers.svh}
+      read_verilog -sv {src/vc707.svh ../../common/submodules/common_cells/include/common_cells/registers.svh}
       set file "src/vc707.svh"
-      set registers "../src/common_cells/include/common_cells/registers.svh"
+      set registers "../../common/submodules/common_cells/include/common_cells/registers.svh"
 } else {
     exit 1
 }
diff --git a/corev_apu/riscv-dbg b/corev_apu/riscv-dbg
index 6d768ac637..989389b0d0 160000
--- a/corev_apu/riscv-dbg
+++ b/corev_apu/riscv-dbg
@@ -1 +1 @@
-Subproject commit 6d768ac6371356b6e382c01ae7d860dd3e45248b
+Subproject commit 989389b0d03ec19dda96b0eab525ea5b43a9faa9
diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv
index 77206edefe..f77d732375 100644
--- a/corev_apu/tb/ariane_testharness.sv
+++ b/corev_apu/tb/ariane_testharness.sv
@@ -32,6 +32,8 @@ module ariane_testharness #(
   output logic [31:0]                    exit_o
 );
 
+  localparam [7:0] hart_id = '0;
+
   // disable test-enable
   logic        test_en;
   logic        ndmreset;
@@ -678,6 +680,7 @@ module ariane_testharness #(
   // ---------------
   ariane_axi_soc::req_t    axi_ariane_req;
   ariane_axi_soc::resp_t   axi_ariane_resp;
+  rvfi_pkg::rvfi_port_t rvfi;
 
   ariane #(
     .ArianeCfg  ( ariane_soc::ArianeSocCfg )
@@ -685,10 +688,11 @@ module ariane_testharness #(
     .clk_i                ( clk_i               ),
     .rst_ni               ( ndmreset_n          ),
     .boot_addr_i          ( ariane_soc::ROMBase ), // start fetching from ROM
-    .hart_id_i            ( '0                  ),
+    .hart_id_i            ( {56'h0, hart_id}    ),
     .irq_i                ( irqs                ),
     .ipi_i                ( ipi                 ),
     .time_irq_i           ( timer_irq           ),
+    .rvfi_o               ( rvfi                ),
 // Disable Debug when simulating with Spike
 `ifdef SPIKE_TANDEM
     .debug_req_i          ( 1'b0                ),
@@ -722,6 +726,17 @@ module ariane_testharness #(
     end
   end
 
+  rvfi_tracer  #(
+    .SIM_FINISH(2000000),
+    .HART_ID(hart_id),
+    .DEBUG_START(0),
+    .DEBUG_STOP(0)
+  ) rvfi_tracer_i (
+    .clk_i(clk_i),
+    .rst_ni(rst_ni),
+    .rvfi_i(rvfi)
+  );
+
 `ifdef AXI_SVA
   // AXI 4 Assertion IP integration - You will need to get your own copy of this IP if you want
   // to use it
diff --git a/corev_apu/tb/rvfi_pkg.sv b/corev_apu/tb/rvfi_pkg.sv
new file mode 100644
index 0000000000..b42b7eea97
--- /dev/null
+++ b/corev_apu/tb/rvfi_pkg.sv
@@ -0,0 +1,43 @@
+// Copyright 2020 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
+
+package rvfi_pkg;
+
+  localparam NRET = 1;
+  localparam ILEN = 32;
+
+  typedef struct packed {
+    logic [NRET-1:0]                 valid;
+    logic [NRET*63:0]                order;
+    logic [NRET*ILEN-1:0]            insn;
+    logic [NRET-1:0]                 trap;
+    logic [NRET-1:0]                 halt;
+    logic [NRET-1:0]                 intr;
+    logic [NRET*2-1:0]               mode;
+    logic [NRET*2-1:0]               ixl;
+    logic [NRET*5-1:0]               rs1_addr;
+    logic [NRET*5-1:0]               rs2_addr;
+    logic [NRET*riscv::XLEN-1:0]     rs1_rdata;
+    logic [NRET*riscv::XLEN-1:0]     rs2_rdata;
+    logic [NRET*5-1:0]               rd_addr;
+    logic [NRET*riscv::XLEN-1:0]     rd_wdata;
+
+    logic [NRET*riscv::XLEN-1:0]     pc_rdata;
+    logic [NRET*riscv::XLEN-1:0]     pc_wdata;
+
+    logic [NRET*riscv::XLEN-1:0]     mem_addr;
+    logic [NRET*(riscv::XLEN/8)-1:0] mem_rmask;
+    logic [NRET*(riscv::XLEN/8)-1:0] mem_wmask;
+    logic [NRET*riscv::XLEN-1:0]     mem_rdata;
+    logic [NRET*riscv::XLEN-1:0]     mem_wdata;
+  } rvfi_instr_t;
+
+  typedef rvfi_instr_t [ariane_pkg::NR_COMMIT_PORTS-1:0] rvfi_port_t;
+
+endpackage
diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv
new file mode 100644
index 0000000000..656f1a0059
--- /dev/null
+++ b/corev_apu/tb/rvfi_tracer.sv
@@ -0,0 +1,83 @@
+// Copyright 2020 Thales DIS design services SAS
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// You may obtain a copy of the License at https://solderpad.org/licenses/
+//
+// Original Author: Jean-Roch COULON (jean-roch.coulon@invia.fr)
+
+module rvfi_tracer import ariane_pkg::*; #(
+  parameter int unsigned SIM_FINISH  = 1000000,
+  parameter logic [7:0] HART_ID      = '0,
+  parameter int unsigned DEBUG_START = 0,
+  parameter int unsigned DEBUG_STOP  = 0
+)(
+  input logic                           clk_i,
+  input logic                           rst_ni,
+  input rvfi_pkg::rvfi_port_t           rvfi_i
+);
+
+  int f;
+  initial f = $fopen($sformatf("trace_rvfi_hart_%h.dasm", HART_ID), "w");
+  final $fclose(f);
+
+  logic [31:0] cycles;
+  // Generate the trace based on RVFI
+  logic [63:0] pc64;
+  always_ff @(posedge clk_i) begin
+    for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
+      pc64 = {{riscv::XLEN-riscv::VLEN{rvfi_i[i].pc_rdata[riscv::VLEN-1]}}, rvfi_i[i].pc_rdata};
+      // print the instruction information if the instruction is valid or a trap is taken
+      if (rvfi_i[i].valid) begin
+        // Instruction information
+        $fwrite(f, "core   0: 0x%h (0x%h) DASM(%h)\n",
+          pc64, rvfi_i[i].insn, rvfi_i[i].insn);
+        // Destination register information
+        $fwrite(f, "%h 0x%h (0x%h)",
+          rvfi_i[i].mode, pc64, rvfi_i[i].insn);
+        // Decode instruction to know if destination register is FP register
+        if ( rvfi_i[i].insn[6:0] == 7'b1001111 ||
+             rvfi_i[i].insn[6:0] == 7'b1001011 ||
+             rvfi_i[i].insn[6:0] == 7'b1000111 ||
+             rvfi_i[i].insn[6:0] == 7'b1000011 ||
+             rvfi_i[i].insn[6:0] == 7'b0000111 ||
+            (rvfi_i[i].insn[6:0] == 7'b1010011 && rvfi_i[i].insn[31:26] != 6'b111000
+                                               && rvfi_i[i].insn[31:26] != 6'b101000
+                                               && rvfi_i[i].insn[31:26] != 6'b110000) )
+          $fwrite(f, " f%d 0x%h\n",
+            rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
+        else if (rvfi_i[i].rd_addr != 0) begin
+          $fwrite(f, " x%d 0x%h\n",
+            rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
+        end else $fwrite(f, "\n");
+        if (rvfi_i[i].insn == 32'h00000073) begin
+          $finish(1);
+          $finish(1);
+        end
+      end else if (rvfi_i[i].trap)
+        $fwrite(f, "exception : 0x%h\n", pc64);
+    end
+    if (cycles > SIM_FINISH) $finish(1);
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni)
+    if (~rst_ni)
+      cycles <= 0;
+    else
+      cycles <= cycles+1;
+
+  // Trace any custom signals
+  // Define signals to be traced by adding them into debug and name arrays
+  string name[0:10];
+  logic[63:0] debug[0:10], debug_previous[0:10];
+
+  always_ff @(posedge clk_i) begin
+    if (cycles > DEBUG_START && cycles < DEBUG_STOP)
+      for (int index = 0; index < 100; index++)
+        if (debug_previous[index] != debug[index])
+          $fwrite(f, "%d %s %x\n", cycles, name[index], debug[index]);
+    debug_previous <= debug;
+  end
+
+endmodule // rvfi_tracer