main.stanza

; Generated by JITX 3.23.0
#use-added-syntax(jitx)
defpackage main :
  import core
  import jitx
  import jitx/commands
  import ocdb/utils/generic-components
  import jitx/parts

  import helpers
  import jsl/bundles
  import jsl/protocols/usb
  import jsl/si/constraints
  import jsl/si/pairs
  import jsl/si/helpers
  import jsl/si/couplers
  import jsl/symbols/net-symbols


  import jsl/examples/protocols/common/example-board
  import ASM001/common/components

; Define the shape/size of the board
; val board-shape = RoundedRectangle(30.0, 18.5, 0.25)



; Module to run as a design
pcb-module my-design :
  ; define some pins/ports
  port gnd
  port vdd
  port signal

  net GND (gnd)
  net VDD (vdd)
  net SIGNAL (signal)

  ; 1.05v reg 2a/3a/4a
  ; 1.8v reg 2a/3a/4a
  ; 3.3v reg 2a/3a/4a
  ; 3.3v LDO 500mA

  ; inst W25Q32JVSSIQ : database-part(["manufacturer" => "Winbond", "mpn" => "W25Q32JVSSIQ"])
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             

  inst asm2464pdx : ASM001/components/Asmedia/ASM2464PDX/module
  inst usb4_type_c : ASM001/components/TE_2388749-1/device

  require ep1 : usb-superspeed() from asm2464pdx
  require ep2 : usb-superspeed() from usb4_type_c

  val ti-2 = usb-get-trace-impedance(USB2)
  val usb2-constraints = USB-Constraint(proto = USB2, route-struct = diff(ti-2))
  constrain-topology(ep1.data => ep2.data, usb2-constraints)

  val b-cap = block-cap(100.0e-9)

  val ti-3 = usb-get-trace-impedance(USB3)
  val usb3-constraints = USB-Constraint(proto = USB3, route-struct = diff(ti-3))
  val lane-constraint = LaneConstraint(usb3-constraints)
  within [src, dst] = constrain-topology(ep1.lane[0] => ep2.lane[0], lane-constraint):
    ; Here we construct the differential pair topology for the lane.
    ; The Lane consists of two diff-pairs - TX and RX
    topo-net(src.RX => dst.RX)

    ; The TX channel needs a blocking capacitor which we add with
    ;  the help of the `topo-pair` utility. This is like `topo-net`
    ;  but handles extracting the `dual-pair` require from the
    ;  `tx-bcap` for us.
    inst tx-bcap : dp-coupler(b-cap)
    topo-pair(src.TX => tx-bcap => dst.TX)

  inst header : pin-header(2, 1)
  place(header) at loc(0.0, 0.0) on Top

  inst m2_connector : ASM001/components/TE_1-2199230-6/component

  ; Instantiate and connect a 10k resistor component between vdd and signal
  insert-resistor(VDD, SIGNAL, res-query, resistance = 10.0e3)
  ; Instantiate and connect a 100nF capacitor component between vdd and gnd
  insert-capacitor(VDD, GND, cap-query, capacitance = 100.0e-9)

  ; schematic symbols
  symbol(GND) = GND-SYMB
  symbol(VDD) = PWR-SYMB

; Set the :
;     design-name     - a directory with this name will be created in the "designs" directory
;     board           - a Board object representing the stackup, rules and board shape for a particular design
setup-design("jitx-design", board-shape)

; Set the top level module (the module to be compile into a schematic and PCB)
set-main-module(my-design)

; View the results
; take a look at the BOM that was generated
view-bom(BOM-STD)
; examine the schematic that was auto-generated
view-schematic()
; view the board that was created
view-board()