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‎core.json

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,13 @@
22
"core": {
33
"magic": "APF_VER_1",
44
"metadata": {
5-
"platform_ids": [],
6-
"shortname": "template",
7-
"description": "Core template. Displays gray test screen.",
5+
"platform_ids": ["ex_platform"],
6+
"shortname": "Core Template",
7+
"description": "APF core template. Displays gray test screen.",
88
"author": "Developer",
99
"url": "https://github.com/open-fpga/core-template",
10-
"version": "1.0",
11-
"date_release": "2022-06-30"
10+
"version": "1.1.0",
11+
"date_release": "2022-08-23"
1212
},
1313
"framework": {
1414
"target_product": "Analogue Pocket",

‎output/assets/.keep renamed to ‎dist/.gitkeep

File renamed without changes.

‎dist/assets/.keep

Whitespace-only changes.

‎dist/icon.bin

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‎dist/platforms/_images/ex_platform.bin

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‎dist/platforms/ex_platform.json

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
{
2+
"platform": {
3+
"category": "Example Cores",
4+
"name": "Example Platform",
5+
"year": 2022,
6+
"manufacturer": "Example Manufacturer"
7+
}
8+
}

‎info.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
Example Core - Core Template
2+
3+
This is a template for a core containing all of the core definition JSON files and FPGA starter code.

‎output/bitstream.rbf_r

-1.34 KB
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‎src/fpga/ap_core.qsf

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -678,12 +678,12 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[21]
678678
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin31
679679
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin30
680680
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_pin30_pwroff_reset
681-
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_spimosi
682-
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_spimiso
683-
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_1wire
681+
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimosi
682+
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimiso
683+
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_1wire
684684
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_sda
685685
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_scl
686-
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to bridge_spiclk
686+
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spiclk
687687
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_de
688688
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vs
689689
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[0]
@@ -744,5 +744,5 @@ set_global_assignment -name SDC_FILE core/core_constraints.sdc
744744
set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
745745
set_global_assignment -name QIP_FILE core/mf_pllbase.qip
746746
set_global_assignment -name SIP_FILE core/mf_pllbase.sip
747-
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
748-
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
747+
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
748+
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎src/fpga/apf/apf_top.v

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,11 @@
88
// laws, including, but not limited to, U.S. copyright law. All rights are
99
// reserved. By using the APF code you are agreeing to the terms of the End User
1010
// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
11-
// and incorporated herein by reference.
11+
// and incorporated herein by reference. To the extent any use of the APF requires
12+
// application of the MIT License or the GNU General Public License and terms of
13+
// this APF Software License Agreement and EULA are inconsistent with such license,
14+
// the applicable terms of the MIT License or the GNU General Public License, as
15+
// applicable, will prevail.
1216

1317
// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
1418
// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,
@@ -33,7 +37,7 @@
3337
// 6515C - Analogue Pocket main unit
3438
// SOCRATES FPGA
3539
//
36-
// 2022-06-28 Analogue
40+
// 2022-08-17 Analogue
3741

3842
`default_nettype none
3943

‎src/fpga/apf/build_id.mif

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ DATA_RADIX = HEX;
99
CONTENT
1010
BEGIN
1111

12-
0E0 : 20220712;
13-
0E1 : 00223030;
14-
0E2 : 01c3abc0;
12+
0E0 : 20220823;
13+
0E1 : 00024957;
14+
0E2 : b7d9142a;
1515

1616
END;

‎src/fpga/apf/common.v

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,11 @@
88
// laws, including, but not limited to, U.S. copyright law. All rights are
99
// reserved. By using the APF code you are agreeing to the terms of the End User
1010
// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
11-
// and incorporated herein by reference.
11+
// and incorporated herein by reference. To the extent any use of the APF requires
12+
// application of the MIT License or the GNU General Public License and terms of
13+
// this APF Software License Agreement and EULA are inconsistent with such license,
14+
// the applicable terms of the MIT License or the GNU General Public License, as
15+
// applicable, will prevail.
1216

1317
// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
1418
// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,

‎src/fpga/apf/io_bridge_peripheral.v

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,11 @@
88
// laws, including, but not limited to, U.S. copyright law. All rights are
99
// reserved. By using the APF code you are agreeing to the terms of the End User
1010
// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
11-
// and incorporated herein by reference.
11+
// and incorporated herein by reference. To the extent any use of the APF requires
12+
// application of the MIT License or the GNU General Public License and terms of
13+
// this APF Software License Agreement and EULA are inconsistent with such license,
14+
// the applicable terms of the MIT License or the GNU General Public License, as
15+
// applicable, will prevail.
1216

1317
// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
1418
// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,
@@ -73,7 +77,7 @@ input wire phy_spiss
7377
synch_3 s00(reset_n, reset_n_s, clk);
7478

7579
wire endian_little_s;
76-
synch_3 s81(endian_little, endian_little_s, clk);
80+
synch_3 s01(endian_little, endian_little_s, clk);
7781

7882
wire phy_spiss_s, phy_spiss_r, phy_spiss_f;
7983
synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f);
@@ -89,7 +93,6 @@ synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f);
8993
localparam ST_WRITE_0 = 'd6;
9094
localparam ST_WRITE_1 = 'd7;
9195
localparam ST_WRITE_2 = 'd8;
92-
localparam ST_WRITE_3 = 'd9;
9396
localparam ST_ADDR_0 = 'd9;
9497

9598
reg [1:0] addr_cnt;
@@ -99,8 +102,6 @@ synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f);
99102
// synchronize rd byte flag's rising edge into clk
100103
wire rx_byte_done_s, rx_byte_done_r;
101104
synch_3 s03(rx_byte_done, rx_byte_done_s, clk, rx_byte_done_r);
102-
103-
reg bursting;
104105

105106
reg [4:0] spis;
106107
localparam ST_SIDLE = 'd1;
@@ -167,6 +168,7 @@ always @(posedge clk) begin
167168
pmp_addr[ 7: 0] <= {rx_byte_2[7:2], 2'b00};
168169
// address is latched
169170
if( rx_byte_2[0] ) begin
171+
data_cnt <= 0;
170172
state <= ST_WRITE_0;
171173
end else begin
172174
data_cnt <= 0;
@@ -320,7 +322,7 @@ always @(posedge phy_spiclk or posedge phy_spiss) begin
320322
1: begin rx_dat[5:4] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 2; end
321323
2: begin rx_dat[3:2] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 3; end
322324
3: begin
323-
// last bit of the byte
325+
// final 2 bits
324326
rx_byte <= {rx_dat[7:2], phy_spimosi, phy_spimiso};
325327
rx_latch_idx <= 0;
326328
rx_byte_done <= 1;

‎src/fpga/apf/io_pad_controller.v

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,11 @@
88
// laws, including, but not limited to, U.S. copyright law. All rights are
99
// reserved. By using the APF code you are agreeing to the terms of the End User
1010
// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula]
11-
// and incorporated herein by reference.
11+
// and incorporated herein by reference. To the extent any use of the APF requires
12+
// application of the MIT License or the GNU General Public License and terms of
13+
// this APF Software License Agreement and EULA are inconsistent with such license,
14+
// the applicable terms of the MIT License or the GNU General Public License, as
15+
// applicable, will prevail.
1216

1317
// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED
1418
// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO,
@@ -31,7 +35,7 @@
3135
// FULLEST EXTENT PERMITTED BY APPLICABLE LAW.
3236
//
3337
// pad controller
34-
// 2020-08-10 Analogue - started
38+
// 2020-08-17 Analogue
3539
//
3640

3741
module io_pad_controller (
@@ -136,22 +140,22 @@ always @(posedge clk) begin
136140
if(rx_word_done) begin
137141
cnt <= cnt + 1'b1;
138142
case(cnt)
139-
0: cont1_key <= rx_word;
143+
0: cont1_key <= rx_word[15:0];
140144
1: cont1_joy <= rx_word;
141-
2: cont1_trig <= rx_word;
145+
2: cont1_trig <= rx_word[15:0];
142146

143-
3: cont2_key <= rx_word;
147+
3: cont2_key <= rx_word[15:0];
144148
4: cont2_joy <= rx_word;
145-
5: cont2_trig <= rx_word;
149+
5: cont2_trig <= rx_word[15:0];
146150

147-
6: cont3_key <= rx_word;
151+
6: cont3_key <= rx_word[15:0];
148152
7: cont3_joy <= rx_word;
149-
8: cont3_trig <= rx_word;
153+
8: cont3_trig <= rx_word[15:0];
150154

151-
9: cont4_key <= rx_word;
155+
9: cont4_key <= rx_word[15:0];
152156
10: cont4_joy <= rx_word;
153157
11: begin
154-
cont4_trig <= rx_word;
158+
cont4_trig <= rx_word[15:0];
155159
state <= ST_IDLE;
156160
end
157161
endcase

‎src/fpga/core/core_bridge_cmd.v

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,8 @@ input wire [31:0] savestate_addr,
5050
input wire [31:0] savestate_size,
5151
input wire [31:0] savestate_maxloadsize,
5252

53+
output reg osnotify_inmenu,
54+
5355
output reg savestate_start, // core should detect rising edge on this,
5456
input wire savestate_start_ack, // and then assert ack for at least 1 cycle
5557
input wire savestate_start_busy, // assert constantly while in progress after ack
@@ -163,6 +165,7 @@ initial begin
163165
dataslot_allcomplete <= 0;
164166
savestate_start <= 0;
165167
savestate_load <= 0;
168+
osnotify_inmenu <= 0;
166169
status_setup_done_queue <= 0;
167170
end
168171

@@ -297,6 +300,7 @@ always @(posedge clk) begin
297300
end
298301
16'h0080: begin
299302
// Data slot request read
303+
dataslot_allcomplete <= 0;
300304
dataslot_requestread <= 1;
301305
dataslot_requestread_id <= host_20[15:0];
302306
if(dataslot_requestread_ack) begin
@@ -307,6 +311,7 @@ always @(posedge clk) begin
307311
end
308312
16'h0082: begin
309313
// Data slot request write
314+
dataslot_allcomplete <= 0;
310315
dataslot_requestwrite <= 1;
311316
dataslot_requestwrite_id <= host_20[15:0];
312317
if(dataslot_requestwrite_ack) begin
@@ -364,6 +369,11 @@ always @(posedge clk) begin
364369
hstate <= ST_DONE_CODE;
365370
end
366371
end
372+
16'h00B0: begin
373+
// OS Notify: Menu State
374+
osnotify_inmenu <= host_20[0];
375+
hstate <= ST_DONE_OK;
376+
end
367377
default: begin
368378
hstate <= ST_DONE_ERR;
369379
end

‎src/fpga/core/core_top.v

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,15 +258,66 @@ assign port_tran_sck_dir = 1'b0; // clock direction can change
258258
assign port_tran_sd = 1'bz;
259259
assign port_tran_sd_dir = 1'b0; // SD is input and not used
260260

261+
// tie off the rest of the pins we are not using
262+
assign cram0_a = 'h0;
263+
assign cram0_dq = {16{1'bZ}};
264+
assign cram0_clk = 0;
265+
assign cram0_adv_n = 1;
266+
assign cram0_cre = 0;
267+
assign cram0_ce0_n = 1;
268+
assign cram0_ce1_n = 1;
269+
assign cram0_oe_n = 1;
270+
assign cram0_we_n = 1;
271+
assign cram0_ub_n = 1;
272+
assign cram0_lb_n = 1;
273+
274+
assign cram1_a = 'h0;
275+
assign cram1_dq = {16{1'bZ}};
276+
assign cram1_clk = 0;
277+
assign cram1_adv_n = 1;
278+
assign cram1_cre = 0;
279+
assign cram1_ce0_n = 1;
280+
assign cram1_ce1_n = 1;
281+
assign cram1_oe_n = 1;
282+
assign cram1_we_n = 1;
283+
assign cram1_ub_n = 1;
284+
assign cram1_lb_n = 1;
285+
286+
assign dram_a = 'h0;
287+
assign dram_ba = 'h0;
288+
assign dram_dq = {16{1'bZ}};
289+
assign dram_dqm = 'h0;
290+
assign dram_clk = 'h0;
291+
assign dram_cke = 'h0;
292+
assign dram_ras_n = 'h1;
293+
assign dram_cas_n = 'h1;
294+
assign dram_we_n = 'h1;
295+
296+
assign sram_a = 'h0;
297+
assign sram_dq = {16{1'bZ}};
298+
assign sram_oe_n = 1;
299+
assign sram_we_n = 1;
300+
assign sram_ub_n = 1;
301+
assign sram_lb_n = 1;
302+
303+
assign dbg_tx = 1'bZ;
304+
assign user1 = 1'bZ;
305+
assign aux_scl = 1'bZ;
306+
assign vpll_feed = 1'bZ;
307+
261308

262309
// for bridge write data, we just broadcast it to all bus devices
263310
// for bridge read data, we have to mux it
264311
// add your own devices here
265312
always @(*) begin
266313
casex(bridge_addr)
314+
default: begin
315+
bridge_rd_data <= 0;
316+
end
267317
32'h10xxxxxx: begin
268318
// example
269319
// bridge_rd_data <= example_device_data;
320+
bridge_rd_data <= 0;
270321
end
271322
32'hF8xxxxxx: begin
272323
bridge_rd_data <= cmd_bridge_rd_data;
@@ -315,6 +366,8 @@ end
315366
wire savestate_load_busy;
316367
wire savestate_load_ok;
317368
wire savestate_load_err;
369+
370+
wire osnotify_inmenu;
318371

319372
// bridge target commands
320373
// synchronous to clk_74a
@@ -372,6 +425,8 @@ core_bridge_cmd icb (
372425
.savestate_load_ok ( savestate_load_ok ),
373426
.savestate_load_err ( savestate_load_err ),
374427

428+
.osnotify_inmenu ( osnotify_inmenu ),
429+
375430
.datatable_addr ( datatable_addr ),
376431
.datatable_wren ( datatable_wren ),
377432
.datatable_data ( datatable_data ),

‎src/fpga/output_files/ap_core.rbf

-1.75 KB
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‎src/fpga/output_files/ap_core.sof

0 Bytes
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