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epc-aapoepc-aapo
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dts: Add tau device tree
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‎arch/arm/dts/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1182,7 +1182,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mq-pico-pi.dtb \
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imx8mq-kontron-pitx-imx8m.dtb \
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imx8mq-librem5-r4.dtb \
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imx8mn-epc-som-rev2-base-rev3.dtb
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imx8mn-epc-som-rev2-base-rev3.dtb \
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imx8mp-epc-tau-rev1.dtb
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dtb-$(CONFIG_ARCH_IMX9) += \
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imx95-15x15-evk.dtb \

‎arch/arm/dts/imx8mp-epc-tau-rev1-u-boot.dtsi‎

Lines changed: 216 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,216 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019, 2021 NXP
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*/
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#include "imx8mp-sec-def.h"
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#include "imx8mp-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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mcu_rdc {
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compatible = "imx8m,mcu_rdc";
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/* rdc config when MCU starts
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* master
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* SDMA3p --> domain 1
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* SDMA3b --> domian 1
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* SDMA3_SPBA2 --> domian 1
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* peripheral:
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* SAI3 --> Only Domian 1 can access
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* UART4 --> Only Domian 1 can access
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* GPT1 --> Only Domian 1 can access
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* SDMA3 --> Only Domian 1 can access
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* I2C3 --> Only Domian 1 can access
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* memory:
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* TCM --> Only Domian 1 can access (0x7E0000~0x81FFFF)
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* DDR --> Only Domian 1 can access (0x80000000~0x81000000)
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* end.
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*/
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start-config = <
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RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0
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RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0
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RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0
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RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0
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RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
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RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0
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RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0
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RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
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RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0
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RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0
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RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0
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RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS
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RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS
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0x0 0x0 0x0 0x0 0x0
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>;
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/* rdc config when MCU stops
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* memory:
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* TCM --> domain 0/1 can access (0x7E0000~0x81FFFF)
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* DDR --> domain 0/1 can access (0x80000000~0x81000000)
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* end.
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*/
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stop-config = <
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RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS
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RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS
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0x0 0x0 0x0 0x0 0x0
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>;
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};
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};
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&pinctrl_i2c1 {
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bootph-all;
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};
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&pinctrl_i2c1_gpio {
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bootph-all;
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};
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&pinctrl_pmic {
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bootph-all;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
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bootph-all;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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bootph-all;
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};
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&reg_usdhc2_vmmc {
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bootph-pre-ram;
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u-boot,off-on-delay-us = <20000>;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&uart2 {
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bootph-pre-ram;
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};
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&i2c1 {
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bootph-all;
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc2 {
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bootph-pre-ram;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc3 {
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bootph-pre-ram;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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&ethphy0 {
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&flexspi {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&mipi_dsi {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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&media_blk_ctrl {
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assigned-clock-rates = <500000000>, <200000000>;
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};
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&usb_dwc3_0 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};
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&usb_dwc3_1 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};

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