STM32 Spi state as MODM_FLAGS8

Author: TomSaw

src/modm/platform/spi/stm32/spi_base.hpp.in

@@ -139,6 +139,14 @@ public:
 		QuarterFull = SPI_CR2_FRXTH,
 	};
 %% endif
+	enum State : uint8_t {
+		// Word = Bit0,		// 0: Byte (uint8_t) transaction, 1: Word (uint16_t) transaction
+		// AutoIncr = Bit1,	// 0: Always send first data of tx, 1: Send consecutive data of tx
+		Idle = Bit2,		// 1: Transaction is Running
+		LowByte = Bit3,		// 1: Low byte has been transmitted
+		ByteHigh = Bit4,	// 1: High byte of word has been transmitted
+	};
+	MODM_FLAGS8(State);
 };
 
 } // namespace platform

src/modm/platform/spi/stm32/spi_master.cpp.in

@@ -19,7 +19,7 @@
 
 // Bit0: single transfer state
 // Bit1: block transfer state
-uint8_t
+modm::platform::SpiBase::State_t
 modm::platform::SpiMaster{{ id }}::state(0);
 
 std::size_t

src/modm/platform/spi/stm32/spi_master.hpp.in

@@ -39,7 +39,7 @@ namespace platform
  */
 class SpiMaster{{ id }} : public modm::SpiMaster
 {
-	static uint8_t state;
+	static SpiBase::State_t state;
 	static std::size_t index;
 
 	static uint8_t count;
@@ -99,7 +99,7 @@ public:
 
 		// initialize the Spi
 		SpiHal{{ id }}::initialize(prescaler);
-		state = 0;
+		state = SpiBase::State(0);
 	}
 
 	static modm_always_inline void

src/modm/platform/spi/stm32/spi_master_dma_impl.hpp.in

@@ -61,8 +61,8 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transmit(T da
 	// there are only two states encoded into 1 bit (LSB of state):
 	//   1. waiting to start, and
 	//   2. waiting to finish.
-	// LSB != Bit0 ?
-	if ( !(state & Bit0) )
+
+	if (!state.all(SpiBase::LowByte))
 	{
 		// disable DMA for single transfer
 		SpiHal{{ id }}::disableInterrupt(SpiBase::Interrupt::TxDmaEnable |
@@ -76,7 +76,7 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transmit(T da
 		SpiHal{{ id }}::write(data);
 
 		// set LSB = Bit0
-		state |= Bit0;
+		state.set(SpiBase::LowByte);
 	}
 
 	if (!SpiHal{{ id }}::isReceiveRegisterNotEmpty())
@@ -85,7 +85,7 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transmit(T da
 	SpiHal{{ id }}::read(data);
 
 	// transfer finished
-	state &= ~Bit0;
+	state.reset(SpiBase::LowByte);
 	return {modm::rf::Stop, data};
 }
 
@@ -101,12 +101,11 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transmit(cons
 	//   1. initialize index, and
 	//   2. wait for transfer to finish.
 
-	// we are only interested in Bit1
-	switch(state & Bit1)
+	switch(int(state.all(SpiBase::Idle)))
 	{
 	case 0:
 		// we will only visit this state once
-		state |= Bit1;
+		state.set(SpiBase::Idle);
 		dmaError = false;
 
 		SpiHal{{ id }}::enableInterrupt(SpiBase::Interrupt::TxDmaEnable |
@@ -145,8 +144,8 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transmit(cons
 
 		SpiHal{{ id }}::disableInterrupt(SpiBase::Interrupt::TxDmaEnable |
 				SpiBase::Interrupt::RxDmaEnable);
-		// clear the state
-		state &= ~Bit1;
+		
+		state.reset(SpiBase::Idle);
 		return {modm::rf::Stop};
 	}
 }
@@ -164,11 +163,11 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transmit(cons
 	//   2. wait for transfer to finish.
 
 	// we are only interested in Bit1
-	switch(state & Bit1)
+	switch(int(state.all(SpiBase::Idle)))
 	{
 	case 0:
 		// we will only visit this state once
-		state |= Bit1;
+		state.set(SpiBase::Idle);
 		dmaError = false;
 
 		SpiHal{{ id }}::enableInterrupt(SpiBase::Interrupt::TxDmaEnable |
@@ -219,8 +218,8 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transmit(cons
 
 		SpiHal{{ id }}::disableInterrupt(SpiBase::Interrupt::TxDmaEnable |
 				SpiBase::Interrupt::RxDmaEnable);
-		// clear the state
-		state &= ~Bit1;
+		
+		state.reset(SpiBase::Idle);
 		return {modm::rf::Stop};
 	}
 }

src/modm/platform/spi/stm32/spi_master_impl.hpp.in

@@ -28,8 +28,7 @@ modm::platform::SpiMaster{{ id }}::transmit(T data)
 	//   1. waiting to start, and
 	//   2. waiting to finish.
 
-	// LSB != Bit0 ?
-	if ( !(state & Bit0) )
+	if (!state.all(SpiBase::LowByte))
 	{
 		// wait for previous transfer to finish
 		if (!SpiHal{{ id }}::isTransmitRegisterEmpty())
@@ -38,8 +37,7 @@ modm::platform::SpiMaster{{ id }}::transmit(T data)
 		// start transfer by copying data into register
 		SpiHal{{ id }}::write(data);
 
-		// set LSB = Bit0
-		state |= Bit0;
+		state.set(SpiBase::LowByte);
 	}
 
 	if (!SpiHal{{ id }}::isReceiveRegisterNotEmpty())
@@ -48,7 +46,7 @@ modm::platform::SpiMaster{{ id }}::transmit(T data)
 	SpiHal{{ id }}::read(data);
 
 	// transfer finished
-	state &= ~Bit0;
+	state.reset(SpiBase::LowByte);
 	return {modm::rf::Stop, data};
 }
 
@@ -63,11 +61,11 @@ modm::platform::SpiMaster{{ id }}::transmit(const T *tx, const std::size_t repea
 	//   2. wait for transfer to finish.
 
 	// we are only interested in Bit1
-	switch(state & Bit1)
+	switch(int(state.all(SpiBase::Idle)))
 	{
 		case 0:
 			// we will only visit this state once
-			state |= Bit1;
+			state.set(SpiBase::Idle);
 
 			// initialize index and check range
 			index = 0;
@@ -86,8 +84,7 @@ modm::platform::SpiMaster{{ id }}::transmit(const T *tx, const std::size_t repea
 				index++;
 			}
 
-			// clear the state
-			state &= ~Bit1;
+			state.reset(SpiBase::Idle);
 			return {modm::rf::Stop};
 	}
 }
@@ -102,12 +99,11 @@ modm::platform::SpiMaster{{ id }}::transmit(const T * tx, T * rx, const std::siz
 	//   1. initialize index, and
 	//   2. wait for transfer to finish.
 
-	// we are only interested in Bit1
-	switch(state & Bit1)
+	switch(int(state.all(SpiBase::Idle)))
 	{
 		case 0:
 			// we will only visit this state once
-			state |= Bit1;
+			state.set(SpiBase::Idle);
 
 			// initialize index and check range
 			index = 0;
@@ -131,7 +127,7 @@ modm::platform::SpiMaster{{ id }}::transmit(const T * tx, T * rx, const std::siz
 			}
 
 			// clear the state
-			state &= ~Bit1;
+			state.reset(SpiBase::Idle);
 			return {modm::rf::Stop};
 	}
 }