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custom.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Custom chip emulation
*
* Copyright 1995-2002 Bernd Schmidt
* Copyright 1995 Alessandro Bissacco
* Copyright 2000-2025 Toni Wilen
*
* Complete rewrite 2024-2025
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include <ctype.h>
#include <assert.h>
#include <math.h>
#include "options.h"
#include "uae.h"
#include "gensound.h"
#include "audio.h"
#include "sounddep/sound.h"
#include "events.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cia.h"
#include "disk.h"
#include "blitter.h"
#include "xwin.h"
#include "inputdevice.h"
#ifdef SERIAL_PORT
#include "serial.h"
#endif
#include "autoconf.h"
#include "traps.h"
#include "gui.h"
#include "picasso96.h"
#include "drawing.h"
#include "savestate.h"
#include "ar.h"
#include "debug.h"
#include "akiko.h"
#if defined(ENFORCER)
#include "enforcer.h"
#endif
#include "threaddep/thread.h"
#include "luascript.h"
#include "devices.h"
#include "rommgr.h"
#include "specialmonitors.h"
#define VPOSW_DEBUG 0
#define FRAMEWAIT_MIN_MS 2
#define FRAMEWAIT_SPLIT 4
#define CYCLE_CONFLICT_LOGGING 0
#define CUSTOM_DEBUG 0
#define SPRITE_DEBUG 0
#define REFRESH_FIRST_HPOS 3
#define COPPER_CYCLE_POLARITY 1
#define HARDWIRED_DMA_TRIGGER_HPOS 1
#define REF_RAS_ADD_AGA 0x000
#define REF_RAS_ADD_ECS 0x200
#define REF_RAS_ADD_OCS 0x002
#define SPRBORDER 0
#define EXTRAWIDTH_BROADCAST 7
#define EXTRAHEIGHT_BROADCAST_TOP 0
#define EXTRAHEIGHT_BROADCAST_BOTTOM 0
#define EXTRAWIDTH_EXTREME 38
#define EXTRAHEIGHT_EXTREME 28
#define EXTRAWIDTH_ULTRA 77
#define LORES_TO_SHRES_SHIFT 2
#ifdef SERIAL_PORT
extern uae_u16 serper;
#endif
#define MAX_SCANDOUBLED_LINES 1200
struct pipeline_func
{
evfunc2 func;
uae_u16 v;
uae_u16 cck;
};
#define MAX_PIPELINE_REG 3
struct pipeline_reg
{
uae_u16 *p;
uae_u16 v;
};
static uae_u32 displayresetcnt;
uae_u8 agnus_hpos;
int agnus_hpos_prev, agnus_hpos_next, agnus_vpos_next;
static int agnus_pos_change;
static uae_u32 dmal_shifter;
static uae_u16 pipelined_write_addr;
static uae_u16 pipelined_write_value;
static struct rgabuf rga_pipe[RGA_SLOT_TOTAL + 1];
struct denise_rga rga_denise[DENISE_RGA_SLOT_TOTAL];
static struct linestate *current_line_state;
static struct linestate lines[MAX_SCANDOUBLED_LINES][2];
static int rga_denise_cycle, rga_denise_cycle_start, rga_denise_cycle_count;
static int rga_denise_cycle_line = 1;
static struct pipeline_reg preg;
static struct pipeline_func pfunc[MAX_PIPELINE_REG];
static uae_u16 prev_strobe;
static uae_u32 custom_state_flags;
static int not_safe_mode;
static bool dmal_next;
static int fast_lines_cnt;
static uae_u32 scandoubled_bpl_ptr[MAX_SCANDOUBLED_LINES][2][MAX_PLANES];
static bool scandoubled_bpl_ena[MAX_SCANDOUBLED_LINES];
static evt_t blitter_dma_change_cycle, copper_dma_change_cycle, sprite_dma_change_cycle_on, sprite_dma_change_cycle_off;
static void empty_pipeline(void)
{
if (preg.p) {
*preg.p = preg.v;
preg.p = NULL;
}
}
static void push_pipeline(uae_u16 *p, uae_u16 v)
{
if (preg.p) {
// cpu or fast copper can cause this
empty_pipeline();
}
preg.p = p;
preg.v = v;
}
static void pipelined_custom_write(evfunc2 func, uae_u16 v, uae_u16 cck)
{
if (!cck || isrestore()) {
func(v);
return;
}
for (int i = 0 ; i < MAX_PIPELINE_REG; i++) {
struct pipeline_func *p = &pfunc[i];
if (!p->func) {
p->func = func;
p->v = v;
p->cck = cck;
return;
}
}
write_log("pipelined_custom_write overflow!\n");
}
static void handle_pipelined_custom_write(bool now)
{
for (int i = 0 ; i < MAX_PIPELINE_REG; i++) {
struct pipeline_func *p = &pfunc[i];
if (p->func) {
p->cck--;
if (!p->cck || now) {
p->func(p->v);
p->func = NULL;
}
}
}
}
static uae_u32 rga_slot_in_offset, rga_slot_first_offset, rga_slot_out_offset;
static evt_t last_rga_cycle;
static bool drga_written;
static bool fast_mode_ce_not;
static bool drga_bpl, drga_spr;
static int fast_mode_strobe_cnt;
static uae_u8 bpl_line_store[256 * 8];
static void write_drga_strobe(uae_u16 rga)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
r->rga = rga;
r->flags = 0;
r->line = rga_denise_cycle_line;
if (rga == 0x38 || rga == 0x3a || rga == 0x3c) {
if (agnus_hpos != 3 || fast_mode_strobe_cnt != 0) {
fast_mode_ce_not = true;
}
}
if (rga == 0x3e) {
if (agnus_hpos != 5 || fast_mode_strobe_cnt != 1) {
fast_mode_ce_not = true;
}
}
fast_mode_strobe_cnt++;
};
static void write_drga(uae_u16 rga, uaecptr pt, uae_u32 v)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
r->rga = rga;
r->v = v;
r->pt = pt;
r->flags = 0;
r->line = rga_denise_cycle_line;
fast_mode_ce_not = true;
};
static void write_drga_dat_spr(uae_u16 rga, uaecptr pt, uae_u32 v)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
r->rga = rga;
r->v = v;
r->pt = pt;
r->flags = 0;
r->line = rga_denise_cycle_line;
drga_spr = true;
};
static void write_drga_dat_spr_wide(uae_u16 rga, uaecptr pt, uae_u64 v)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
r->rga = rga;
r->v64 = v;
r->pt = pt;
r->flags = 0;
r->line = rga_denise_cycle_line;
drga_spr = true;
};
static uae_u16 *fast_plane_store16[MAX_PLANES];
static uae_u32 *fast_plane_store32[MAX_PLANES];
static uae_u64 *fast_plane_store64[MAX_PLANES];
static void write_drga_dat_bpl16(uae_u16 rga, uaecptr pt, uae_u16 v, int plane)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
r->rga = rga;
r->v = v;
r->pt = pt;
r->flags = 0;
r->line = rga_denise_cycle_line;
if (currprefs.cpu_memory_cycle_exact) {
*fast_plane_store16[plane] = v;
fast_plane_store16[plane]++;
}
drga_bpl = true;
};
static void write_drga_dat_bpl32(uae_u16 rga, uaecptr pt, uae_u32 v, int plane)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
r->rga = rga;
r->v = v;
r->pt = pt;
r->flags = 0;
r->line = rga_denise_cycle_line;
if (currprefs.cpu_memory_cycle_exact) {
*fast_plane_store32[plane] = v;
fast_plane_store32[plane]++;
}
drga_bpl = true;
};
static void write_drga_dat_bpl64(uae_u16 rga, uaecptr pt, uae_u64 v, int plane)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
r->rga = rga;
r->v64 = v;
r->pt = pt;
r->flags = 0;
r->line = rga_denise_cycle_line;
if (currprefs.cpu_memory_cycle_exact) {
*fast_plane_store64[plane] = v;
fast_plane_store64[plane]++;
}
drga_bpl = true;
};
static void write_drga_flag(uae_u32 flags, uae_u32 mask)
{
struct denise_rga *r = &rga_denise[rga_denise_cycle];
if (r->line != rga_denise_cycle_line) {
r->line = rga_denise_cycle_line;
r->rga = 0x1fe;
r->flags = 0;
}
r->flags &= ~mask;
r->flags |= flags;
}
static uae_u32 dummyrgaaddr;
struct rgabuf *write_rga(int slot, int type, uae_u16 v, uae_u32 *p)
{
struct rgabuf *r = &rga_pipe[(slot + rga_slot_first_offset) & 3];
bool strobe = (v >= 0x38 && v < 0x40) || v == 0x1fe;
if (r->reg != 0x1fe && !strobe) {
write_log("RGA conflict: %04x -> %04x, %08x | %08x -> %08x, %04x, %d\n",
r->reg, v,
p ? *p : 0, r->pv, (p ? *p : 0) | r->pv,
v,
slot);
}
// RGA bus address conflict causes AND operation
r->reg &= v;
r->type |= type;
r->alloc = 1;
if (p && r->p) {
// DMA address pointer conflict causes both old and new address to becomes old OR new.
r->conflict = r->p;
*r->p |= *p;
*p = *r->p;
r->pv |= *p;
} else if (p) {
r->p = p;
r->pv = *p;
}
return r;
}
STATIC_INLINE rgabuf *read_rga_out(void)
{
struct rgabuf *r = &rga_pipe[rga_slot_out_offset];
return r;
}
STATIC_INLINE rgabuf *read_rga_in(void)
{
struct rgabuf *r = &rga_pipe[rga_slot_in_offset];
return r;
}
struct rgabuf *read_rga(int slot)
{
struct rgabuf *r = &rga_pipe[(slot + rga_slot_first_offset) & 3];
return r;
}
bool check_rga_free_slot_in(void)
{
struct rgabuf *r = &rga_pipe[rga_slot_in_offset];
return r->alloc <= 0;
}
STATIC_INLINE bool check_rga_out(void)
{
struct rgabuf *r = &rga_pipe[rga_slot_out_offset];
return r->alloc;
}
bool check_rga(int slot)
{
struct rgabuf *r = &rga_pipe[(slot + rga_slot_first_offset) & 3];
return r->alloc;
}
static void clear_rga(struct rgabuf *r)
{
r->reg = 0x1fe;
r->p = NULL;
r->pv = 0;
r->type = 0;
r->alloc = 0;
r->write = false;
r->conflict = NULL;
}
static void shift_rga(void)
{
rga_slot_first_offset--;
rga_slot_in_offset--;
rga_slot_out_offset--;
rga_slot_first_offset &= 3;
rga_slot_in_offset &= 3;
rga_slot_out_offset &= 3;
struct rgabuf *r = &rga_pipe[rga_slot_first_offset];
clear_rga(r);
}
static void uae_abort (const TCHAR *format,...)
{
static int nomore;
va_list parms;
TCHAR buffer[1000];
va_start (parms, format);
_vsntprintf (buffer, sizeof (buffer) / sizeof(TCHAR) - 1, format, parms );
va_end (parms);
if (nomore) {
write_log (_T("%s\n"), buffer);
return;
}
gui_message (buffer);
nomore = 1;
}
static uae_u32 total_skipped = 0;
extern int cpu_last_stop_vpos, cpu_stopped_lines;
static int cpu_sleepmode, cpu_sleepmode_cnt;
extern int vsync_activeheight, vsync_totalheight;
extern float vsync_vblank, vsync_hblank;
/* Events */
evt_t vsync_cycles;
static int extra_cycle;
static int rpt_did_reset;
struct ev eventtab[ev_max];
struct ev2 eventtab2[ev2_max];
int vpos, vpos_prev;
bool lof_store; // real bit in custom registers
bool lof_display; // what display device thinks
static bool lof_detect, lof_pdetect;
static bool lof_detect_vsync;
static bool lol;
static bool linetoggle;
static int next_lineno;
int linear_vpos, linear_hpos, linear_vpos_prev[3], linear_hpos_prev[3];
static int linear_vpos_vsync;
static int linear_display_vpos;
int current_linear_vpos, current_linear_hpos;
static int display_hstart_cyclewait, display_hstart_cyclewait_cnt, display_hstart_cyclewait_end;
static int display_hstart_cyclewait_skip, display_hstart_cyclewait_skip2;
static bool display_hstart_cyclewait_start;
static int agnus_trigger_cck;
static int linear_vpos_changes;
static enum nln_how nextline_how;
static int lof_changed = 0, lof_changing = 0;
static bool prevlofs[3];
static bool vsync_rendered, frame_rendered, frame_shown;
static frame_time_t vsynctimeperline;
static frame_time_t frameskiptime;
static bool genlockhtoggle;
static bool genlockvtoggle;
static bool graphicsbuffer_retry;
static int cia_hsync;
static int nosignal_cnt, nosignal_status;
static bool nosignal_trigger;
static bool syncs_stopped;
int display_reset;
static bool initial_frame;
static int custom_fastmode_exit;
#if 0
static int custom_fastmode_bplextendmask;
#endif
static int plffirstline, plflastline;
/* Stupid genlock-detection prevention hack.
* We should stop calling vsync_handler() and
* hstop_handler() completely but it is not
* worth the trouble..
*/
static int vpos_lpen, hpos_lpen, hhpos_lpen, lightpen_triggered;
int lightpen_x[2], lightpen_y[2];
int lightpen_cx[2], lightpen_cy[2], lightpen_active, lightpen_enabled, lightpen_enabled2;
/*
* Hardware registers of all sorts.
*/
static uae_u16 cregs[256];
uae_u16 intena, intreq;
static uae_u16 intena2, intreq2;
uae_u16 dmacon;
static uae_u16 dmacon_next;
uae_u16 adkcon; /* used by audio code */
uae_u16 last_custom_value;
static bool dmacon_bpl;
static uae_u32 cop1lc, cop2lc, copcon;
/*
* Horizontal hardwired defaults
*
* 0x00 0 HC0 (genlock handling)
* 0x01 1 HC1 (START), (VSY serration pulse start)
* 0x09 9 VR1 (LOF=0 -> VE start, LOF=1 -> VE stop)
* 0x12 18 SHS ([HSSTRT] horizontal sync start), (VSY serration pulse end)
* 0x1a 26 VER1_P (HSY end of equalization pulse in PAL)
* 0x1b 27 VER1_N (HSY end of equalization pulse in NTSC)
* 0x23 35 RHS ([HSSTOP] horizontal sync end)
* 0x73 115 VR2 (LOF=1 -> VE start, LOF=0 -> VE stop), (VSY serration pulse start)
* 0x84 132 CEN ([HCENTER]), (VSY serration pulse end)
* 0x8c 140 VER2_P (CEN end of equalization pulse in PAL)
* 0x8d 141 VER2_N (CEN end of equalization pulse in NTSC)
* 0xe2 226 HC226 (LOL=0, [HTOTAL] PAL line, NTSC short line)
* 0xe3 227 HC227 (LOL=1, NTSC long line)
*
* Vertical hardwired defaults
*
* 0 SVB (start for Vertical Equalization zone)
* 2 VC2 (PAL/CEN/LOF=0 -> enable Vertical Sync zone)
* 3 VC3 (NTSC + PAL/SHS/LOF=1 enable Vertical Sync zone)
* 5 VC5 (PAL/SHS/LOF=0 + PAL/CEN/LOF=1 -> disable Vertical Sync zone)
* 6 VC6 (NTSC disable Vertical Sync zone)
* 7 VC7 (PAL LOF=0 stop for Vertical Equalization zone)
* 8 VC8 (PAL LOF=1 stop for Vertical Equalization zone)
* 9 VC9 (NTSC stop for Vertical Equalization zone)
* 20 RVB_N ([VBSTOP] NTSC)
* 25 RVB_P ([VBSTOP] PAL)
* 261 VC261 ([VBSTRT][VTOTAL] LOF=0, NTSC short frame)
* 262 VC262 ([VBSTRT] LOF=1, NTSC long frame)
* 311 VC311 ([VBSTRT][VTOTAL] LOF=0, PAL short frame)
* 312 VC312 ([VBSTRT] LOF=1, PAL long frame)
*/
/*
* Odd field:
*
* PAL
*
* HSYNC SHS to RHS
* VSYNC VC2/CEN to VC5/SHS
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC312 + HC1 to RVB + HC1
* Vertical equalization = SVB + VR1 to VC7 + VR2
*
* Even field:
*
* HSYNC SHS to RHS
* VSYNC VC3/SHS to VC5/CEN
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC311 + HC1 to RVB + HC1
* Vertical equalization start = SVB + VR2 to VC8 + VR1
*
*
* NTSC
*
* Odd field:
*
* HSYNC SHS to RHS
* VSYNC VC3/SHS to VC6/SHS
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC262/HC1 to RVB/HC1
* Vertical equalization = SVB/VR1 to VC9/VR1
*
* Even field:
*
* HSYNC SHS to RHS
* VSYNC VC3/CEN to VC6/CEN
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC261/HC1 to RVB/HC1
* Vertical equalization = SVB/VR2 to VC9/VR2
*
*/
/*
* Bitplane DMA enable logic OCS/ECS differences:
*
* OCS: DDFSTRT hard start limit flag is disabled when horizontal hard start position matches.
* It is enabled during active bitplane DMA's last cycle. (Ending due to either DDFSTOP or hardstop match).
* ECS: DDFTSTR/STOP hard limit work as documented.
* It is cleared when hard start matches and set when hard stop matches.
*
* OCS hard start limit bug: if line didn't have BPL DMA active, next line's BPL DMA can start earlier than start limit.
* (See music disk Ode to Ramon by Digital Force, bottom scroller "scanline affect" )
* This feature also prevents multiple DDFSTRT/STOP regions in same scanline. ECS/AGA does not have this limit.
*
* DDFSTRT match is ignored if DMACON BPLEN is not enabled. ECS/AGA allows it. Does not affect DDFSTOP.
* Switch DMACON BPLEN off, wait value to DDFSTRT that matches during current scanline,
* switch BPLEN on: if OCS, bitplane DMA won't start, ECS/AGA: bitplane DMA starts.
*
*/
static bool agnus_phsync, agnus_phblank;
static uae_u32 agnus_phblank_start, agnus_phblank_end, agnus_phsync_start, agnus_phsync_end, agnus_hsync_start, agnus_hsync_end;
static bool agnus_pvsync, agnus_pcsync, agnus_csync;
static int agnus_vb, agnus_pvb;
static bool agnus_vb_active;
static bool agnus_vb_start_line, agnus_pvb_start_line, agnus_vb_active_start_line;
static bool agnus_vb_end_line, agnus_pvb_end_line, agnus_vb_active_end_line;
static bool agnus_equzone;
static bool agnus_hsync, agnus_vsync, agnus_ve, agnus_p_ve;
static bool agnus_bsvb, agnus_bsvb_prev;
static bool agnus_equdis;
int maxhpos = MAXHPOS_PAL;
static int maxhpos_long;
int maxhpos_short = MAXHPOS_PAL;
int maxvpos = MAXVPOS_PAL;
int maxvpos_nom = MAXVPOS_PAL; // nominal value (same as maxvpos but "faked" maxvpos in fake 60hz modes)
static int maxvpos_long;
int maxvpos_display = MAXVPOS_PAL; // value used for display size
int maxhpos_display = AMIGA_WIDTH_MAX;
int maxvsize_display = AMIGA_HEIGHT_MAX;
int maxvpos_display_vsync;
int vsync_startline;
static bool maxvpos_display_vsync_next;
static int maxhposm1;
int maxhposm0 = MAXHPOS_PAL;
static bool maxhposeven;
static int hsyncendpos, hsyncstartpos;
int hsync_end_left_border, hdisplay_left_border;
static int hsyncstartpos_start, hsyncstartpos_start_cycles;
static int hsyncstartpos_start_hw;
int hsyncstartpos_hw;
int hsyncendpos_hw;
int denisehtotal;
static int maxvpos_total = 511;
int minfirstline = VBLANK_ENDLINE_PAL;
int minfirstline_linear = VBLANK_ENDLINE_PAL;
float vblank_hz = VBLANK_HZ_PAL, fake_vblank_hz, vblank_hz_stored, vblank_hz_nom;
float hblank_hz;
static float vblank_hz_lof, vblank_hz_shf, vblank_hz_lace;
static int vblank_hz_mult, vblank_hz_state;
static struct chipset_refresh *stored_chipset_refresh;
int doublescan;
int programmedmode;
frame_time_t syncbase;
static int fmode_saved, fmode;
uae_u16 beamcon0, new_beamcon0;
static bool beamcon0_dual, beamcon0_pal;
uae_u16 bemcon0_hsync_mask, bemcon0_vsync_mask;
bool beamcon0_has_hsync, beamcon0_has_vsync, beamcon0_has_csync;
static uae_u16 beamcon0_saved;
static uae_u16 bplcon0_saved, bplcon1_saved, bplcon2_saved;
static uae_u16 bplcon3_saved, bplcon4_saved;
static uae_u16 ddfstrt_saved, ddfstop_saved, diwhigh_saved;
static uae_u32 saved_color_regs_aga[32];
static struct color_entry agnus_colors;
static int varsync_changed, varsync_maybe_changed[2];
static bool programmed_register_accessed_v, programmed_register_accessed_h;
static bool need_vdiw_check;
static int varhblank_lines, varhblank_val[2];
static int exthblank_lines[2];
static uae_u16 vt_old, ht_old, hs_old, vs_old;
uae_u16 vtotal, htotal;
static int maxvpos_stored, maxhpos_stored;
uae_u16 hsstop, hsstrt;
uae_u16 hbstop, hbstrt;
static int hbstop_cck, hbstrt_cck;
static int hsstop_detect, hsstop_detect2;
static uae_u16 vsstop, vsstrt;
static uae_u16 vbstop, vbstrt;
static uae_u16 hcenter;
static uae_u16 hsstrt_v2, hsstop_v2;
static bool ocs_blanked;
static uae_u16 sprhstrt, sprhstop, bplhstrt, bplhstop, hhpos;
static bool uhres_spr, uhres_bpl;
static int uhres_state;
static uae_u16 sprhstrt_v, sprhstop_v, bplhstrt_v, bplhstop_v;
static uaecptr hhbpl, hhspr;
static uae_s16 bplhmod;
static int ciavsyncmode;
static int diw_hstrt, diw_hstop;
static uae_u32 ref_ras_add;
static uaecptr refptr, refptr_p;
static uae_u32 refmask;
static int line_disabled;
static bool custom_disabled;
static int display_hstart_fastmode;
#define HSYNCTIME (maxhpos * CYCLE_UNIT)
struct sprite {
uaecptr pt;
int vstart;
int vstop;
bool dblscan; /* AGA SSCAN2 */
int dmastate;
int dmacycle;
uae_u16 ctl, pos;
};
static struct sprite spr[MAX_SPRITES];
static int plfstrt_sprite;
uaecptr sprite_0;
int sprite_0_width, sprite_0_height, sprite_0_doubled;
uae_u32 sprite_0_colors[4];
static uae_u8 magic_sprite_mask = 0xff;
static int sprite_width;
static int sprite_sprctlmask;
int sprite_buffer_res;
static uae_s16 bpl1mod, bpl2mod;
static uaecptr bplpt[MAX_PLANES];
static uaecptr bplptx[MAX_PLANES];
uae_u16 bplcon0;
static uae_u16 bplcon1, bplcon2, bplcon3, bplcon4;
static uae_u32 bplcon0_res, bplcon0_planes, bplcon0_planes_limit;
static int diwstrt, diwstop, diwhigh;
static int diwhigh_written;
static uae_u16 ddfstrt, ddfstop, ddf_mask;
static int diw_change;
/* The display and data fetch windows */
enum class diw_states
{
DIW_waiting_start, DIW_waiting_stop
};
int plffirstline_total, plflastline_total;
static int autoscale_bordercolors;
static int first_bpl_vpos;
static int last_decide_line_hpos;
static int last_fetch_hpos, last_decide_sprite_hpos;
static int diwfirstword, diwlastword;
static int last_diwlastword;
static int hb_last_diwlastword;
static int last_hdiw;
static diw_states vdiwstate, hdiwstate;
static int hdiwbplstart;
static int bpl_hstart;
static bool exthblank;
static int hsyncdebug;
int first_planes_vpos, last_planes_vpos;
static int first_bplcon0, first_bplcon0_old;
static int first_planes_vpos_old, last_planes_vpos_old;
int diwfirstword_total, diwlastword_total;
int ddffirstword_total, ddflastword_total;
static int diwfirstword_total_old, diwlastword_total_old;
static int ddffirstword_total_old, ddflastword_total_old;
bool vertical_changed, horizontal_changed;
int firstword_bplcon1;
static int copper_access;
uae_u16 clxdat;
static uae_u16 clxcon, clxcon2;
enum copper_states {
COP_stop,
COP_waitforever,
COP_read1,
COP_read2,
COP_bltwait,
COP_bltwait2,
COP_wait_in2,
COP_skip_in2,
COP_wait1,
COP_wait,
COP_skip,
COP_skip1,
COP_strobe_vbl_delay,
COP_strobe_vbl_delay2,
COP_strobe_vbl_delay_nodma,
COP_strobe_vbl_extra_delay1,
COP_strobe_vbl_extra_delay2,
COP_strobe_vbl_extra_delay3,
COP_strobe_delay_start,
COP_strobe_delay_start_odd,
COP_strobe_delay1,
COP_strobe_delay1_odd,
COP_strobe_delay2,
COP_strobe_extra // just to skip current cycle when CPU wrote to COPJMP
};
struct copper {
/* The current instruction words. */
uae_u16 ir[2];
enum copper_states state, state_prev;
/* Instruction pointer. */
uaecptr ip;
uaecptr strobeip;
// following move does not enable COPRS
int ignore_next;
int vcmp, hcmp;
int strobe; /* COPJMP1 / COPJMP2 accessed */
int strobetype;
enum copper_states strobe_next;
int moveaddr, movedata, movedelay;
uaecptr moveptr;
uaecptr vblankip;
evt_t strobe_cycles;
};
static struct copper cop_state;
static int copper_enabled_thisline;
/*
* Statistics
*/
uae_u32 timeframes;
evt_t frametime;
frame_time_t lastframetime;
uae_u32 hsync_counter, vsync_counter;
frame_time_t idletime;
int bogusframe;
static int display_vsync_counter, display_hsync_counter;
static evt_t display_last_hsync, display_last_vsync;
static int fetch_cycle;
static bool ddf_limit, ddfstrt_match, hwi_old;
static int ddf_stopping, ddf_enable_on;
static int bprun;
static evt_t bprun_end;
static int bprun_cycle;
static bool harddis_v, harddis_h;
struct custom_store custom_storage[256];
static uae_u16 dmal;
static int REGPARAM3 custom_wput_1(uaecptr, uae_u32, int) REGPARAM;
/*
* helper functions
*/
static bool safecpu(void)
{
return currprefs.cpu_model == 68000 && currprefs.cpu_cycle_exact && currprefs.blitter_cycle_exact && currprefs.m68k_speed == 0 && !(currprefs.cs_hacks & 16);
}
static void check_nocustom(void)
{
struct amigadisplay* ad = &adisplays[0];
if (ad->picasso_on && currprefs.picasso96_nocustom) {
custom_disabled = true;
line_disabled |= 2;
} else {
custom_disabled = false;
line_disabled &= ~2;
}
}
STATIC_INLINE bool nodraw(void)
{
struct amigadisplay *ad = &adisplays[0];
bool nd = !currprefs.cpu_memory_cycle_exact && ad->framecnt != 0;
return nd;
}
static bool doflickerfix_possible(void)
{
return currprefs.gfx_vresolution && doublescan < 0 && vpos < MAXVPOS;
}
static bool doflickerfix_active(void)
{
return interlace_seen > 0 && doflickerfix_possible();
}
uae_u32 get_copper_address(int copno)
{
switch (copno) {
case 1: return cop1lc;
case 2: return cop2lc;
case 3: return cop_state.vblankip;
case -1: return cop_state.ip;
default: return 0;
}
}
void reset_frame_rate_hack(void)
{
if (currprefs.m68k_speed >= 0) {
return;
}
rpt_did_reset = 1;
events_reset_syncline();
vsyncmintime = read_processor_time() + vsynctimebase;
write_log(_T("Resetting frame rate hack\n"));
}
static void setclr(uae_u16 *p, uae_u16 val)
{
if (val & 0x8000) {
*p |= val & 0x7FFF;
} else {
*p &= ~val;
}
}
STATIC_INLINE bool is_last_line(void)
{
return vpos + 1 == maxvpos + lof_store;
}
STATIC_INLINE uae_u8 *pfield_xlateptr(uaecptr plpt, int bytecount)
{
if (!chipmem_check_indirect(plpt, bytecount)) {
static int count = 0;
if (!count) {
count++;
write_log(_T("Warning: Bad playfield pointer %08x\n"), plpt);
}
return NULL;
}
return chipmem_xlate_indirect(plpt);
}
static void docols(struct color_entry *colentry)
{
#ifdef AGA
if (aga_mode) {
for (int i = 0; i < 256; i++) {
int v = color_reg_get(colentry, i);
colentry->acolors[i] = getxcolor(v);
}
} else {
#endif
for (int i = 0; i < 32; i++) {
int v = color_reg_get(colentry, i);
colentry->acolors[i] = getxcolor(v);
}
#ifdef AGA
}
#endif
}
#define HW_HPOS_TABLE_MAX 142
static bool hw_hpos_table[HW_HPOS_TABLE_MAX];
static uae_u8 prg_hpos_table[256];
static void updateprghpostable(void)
{
memset(prg_hpos_table, 0, sizeof prg_hpos_table);
prg_hpos_table[hsstrt & 0xff] |= 1;
prg_hpos_table[hsstop & 0xff] |= 2;
prg_hpos_table[hbstrt & 0xff] |= 4;
prg_hpos_table[hbstop & 0xff] |= 8;
prg_hpos_table[hcenter & 0xff] |= 16;
}
static void updatehwhpostable(void)
{
int isntsc = (beamcon0 & BEAMCON0_PAL) ? 0 : 1;
hw_hpos_table[26] = false;
hw_hpos_table[27] = false;
hw_hpos_table[140] = false;
hw_hpos_table[141] = false;
if (isntsc) {
hw_hpos_table[27] = true;
hw_hpos_table[141] = true;
} else {
hw_hpos_table[26] = true;
hw_hpos_table[140] = true;
}
}
/* The fetch unit mainly controls ddf stop. It's the number of cycles that
are contained in an indivisible block during which ddf is active. E.g.
if DDF starts at 0x30, and fetchunit is 8, then possible DDF stops are
0x30 + n * 8. */
static uae_u32 fetchunit, fetchunit_mask;
/* The delay before fetching the same bitplane again. Can be larger than
the number of bitplanes; in that case there are additional empty cycles
with no data fetch (this happens for high fetchmodes and low
resolutions). */
static uae_u32 fetchstart, fetchstart_shift, fetchstart_mask;
/* fm_maxplane holds the maximum number of planes possible with the current
fetch mode. This selects the cycle diagram:
8 planes: 73516240
4 planes: 3120
2 planes: 10. */
static uae_u32 fm_maxplane, fm_maxplane_shift;
/* The corresponding values, by fetchmode and display resolution. */
static const uae_u8 fetchunits[] = { 8,8,8,0, 16,8,8,0, 32,16,8,0 };
static const uae_u8 fetchstarts[] = { 3,2,1,0, 4,3,2,0, 5,4,3,0 };
static const uae_u8 fm_maxplanes[] = { 3,2,1,0, 3,3,2,0, 3,3,3,0 };
static uae_s8 cycle_diagram_table[3][3][9][32];
static uae_s8 cycle_diagram_free_cycles[3][3][9];
static uae_s8 cycle_diagram_total_cycles[3][3][9];
static uae_s8 *curr_diagram;
static const uae_s8 cycle_sequences[3 * 8] = { 2,1,2,1,2,1,2,1, 4,2,3,1,4,2,3,1, 8,4,6,2,7,3,5,1 };
static int fetchmode, fetchmode_size, fetchmode_mask, fetchmode_bytes;
static int fetchmode_fmode_bpl, fetchmode_fmode_spr;
static int real_bitplane_number[3][3][9];
/* Disable bitplane DMA if planes > available DMA slots. This is needed
e.g. by the Sanity WOC demo (at the "Party Effect"). */
STATIC_INLINE int GET_PLANES_LIMIT(uae_u16 bc0)
{
int res = GET_RES_AGNUS(bc0);
int planes = GET_PLANES(bc0);
return real_bitplane_number[fetchmode][res][planes];
}
static void debug_cycle_diagram(void)
{
int fm, res, planes, cycle, v;
TCHAR aa;
for (fm = 0; fm <= 2; fm++) {
write_log(_T("FMODE %d\n=======\n"), fm);
for (res = 0; res <= 2; res++) {