Installation instructions for the SNS-CPU-RGB-01 board

[ttoffalori]

Hi,

what installation guide can I use for the SNS-CPU-RGB-01?
I checked the existing SNS guides, but they all look a bit different to my board.
Do you have a guide for this or can you assist me?

Thank you.

[marqs85]

It is supposed to be close to SNS-CPU-GPM boards so I'd check SNS-CPU-GPM-02 instructions to see if

• R4, R5 are in the output of oscillator circuit (U9 etc.)
• R25 is between CSYNC driver and multi-AV pin 3

[ttoffalori]

Hi marqs85, thank you very much for the fast response.

I am very sorry, but I do not understand what you mean. I checked the GPM-02 instructions, but to me it looks completely different.

Here is an image of my board and I highlighted the R4, R5 and R25. Do I still have to remove them?

[marqs85]

Part codes probably match even though part placement is somewhat different, but to be sure you should check with a multimeter against this schematic (see my questions above).

[ttoffalori]

Your answer is highly appreciated. Unfortunately I am not skilled enough to answer this questions myself.
Is there any chance we can solve this together?

Then I could test and write a guide for this model number and add it to your instructions for other people.

[marqs85]

I can only give instructions what to check, but for you'd need to test continuities with a multimeter. If the component numbers are match between revisions, you should see continuity between either end of of R4 and R5 and cartridge connector pin 1. Similarly there should be continuity between either end of R25 and multi-out pin 3.

[ttoffalori]

OK that one I can check.
Might be a stupid question for you, but which pin exactly is the R25? :D
And does it matter if I check the right or the left part of the pin?

Thank you.

[marqs85]

R25 refers to the component. It has 2 pins of which another one is most likely connected to multi-out pin 3. The point here is to check which one (or if neither) is.

[ttoffalori]

Thanks marqs. I will try this next weekend.

[toffalori]

Thanks marqs. I will try this next weekend.

Update: Unfortunately I faced some other issues with my SNES, thats why I decided to not install this mod anymore.

From my side this issue can be closed.
Thanks again for all your help.

[davedoc1984]

Hi, I have one of these boards and have noticed the same issue in that the components look the same as SNS-CPU-APU-01.

I have installed the board as per those instructions but I am still getting the "Jitter" with the OSSC. It works fine with my Framemeister.

To answer the questions above that marqs asked of the OP:

R25 on this board does not have continuity to Pin 3 of the Multi-Out. R14 Does.

Also R4 and R5 on this board does not have continuity to Pin 1 of the Cartridge slot. R12 Does which I have removed as per the SNS-CPU-APU-01 instructions.

[marqs85]

Ok, so the board should not have differences compared to SNS-CPU-APU-01 in this context. Are you sure it's the jitter issue which causes OSSC not to sync with your TV? Do have any game using 480i (which natively does not have jitter) to see if this is the case? Also, which OSSC firmware version are you using?

[davedoc1984]

Hi Marqs :)

OSSC Firmware 1.11a. I actually have 2 of your awesome OSSC's and they both exhibit the same issue where the screen will blank out for a few seconds and then come back and then blank out again.

None of my other Consoles exhibit this issue with the OSSC. I have a Japanese MegaDrive which is Solid and never drops out and I have used my PS1 consoles with it.

I do have an FXPakPro and even just on the Menu Screen it will blank out. However, when I use this same Super Famicom, Same CSYNC RGB Scart cable with my Framemeister, I get no such issues.

[marqs85]

It's worth trying out setting "ADC PLL BW" to Medium under sync opt (possibly with also "FPGA PLL BW" set to low). These options were recently added but the default value has reduced compatibility in some setups.

[davedoc1984]

Hi Marqs :) that looks to have solved the issue for me! Thank You :).

Out of interest what do those 2 settings do?

[marqs85]

They reduce PLL bandwidths and thus spread out any disturbances in time domain, resulting to better clock signal quality (but potentially higher sampling jitter). Was it sufficient to change the first setting or did you also need to lower FPGA PLL BW?