[subclass 1] sample sysref, LMFC, align ILAS to sysref

[jordens]

No description provided.

[jbqubit]

I see that JESD204B Subclass 1 is not yet supported. Subclass 1 is part of the planned Sayma synchronization plan: "Timestamping a certain sample to a specific RTIO cycle requires two things in addition to JESD204B subclass 1 deterministic latency."

Some questions.

• What is the status of Subclass 1 support?
• What are the implications of the current status of this codebase for testing the Sayma hardware? In particular we want to check the following.
  • Phase synchronous operation of:
    • DACs on a single Sayma
    • DACs on different Sayma (but in same microTCA chassis).
  • Deterministic phase offset between power cycles for:
    • DACs on a single Sayma
    • DACs on different Sayma (but in same microTCA chassis).

[jbqubit]

I looked at my notes... I see from quote Q0059 that JESD204B Subclass 1 is slated for delivery +1 moth after the Sayma prototype hardware is available. I've updated my questions slightly to reflect this.

[sbourdeauducq]

Currently there is no support for it; it depends on what clock chip (e.g. HMC7043) is used, and we need hardware to develop it.

[jbqubit]

@sbourdeauducq This should be part of milestone 4.0. I think it just got missed in the Sayma Issue sweep.
https://github.com/m-labs/artiq/milestone/11

[sbourdeauducq]

You are in the wrong repository, the corresponding ARTIQ issue is m-labs/artiq#794 (and m-labs/artiq#795 for inter-card)

[jbqubit]

Great! Thanks.

[sbourdeauducq]

@enjoy-digital This is done, isn't it?