@@ -220,6 +220,7 @@ struct OtAlertState {
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MemoryRegion mmio ;
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IbexIRQ * irqs ;
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IbexIRQ * esc_txs ;
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+ IbexIRQ nmi_alert ;
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OtAlertScheduler * schedulers ;
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OtAlertRegs regs ; /* not ordered by register index */
@@ -571,6 +572,7 @@ static void ot_alert_clear_alert(OtAlertState *s, unsigned nclass)
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trace_ot_alert_escalation (s -> ot_id , ACLASS (nclass ), ix , "release" );
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}
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ibex_irq_set (esc_tx , 0 );
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+ ibex_irq_set (& s -> nmi_alert , 0u );
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}
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/*
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* "Software can clear CLASSn_ACCUM_CNT with a write to CLASSA_CLR_SHADOWED"
@@ -741,6 +743,10 @@ static void ot_alert_signal_tx(void *opaque, int n, int level)
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trace_ot_alert_signal_tx (s -> ot_id , alert , (bool )level , alert_en );
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+ if (alert_en && level ) {
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+ ibex_irq_set (& s -> nmi_alert , 1u );
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+ }
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+
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if (!alert_en || !level ) {
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/* releasing the alert does not clear it */
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return ;
@@ -1034,6 +1040,7 @@ static void ot_alert_realize(DeviceState *dev, Error **errp)
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s -> esc_txs = g_new0 (IbexIRQ , PARAM_N_ESC_SEV );
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ibex_qdev_init_irqs (OBJECT (dev ), s -> esc_txs , OT_ALERT_ESCALATE ,
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PARAM_N_ESC_SEV );
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+ ibex_qdev_init_irq (OBJECT (dev ), & s -> nmi_alert , OT_ALERT_NMI );
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qdev_init_gpio_in_named (dev , & ot_alert_signal_tx , OT_DEVICE_ALERT ,
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s -> n_alerts );
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