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ctopal
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Updating parameters for OpenTitan option
Updated the parameters with respect to top_earlgrey.hjson in OpenTitan repository. For other builds, kept the previously undeclared parameters as their default values. Signed-off-by: Canberk Topal <[email protected]>
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11 files changed

+279
-104
lines changed

11 files changed

+279
-104
lines changed

‎dv/riscv_compliance/ibex_riscv_compliance.core

+28-7
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,24 @@ parameters:
7777
default: 0
7878
description: "Enables static branch prediction (EXPERIMENTAL)"
7979

80+
DbgTriggerEn:
81+
datatype: int
82+
default: 0
83+
paramtype: vlogparam
84+
description: "Enable support for debug triggers. "
85+
86+
SecureIbex:
87+
datatype: int
88+
default: 0
89+
paramtype: vlogparam
90+
description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
91+
92+
ICacheScramble:
93+
datatype: int
94+
default: 0
95+
paramtype: vlogparam
96+
description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]"
97+
8098
PMPEnable:
8199
datatype: int
82100
default: 0
@@ -95,17 +113,17 @@ parameters:
95113
paramtype: vlogparam
96114
description: "Number of PMP regions"
97115

98-
SecureIbex:
116+
MHPMCounterNum:
99117
datatype: int
100118
paramtype: vlogparam
101119
default: 0
102-
description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
120+
description: Number of performance monitor event counters [0/29]
103121

104-
ICacheScramble:
122+
MHPMCounterWidth:
105123
datatype: int
106124
paramtype: vlogparam
107-
default: 0
108-
description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]"
125+
default: 40
126+
description: Bit width of performance monitor event counters [32/64]
109127

110128
targets:
111129
sim:
@@ -123,11 +141,14 @@ targets:
123141
- BranchTargetALU
124142
- WritebackStage
125143
- BranchPredictor
144+
- DbgTriggerEn
145+
- SecureIbex
146+
- ICacheScramble
126147
- PMPEnable
127148
- PMPGranularity
128149
- PMPNumRegions
129-
- SecureIbex
130-
- ICacheScramble
150+
- MHPMCounterNum
151+
- MHPMCounterWidth
131152
toplevel: ibex_riscv_compliance
132153
tools:
133154
verilator:

‎dv/riscv_compliance/rtl/ibex_riscv_compliance.sv

+36-30
Original file line numberDiff line numberDiff line change
@@ -15,20 +15,23 @@ module ibex_riscv_compliance (
1515
input IO_RST_N
1616
);
1717

18-
parameter bit PMPEnable = 1'b0;
19-
parameter int unsigned PMPGranularity = 0;
20-
parameter int unsigned PMPNumRegions = 4;
21-
parameter bit RV32E = 1'b0;
22-
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast;
23-
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone;
24-
parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF;
25-
parameter bit BranchTargetALU = 1'b0;
26-
parameter bit WritebackStage = 1'b0;
27-
parameter bit ICache = 1'b0;
28-
parameter bit ICacheECC = 1'b0;
29-
parameter bit BranchPredictor = 1'b0;
30-
parameter bit SecureIbex = 1'b0;
31-
parameter bit ICacheScramble = 1'b0;
18+
parameter bit PMPEnable = 1'b0;
19+
parameter int unsigned PMPGranularity = 0;
20+
parameter int unsigned PMPNumRegions = 4;
21+
parameter int unsigned MHPMCounterNum = 0;
22+
parameter int unsigned MHPMCounterWidth = 40;
23+
parameter bit RV32E = 1'b0;
24+
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast;
25+
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone;
26+
parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF;
27+
parameter bit BranchTargetALU = 1'b0;
28+
parameter bit WritebackStage = 1'b0;
29+
parameter bit ICache = 1'b0;
30+
parameter bit ICacheECC = 1'b0;
31+
parameter bit BranchPredictor = 1'b0;
32+
parameter bit SecureIbex = 1'b0;
33+
parameter bit ICacheScramble = 1'b0;
34+
parameter bit DbgTriggerEn = 1'b0;
3235

3336
logic clk_sys, rst_sys_n;
3437

@@ -135,22 +138,25 @@ module ibex_riscv_compliance (
135138
end
136139

137140
ibex_top_tracing #(
138-
.PMPEnable (PMPEnable ),
139-
.PMPGranularity (PMPGranularity ),
140-
.PMPNumRegions (PMPNumRegions ),
141-
.RV32E (RV32E ),
142-
.RV32M (RV32M ),
143-
.RV32B (RV32B ),
144-
.RegFile (RegFile ),
145-
.BranchTargetALU (BranchTargetALU ),
146-
.WritebackStage (WritebackStage ),
147-
.ICache (ICache ),
148-
.ICacheECC (ICacheECC ),
149-
.BranchPredictor (BranchPredictor ),
150-
.SecureIbex (SecureIbex ),
151-
.ICacheScramble (ICacheScramble ),
152-
.DmHaltAddr (32'h00000000 ),
153-
.DmExceptionAddr (32'h00000000 )
141+
.PMPEnable (PMPEnable ),
142+
.PMPGranularity (PMPGranularity ),
143+
.PMPNumRegions (PMPNumRegions ),
144+
.MHPMCounterNum (MHPMCounterNum ),
145+
.MHPMCounterWidth (MHPMCounterWidth ),
146+
.RV32E (RV32E ),
147+
.RV32M (RV32M ),
148+
.RV32B (RV32B ),
149+
.RegFile (RegFile ),
150+
.BranchTargetALU (BranchTargetALU ),
151+
.WritebackStage (WritebackStage ),
152+
.ICache (ICache ),
153+
.ICacheECC (ICacheECC ),
154+
.BranchPredictor (BranchPredictor ),
155+
.DbgTriggerEn (DbgTriggerEn ),
156+
.SecureIbex (SecureIbex ),
157+
.ICacheScramble (ICacheScramble ),
158+
.DmHaltAddr (32'h00000000 ),
159+
.DmExceptionAddr (32'h00000000 )
154160
) u_top (
155161
.clk_i (clk_sys ),
156162
.rst_ni (rst_sys_n ),

‎dv/uvm/core_ibex/tb/core_ibex_tb_top.sv

+38-30
Original file line numberDiff line numberDiff line change
@@ -51,38 +51,46 @@ module core_ibex_tb_top;
5151
`define IBEX_CFG_RegFile ibex_pkg::RegFileFF
5252
`endif
5353

54-
parameter bit PMPEnable = 1'b0;
55-
parameter int unsigned PMPGranularity = 0;
56-
parameter int unsigned PMPNumRegions = 4;
57-
parameter bit RV32E = 1'b0;
58-
parameter ibex_pkg::rv32m_e RV32M = `IBEX_CFG_RV32M;
59-
parameter ibex_pkg::rv32b_e RV32B = `IBEX_CFG_RV32B;
60-
parameter ibex_pkg::regfile_e RegFile = `IBEX_CFG_RegFile;
61-
parameter bit BranchTargetALU = 1'b0;
62-
parameter bit WritebackStage = 1'b0;
63-
parameter bit ICache = 1'b0;
64-
parameter bit ICacheECC = 1'b0;
65-
parameter bit BranchPredictor = 1'b0;
66-
parameter bit SecureIbex = 1'b0;
67-
parameter bit ICacheScramble = 1'b0;
54+
parameter bit PMPEnable = 1'b0;
55+
parameter int unsigned PMPGranularity = 0;
56+
parameter int unsigned PMPNumRegions = 4;
57+
parameter int unsigned MHPMCounterNum = 0;
58+
parameter int unsigned MHPMCounterWidth = 40;
59+
parameter bit RV32E = 1'b0;
60+
parameter ibex_pkg::rv32m_e RV32M = `IBEX_CFG_RV32M;
61+
parameter ibex_pkg::rv32b_e RV32B = `IBEX_CFG_RV32B;
62+
parameter ibex_pkg::regfile_e RegFile = `IBEX_CFG_RegFile;
63+
parameter bit BranchTargetALU = 1'b0;
64+
parameter bit WritebackStage = 1'b0;
65+
parameter bit ICache = 1'b0;
66+
parameter bit ICacheECC = 1'b0;
67+
parameter bit BranchPredictor = 1'b0;
68+
parameter bit SecureIbex = 1'b0;
69+
parameter bit ICacheScramble = 1'b0;
70+
parameter bit DbgTriggerEn = 1'b0;
71+
6872

6973
ibex_top_tracing #(
70-
.DmHaltAddr (32'h`BOOT_ADDR + 'h0 ),
71-
.DmExceptionAddr (32'h`BOOT_ADDR + 'h4 ),
72-
.PMPEnable (PMPEnable ),
73-
.PMPGranularity (PMPGranularity ),
74-
.PMPNumRegions (PMPNumRegions ),
75-
.RV32E (RV32E ),
76-
.RV32M (RV32M ),
77-
.RV32B (RV32B ),
78-
.RegFile (RegFile ),
79-
.BranchTargetALU (BranchTargetALU ),
80-
.WritebackStage (WritebackStage ),
81-
.ICache (ICache ),
82-
.ICacheECC (ICacheECC ),
83-
.SecureIbex (SecureIbex ),
84-
.ICacheScramble (ICacheScramble ),
85-
.BranchPredictor (BranchPredictor )
74+
.DmHaltAddr (32'h`BOOT_ADDR + 'h0 ),
75+
.DmExceptionAddr (32'h`BOOT_ADDR + 'h4 ),
76+
.PMPEnable (PMPEnable ),
77+
.PMPGranularity (PMPGranularity ),
78+
.PMPNumRegions (PMPNumRegions ),
79+
.MHPMCounterNum (MHPMCounterNum ),
80+
.MHPMCounterWidth (MHPMCounterWidth ),
81+
.RV32E (RV32E ),
82+
.RV32M (RV32M ),
83+
.RV32B (RV32B ),
84+
.RegFile (RegFile ),
85+
.BranchTargetALU (BranchTargetALU ),
86+
.WritebackStage (WritebackStage ),
87+
.ICache (ICache ),
88+
.ICacheECC (ICacheECC ),
89+
.SecureIbex (SecureIbex ),
90+
.ICacheScramble (ICacheScramble ),
91+
.BranchPredictor (BranchPredictor ),
92+
.DbgTriggerEn (DbgTriggerEn )
93+
8694
) dut (
8795
.clk_i (clk ),
8896
.rst_ni (rst_n ),

‎dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core

+21
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,12 @@ parameters:
8282
default: 0
8383
description: "Enables static branch prediction (EXPERIMENTAL)"
8484

85+
DbgTriggerEn:
86+
datatype: int
87+
default: 0
88+
paramtype: vlogparam
89+
description: "Enable support for debug triggers. "
90+
8591
PMPEnable:
8692
datatype: int
8793
default: 0
@@ -100,6 +106,18 @@ parameters:
100106
paramtype: vlogparam
101107
description: "Number of PMP regions"
102108

109+
MHPMCounterNum:
110+
datatype: int
111+
paramtype: vlogparam
112+
default: 0
113+
description: Number of performance monitor event counters [0/29]
114+
115+
MHPMCounterWidth:
116+
datatype: int
117+
paramtype: vlogparam
118+
default: 40
119+
description: Bit width of performance monitor event counters [32/64]
120+
103121
ICacheScramble:
104122
datatype: int
105123
default: 0
@@ -122,9 +140,12 @@ targets:
122140
- WritebackStage
123141
- SecureIbex
124142
- BranchPredictor
143+
- DbgTriggerEn
125144
- PMPEnable
126145
- PMPGranularity
127146
- PMPNumRegions
147+
- MHPMCounterNum
148+
- MHPMCounterWidth
128149
- ICacheScramble
129150
- SRAMInitFile
130151

‎examples/simple_system/ibex_simple_system.core

+21
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,12 @@ parameters:
8484
default: 0
8585
description: "Enables static branch prediction (EXPERIMENTAL)"
8686

87+
DbgTriggerEn:
88+
datatype: int
89+
default: 0
90+
paramtype: vlogparam
91+
description: "Enable support for debug triggers. "
92+
8793
PMPEnable:
8894
datatype: int
8995
default: 0
@@ -102,6 +108,18 @@ parameters:
102108
paramtype: vlogparam
103109
description: "Number of PMP regions"
104110

111+
MHPMCounterNum:
112+
datatype: int
113+
paramtype: vlogparam
114+
default: 0
115+
description: Number of performance monitor event counters [0/29]
116+
117+
MHPMCounterWidth:
118+
datatype: int
119+
paramtype: vlogparam
120+
default: 40
121+
description: Bit width of performance monitor event counters [32/64]
122+
105123
targets:
106124
default: &default_target
107125
filesets:
@@ -119,9 +137,12 @@ targets:
119137
- WritebackStage
120138
- SecureIbex
121139
- BranchPredictor
140+
- DbgTriggerEn
122141
- PMPEnable
123142
- PMPGranularity
124143
- PMPNumRegions
144+
- MHPMCounterNum
145+
- MHPMCounterWidth
125146
- SRAMInitFile
126147

127148
lint:

‎examples/simple_system/rtl/ibex_simple_system.sv

+22-17
Original file line numberDiff line numberDiff line change
@@ -40,13 +40,16 @@ module ibex_simple_system (
4040
parameter bit PMPEnable = 1'b0;
4141
parameter int unsigned PMPGranularity = 0;
4242
parameter int unsigned PMPNumRegions = 4;
43+
parameter int unsigned MHPMCounterNum = 0;
44+
parameter int unsigned MHPMCounterWidth = 40;
4345
parameter bit RV32E = 1'b0;
4446
parameter ibex_pkg::rv32m_e RV32M = `RV32M;
4547
parameter ibex_pkg::rv32b_e RV32B = `RV32B;
4648
parameter ibex_pkg::regfile_e RegFile = `RegFile;
4749
parameter bit BranchTargetALU = 1'b0;
4850
parameter bit WritebackStage = 1'b0;
4951
parameter bit ICache = 1'b0;
52+
parameter bit DbgTriggerEn = 1'b0;
5053
parameter bit ICacheECC = 1'b0;
5154
parameter bit BranchPredictor = 1'b0;
5255
parameter SRAMInitFile = "";
@@ -184,23 +187,25 @@ module ibex_simple_system (
184187
end
185188

186189
ibex_top_tracing #(
187-
.SecureIbex ( SecureIbex ),
188-
.ICacheScramble ( ICacheScramble ),
189-
.PMPEnable ( PMPEnable ),
190-
.PMPGranularity ( PMPGranularity ),
191-
.PMPNumRegions ( PMPNumRegions ),
192-
.MHPMCounterNum ( 29 ),
193-
.RV32E ( RV32E ),
194-
.RV32M ( RV32M ),
195-
.RV32B ( RV32B ),
196-
.RegFile ( RegFile ),
197-
.BranchTargetALU ( BranchTargetALU ),
198-
.ICache ( ICache ),
199-
.ICacheECC ( ICacheECC ),
200-
.WritebackStage ( WritebackStage ),
201-
.BranchPredictor ( BranchPredictor ),
202-
.DmHaltAddr ( 32'h00100000 ),
203-
.DmExceptionAddr ( 32'h00100000 )
190+
.SecureIbex ( SecureIbex ),
191+
.ICacheScramble ( ICacheScramble ),
192+
.PMPEnable ( PMPEnable ),
193+
.PMPGranularity ( PMPGranularity ),
194+
.PMPNumRegions ( PMPNumRegions ),
195+
.MHPMCounterNum ( 29 ),
196+
.MHPMCounterWidth( MHPMCounterWidth ),
197+
.RV32E ( RV32E ),
198+
.RV32M ( RV32M ),
199+
.RV32B ( RV32B ),
200+
.RegFile ( RegFile ),
201+
.BranchTargetALU ( BranchTargetALU ),
202+
.ICache ( ICache ),
203+
.ICacheECC ( ICacheECC ),
204+
.WritebackStage ( WritebackStage ),
205+
.BranchPredictor ( BranchPredictor ),
206+
.DbgTriggerEn ( DbgTriggerEn ),
207+
.DmHaltAddr ( 32'h00100000 ),
208+
.DmExceptionAddr ( 32'h00100000 )
204209
) u_top (
205210
.clk_i (clk_sys),
206211
.rst_ni (rst_sys_n),

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