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labrinealabrinea
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[FMV] Remove useless features according the latest ACLE spec. (#88965)
As explained in ARM-software/acle#315 we are deprecating features which aren't adding any value. These are: sha1, pmull, dit, dgh, ebf16, sve-bf16, sve-ebf16, sve-i8mm, sve2-pmull128, memtag2, memtag3, ssbs2, bti, ls64_v, ls64_accdata
1 parent da70f2c commit 19c6a7f

15 files changed

+287
-377
lines changed

‎clang/test/CodeGen/aarch64-cpu-supports.c

+16-8
Original file line numberDiff line numberDiff line change
@@ -1,33 +1,35 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --version 2
22
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
33

4+
//.
45
// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
6+
//.
57
// CHECK-LABEL: define dso_local i32 @main
68
// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
79
// CHECK-NEXT: entry:
810
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
911
// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
1012
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
11-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
12-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
13+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 34359738368
14+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 34359738368
1315
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
1416
// CHECK-NEXT: br i1 [[TMP3]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
1517
// CHECK: if.then:
1618
// CHECK-NEXT: store i32 1, ptr [[RETVAL]], align 4
1719
// CHECK-NEXT: br label [[RETURN:%.*]]
1820
// CHECK: if.end:
1921
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
20-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 9070970929152
21-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 9070970929152
22+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17716740096
23+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17716740096
2224
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
2325
// CHECK-NEXT: br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
2426
// CHECK: if.then1:
2527
// CHECK-NEXT: store i32 2, ptr [[RETVAL]], align 4
2628
// CHECK-NEXT: br label [[RETURN]]
2729
// CHECK: if.end2:
2830
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
29-
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 166633186212708352
30-
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 166633186212708352
31+
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 5222680231936
32+
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 5222680231936
3133
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
3234
// CHECK-NEXT: br i1 [[TMP11]], label [[IF_THEN3:%.*]], label [[IF_END4:%.*]]
3335
// CHECK: if.then3:
@@ -49,14 +51,20 @@ int main(void) {
4951
if (__builtin_cpu_supports("sb"))
5052
return 1;
5153

52-
if (__builtin_cpu_supports("sve2-pmull128+memtag"))
54+
if (__builtin_cpu_supports("sve2-aes+memtag"))
5355
return 2;
5456

55-
if (__builtin_cpu_supports("sme2+ls64_v+wfxt"))
57+
if (__builtin_cpu_supports("sme2+ls64+wfxt"))
5658
return 3;
5759

5860
if (__builtin_cpu_supports("avx2"))
5961
return 4;
6062

6163
return 0;
6264
}
65+
//.
66+
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
67+
//.
68+
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
69+
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
70+
//.

‎clang/test/CodeGen/aarch64-mixed-target-attributes.c

+6-6
Original file line numberDiff line numberDiff line change
@@ -69,8 +69,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
6969
// CHECK-NEXT: resolver_entry:
7070
// CHECK-NEXT: call void @__init_cpu_features_resolver()
7171
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
72-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
73-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
72+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
73+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
7474
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
7575
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
7676
// CHECK: resolver_return:
@@ -143,8 +143,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
143143
// CHECK-NEXT: resolver_entry:
144144
// CHECK-NEXT: call void @__init_cpu_features_resolver()
145145
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
146-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
147-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
146+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
147+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
148148
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
149149
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
150150
// CHECK: resolver_return:
@@ -210,8 +210,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
210210
// CHECK-NEXT: resolver_entry:
211211
// CHECK-NEXT: call void @__init_cpu_features_resolver()
212212
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
213-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
214-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
213+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
214+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
215215
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
216216
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
217217
// CHECK: resolver_return:

‎clang/test/CodeGen/attr-target-clones-aarch64.c

+38-39
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
44

55
int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
6-
int __attribute__((target_clones("sha2", "sha2+memtag2", " default "))) ftc_def(void) { return 1; }
6+
int __attribute__((target_clones("sha2", "sha2+memtag", " default "))) ftc_def(void) { return 1; }
77
int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; }
88
int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; }
99
int foo() {
@@ -12,7 +12,7 @@ int foo() {
1212

1313
inline int __attribute__((target_clones("rng+simd", "rcpc+predres", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; }
1414
inline int __attribute__((target_clones("fp16", "fcma+sve2-bitperm", "default"))) ftc_inline2(void);
15-
inline int __attribute__((target_clones("bti", "sve+sb"))) ftc_inline3(void) { return 3; }
15+
inline int __attribute__((target_clones("mops", "sve+sb"))) ftc_inline3(void) { return 3; }
1616

1717
int __attribute__((target_clones("default"))) ftc_direct(void) { return 4; }
1818

@@ -56,16 +56,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
5656
// CHECK-NEXT: resolver_entry:
5757
// CHECK-NEXT: call void @__init_cpu_features_resolver()
5858
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
59-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16512
60-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
59+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 8320
60+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8320
6161
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
6262
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
6363
// CHECK: resolver_return:
6464
// CHECK-NEXT: ret ptr @ftc._MaesMlse
6565
// CHECK: resolver_else:
6666
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
67-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
68-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68719476736
67+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 268435456
68+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 268435456
6969
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
7070
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
7171
// CHECK: resolver_return1:
@@ -81,7 +81,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
8181
//
8282
//
8383
// CHECK: Function Attrs: noinline nounwind optnone
84-
// CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
84+
// CHECK-LABEL: @ftc_def._MmemtagMsha2(
8585
// CHECK-NEXT: entry:
8686
// CHECK-NEXT: ret i32 1
8787
//
@@ -90,16 +90,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
9090
// CHECK-NEXT: resolver_entry:
9191
// CHECK-NEXT: call void @__init_cpu_features_resolver()
9292
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
93-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512
94-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512
93+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17179871232
94+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17179871232
9595
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
9696
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
9797
// CHECK: resolver_return:
98-
// CHECK-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
98+
// CHECK-NEXT: ret ptr @ftc_def._MmemtagMsha2
9999
// CHECK: resolver_else:
100100
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
101-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
102-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096
101+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2048
102+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2048
103103
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
104104
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
105105
// CHECK: resolver_return1:
@@ -118,8 +118,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
118118
// CHECK-NEXT: resolver_entry:
119119
// CHECK-NEXT: call void @__init_cpu_features_resolver()
120120
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
121-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096
122-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
121+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2048
122+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2048
123123
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
124124
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
125125
// CHECK: resolver_return:
@@ -198,16 +198,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
198198
// CHECK-NEXT: resolver_entry:
199199
// CHECK-NEXT: call void @__init_cpu_features_resolver()
200200
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
201-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
202-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
201+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 550292684800
202+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 550292684800
203203
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
204204
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
205205
// CHECK: resolver_return:
206206
// CHECK-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt
207207
// CHECK: resolver_else:
208208
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
209-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632
210-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632
209+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68720001024
210+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68720001024
211211
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
212212
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
213213
// CHECK: resolver_return1:
@@ -228,16 +228,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
228228
// CHECK-NEXT: resolver_entry:
229229
// CHECK-NEXT: call void @__init_cpu_features_resolver()
230230
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
231-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 549757911040
232-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 549757911040
231+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1074003968
232+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1074003968
233233
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
234234
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
235235
// CHECK: resolver_return:
236236
// CHECK-NEXT: ret ptr @ftc_inline2._MfcmaMsve2-bitperm
237237
// CHECK: resolver_else:
238238
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
239-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 65536
240-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65536
239+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16384
240+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 16384
241241
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
242242
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
243243
// CHECK: resolver_return1:
@@ -250,20 +250,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
250250
// CHECK-NEXT: resolver_entry:
251251
// CHECK-NEXT: call void @__init_cpu_features_resolver()
252252
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
253-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817919488
254-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817919488
253+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 34393292800
254+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 34393292800
255255
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
256256
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
257257
// CHECK: resolver_return:
258258
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
259259
// CHECK: resolver_else:
260260
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
261-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
262-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
261+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416
262+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416
263263
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
264264
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
265265
// CHECK: resolver_return1:
266-
// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
266+
// CHECK-NEXT: ret ptr @ftc_inline3._Mmops
267267
// CHECK: resolver_else2:
268268
// CHECK-NEXT: ret ptr @ftc_inline3.default
269269
//
@@ -329,7 +329,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
329329
//
330330
//
331331
// CHECK: Function Attrs: noinline nounwind optnone
332-
// CHECK-LABEL: @ftc_inline3._Mbti(
332+
// CHECK-LABEL: @ftc_inline3._Mmops(
333333
// CHECK-NEXT: entry:
334334
// CHECK-NEXT: ret i32 3
335335
//
@@ -407,17 +407,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
407407
// CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" }
408408
// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" }
409409
// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sha2" }
410-
// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" }
411-
// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
412-
// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" }
413-
// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
414-
// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
415-
// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" }
416-
// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" }
417-
// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" }
418-
// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
419-
// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" }
420-
// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" }
410+
// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
411+
// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" }
412+
// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
413+
// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
414+
// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" }
415+
// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" }
416+
// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" }
417+
// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
418+
// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops" }
419+
// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" }
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//.
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// CHECK-NOFMV: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
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// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }

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