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[ESI] FIFO with ESI channels (#8004)
Adds an op which provides a FIFO with ESI channels (FIFO signaling semantics only for now) on both ends.
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8 files changed

+286
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‎include/circt/Dialect/ESI/ESIChannels.td‎

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Original file line numberDiff line numberDiff line change
@@ -476,6 +476,27 @@ def PipelineStageOp : ESI_Physical_Op<"stage", [
476476
// Misc operations
477477
//===----------------------------------------------------------------------===//
478478

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def FIFOOp : ESI_Physical_Op<"fifo", []> {
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let summary = "A FIFO with ESI channel connections";
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let description = [{
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A FIFO is a first-in-first-out buffer. This operation is a simple FIFO
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which can be used to connect two ESI channels. The ESI channels MUST have
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FIFO signaling semantics.
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}];
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let arguments = (ins
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ClockType:$clk, I1:$rst, ChannelType:$input,
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ConfinedAttr<I64Attr, [IntMinValue<1>]>:$depth
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);
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let results = (outs ChannelType:$output);
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let assemblyFormat = [{
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`in` $input `clk` $clk `rst` $rst `depth` $depth attr-dict
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`:` type($input) `->` type($output)
496+
}];
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let hasVerifier = 1;
498+
}
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479500
def CosimToHostEndpointOp : ESI_Physical_Op<"cosim.to_host", []> {
480501
let summary = "Co-simulation endpoint sending data to the host.";
481502
let description = [{

‎integration_test/Dialect/ESI/runtime/lit.local.cfg.py‎ renamed to ‎integration_test/Dialect/ESI/lit.local.cfg.py‎

File renamed without changes.

‎integration_test/Dialect/ESI/widgets/esi_widgets.mlir‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
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// REQUIRES: iverilog,cocotb
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// Test the original HandshakeToHW flow.
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// RUN: circt-opt %s --lower-esi-to-physical --lower-esi-ports --lower-esi-to-hw --lower-seq-fifo --lower-seq-hlmem --lower-seq-to-sv --lower-verif-to-sv --sv-trace-iverilog --prettify-verilog --export-verilog -o %t.hw.mlir > %t.sv
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// RUN: circt-cocotb-driver.py --objdir=%T --topLevel=fifo1 --pythonModule=esi_widgets --pythonFolder="%S" %t.sv %esi_prims
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module attributes {circt.loweringOptions = "disallowLocalVariables"} {
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hw.module @fifo1(in %clk: !seq.clock, in %rst: i1, in %in: !esi.channel<i32, FIFO>, out out: !esi.channel<i32, FIFO(2)>) {
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%fifo = esi.fifo in %in clk %clk rst %rst depth 12 : !esi.channel<i32, FIFO> -> !esi.channel<i32, FIFO(2)>
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hw.output %fifo : !esi.channel<i32, FIFO(2)>
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}
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}

‎integration_test/Dialect/ESI/widgets/esi_widgets.py‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,151 @@
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from typing import List, Optional
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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async def init(dut, timeout: Optional[int] = None):
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# Create a 10ns period (100MHz) clock on port clock
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clk = Clock(dut.clk, 10, units="ns")
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cocotb.start_soon(clk.start()) # Start the clock
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# Reset
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dut.rst.value = 1
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for i in range(10):
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await RisingEdge(dut.clk)
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dut.rst.value = 0
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await RisingEdge(dut.clk)
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if timeout is None:
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return
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async def timeout_fn():
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for i in range(timeout):
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await RisingEdge(dut.clk)
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assert False, "Timeout"
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cocotb.start_soon(timeout_fn())
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class ESIInputPort:
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async def write(self, data):
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raise RuntimeError("Must be implemented by subclass")
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class ESIFifoInputPort(ESIInputPort):
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def __init__(self, dut, name):
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self.dut = dut
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self.name = name
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self.data = getattr(dut, name)
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self.rden = getattr(dut, f"{name}_rden")
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self.empty = getattr(dut, f"{name}_empty")
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# Configure initial state
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self.empty.value = 1
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async def write(self, data: int):
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self.data.value = data
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self.empty.value = 0
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await RisingEdge(self.dut.clk)
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while self.rden.value == 0:
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await RisingEdge(self.dut.clk)
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self.empty.value = 1
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class ESIOutputPort:
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async def read(self) -> Optional[int]:
59+
raise RuntimeError("Must be implemented by subclass")
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async def cmd_read(self):
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raise RuntimeError("Must be implemented by subclass")
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class ESIFifoOutputPort(ESIOutputPort):
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def __init__(self, dut, name: str, latency: int = 0):
68+
self.dut = dut
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self.name = name
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self.data = getattr(dut, name)
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self.rden = getattr(dut, f"{name}_rden")
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self.empty = getattr(dut, f"{name}_empty")
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self.latency = latency
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# Configure initial state
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self.rden.value = 0
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self.running = 0
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self.q: List[int] = []
78+
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async def init_read(self):
80+
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async def read_after_latency():
82+
for i in range(self.latency):
83+
await RisingEdge(self.dut.clk)
84+
self.q.append(self.data.value)
85+
86+
self.running = 1
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self.empty.value = 0
88+
while await RisingEdge(self.dut.clk):
89+
if self.rden.value == 1:
90+
cocotb.start_soon(read_after_latency())
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async def read(self) -> Optional[int]:
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if len(self.q) == 0:
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await RisingEdge(self.dut.clk)
95+
return self.q.pop(0)
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async def cmd_read(self):
98+
if self.running == 0:
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cocotb.start_soon(self.init_read())
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while self.empty.value == 1:
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await RisingEdge(self.dut.clk)
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self.rden.value = 1
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await RisingEdge(self.dut.clk)
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self.rden.value = 0
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@cocotb.test()
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async def fillAndDrain(dut):
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in_port = ESIFifoInputPort(dut, "in")
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out_port = ESIFifoOutputPort(dut, "out", 2)
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await init(dut, timeout=10000)
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for i in range(10):
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for i in range(12):
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await in_port.write(i)
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for i in range(12):
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await out_port.cmd_read()
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for i in range(12):
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data = await out_port.read()
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# print(f"{i:2}: 0x{int(data):016x}")
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assert data == i
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for i in range(4):
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def backToBack(dut):
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in_port = ESIFifoInputPort(dut, "in")
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out_port = ESIFifoOutputPort(dut, "out", 2)
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await init(dut)
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NUM_ITERS = 500
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async def write():
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for i in range(NUM_ITERS):
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await in_port.write(i)
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cocotb.start_soon(write())
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for i in range(NUM_ITERS):
143+
await out_port.cmd_read()
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for i in range(NUM_ITERS):
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data = await out_port.read()
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# print(f"{i:2}: 0x{int(data):016x}")
148+
assert data == i
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for i in range(4):
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await RisingEdge(dut.clk)

‎lib/Dialect/ESI/ESIOps.cpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,22 @@ LogicalResult ChannelBufferOp::verify() {
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return success();
7373
}
7474

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//===----------------------------------------------------------------------===//
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// FIFO functions.
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//===----------------------------------------------------------------------===//
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LogicalResult FIFOOp::verify() {
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ChannelType inputType = getInput().getType();
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if (inputType.getSignaling() != ChannelSignaling::FIFO)
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return emitOpError("only supports FIFO signaling on input");
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ChannelType outputType = getOutput().getType();
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if (outputType.getSignaling() != ChannelSignaling::FIFO)
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return emitOpError("only supports FIFO signaling on output");
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if (outputType.getInner() != inputType.getInner())
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return emitOpError("input and output types must match");
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return success();
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}
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7591
//===----------------------------------------------------------------------===//
7692
// PipelineStageOp functions.
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//===----------------------------------------------------------------------===//

‎lib/Dialect/ESI/Passes/ESILowerPhysical.cpp‎

Lines changed: 63 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,10 @@
1212

1313
#include "../PassDetails.h"
1414

15+
#include "circt/Dialect/Comb/CombOps.h"
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#include "circt/Dialect/ESI/ESIOps.h"
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Dialect/Seq/SeqOps.h"
1719
#include "circt/Support/BackedgeBuilder.h"
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#include "circt/Support/LLVM.h"
1921

@@ -78,6 +80,64 @@ LogicalResult ChannelBufferLowering::matchAndRewrite(
7880
return success();
7981
}
8082

83+
namespace {
84+
/// Lower `ChannelBufferOp`s, breaking out the various options. For now, just
85+
/// replace with the specified number of pipeline stages (since that's the only
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/// option).
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struct FIFOLowering : public OpConversionPattern<FIFOOp> {
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public:
89+
using OpConversionPattern::OpConversionPattern;
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LogicalResult
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matchAndRewrite(FIFOOp, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const final;
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};
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} // anonymous namespace
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LogicalResult
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FIFOLowering::matchAndRewrite(FIFOOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const {
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auto loc = op.getLoc();
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auto outputType = op.getType();
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BackedgeBuilder bb(rewriter, loc);
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auto i1 = rewriter.getI1Type();
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auto c1 = rewriter.create<hw::ConstantOp>(loc, rewriter.getI1Type(),
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rewriter.getBoolAttr(true));
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if (op.getInput().getType().getDataDelay() != 0)
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return op.emitOpError(
108+
"currently only supports input channels with zero data delay");
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110+
Backedge inputEn = bb.get(i1);
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auto unwrapPull = rewriter.create<UnwrapFIFOOp>(loc, op.getInput(), inputEn);
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Backedge outputRdEn = bb.get(i1);
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auto seqFifo = rewriter.create<seq::FIFOOp>(
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loc, outputType.getInner(), i1, i1, Type(), Type(), unwrapPull.getData(),
116+
outputRdEn, inputEn, op.getClk(), op.getRst(), op.getDepthAttr(),
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rewriter.getI64IntegerAttr(outputType.getDataDelay()), IntegerAttr(),
118+
IntegerAttr());
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auto inputNotEmpty =
120+
rewriter.create<comb::XorOp>(loc, unwrapPull.getEmpty(), c1);
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inputNotEmpty->setAttr("sv.namehint",
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rewriter.getStringAttr("inputNotEmpty"));
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auto seqFifoNotFull =
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rewriter.create<comb::XorOp>(loc, seqFifo.getFull(), c1);
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seqFifoNotFull->setAttr("sv.namehint",
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rewriter.getStringAttr("seqFifoNotFull"));
127+
inputEn.setValue(
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rewriter.create<comb::AndOp>(loc, inputNotEmpty, seqFifoNotFull));
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static_cast<Value>(inputEn).getDefiningOp()->setAttr(
130+
"sv.namehint", rewriter.getStringAttr("inputEn"));
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auto output =
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rewriter.create<WrapFIFOOp>(loc, mlir::TypeRange{outputType, i1},
134+
seqFifo.getOutput(), seqFifo.getEmpty());
135+
outputRdEn.setValue(output.getRden());
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137+
rewriter.replaceOp(op, output.getChanOutput());
138+
return success();
139+
}
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81141
namespace {
82142
/// Lower pure modules into hw.modules.
83143
struct PureModuleLowering : public OpConversionPattern<ESIPureModuleOp> {
@@ -186,13 +246,12 @@ void ESIToPhysicalPass::runOnOperation() {
186246
// Set up a conversion and give it a set of laws.
187247
ConversionTarget target(getContext());
188248
target.markUnknownOpDynamicallyLegal([](Operation *) { return true; });
189-
target.addIllegalOp<ChannelBufferOp>();
190-
target.addIllegalOp<ESIPureModuleOp>();
249+
target.addIllegalOp<ChannelBufferOp, ESIPureModuleOp, FIFOOp>();
191250

192251
// Add all the conversion patterns.
193252
RewritePatternSet patterns(&getContext());
194-
patterns.insert<ChannelBufferLowering>(&getContext());
195-
patterns.insert<PureModuleLowering>(&getContext());
253+
patterns.insert<ChannelBufferLowering, PureModuleLowering, FIFOLowering>(
254+
&getContext());
196255

197256
// Run the conversion.
198257
if (failed(

‎test/Dialect/ESI/errors.mlir‎

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Original file line numberDiff line numberDiff line change
@@ -46,6 +46,14 @@ hw.module @test(in %m : !sv.modport<@IData::@Noexist>) {
4646

4747
// -----
4848

49+
hw.module @testFifoTypes(in %clk: !seq.clock, in %rst: i1, in %a: !esi.channel<i32, FIFO>, in %b: !esi.channel<i16, FIFO(2)>) {
50+
// expected-error @+1 {{input and output types must match}}
51+
%fifo = esi.fifo in %a clk %clk rst %rst depth 12 : !esi.channel<i32, FIFO> -> !esi.channel<i16, FIFO(2)>
52+
hw.output %fifo : !esi.channel<i16, FIFO(2)>
53+
}
54+
55+
// -----
56+
4957
esi.service.decl @HostComms {
5058
esi.service.port @Send : !esi.bundle<[!esi.channel<i16> from "send"]>
5159
}

‎test/Dialect/ESI/lowering.mlir‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,3 +197,17 @@ hw.module @i3LoopbackOddNames(in %in: !esi.channel<i3>, out out: !esi.channel<i3
197197
esi.portReadySuffix="_letErRip", esi.portOutSuffix="_out"} {
198198
hw.output %in : !esi.channel<i3>
199199
}
200+
201+
// CHECK-LABEL: hw.module @fifo1(in %clk : !seq.clock, in %rst : i1, in %in : !esi.channel<i32, FIFO>, out out : !esi.channel<i32, FIFO(2)>) {
202+
// CHECK-NEXT: %true = hw.constant true
203+
// CHECK-NEXT: %data, %empty = esi.unwrap.fifo %in, [[R2:%.+]] : !esi.channel<i32, FIFO>
204+
// CHECK-NEXT: %out, %full, %empty_0 = seq.fifo depth 12 rd_latency 2 in %data rdEn %rden wrEn [[R2]] clk %clk rst %rst : i32
205+
// CHECK-NEXT: [[R0:%.+]] = comb.xor %empty, %true {sv.namehint = "inputNotEmpty"} : i1
206+
// CHECK-NEXT: [[R1:%.+]] = comb.xor %full, %true {sv.namehint = "seqFifoNotFull"} : i1
207+
// CHECK-NEXT: [[R2]] = comb.and [[R0]], [[R1]] {sv.namehint = "inputEn"} : i1
208+
// CHECK-NEXT: %chanOutput, %rden = esi.wrap.fifo %out, %empty_0 : !esi.channel<i32, FIFO(2)>
209+
// CHECK-NEXT: hw.output %chanOutput : !esi.channel<i32, FIFO(2)>
210+
hw.module @fifo1(in %clk: !seq.clock, in %rst: i1, in %in: !esi.channel<i32, FIFO>, out out: !esi.channel<i32, FIFO(2)>) {
211+
%fifo = esi.fifo in %in clk %clk rst %rst depth 12 : !esi.channel<i32, FIFO> -> !esi.channel<i32, FIFO(2)>
212+
hw.output %fifo : !esi.channel<i32, FIFO(2)>
213+
}

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