From af8c91901078c0ded0aa960693c55ee977ba0a8c Mon Sep 17 00:00:00 2001
From: Brian Neff <brian@liquidinstruments.com>
Date: Mon, 16 Mar 2026 13:37:26 -0400
Subject: [PATCH 1/2] Added MC Files for Digital Up and Down Conversion for
 Full Rate MC

---
 .../DigitalUpDownConversion/cos_lut.mem       | 4096 +++++++++++++++++
 mc/Advanced/DigitalUpDownConversion/design.v  |  707 +++
 .../DigitalUpDownConversion/sin_lut.mem       | 4096 +++++++++++++++++
 3 files changed, 8899 insertions(+)
 create mode 100644 mc/Advanced/DigitalUpDownConversion/cos_lut.mem
 create mode 100644 mc/Advanced/DigitalUpDownConversion/design.v
 create mode 100644 mc/Advanced/DigitalUpDownConversion/sin_lut.mem

diff --git a/mc/Advanced/DigitalUpDownConversion/cos_lut.mem b/mc/Advanced/DigitalUpDownConversion/cos_lut.mem
new file mode 100644
index 0000000..a1c9970
--- /dev/null
+++ b/mc/Advanced/DigitalUpDownConversion/cos_lut.mem
@@ -0,0 +1,4096 @@
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diff --git a/mc/Advanced/DigitalUpDownConversion/design.v b/mc/Advanced/DigitalUpDownConversion/design.v
new file mode 100644
index 0000000..7cbb880
--- /dev/null
+++ b/mc/Advanced/DigitalUpDownConversion/design.v
@@ -0,0 +1,707 @@
+// Combined DDC/DUC Instrument
+// 16x interlaced design at 312.5 MHz clock (5 GS/s effective)
+//
+// Modes:
+//   DDC (Control3[0]=0): InputA -> Mixer -> 6-section IIR -> OutputA(I), OutputB(Q)
+//   DUC (Control3[0]=1): InputA(I)*cos - InputB(Q)*sin -> OutputA
+//
+// Pipeline Latency:
+//   DDC: 19 cycles (3 input + 3 NCO + 2 mixer + 12 IIR output)
+//   DUC: 8 cycles (3 input + 3 NCO + 2 mixer + 1 combine)
+
+/* verilator lint_off UNUSEDSIGNAL */
+/* verilator lint_off UNDRIVEN */
+
+module CustomInstrumentInterlaced #(
+    parameter INPUT_INTERLACING_FACTOR = 16,
+    parameter OUTPUT_INTERLACING_FACTOR = 16
+) (
+    input wire clk,
+    input wire reset,
+    input wire [31:0] sync,
+
+    input wire signed [15:0] inputa [0:INPUT_INTERLACING_FACTOR-1],
+    input wire signed [15:0] inputb [0:INPUT_INTERLACING_FACTOR-1],
+    input wire signed [15:0] inputc [0:INPUT_INTERLACING_FACTOR-1],
+    input wire signed [15:0] inputd [0:INPUT_INTERLACING_FACTOR-1],
+
+    input wire exttrig [0:INPUT_INTERLACING_FACTOR-1],
+
+    output wire signed [15:0] outputa [0:OUTPUT_INTERLACING_FACTOR-1],
+    output wire signed [15:0] outputb [0:OUTPUT_INTERLACING_FACTOR-1],
+    output wire signed [15:0] outputc [0:OUTPUT_INTERLACING_FACTOR-1],
+    output wire signed [15:0] outputd [0:OUTPUT_INTERLACING_FACTOR-1],
+
+    input wire [31:0] control [0:15],
+    output wire [31:0] status [0:15]
+);
+
+    // ========================================================================
+    // Parameters and Constants
+    // ========================================================================
+    localparam NUM_LANES = INPUT_INTERLACING_FACTOR;
+    localparam LUT_DEPTH = 4096;
+    localparam LUT_ADDR_BITS = 12;
+    localparam NUM_IIR_SECTIONS = 6;
+
+    // Phase increment constant: K = round(2^64 / 5e9) = 3,689,348,815
+    // phase_inc = (freq_hz * K) >> 32
+    localparam [63:0] FREQ_TO_PHASE_K = 64'd3689348815;
+
+    // ========================================================================
+    // Type Definitions
+    // ========================================================================
+    typedef logic signed [15:0] sample_t;
+    typedef logic signed [31:0] wide_t;
+    typedef logic signed [32:0] wider_t;
+    typedef logic [31:0] phase_t;
+    typedef logic [15:0] coeff_t;  // Q0.16 unsigned coefficient
+
+    // ========================================================================
+    // Control Register Extraction
+    // ========================================================================
+    wire [31:0] carrier_freq_hz = control[0];
+    wire [31:0] cutoff_freq_hz  = control[1];
+    wire        mode_select     = control[3][0];  // 0=DDC, 1=DUC
+
+    // ========================================================================
+    // IO Boundary Registers
+    // ========================================================================
+    sample_t inputa_io [0:NUM_LANES-1];
+    sample_t inputb_io [0:NUM_LANES-1];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                inputa_io[i] <= '0;
+                inputb_io[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                inputa_io[i] <= inputa[i];
+                inputb_io[i] <= inputb[i];
+            end
+        end
+    end
+
+    // ========================================================================
+    // Input Pipeline (3 stages: d1, d2, d3)
+    // ========================================================================
+    sample_t input_d1_a [0:NUM_LANES-1];
+    sample_t input_d1_b [0:NUM_LANES-1];
+    sample_t input_d2_a [0:NUM_LANES-1];
+    sample_t input_d2_b [0:NUM_LANES-1];
+    sample_t input_d3_a [0:NUM_LANES-1];
+    sample_t input_d3_b [0:NUM_LANES-1];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                input_d1_a[i] <= '0;
+                input_d1_b[i] <= '0;
+                input_d2_a[i] <= '0;
+                input_d2_b[i] <= '0;
+                input_d3_a[i] <= '0;
+                input_d3_b[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                input_d1_a[i] <= inputa_io[i];
+                input_d1_b[i] <= inputb_io[i];
+                input_d2_a[i] <= input_d1_a[i];
+                input_d2_b[i] <= input_d1_b[i];
+                input_d3_a[i] <= input_d2_a[i];
+                input_d3_b[i] <= input_d2_b[i];
+            end
+        end
+    end
+
+    // ========================================================================
+    // Phase Increment Computation
+    // ========================================================================
+    // phase_increment = (carrier_freq_hz * K) >> 32
+    // This is computed combinationally and registered for use
+    logic [63:0] phase_inc_product;
+    phase_t phase_increment_r;
+
+    always_comb begin
+        phase_inc_product = carrier_freq_hz * FREQ_TO_PHASE_K;
+    end
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            phase_increment_r <= '0;
+        end else begin
+            phase_increment_r <= phase_inc_product[63:32];
+        end
+    end
+
+    // ========================================================================
+    // NCO Phase Accumulator
+    // ========================================================================
+    phase_t phase_acc;
+    phase_t phase_acc_next;
+
+    // Phase accumulator advances by phase_increment * NUM_LANES per clock
+    always_comb begin
+        phase_acc_next = phase_acc + (phase_increment_r * NUM_LANES);
+    end
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            phase_acc <= '0;
+        end else begin
+            phase_acc <= phase_acc_next;
+        end
+    end
+
+    // ========================================================================
+    // Per-Lane Phase Computation
+    // ========================================================================
+    // lane_phase[g] = phase_acc + phase_increment * g
+    // Pre-compute increments for timing
+    phase_t lane_phase [0:NUM_LANES-1];
+    phase_t phase_offset [0:NUM_LANES-1];
+
+    // Register the phase offsets (phase_increment * lane_index)
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                phase_offset[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                phase_offset[i] <= phase_increment_r * i[3:0];
+            end
+        end
+    end
+
+    // Compute per-lane phase combinationally from registered values
+    always_comb begin
+        for (int i = 0; i < NUM_LANES; i++) begin
+            lane_phase[i] = phase_acc + phase_offset[i];
+        end
+    end
+
+    // ========================================================================
+    // NCO Sin/Cos LUT (16 replicated pairs for parallel access)
+    // ========================================================================
+    // LUT address = phase[31:20] (top 12 bits)
+    sample_t sin_val [0:NUM_LANES-1];
+    sample_t cos_val [0:NUM_LANES-1];
+    sample_t sin_val_r [0:NUM_LANES-1];
+    sample_t cos_val_r [0:NUM_LANES-1];
+
+    // Replicated sin/cos LUTs per lane with integrated read logic
+    genvar g;
+    generate
+        for (g = 0; g < NUM_LANES; g = g + 1) begin : NCO_LUT
+            (* ram_style = "block" *) sample_t sin_lut [0:LUT_DEPTH-1];
+            (* ram_style = "block" *) sample_t cos_lut [0:LUT_DEPTH-1];
+
+            initial begin
+                $readmemh("sin_lut.mem", sin_lut);
+                $readmemh("cos_lut.mem", cos_lut);
+            end
+
+            // LUT address for this lane
+            logic [LUT_ADDR_BITS-1:0] addr_comb;
+            logic [LUT_ADDR_BITS-1:0] addr_reg;
+
+            // Combinational address from phase
+            always_comb begin
+                addr_comb = lane_phase[g][31:20];
+            end
+
+            // Stage 1: Register LUT address
+            always_ff @(posedge clk) begin
+                if (reset) begin
+                    addr_reg <= '0;
+                end else begin
+                    addr_reg <= addr_comb;
+                end
+            end
+
+            // Stage 2: LUT read (BRAM output)
+            always_ff @(posedge clk) begin
+                if (reset) begin
+                    sin_val[g] <= '0;
+                    cos_val[g] <= '0;
+                end else begin
+                    sin_val[g] <= sin_lut[addr_reg];
+                    cos_val[g] <= cos_lut[addr_reg];
+                end
+            end
+
+            // Stage 3: Pipeline register for NCO output
+            always_ff @(posedge clk) begin
+                if (reset) begin
+                    sin_val_r[g] <= '0;
+                    cos_val_r[g] <= '0;
+                end else begin
+                    sin_val_r[g] <= sin_val[g];
+                    cos_val_r[g] <= cos_val[g];
+                end
+            end
+        end
+    endgenerate
+
+    // ========================================================================
+    // External LO Mode Selection
+    // ========================================================================
+    // When carrier_freq_hz = 0:
+    //   DDC: Use InputB as cos, zero sin (external LO mode)
+    //   DUC: cos(0)=32767, sin(0)=0 (bypass mode)
+    wire use_external_lo = (carrier_freq_hz == 32'd0);
+
+    sample_t nco_cos [0:NUM_LANES-1];
+    sample_t nco_sin [0:NUM_LANES-1];
+
+    always_comb begin
+        for (int i = 0; i < NUM_LANES; i++) begin
+            if (use_external_lo && !mode_select) begin
+                // DDC external LO mode: use InputB as cos, zero sin
+                nco_cos[i] = input_d3_b[i];
+                nco_sin[i] = 16'sd0;
+            end else begin
+                // Normal NCO operation
+                nco_cos[i] = cos_val_r[i];
+                nco_sin[i] = sin_val_r[i];
+            end
+        end
+    end
+
+    // ========================================================================
+    // Mixer: 16x16 -> 32-bit multiply with Q1.15 normalization
+    // ========================================================================
+    // DDC: I = InputA * cos, Q = InputA * (-sin)
+    // DUC: I_mix = InputA * cos, Q_mix = InputB * sin
+
+    // Stage 1: Register mixer inputs (ensures DSP48 AREG/BREG absorption)
+    sample_t mixer_in_i [0:NUM_LANES-1];
+    sample_t mixer_in_q [0:NUM_LANES-1];
+    sample_t mixer_cos [0:NUM_LANES-1];
+    sample_t mixer_sin [0:NUM_LANES-1];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                mixer_in_i[i] <= '0;
+                mixer_in_q[i] <= '0;
+                mixer_cos[i] <= '0;
+                mixer_sin[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                if (mode_select) begin
+                    // DUC mode: I input = InputA, Q input = InputB
+                    mixer_in_i[i] <= input_d3_a[i];
+                    mixer_in_q[i] <= input_d3_b[i];
+                end else begin
+                    // DDC mode: Both paths use InputA
+                    mixer_in_i[i] <= input_d3_a[i];
+                    mixer_in_q[i] <= input_d3_a[i];
+                end
+                mixer_cos[i] <= nco_cos[i];
+                mixer_sin[i] <= nco_sin[i];
+            end
+        end
+    end
+
+    // Stage 2: Multiply (DSP48 MREG)
+    wide_t mix_prod_i [0:NUM_LANES-1];
+    wide_t mix_prod_q [0:NUM_LANES-1];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                mix_prod_i[i] <= '0;
+                mix_prod_q[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                mix_prod_i[i] <= mixer_in_i[i] * mixer_cos[i];
+                mix_prod_q[i] <= mixer_in_q[i] * mixer_sin[i];
+            end
+        end
+    end
+
+    // Stage 3: Scale (>>>15 with rounding) and saturate
+    // DDC Q path uses -sin, so negate the product
+    sample_t mix_out_i [0:NUM_LANES-1];
+    sample_t mix_out_q [0:NUM_LANES-1];
+
+    // Saturation function
+    function automatic sample_t saturate_32to16(input wide_t val);
+        if (val > 32'sd32767)
+            return 16'sd32767;
+        else if (val < -32'sd32768)
+            return -16'sd32768;
+        else
+            return val[15:0];
+    endfunction
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                mix_out_i[i] <= '0;
+                mix_out_q[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                // I path: InputA * cos >>> 15 with rounding
+                wide_t i_rounded;
+                wide_t q_rounded;
+                wide_t q_negated;
+
+                i_rounded = (mix_prod_i[i] + 32'sd16384) >>> 15;
+                mix_out_i[i] <= saturate_32to16(i_rounded);
+
+                if (mode_select) begin
+                    // DUC mode: Q = InputB * sin >>> 15
+                    q_rounded = (mix_prod_q[i] + 32'sd16384) >>> 15;
+                    mix_out_q[i] <= saturate_32to16(q_rounded);
+                end else begin
+                    // DDC mode: Q = InputA * (-sin) >>> 15
+                    // Negate the product before scaling
+                    q_negated = -mix_prod_q[i];
+                    q_rounded = (q_negated + 32'sd16384) >>> 15;
+                    mix_out_q[i] <= saturate_32to16(q_rounded);
+                end
+            end
+        end
+    end
+
+    // ========================================================================
+    // IIR Coefficient Computation
+    // ========================================================================
+    // alpha_q16 = clamp(round(2*pi * f_cutoff * 65536 / 312,500,000), 0, 65535)
+    // Simplify: alpha_q16 = clamp(round(f_cutoff * 0.001319469), 0, 65535)
+    // Using integer math: alpha = (f_cutoff * 1319) >> 20 (approximation)
+    // More accurate: alpha = (f_cutoff * 2199023) >> 31 (matches 2*pi*65536/312.5e6)
+
+    logic [51:0] alpha_product;
+    coeff_t alpha_q16;
+    logic [16:0] beta_q16;  // 17-bit to hold 65536
+
+    // Constant: round(2 * pi * 65536 / 312500000 * 2^20) = 1382
+    // Verification: For 1 MHz cutoff: (1000000 * 1382) >> 20 = 1318
+    // For 10 MHz cutoff: (10000000 * 1382) >> 20 = 13179
+    localparam [31:0] ALPHA_CONSTANT = 32'd1382;
+
+    always_comb begin
+        alpha_product = cutoff_freq_hz * ALPHA_CONSTANT;
+    end
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            alpha_q16 <= '0;
+            beta_q16 <= 17'd65536;
+        end else begin
+            // alpha = (f_cutoff * K) >> 20, clamped to [0, 65535]
+            logic [31:0] alpha_raw;
+            alpha_raw = alpha_product[51:20];
+            if (alpha_raw > 32'd65535)
+                alpha_q16 <= 16'd65535;
+            else
+                alpha_q16 <= alpha_raw[15:0];
+            beta_q16 <= 17'd65536 - {1'b0, alpha_q16};
+        end
+    end
+
+    // ========================================================================
+    // IIR Filter: 6-Section First-Order Cascade (per lane, I and Q)
+    // ========================================================================
+    // Each section: y[n] = alpha*x[n] + beta*y[n-1]
+    // Q0.16 * Q1.15 = Q1.31, then >>16 to get Q1.15
+    // 2-cycle pipeline per section:
+    //   Cycle 1: products = alpha*x, beta*y_prev
+    //   Cycle 2: sum = products, shift, saturate
+
+    // IIR state arrays: [lane][section]
+    // dont_touch ensures state registers aren't optimized away or merged
+    (* dont_touch = "true" *) sample_t iir_state_i [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+    (* dont_touch = "true" *) sample_t iir_state_q [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+
+    // Pipeline registers for IIR
+    // Section inputs
+    sample_t iir_in_i [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+    sample_t iir_in_q [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+
+    // Products (stage 1 output)
+    // Alpha product: Q0.17 * Q1.15 = Q1.32 (max 33 bits)
+    // Beta product: Q0.18 * Q1.15 = Q1.33 (max 34 bits, beta can be 65536)
+    logic signed [33:0] iir_prod_alpha_i [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+    logic signed [33:0] iir_prod_alpha_q [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+    logic signed [33:0] iir_prod_beta_i [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+    logic signed [33:0] iir_prod_beta_q [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+
+    // Section outputs (stage 2 output)
+    sample_t iir_out_i [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+    sample_t iir_out_q [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+
+    // Coefficient registers (replicated per lane AND per section for reduced fanout)
+    // Each register feeds only 2 DSP multiply inputs (I and Q for one lane/section)
+    (* dont_touch = "true" *) coeff_t alpha_r [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+    (* dont_touch = "true" *) logic [16:0] beta_r [0:NUM_LANES-1][0:NUM_IIR_SECTIONS-1];
+
+    // Register coefficients for all lanes and sections
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int lane = 0; lane < NUM_LANES; lane++) begin
+                for (int s = 0; s < NUM_IIR_SECTIONS; s++) begin
+                    alpha_r[lane][s] <= '0;
+                    beta_r[lane][s] <= 17'd65536;
+                end
+            end
+        end else begin
+            for (int lane = 0; lane < NUM_LANES; lane++) begin
+                for (int s = 0; s < NUM_IIR_SECTIONS; s++) begin
+                    alpha_r[lane][s] <= alpha_q16;
+                    beta_r[lane][s] <= beta_q16;
+                end
+            end
+        end
+    end
+
+    // Generate IIR filter chains for all lanes
+    generate
+        for (g = 0; g < NUM_LANES; g = g + 1) begin : IIR_LANE
+
+            // Section 0 input comes from mixer output
+            always_ff @(posedge clk) begin
+                if (reset) begin
+                    iir_in_i[g][0] <= '0;
+                    iir_in_q[g][0] <= '0;
+                end else begin
+                    iir_in_i[g][0] <= mix_out_i[g];
+                    iir_in_q[g][0] <= mix_out_q[g];
+                end
+            end
+
+            // Generate 6 sections
+            for (genvar s = 0; s < NUM_IIR_SECTIONS; s = s + 1) begin : IIR_SECTION
+
+                // Initialize state on reset
+                initial begin
+                    iir_state_i[g][s] = '0;
+                    iir_state_q[g][s] = '0;
+                end
+
+                // Stage 1: Compute products
+                always_ff @(posedge clk) begin
+                    if (reset) begin
+                        iir_prod_alpha_i[g][s] <= '0;
+                        iir_prod_alpha_q[g][s] <= '0;
+                        iir_prod_beta_i[g][s] <= '0;
+                        iir_prod_beta_q[g][s] <= '0;
+                    end else begin
+                        // alpha * x (Q0.16 * Q1.15 = Q1.31)
+                        // Use per-lane coefficients to reduce fanout
+                        iir_prod_alpha_i[g][s] <= $signed({1'b0, alpha_r[g][s]}) * iir_in_i[g][s];
+                        iir_prod_alpha_q[g][s] <= $signed({1'b0, alpha_r[g][s]}) * iir_in_q[g][s];
+                        // beta * y_prev (Q0.17 * Q1.15 = Q1.32, but beta <= 65536)
+                        iir_prod_beta_i[g][s] <= $signed({1'b0, beta_r[g][s]}) * iir_state_i[g][s];
+                        iir_prod_beta_q[g][s] <= $signed({1'b0, beta_r[g][s]}) * iir_state_q[g][s];
+                    end
+                end
+
+                // Stage 2: Sum, shift (>>16), saturate
+                // Optimized for timing: narrower overflow detection, direct saturation
+                logic signed [34:0] sum_i_comb, sum_q_comb;
+                logic signed [18:0] scaled_i_comb, scaled_q_comb;  // 19 bits after >>16
+                sample_t sat_i_comb, sat_q_comb;
+
+                always_comb begin
+                    // Sum products with rounding
+                    sum_i_comb = iir_prod_alpha_i[g][s] + iir_prod_beta_i[g][s] + 35'sd32768;
+                    sum_q_comb = iir_prod_alpha_q[g][s] + iir_prod_beta_q[g][s] + 35'sd32768;
+
+                    // Extract 19-bit scaled result (sum[34:16])
+                    scaled_i_comb = sum_i_comb[34:16];
+                    scaled_q_comb = sum_q_comb[34:16];
+
+                    // Optimized saturation: check only bits [18:15] for overflow
+                    // If [18:15] are all 0s or all 1s, no overflow (value fits in 16-bit signed)
+                    // Positive overflow: upper bits are 0001, 0010, 0011, ... 0111 (value > 32767)
+                    // Negative overflow: upper bits are 1110, 1101, 1100, ... 1000 (value < -32768)
+                    if (scaled_i_comb[18:15] == 4'b0000 || scaled_i_comb[18:15] == 4'b1111)
+                        sat_i_comb = scaled_i_comb[15:0];
+                    else if (scaled_i_comb[18])  // Negative overflow
+                        sat_i_comb = -16'sd32768;
+                    else  // Positive overflow
+                        sat_i_comb = 16'sd32767;
+
+                    if (scaled_q_comb[18:15] == 4'b0000 || scaled_q_comb[18:15] == 4'b1111)
+                        sat_q_comb = scaled_q_comb[15:0];
+                    else if (scaled_q_comb[18])  // Negative overflow
+                        sat_q_comb = -16'sd32768;
+                    else  // Positive overflow
+                        sat_q_comb = 16'sd32767;
+                end
+
+                always_ff @(posedge clk) begin
+                    if (reset) begin
+                        iir_out_i[g][s] <= '0;
+                        iir_out_q[g][s] <= '0;
+                        iir_state_i[g][s] <= '0;
+                        iir_state_q[g][s] <= '0;
+                    end else begin
+                        // Register the saturated values
+                        iir_out_i[g][s] <= sat_i_comb;
+                        iir_out_q[g][s] <= sat_q_comb;
+
+                        // Update state (feedback) - same value
+                        iir_state_i[g][s] <= sat_i_comb;
+                        iir_state_q[g][s] <= sat_q_comb;
+                    end
+                end
+
+                // Connect section output to next section input (except last)
+                if (s < NUM_IIR_SECTIONS - 1) begin : CHAIN
+                    always_ff @(posedge clk) begin
+                        if (reset) begin
+                            iir_in_i[g][s+1] <= '0;
+                            iir_in_q[g][s+1] <= '0;
+                        end else begin
+                            iir_in_i[g][s+1] <= iir_out_i[g][s];
+                            iir_in_q[g][s+1] <= iir_out_q[g][s];
+                        end
+                    end
+                end
+
+            end : IIR_SECTION
+        end : IIR_LANE
+    endgenerate
+
+    // Final IIR output (last section output)
+    sample_t ddc_out_i [0:NUM_LANES-1];
+    sample_t ddc_out_q [0:NUM_LANES-1];
+
+    always_comb begin
+        for (int i = 0; i < NUM_LANES; i++) begin
+            ddc_out_i[i] = iir_out_i[i][NUM_IIR_SECTIONS-1];
+            ddc_out_q[i] = iir_out_q[i][NUM_IIR_SECTIONS-1];
+        end
+    end
+
+    // ========================================================================
+    // DUC Combiner: (I*cos - Q*sin) >> 1
+    // ========================================================================
+    sample_t duc_out [0:NUM_LANES-1];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                duc_out[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                // Subtract: I*cos - Q*sin (both already scaled by >>>15)
+                // Then >>1 for headroom
+                wide_t diff;
+                diff = $signed({{16{mix_out_i[i][15]}}, mix_out_i[i]}) -
+                       $signed({{16{mix_out_q[i][15]}}, mix_out_q[i]});
+                duc_out[i] <= diff[16:1];  // >>1 with truncation
+            end
+        end
+    end
+
+    // ========================================================================
+    // Output Multiplexer
+    // ========================================================================
+    sample_t outa_r [0:NUM_LANES-1];
+    sample_t outb_r [0:NUM_LANES-1];
+
+    // Pipeline the mode_select to match output timing
+    logic mode_select_d [0:19];  // Delay chain for mode select
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < 20; i++) begin
+                mode_select_d[i] <= 1'b0;
+            end
+        end else begin
+            mode_select_d[0] <= mode_select;
+            for (int i = 1; i < 20; i++) begin
+                mode_select_d[i] <= mode_select_d[i-1];
+            end
+        end
+    end
+
+    // Use delayed mode select for output mux (8 cycles for DUC path)
+    wire mode_at_output = mode_select_d[7];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                outa_r[i] <= '0;
+                outb_r[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                if (mode_at_output) begin
+                    // DUC mode: OutputA = DUC result, OutputB = 0
+                    outa_r[i] <= duc_out[i];
+                    outb_r[i] <= '0;
+                end else begin
+                    // DDC mode: OutputA = I, OutputB = Q
+                    outa_r[i] <= ddc_out_i[i];
+                    outb_r[i] <= ddc_out_q[i];
+                end
+            end
+        end
+    end
+
+    // ========================================================================
+    // Output IO Registers and Assignments
+    // ========================================================================
+    sample_t outa_io [0:NUM_LANES-1];
+    sample_t outb_io [0:NUM_LANES-1];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                outa_io[i] <= '0;
+                outb_io[i] <= '0;
+            end
+        end else begin
+            for (int i = 0; i < NUM_LANES; i++) begin
+                outa_io[i] <= outa_r[i];
+                outb_io[i] <= outb_r[i];
+            end
+        end
+    end
+
+    // Output wire assignments
+    genvar lane;
+    generate
+        for (lane = 0; lane < OUTPUT_INTERLACING_FACTOR; lane = lane + 1) begin : OUT_ASSIGN
+            assign outputa[lane] = outa_io[lane];
+            assign outputb[lane] = outb_io[lane];
+            assign outputc[lane] = 16'sd0;
+            assign outputd[lane] = 16'sd0;
+        end
+    endgenerate
+
+    // ========================================================================
+    // Status Registers
+    // ========================================================================
+    assign status[0] = {16'd0, alpha_q16};           // Current IIR alpha_q16
+    assign status[1] = 32'd0;                         // Reserved
+    assign status[2] = phase_increment_r;             // Current NCO phase increment
+    assign status[3] = {31'd0, mode_select};          // Current mode
+    assign status[4] = 32'd0;
+    assign status[5] = 32'd0;
+    assign status[6] = 32'd0;
+    assign status[7] = 32'd0;
+    assign status[8] = 32'd0;
+    assign status[9] = 32'd0;
+    assign status[10] = 32'd0;
+    assign status[11] = 32'd0;
+    assign status[12] = 32'd0;
+    assign status[13] = 32'd0;
+    assign status[14] = 32'd0;
+    assign status[15] = 32'd0;
+
+endmodule
diff --git a/mc/Advanced/DigitalUpDownConversion/sin_lut.mem b/mc/Advanced/DigitalUpDownConversion/sin_lut.mem
new file mode 100644
index 0000000..f8d380c
--- /dev/null
+++ b/mc/Advanced/DigitalUpDownConversion/sin_lut.mem
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From 7fbfd86cc6a21353247004df2b27b029c0938050 Mon Sep 17 00:00:00 2001
From: Brian Neff <brian@liquidinstruments.com>
Date: Mon, 16 Mar 2026 14:01:07 -0400
Subject: [PATCH 2/2] Added README File for Digital Up and Down Conversion for
 Full Rate MC

---
 mc/Advanced/DigitalUpDownConversion/README.md | 334 ++++++++++++++++++
 1 file changed, 334 insertions(+)
 create mode 100644 mc/Advanced/DigitalUpDownConversion/README.md

diff --git a/mc/Advanced/DigitalUpDownConversion/README.md b/mc/Advanced/DigitalUpDownConversion/README.md
new file mode 100644
index 0000000..9a17d63
--- /dev/null
+++ b/mc/Advanced/DigitalUpDownConversion/README.md
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+# Combined DDC/DUC Instrument Specification
+
+## 1. Overview
+
+This instrument implements a dual-mode digital frequency converter on the Moku:Delta platform. It operates as either a Digital Down Converter (DDC) for narrowband I/Q extraction, or a Digital Up Converter (DUC) for wideband RF synthesis. Mode selection is via Control3[0].
+
+The instrument uses 16x interlacing at a 312.5 MHz clock, giving an effective sample rate of 5 GS/s. Both DDC and DUC paths produce 16 distinct output samples per clock cycle at full 5 GS/s effective bandwidth.
+
+```
+                                                 DDC path (Control3[0]=0)
+                                                ┌──────────────────────────────────────────────┐
+                                                │                                              │
+InputA ──[d1]──[d2]──[d3]──┬── × lo_cos ── >>15 ── per-lane IIR(6) ──────────────────────────► OutputA (I)
+                            │                      (16 independent lanes, 16 distinct samples)
+              ┌─────────────┤
+              │ DDC: InputA │
+              │ DUC: InputB │
+              └──── mux ────┴── × (−lo_sin) ── >>15 ── per-lane IIR(6) ──────────────────────► OutputB (Q)
+                                                   │    (16 independent lanes, 16 distinct samples)
+InputB ──[d1]──[d2]──[d3]──┘                       │
+                                                   │  DUC path (Control3[0]=1)
+                                 NCO               │ ┌────────────────────────────────────────────┐
+carrier_freq ──► phase_acc ──► sin/cos LUT ──────  └─┤  I×cos − Q×sin  ── >>1 ──────────────────► OutputA
+                 (32-bit)      (4096-entry)          │  (per-lane subtract)          OutputB = 0
+                                                     └────────────────────────────────────────────┘
+```
+
+## 2. Inputs
+
+### 2.1 InputA — Primary Signal
+
+16-bit signed, 16 lanes.
+
+- **DDC mode**: Wideband RF signal to be downconverted. The I mixer path multiplies InputA by cos; the Q mixer path multiplies InputA by **−sin** (negative sine). This sign convention ensures that a tone above the carrier maps to a positive baseband frequency.
+- **DUC mode**: In-phase (I) baseband component. Multiplied by cos(2πf_c t).
+
+### 2.2 InputB — Secondary Signal
+
+16-bit signed, 16 lanes.
+
+- **DDC mode, Control0 > 0**: Ignored.
+- **DDC mode, Control0 = 0**: External LO. Replaces the NCO cosine output in the I mixer path. The sin path is zeroed (no quadrature without a Hilbert transform).
+- **DUC mode**: Quadrature (Q) baseband component. Multiplied by sin(2πf_c t).
+
+### 2.3 InputC, InputD
+
+Unused. Not connected internally.
+
+## 3. Outputs
+
+### 3.1 DDC Mode (Control3[0] = 0)
+
+| Port | Content |
+|------|---------|
+| OutputA | Filtered I (in-phase) channel. Each of the 16 lanes carries a **distinct** time sample at full 5 GS/s effective bandwidth. |
+| OutputB | Filtered Q (quadrature) channel. Each of the 16 lanes carries a **distinct** time sample at full 5 GS/s effective bandwidth. |
+| OutputC | Zero. |
+| OutputD | Zero. |
+
+### 3.2 DUC Mode (Control3[0] = 1)
+
+| Port | Content |
+|------|---------|
+| OutputA | Up-converted RF signal: InputA × cos(2πf_c t) − InputB × sin(2πf_c t). Each of the 16 lanes carries a distinct time sample at full 5 GS/s bandwidth. |
+| OutputB | Zero. |
+| OutputC | Zero. |
+| OutputD | Zero. |
+
+## 4. Control Registers
+
+All control registers are 32-bit and read dynamically every clock cycle. Default values are the power-on reset state.
+
+| Register               | Bits     | Name               | Mode | Format          | Default | Description                                                          |
+|:-----------------------|:--------:|:------------------:|:----:|:----------------|:-------:|:---------------------------------------------------------------------|
+| `Control0`             | `[31:0]` | `CarrierFrequency` | Both | Unsigned 32-bit |   `0`   | NCO phase increment. `0` selects external LO (DDC) or bypass (DUC). |
+| `Control1`             | `[31:0]` | `CutoffFrequency`  | DDC  | Unsigned 32-bit |   `0`   | IIR lowpass cutoff in Hz. Controls per-lane IIR coefficient.         |
+| `Control2`             | `[31:0]` | —                  | —    | —               |   `0`   | Reserved. Write as zero.                                             |
+| `Control3`             | `[0]`    | `ModeSelect`       | Both | Single bit      |   `0`   | `0` = DDC, `1` = DUC.                                               |
+| `Control3`             | `[31:1]` | —                  | —    | —               |   `0`   | Reserved. Write as zero.                                             |
+| `Control4`–`Control15` | `[31:0]` | —                  | —    | —               |   `0`   | Reserved. Write as zero.                                             |
+
+### 4.1 Control0 — Carrier Frequency
+
+**Bits**: [31:0]
+**Applies to**: Both modes.
+**Range**: 0 to 2,000,000,000 (2 GHz).
+**Units**: Hz.
+
+Sets the NCO carrier frequency. The NCO converts this to a 32-bit phase increment:
+
+```
+phase_increment = (carrier_freq_hz × 3,689,348,815) >> 32
+```
+
+Frequency resolution is 5 GHz / 2^32 = 1.16 Hz.
+
+**When Control0 = 0:**
+
+| Mode | Behaviour |
+|------|-----------|
+| DDC | External LO mode. InputB replaces the NCO cosine; the sine path is zeroed. OutputB (Q) will be near-zero. |
+| DUC | Natural bypass. The NCO produces cos(0) = +32767 and sin(0) = 0. OutputA = InputA × 0.5 (attenuated by the mixer and subtractor scaling stages). InputB has no effect. |
+
+### 4.2 Control1 — Cutoff Frequency
+
+**Bits**: [31:0]
+**Applies to**: DDC mode only. Ignored in DUC mode.
+**Units**: Hz.
+
+Controls the per-lane IIR lowpass filter cutoff. The IIR consists of 6 cascaded first-order sections per lane: `y[n] = α·x[n] + (1−α)·y[n-1]`. Each of the 16 I lanes and 16 Q lanes has its own independent IIR filter chain (32 chains total, 192 first-order sections).
+
+The coefficient α is computed from Control1:
+
+```
+α = 2π × f_cutoff / 312,500,000
+```
+
+In Q0.16 fixed-point:
+
+```
+alpha_q16 = clamp(round(2π × f_cutoff × 65536 / 312,500,000), 0, 65535)
+beta_q16  = 65536 − alpha_q16
+```
+
+**Recomputation timing:** α and β are recomputed whenever Control1 changes. Since Control1 is read every clock cycle, the coefficient registers should be updated combinationally from Control1, then registered for use by the IIR.
+
+**Examples:**
+
+| Control1 (Hz) | alpha_q16 | Per-section −3 dB (Hz) |
+|---|---|---|
+| 10,000 | 13 | 9.87 kHz |
+| 100,000 | 132 | 100 kHz |
+| 500,000 | 659 | 500 kHz |
+| 1,000,000 | 1,318 | 1.00 MHz |
+| 5,000,000 | 6,589 | 5.00 MHz |
+| 10,000,000 | 13,177 | 10.0 MHz |
+| 50,000,000 | 65,535 (clamped) | ~49.7 MHz (passthrough) |
+
+**Minimum useful cutoff:** ~760 Hz per section (alpha_q16 = 1). For the 6-section cascade, the effective −3 dB is ~266 Hz.
+
+**Maximum useful cutoff:** ~49.7 MHz per section (alpha_q16 = 65535). Above this, the filter clamps to passthrough.
+
+When alpha_q16 = 0 (Control1 = 0), the IIR output holds at its last value (β = 1.0, the section becomes a latch).
+
+### 4.3 Control3 — Mode Select
+
+**Bits**: [0]
+**Values**: 0 = DDC, 1 = DUC.
+
+Selects the operating mode. May be changed at runtime (see Section 7).
+
+**Bits [31:1]**: Reserved. Write as zero.
+
+### 4.4 Control4–Control15
+
+Reserved. Write as zero.
+
+## 5. Status Registers
+
+| Register | Bits | Content |
+|----------|------|---------|
+| Status0 | [15:0] | Current IIR alpha_q16 value. |
+| Status1 | [31:0] | Reserved (zero). |
+| Status2 | [31:0] | Current NCO phase increment (raw 32-bit value). |
+| Status3 | [0] | Current mode: 0 = DDC, 1 = DUC. |
+| Status4–Status15 | [31:0] | Zero. |
+
+## 6. Operating Modes
+
+### 6.1 DDC — Narrowband Receiver
+
+**Configuration**: Control3[0] = 0, Control0 > 0.
+
+Downconverts a wideband RF input to narrowband baseband I/Q. The NCO generates cos and −sin at the carrier frequency. For each of the 16 lanes independently:
+
+1. **Mixer**: InputA[lane] × cos(phase[lane]) → I; InputA[lane] × (−sin(phase[lane])) → Q. Products are arithmetically right-shifted by 15 bits (Q1.15 normalisation) and saturated to 16 bits.
+2. **Per-lane IIR**: The mixer output passes through 6 cascaded first-order IIR lowpass sections. Each section computes `y[n] = α·x[n] + (1−α)·y[n-1]` where α is derived from Control1.
+3. **Output**: The filtered values are placed directly on OutputA (I) and OutputB (Q). Each lane carries a distinct time sample.
+
+Signals within the passband (set by Control1) of the carrier frequency appear as low-frequency I/Q components on the output. Signals outside the passband are attenuated by the per-lane IIR (120 dB/decade rolloff from the 6-section cascade).
+
+**Example** — extract a 1 MHz channel centered at 50 MHz:
+```
+Control0 = 50000000
+Control1 = 1000000
+Control3 = 0
+```
+
+### 6.2 DDC with External LO
+
+**Configuration**: Control3[0] = 0, Control0 = 0.
+
+Same signal path as Section 6.1, except InputB replaces the NCO cosine and the sine path is zeroed. This provides single-channel (I only) downconversion using an external reference. OutputB will be near-zero.
+
+### 6.3 DUC — Wideband Up Converter
+
+**Configuration**: Control3[0] = 1, Control0 > 0.
+
+Up-converts baseband I/Q to RF. InputA (I) is multiplied by cos(2πf_c t), InputB (Q) is multiplied by sin(2πf_c t), and the results are subtracted per-lane:
+
+```
+OutputA[lane] = (InputA[lane] × cos − InputB[lane] × sin) >> 16
+```
+
+The `>> 16` represents the combined effect of the mixer's `>>> 15` (Q1.15 fixed-point normalisation) and the subtractor's `>> 1` (headroom scaling). The resulting gain is approximately 0.5.
+
+**Upper sideband** — I = cos(ω_m t), Q = sin(ω_m t):
+```
+OutputA = (A/2) × cos((ω_c + ω_m) t)
+```
+
+**Lower sideband** — I = cos(ω_m t), Q = −sin(ω_m t):
+```
+OutputA = (A/2) × cos((ω_c − ω_m) t)
+```
+
+**Double sideband (DSB-SC)** — Q = 0:
+```
+OutputA = (A/2) × InputA × cos(ω_c t)
+```
+
+**Example** — generate upper sideband at 51 MHz from 1 MHz baseband:
+```
+Control0 = 50000000
+Control3 = 1
+InputA   = cos(2π × 1 MHz × t) × amplitude
+InputB   = sin(2π × 1 MHz × t) × amplitude
+```
+
+### 6.4 DUC Bypass
+
+**Configuration**: Control3[0] = 1, Control0 = 0.
+
+Passes InputA to OutputA at 0.5× gain (−6 dB). The NCO produces cos(0) = +32767 and sin(0) = 0, so the Q path contributes nothing. InputB is ignored.
+
+## 7. Mode Switching
+
+Control3[0] may be written at any time.
+
+**DDC to DUC**: The DUC output settles within 7 clock cycles. No overflow risk.
+
+**DUC to DDC**: The per-lane IIR filters will be in an arbitrary state. The IIR settling time is approximately 6/(2π × f_cutoff) seconds. For a 1 MHz cutoff this is ~1.0 µs (~312 clock cycles).
+
+## 8. Pipeline Latency
+
+### 8.1 Shared Stages (both modes)
+
+| Stage | Cycle | Operation |
+|-------|-------|-----------|
+| 1 | N | Input capture (`input_d1`) |
+| 2 | N+1 | Input pipeline (`input_d2`) |
+| 3 | N+2 | Input pipeline (`input_d3`); NCO LUT address registered |
+| 4 | N+3 | NCO LUT read (BRAM output) |
+| 5 | N+4 | NCO pipeline register; input and NCO aligned |
+| 6 | N+5 | Mixer multiply (16 × 16 → 32 product) |
+| 7 | N+6 | Mixer scale (`>>> 15`, saturate to 16-bit) |
+
+### 8.2 DDC Stages
+
+| Stage | Cycle | Operation |
+|-------|-------|-----------|
+| 8 | N+7 | IIR section 0: α·x + β·y_prev (per lane, multiply + accumulate) |
+| 9 | N+8 | IIR section 0: register output |
+| 10 | N+9 | IIR section 1: α·x + β·y_prev (per lane) |
+| 11 | N+10 | IIR section 1: register output |
+| 12 | N+11 | IIR section 2: α·x + β·y_prev (per lane) |
+| 13 | N+12 | IIR section 2: register output |
+| 14 | N+13 | IIR section 3: α·x + β·y_prev (per lane) |
+| 15 | N+14 | IIR section 3: register output |
+| 16 | N+15 | IIR section 4: α·x + β·y_prev (per lane) |
+| 17 | N+16 | IIR section 4: register output |
+| 18 | N+17 | IIR section 5: α·x + β·y_prev (per lane) |
+| 19 | N+18 | IIR section 5: register output → OutputA/OutputB |
+
+**Total DDC latency**: 19 clock cycles from input to output.
+
+### 8.3 DUC Stages
+
+| Stage | Cycle | Operation |
+|-------|-------|-----------|
+| 8 | N+7 | Per-lane subtraction (I×cos − Q×sin), `>> 1`, output register |
+
+**Total DUC latency**: 7 clock cycles from input to output.
+
+## 9. Signal Gain
+
+### 9.1 DDC
+
+The mixer produces a Q1.15 normalised output. The IIR sections are unity-gain at DC. The overall DDC passband gain is approximately 0.5× (−6 dB) due to the mixer normalisation.
+
+For a sinusoidal input at exactly the carrier frequency (DC in baseband), the I output amplitude is approximately `InputA_amplitude / 2`. The Q output is approximately zero.
+
+### 9.2 DUC
+
+The gain from input to output is 0.5× (−6 dB), comprising:
+
+1. Mixer: 16-bit × 16-bit = 32-bit product, arithmetic right shift by 15 → approximately unity in Q1.15 format.
+2. Subtractor: `>> 1` for headroom in the I − Q subtraction → 0.5× additional.
+
+For a DC input of amplitude A on InputA with InputB = 0 and Control0 > 0, the output peak is A/2.
+
+## 10. NCO
+
+The NCO uses a 32-bit phase accumulator with 4096-entry sin/cos BRAM lookup tables (16-bit signed, one pair replicated per lane for parallel access). The LUT is addressed by the top 12 bits of each lane's phase.
+
+Per-lane phase is computed combinationally:
+
+```
+lane_phase[g] = phase_acc + phase_increment × g
+```
+
+where `phase_acc` advances by `phase_increment × 16` each clock cycle. This avoids a per-lane registered multiply, at the cost of a combinational multiply on the phase path. The combinational multiply is safe at 312.5 MHz because it feeds into a registered LUT address (not a DSP critical path).
+
+## 11. Limitations
+
+1. **DUC bypass gain is 0.5×**, not unity. An explicit bypass pipeline would restore unity gain but adds mux complexity.
+
+2. **Minimum DDC cutoff is ~760 Hz** (single section) / ~266 Hz (6-section cascade). Below this, alpha_q16 quantises to zero and the filter output freezes. For sub-kHz narrowband applications, a wider fixed-point representation (e.g., Q0.24) would be needed.
+
+3. **External LO has no quadrature**. In DDC mode with Control0 = 0, only the cosine path uses InputB. The sine path is zeroed. OutputB (Q) is therefore near-zero in this mode.
+
+4. **Per-lane IIR resource cost**. 192 first-order IIR sections (16 lanes × 2 channels × 6 stages). Resource sharing (time-multiplexing across lanes) can reduce DSP usage at the cost of pipeline complexity.
+
+## 12. Resource Estimate
+
+| Resource | Count | Notes |
+|----------|-------|-------|
+| BRAM | 32 | 16 lanes × 2 LUTs (sin + cos), 4096 × 16-bit each |
+| DSP48 (mixer) | 32 | 16 lanes × 2 mixer multiplies (I cos, Q sin) |
+| DSP48 (IIR) | 192 | 16 lanes × 2 (I+Q) × 6 sections × 1 multiply each |
+| DSP48 (total) | ~224 | ~5.2% of Moku:Delta's 4,272 DSP48E2 slices |
+| Registers (IIR state) | ~6,144 | 192 sections × 32-bit accumulator state |
+| LUTs (DUC) | ~800 | 16 subtractors + 16 output muxes |
+| Registers (DUC) | ~512 | 16 × 16-bit duc_out registers + mode decode |