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system_incl.make
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#################################################################
# Makefile generated by Xilinx Platform Studio
# Project:I:\Projects\fin\ex\wo_pm_128_final_compact\system.xmp
#
# WARNING : This file will be re-generated every time a command
# to run a make target is invoked. So, any changes made to this
# file manually, will be lost when make is invoked next.
#################################################################
SHELL = CMD
XILINX_EDK_DIR = C:/Xilinx/14.7/ISE_DS/EDK
SYSTEM = system
MHSFILE = system.mhs
PCWPRJFILE = data/ps7_system_prj.xml
FPGA_ARCH = zynq
DEVICE = xc7z045ffg900-3
INTSTYLE = default
XPS_HDL_LANG = vhdl
GLOBAL_SEARCHPATHOPT =
PROJECT_SEARCHPATHOPT =
SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT)
SUBMODULE_OPT =
PLATGEN_OPTIONS = -p $(DEVICE) -lang $(XPS_HDL_LANG) -intstyle $(INTSTYLE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
OBSERVE_PAR_OPTIONS = -error yes
MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf
PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
BOOTLOOP_DIR = bootloops
BRAMINIT_ELF_IMP_FILES =
BRAMINIT_ELF_IMP_FILE_ARGS =
BRAMINIT_ELF_SIM_FILES =
BRAMINIT_ELF_SIM_FILE_ARGS =
SIM_CMD = vsim
BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do
STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do
TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(XPS_HDL_LANG) -intstyle $(INTSTYLE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) -msg __xps/ise/xmsgprops.lst -s mgm -X I:/Projects/fin/ex/wo_pm_128_final_compact/
CORE_STATE_DEVELOPMENT_FILES = pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x40_32x10.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x2198_64x256.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/pll_50M.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/received_message_buffer.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x40_32x10.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x2198_64x256.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/pll_50M.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/received_message_buffer.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x40_32x10.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x2198_64x256.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/pll_50M.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/received_message_buffer.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x40_32x10.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/dpram_8x2198_64x256.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/pll_50M.ngc \
pcores/sync_ch_ctl_bl16_v1_00_a/netlist/received_message_buffer.ngc \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/coregen_comp_defs.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/conv_funs_pkg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/async_fifo_fg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/sync_fifo_fg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/basic_sfifo_fg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/blk_mem_gen_wrapper.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/addsub.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_bit.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr_ai.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/down_counter.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/eval_timer.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/inferred_lut4.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer128.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_mirror128.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg2.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_bits.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder_bit.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_bit.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_top.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter_top.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_dpram_select.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_mask.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl16_fifo.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo2.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo3.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/valid_be.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_with_enable_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/muxf_struct_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/cntr_incr_decr_addn_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_i_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/compare_vectors_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate_f.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/address_decoder.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/axi_lite_ipif.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_rdmux.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_wr_demux.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_skid2mm_buf.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_skid_buf.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_first_stb_offset.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_stbs_set.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_strb_gen.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_fifo.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_pcc.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_addr_cntl.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_rddata_cntl.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_rd_status_cntl.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_wrdata_cntl.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_wr_status_cntl.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_reset.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_cmd_status.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_rd_wr_cntlr.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_rd_llink.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst_wr_llink.vhd \
C:/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_master_burst_v1_00_a/hdl/vhdl/axi_master_burst.vhd \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ipif_burst.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/pll_50M.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ch_top.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/ch_abt.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/page_buffer.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/dpram_8x40_32x10.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/dpram_8x2198_64x256.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/encoder_ctl.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/encoder.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/parallel_m_lfs_XOR.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/serial_m_lfs_XOR.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder_ctl.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/decoder.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/received_message_buffer.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/Chien_search.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/cs_evaluation_matrices.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/parallel_FFM_gate.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/partial_FFM_gate.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/key_equation_solver.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_DC_2MAXodr.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_DC_NMLodr.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_ELU_eMAXodr.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_ELU_MINodr.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_ELU_NMLodr.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/PE_ELU_sMINodr.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sc_deviders_p_lfs_XOR.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sc_deviders_s_lfs_XOR.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sc_evaluation_matrices.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/syndrome_calculator.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/way_top.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_top.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/nand_reset.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/nand_status.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_setting.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_op.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_top.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_sp.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_read_dt.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_prog.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/verilog/sync_status.v \
pcores/sync_ch_ctl_bl16_v1_00_a/hdl/vhdl/sync_ch_ctl_bl16.vhd \
pcores/pcie_status_check_v1_00_a/hdl/verilog/user_logic.v \
pcores/pcie_status_check_v1_00_a/hdl/vhdl/pcie_status_check.vhd
WRAPPER_NGC_FILES = implementation/system_sync_ch_ctl_bl16_3_wrapper.ngc \
implementation/system_sync_ch_ctl_bl16_2_wrapper.ngc \
implementation/system_sync_ch_ctl_bl16_1_wrapper.ngc \
implementation/system_sync_ch_ctl_bl16_0_wrapper.ngc \
implementation/system_processing_system7_0_wrapper.ngc \
implementation/system_axi_interconnect_hp3_wrapper.ngc \
implementation/system_axi_interconnect_hp2_wrapper.ngc \
implementation/system_axi_cdma_0_wrapper.ngc \
implementation/system_axi_bram_ctrl_0_bram_block_wrapper.ngc \
implementation/system_axi_bram_ctrl_0_wrapper.ngc \
implementation/system_axi4lite_gp0_wrapper.ngc \
implementation/system_axi4_1_wrapper.ngc \
implementation/system_axi4_0_wrapper.ngc \
implementation/system_pcie_diff_clk_i_wrapper.ngc \
implementation/system_pci_express_wrapper.ngc \
implementation/system_pcie_status_check_0_wrapper.ngc
POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
SYSTEM_BIT = implementation/$(SYSTEM).bit
DOWNLOAD_BIT = implementation/download.bit
SYSTEM_ACE = implementation/$(SYSTEM).ace
UCF_FILE = data\system.ucf
BMM_FILE = implementation/$(SYSTEM).bmm
BITGEN_UT_FILE = etc/bitgen.ut
XFLOW_OPT_FILE = etc/fast_runtime.opt
XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
XPLORER_DEPENDENCY = __xps/xplorer.opt
XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
SDK_EXPORT_DIR = SDK\SDK_Export\hw
SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm
SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)