system.mhs

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.7 Build EDK_P.20131013
# Thu Oct 16 01:03:41 2014
# Target Board:  xilinx.com zc706 Rev B
# Family:    zynq
# Device:    xc7z045
# Package:   ffg900
# Speed Grade:  -2
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT PCI_Express_pci_exp_txp = PCI_Express_pci_exp_txp, DIR = O, VEC = [0:0]
 PORT PCI_Express_pci_exp_txn = PCI_Express_pci_exp_txn, DIR = O, VEC = [0:0]
 PORT PCI_Express_pci_exp_rxp = PCI_Express_pci_exp_rxp, DIR = I, VEC = [0:0]
 PORT PCI_Express_pci_exp_rxn = PCI_Express_pci_exp_rxn, DIR = I, VEC = [0:0]
 PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
 PORT processing_system7_0_PS_SRSTB = processing_system7_0_PS_SRSTB, DIR = I
 PORT processing_system7_0_PS_CLK = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_PS_PORB = processing_system7_0_PS_PORB, DIR = I
 PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
 PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
 PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
 PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
 PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
 PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
 PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
 PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
 PORT PCIe_Diff_Clk_P = PCIe_Diff_Clk_P, DIR = I, SIGIS = CLK
 PORT PCIe_Diff_Clk_N = PCIe_Diff_Clk_N, DIR = I, SIGIS = CLK
 PORT SSD_CH0_DQ = sync_ch_ctl_bl16_0_SSD_DQ, DIR = IO, VEC = [7:0]
 PORT SSD_CH0_CLE = sync_ch_ctl_bl16_0_SSD_CLE, DIR = O
 PORT SSD_CH0_ALE = sync_ch_ctl_bl16_0_SSD_ALE, DIR = O
 PORT SSD_CH0_CEN = sync_ch_ctl_bl16_0_SSD_CEN, DIR = O, VEC = [7:0]
 PORT SSD_CH0_CLK = sync_ch_ctl_bl16_0_SSD_CLK, DIR = O
 PORT SSD_CH0_WRN = sync_ch_ctl_bl16_0_SSD_WRN, DIR = O
 PORT SSD_CH0_WPN = sync_ch_ctl_bl16_0_SSD_WPN, DIR = O
 PORT SSD_CH0_RB = sync_ch_ctl_bl16_0_SSD_RB, DIR = I, VEC = [7:0]
 PORT SSD_CH0_DQS = sync_ch_ctl_bl16_0_SSD_DQS, DIR = IO
 PORT SSD_CH1_DQ = sync_ch_ctl_bl16_1_SSD_DQ, DIR = IO, VEC = [7:0]
 PORT SSD_CH1_CLE = sync_ch_ctl_bl16_1_SSD_CLE, DIR = O
 PORT SSD_CH1_ALE = sync_ch_ctl_bl16_1_SSD_ALE, DIR = O
 PORT SSD_CH1_CEN = sync_ch_ctl_bl16_1_SSD_CEN, DIR = O, VEC = [7:0]
 PORT SSD_CH1_CLK = sync_ch_ctl_bl16_1_SSD_CLK, DIR = O
 PORT SSD_CH1_WRN = sync_ch_ctl_bl16_1_SSD_WRN, DIR = O
 PORT SSD_CH1_WPN = sync_ch_ctl_bl16_1_SSD_WPN, DIR = O
 PORT SSD_CH1_RB = sync_ch_ctl_bl16_1_SSD_RB, DIR = I, VEC = [7:0]
 PORT SSD_CH1_DQS = sync_ch_ctl_bl16_1_SSD_DQS, DIR = IO
 PORT SSD_CH2_DQ = sync_ch_ctl_bl16_2_SSD_DQ, DIR = IO, VEC = [7:0]
 PORT SSD_CH2_CLE = sync_ch_ctl_bl16_2_SSD_CLE, DIR = O
 PORT SSD_CH2_ALE = sync_ch_ctl_bl16_2_SSD_ALE, DIR = O
 PORT SSD_CH2_CEN = sync_ch_ctl_bl16_2_SSD_CEN, DIR = O, VEC = [7:0]
 PORT SSD_CH2_CLK = sync_ch_ctl_bl16_2_SSD_CLK, DIR = O
 PORT SSD_CH2_WRN = sync_ch_ctl_bl16_2_SSD_WRN, DIR = O
 PORT SSD_CH2_WPN = sync_ch_ctl_bl16_2_SSD_WPN, DIR = O
 PORT SSD_CH2_RB = sync_ch_ctl_bl16_2_SSD_RB, DIR = I, VEC = [7:0]
 PORT SSD_CH2_DQS = sync_ch_ctl_bl16_2_SSD_DQS, DIR = IO
 PORT SSD_CH3_DQ = sync_ch_ctl_bl16_3_SSD_DQ, DIR = IO, VEC = [7:0]
 PORT SSD_CH3_CLE = sync_ch_ctl_bl16_3_SSD_CLE, DIR = O
 PORT SSD_CH3_ALE = sync_ch_ctl_bl16_3_SSD_ALE, DIR = O
 PORT SSD_CH3_CEN = sync_ch_ctl_bl16_3_SSD_CEN, DIR = O, VEC = [7:0]
 PORT SSD_CH3_CLK = sync_ch_ctl_bl16_3_SSD_CLK, DIR = O
 PORT SSD_CH3_WRN = sync_ch_ctl_bl16_3_SSD_WRN, DIR = O
 PORT SSD_CH3_WPN = sync_ch_ctl_bl16_3_SSD_WPN, DIR = O
 PORT SSD_CH3_RB = sync_ch_ctl_bl16_3_SSD_RB, DIR = I, VEC = [7:0]
 PORT SSD_CH3_DQS = sync_ch_ctl_bl16_3_SSD_DQS, DIR = IO
 PORT processing_system7_0_UART0_RX_pin = processing_system7_0_UART0_RX, DIR = I


BEGIN sync_ch_ctl_bl16
 PARAMETER INSTANCE = sync_ch_ctl_bl16_3
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x66e00000
 PARAMETER C_HIGHADDR = 0x66e0ffff
 BUS_INTERFACE M_AXI = axi_interconnect_HP3
 BUS_INTERFACE S_AXI = axi4lite_GP0
 PORT SSD_CLK_100M = processing_system7_0_FCLK_CLK2
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK2
 PORT SSD_CLK_200M = processing_system7_0_FCLK_CLK3
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT SSD_DQ = sync_ch_ctl_bl16_3_SSD_DQ
 PORT SSD_CLE = sync_ch_ctl_bl16_3_SSD_CLE
 PORT SSD_ALE = sync_ch_ctl_bl16_3_SSD_ALE
 PORT SSD_CEN = sync_ch_ctl_bl16_3_SSD_CEN
 PORT SSD_CLK = sync_ch_ctl_bl16_3_SSD_CLK
 PORT SSD_WRN = sync_ch_ctl_bl16_3_SSD_WRN
 PORT SSD_WPN = sync_ch_ctl_bl16_3_SSD_WPN
 PORT SSD_RB = sync_ch_ctl_bl16_3_SSD_RB
 PORT SSD_DQS = sync_ch_ctl_bl16_3_SSD_DQS
 PORT SSD_RSTN = processing_system7_0_M_AXI_GP0_ARESETN
END

BEGIN sync_ch_ctl_bl16
 PARAMETER INSTANCE = sync_ch_ctl_bl16_2
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x66e20000
 PARAMETER C_HIGHADDR = 0x66e2ffff
 BUS_INTERFACE M_AXI = axi_interconnect_HP3
 BUS_INTERFACE S_AXI = axi4lite_GP0
 PORT SSD_CLK_100M = processing_system7_0_FCLK_CLK2
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK2
 PORT SSD_CLK_200M = processing_system7_0_FCLK_CLK3
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT SSD_DQ = sync_ch_ctl_bl16_2_SSD_DQ
 PORT SSD_CLE = sync_ch_ctl_bl16_2_SSD_CLE
 PORT SSD_ALE = sync_ch_ctl_bl16_2_SSD_ALE
 PORT SSD_CEN = sync_ch_ctl_bl16_2_SSD_CEN
 PORT SSD_CLK = sync_ch_ctl_bl16_2_SSD_CLK
 PORT SSD_WRN = sync_ch_ctl_bl16_2_SSD_WRN
 PORT SSD_WPN = sync_ch_ctl_bl16_2_SSD_WPN
 PORT SSD_RB = sync_ch_ctl_bl16_2_SSD_RB
 PORT SSD_DQS = sync_ch_ctl_bl16_2_SSD_DQS
 PORT SSD_RSTN = processing_system7_0_M_AXI_GP0_ARESETN
END

BEGIN sync_ch_ctl_bl16
 PARAMETER INSTANCE = sync_ch_ctl_bl16_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x66e40000
 PARAMETER C_HIGHADDR = 0x66e4ffff
 BUS_INTERFACE M_AXI = axi_interconnect_HP2
 BUS_INTERFACE S_AXI = axi4lite_GP0
 PORT SSD_CLK_100M = processing_system7_0_FCLK_CLK1
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK1
 PORT SSD_CLK_200M = processing_system7_0_FCLK_CLK3
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT SSD_DQ = sync_ch_ctl_bl16_1_SSD_DQ
 PORT SSD_CLE = sync_ch_ctl_bl16_1_SSD_CLE
 PORT SSD_ALE = sync_ch_ctl_bl16_1_SSD_ALE
 PORT SSD_CEN = sync_ch_ctl_bl16_1_SSD_CEN
 PORT SSD_CLK = sync_ch_ctl_bl16_1_SSD_CLK
 PORT SSD_WRN = sync_ch_ctl_bl16_1_SSD_WRN
 PORT SSD_WPN = sync_ch_ctl_bl16_1_SSD_WPN
 PORT SSD_RB = sync_ch_ctl_bl16_1_SSD_RB
 PORT SSD_DQS = sync_ch_ctl_bl16_1_SSD_DQS
 PORT SSD_RSTN = processing_system7_0_M_AXI_GP0_ARESETN
END

BEGIN sync_ch_ctl_bl16
 PARAMETER INSTANCE = sync_ch_ctl_bl16_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x66e60000
 PARAMETER C_HIGHADDR = 0x66e6ffff
 BUS_INTERFACE M_AXI = axi_interconnect_HP2
 BUS_INTERFACE S_AXI = axi4lite_GP0
 PORT SSD_CLK_100M = processing_system7_0_FCLK_CLK1
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK1
 PORT SSD_CLK_200M = processing_system7_0_FCLK_CLK3
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT SSD_DQ = sync_ch_ctl_bl16_0_SSD_DQ
 PORT SSD_CLE = sync_ch_ctl_bl16_0_SSD_CLE
 PORT SSD_ALE = sync_ch_ctl_bl16_0_SSD_ALE
 PORT SSD_CEN = sync_ch_ctl_bl16_0_SSD_CEN
 PORT SSD_CLK = sync_ch_ctl_bl16_0_SSD_CLK
 PORT SSD_WRN = sync_ch_ctl_bl16_0_SSD_WRN
 PORT SSD_WPN = sync_ch_ctl_bl16_0_SSD_WPN
 PORT SSD_RB = sync_ch_ctl_bl16_0_SSD_RB
 PORT SSD_DQS = sync_ch_ctl_bl16_0_SSD_DQS
 PORT SSD_RSTN = processing_system7_0_M_AXI_GP0_ARESETN
END

BEGIN processing_system7
 PARAMETER INSTANCE = processing_system7_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF
 PARAMETER C_USE_M_AXI_GP0 = 1
 PARAMETER C_USE_S_AXI_HP0 = 1
 PARAMETER C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1
 PARAMETER C_INTERCONNECT_S_AXI_HP0_MASTERS = axi_cdma_0.M_AXI_SG & axi_cdma_0.M_AXI
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 0
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 0
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 1
 PARAMETER C_EMIO_GPIO_WIDTH = 64
 PARAMETER C_EN_QSPI = 1
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 0
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 1
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 1
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 1
 PARAMETER C_EN_SDIO1 = 0
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 0
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 1
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 1
 PARAMETER C_EN_USB1 = 0
 PARAMETER C_EN_WDT = 1
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 1
 PARAMETER C_FCLK_CLK0_FREQ = 100000000
 PARAMETER C_FCLK_CLK1_FREQ = 100000000
 PARAMETER C_FCLK_CLK2_FREQ = 100000000
 PARAMETER C_FCLK_CLK3_FREQ = 200000000
 PARAMETER C_USE_S_AXI_HP1 = 1
 PARAMETER C_INTERCONNECT_S_AXI_HP1_MASTERS = PCI_Express.M_AXI
 PARAMETER C_USE_S_AXI_HP2 = 1
 PARAMETER C_USE_S_AXI_HP3 = 1
 PARAMETER C_INTERCONNECT_S_AXI_HP2_MASTERS = sync_ch_ctl_bl16_0.M_AXI & sync_ch_ctl_bl16_1.M_AXI
 PARAMETER C_INTERCONNECT_S_AXI_HP3_MASTERS = sync_ch_ctl_bl16_2.M_AXI & sync_ch_ctl_bl16_3.M_AXI
 PARAMETER C_USE_M_AXI_GP1 = 0
 PARAMETER C_INTERCONNECT_M_AXI_GP1_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_GP1_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_GP1_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_GP1_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_GP1_B_REGISTER = 1
 BUS_INTERFACE M_AXI_GP0 = axi4lite_GP0
 BUS_INTERFACE S_AXI_HP0 = axi4_0
 BUS_INTERFACE S_AXI_HP1 = axi4_1
 BUS_INTERFACE S_AXI_HP2 = axi_interconnect_HP2
 BUS_INTERFACE S_AXI_HP3 = axi_interconnect_HP3
 PORT MIO = processing_system7_0_MIO
 PORT PS_SRSTB = processing_system7_0_PS_SRSTB
 PORT PS_CLK = processing_system7_0_PS_CLK
 PORT PS_PORB = processing_system7_0_PS_PORB
 PORT DDR_Clk = processing_system7_0_DDR_Clk
 PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
 PORT DDR_CKE = processing_system7_0_DDR_CKE
 PORT DDR_CS_n = processing_system7_0_DDR_CS_n
 PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
 PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
 PORT DDR_WEB = processing_system7_0_DDR_WEB
 PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
 PORT DDR_Addr = processing_system7_0_DDR_Addr
 PORT DDR_ODT = processing_system7_0_DDR_ODT
 PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
 PORT DDR_DQ = processing_system7_0_DDR_DQ
 PORT DDR_DM = processing_system7_0_DDR_DM
 PORT DDR_DQS = processing_system7_0_DDR_DQS
 PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
 PORT DDR_VRN = processing_system7_0_DDR_VRN
 PORT DDR_VRP = processing_system7_0_DDR_VRP
 PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
 PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
 PORT S_AXI_HP0_RACOUNT = processing_system_0_S_AXI_HP0_RACOUNT
 PORT S_AXI_HP0_ACLK = processing_system7_0_FCLK_CLK0
 PORT S_AXI_HP1_RACOUNT = processing_system_0_S_AXI_HP1_RACOUNT
 PORT S_AXI_HP1_ACLK = processing_system7_0_FCLK_CLK0
 PORT IRQ_F2P = axi_cdma_0_cdma_introut
 PORT FCLK_CLK1 = processing_system7_0_FCLK_CLK1
 PORT FCLK_CLK2 = processing_system7_0_FCLK_CLK2
 PORT FCLK_CLK3 = processing_system7_0_FCLK_CLK3
 PORT S_AXI_HP3_ARESETN = processing_system7_0_S_AXI_HP3_ARESETN
 PORT S_AXI_HP2_ARESETN = processing_system7_0_S_AXI_HP2_ARESETN
 PORT S_AXI_HP2_ACLK = processing_system7_0_FCLK_CLK1
 PORT S_AXI_HP3_ACLK = processing_system7_0_FCLK_CLK2
 PORT M_AXI_GP0_ARESETN = processing_system7_0_M_AXI_GP0_ARESETN
 PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
 PORT FCLK_RESET1_N = processing_system7_0_FCLK_RESET1_N
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_HP3
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ARESETN = processing_system7_0_S_AXI_HP3_ARESETN
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK2
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_HP2
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ARESETN = processing_system7_0_S_AXI_HP2_ARESETN
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK1
END

BEGIN axi_cdma
 PARAMETER INSTANCE = axi_cdma_0
 PARAMETER HW_VER = 3.04.a
 PARAMETER C_M_AXI_DATA_WIDTH = 64
 PARAMETER C_M_AXI_MAX_BURST_LEN = 16
 PARAMETER C_INCLUDE_SG = 1
 PARAMETER C_BASEADDR = 0x40200000
 PARAMETER C_HIGHADDR = 0x4020ffff
 BUS_INTERFACE S_AXI_LITE = axi4lite_GP0
 BUS_INTERFACE M_AXI = axi4_0
 BUS_INTERFACE M_AXI_SG = axi4_0
 PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0
 PORT m_axi_aclk = processing_system7_0_FCLK_CLK0
 PORT cdma_introut = axi_cdma_0_cdma_introut
END

BEGIN bram_block
 PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
 BUS_INTERFACE PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = axi_bram_ctrl_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_S_AXI_BASEADDR = 0x66e10000
 PARAMETER C_S_AXI_HIGHADDR = 0x66e1ffff
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta
 BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb
 BUS_INTERFACE S_AXI = axi4lite_GP0
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_GP0
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_1
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
 PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_0
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
 PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

BEGIN util_ds_buf
 PARAMETER INSTANCE = PCIe_Diff_Clk_I
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BUF_TYPE = IBUFDSGTE
 PORT IBUF_DS_P = PCIe_Diff_Clk_P
 PORT IBUF_DS_N = PCIe_Diff_Clk_N
 PORT IBUF_OUT = PCIe_Diff_Clk
END

BEGIN axi_pcie
 PARAMETER INSTANCE = PCI_Express
 PARAMETER HW_VER = 1.09.a
 PARAMETER C_S_AXI_ID_WIDTH = 2
 PARAMETER C_S_AXI_DATA_WIDTH = 64
 PARAMETER C_M_AXI_DATA_WIDTH = 64
 PARAMETER C_NO_OF_LANES = 1
 PARAMETER C_MAX_LINK_SPEED = 1
 PARAMETER C_DEVICE_ID = 0x0505
 PARAMETER C_VENDOR_ID = 0x10EE
 PARAMETER C_CLASS_CODE = 0x058000
 PARAMETER C_REF_CLK_FREQ = 0
 PARAMETER C_PCIE_CAP_SLOT_IMPLEMENTED = 0
 PARAMETER C_INTERRUPT_PIN = 1
 PARAMETER C_COMP_TIMEOUT = 1
 PARAMETER C_INCLUDE_RC = 0
 PARAMETER C_S_AXI_SUPPORTS_NARROW_BURST = 0
 PARAMETER C_INCLUDE_BAROFFSET_REG = 1
 PARAMETER C_AXIBAR_NUM = 1
 PARAMETER C_AXIBAR2PCIEBAR_0 = 0x00000000
 PARAMETER C_AXIBAR_AS_0 = 1
 PARAMETER C_PCIEBAR_NUM = 1
 PARAMETER C_PCIEBAR_AS = 0
 PARAMETER C_PCIEBAR_LEN_0 = 25
 PARAMETER C_PCIEBAR2AXIBAR_0 = 0x08000000
 PARAMETER C_S_AXI_CTL_ACLK_FREQ_HZ = 125000000
 PARAMETER C_AXI_ACLK_FREQ_HZ = 125000000
 PARAMETER C_FAMILY = zynq
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi_cdma_0.M_AXI
 PARAMETER C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC = 1
 PARAMETER C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC = 1
 PARAMETER C_AXIBAR_0 = 0x65c20000
 PARAMETER C_AXIBAR_HIGHADDR_0 = 0x65c2ffff
 PARAMETER C_BASEADDR = 0x65c00000
 PARAMETER C_HIGHADDR = 0x65c0ffff
 BUS_INTERFACE S_AXI_CTL = axi4lite_GP0
 BUS_INTERFACE M_AXI = axi4_1
 BUS_INTERFACE S_AXI = axi4_0
 PORT pci_exp_txp = PCI_Express_pci_exp_txp
 PORT pci_exp_txn = PCI_Express_pci_exp_txn
 PORT pci_exp_rxp = PCI_Express_pci_exp_rxp
 PORT pci_exp_rxn = PCI_Express_pci_exp_rxn
 PORT axi_ctl_aclk = axi_ctl_aclk_out
 PORT axi_aclk = axi_aclk_out
 PORT axi_aclk_out = axi_aclk_out
 PORT axi_ctl_aclk_out = axi_ctl_aclk_out
 PORT REFCLK = PCIe_Diff_Clk
 PORT mmcm_lock = PCI_Express_mmcm_lock
END

BEGIN pcie_status_check
 PARAMETER INSTANCE = pcie_status_check_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x7a000000
 PARAMETER C_HIGHADDR = 0x7a00ffff
 BUS_INTERFACE S_AXI = axi4lite_GP0
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT pcie_mmcm_lock = PCI_Express_mmcm_lock
END