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comparch.micro.channels.md

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C++ links: computer architecture - microarchitectural channels

See also: Computer Architecture

  • Leakage channels: side channels (accidental), covert channels (deliberate).
  • Storage channels (functional behavior), timing channels (temporal behavior).
  • Timing-based channels (operations timing), access-based channels (direct information access), trace-based channels (program execution measurement).

Contents



General


Defense, Mitigation, Protection

Defense - Branch Predictor

Defense - Cache

Defense - Floating Point Unit (FPU)

Defense - Hardware Design & Verification

Defense - Software

Defense - Software - Compilation and Programming Languages

Defense - Speculation


Arithmetic Logic Unit (ALU)


Branch Predictor


Cache

Cache (2020)

Cache (2019)

  • Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World
    • IEEE Symposium on Security and Privacy (SP) 2019
    • Mengjia Yan, Read Sprabery, Bhargava Gopireddy, Christopher Fletcher, Roy Campbell, Josep Torrellas
    • http://iacoma.cs.uiuc.edu/iacoma-papers/ssp19.pdf
    • http://iacoma.cs.uiuc.edu/iacoma-papers/PRES/present_ssp19.pdf
    • http://iacoma.cs.uiuc.edu/iacoma-papers/PRES/present_HASP18.pptx
      • "We design the first cross-core Prime+Probe attack on non-inclusive caches."
      • "Using our Eviction Sets, we reverse engineer the directory structure in Skylake-X, and identify vulnerabilities in directory design that can be leveraged by cache-based side channel attacks."
      • "Based on our EV construction results, we are able to reverse engineer part of the slice hash function in the Intel Skylake-X processor. Our goal here is to show that the slice hash function is not a simple XOR operation of selected physical address bits. This design is significantly different from the one in previous Intel processors such as SandyBridge and IvyBridge. Considering that all of the previous works on reverse-engineering slice hash functions, rely on the use of a simple XOR hash function, our results identify the need for more advanced reverse-engineering approaches."
  • Cache-based Side Channels: Modern Attacks and Defenses
  • The 9 Lives of Bleichenbacher's CAT: New Cache ATtacks on TLS Implementations
    • IEEE Symposium on Security & Privacy 2019
    • Eyal Ronen, Robert Gillham, Daniel Genkin, Adi Shamir, David Wong, Yuval Yarom
    • vhttps://eprint.iacr.org/2018/1173
    • https://eyalro.net/project/cat.html
  • Unveiling your keystrokes: A Cache-based Side-channel Attack on Graphics Libraries

Cache (2018)

Cache (2017)

Cache (2016)

Cache (2015)

Cache (2007-2014)

Cache - Data-Direct I/O (DDIO)


DRAM


Electromagnetic (EM) Emanations


Floating Point Unit (FPU)


FPGA

FPGA remote attacks

(through (partial) access on configuration/bitstream)

FPGA local attacks

(with physical access or within close proximity)

FPGA attacks countermeasures


GPU


Interrupts


Keyboard


Magnetic


Memory Bus


Memory Order Buffer (MOB)


Memory Management Unit (MMU)


Power


Prefetch


Pseudo-Random Number Generator (PRNG)


Return Stack Buffer (RSB)


SMT


Speculation

Transient execution attacks
Classification tree - http://transient.fail/
Proof-of-Concept Repository - https://github.com/IAIK/transientfail/

Refined Speculative Execution Terminology
https://software.intel.com/security-software-guidance/insights/refined-speculative-execution-terminology


Store Buffer

  • Fallout: Reading Kernel Writes From User Space
    • 2019 arXiv
    • Marina Minkin, Daniel Moghimi, Moritz Lipp, Michael Schwarz, Jo Van Bulck, Daniel Genkin, Daniel Gruss, Frank Piessens, Berk Sunar, Yuval Yarom
    • https://arxiv.org/abs/1905.12701
    • CVE-2018-12126 - Microarchitectural Store Buffer Data Sampling (MSBDS) - Fallout

Thermal


Translation Lookaside Buffer (TLB)


Trusted Execution Environments (TEEs)

Arm TrustZone

Intel SGX


TSX


Talks

2020

2019

2018

2017

2016

2015

2014

2009