Can we get an an implementation of this mapper in Verilog so that it'll run on a PowerPak? I'm aware that the PowerPak has only 544 KiB of RAM, but perhaps it could be made to work by using half of the 512 KiB of RAM that most mappers allocate to PRG ROM.
Can we get an an implementation of this mapper in Verilog so that it'll run on a PowerPak? I'm aware that the PowerPak has only 544 KiB of RAM, but perhaps it could be made to work by using half of the 512 KiB of RAM that most mappers allocate to PRG ROM.