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Bone_JTAG_pg3.sch
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T 42800 54500 5 10 0 0 180 6 1
device=RESISTOR
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L 42900 54700 42800 54900 3 0 0 0 -1 -1
L 43000 54900 42900 54700 3 0 0 0 -1 -1
L 43100 54700 43000 54900 3 0 0 0 -1 -1
]
{
T 42800 54500 5 10 0 0 180 6 1
device=RESISTOR
T 42700 54900 5 10 1 1 0 6 1
refdes=R307
T 43500 54900 5 10 1 1 0 6 1
value=100
T 42500 54900 5 10 0 0 270 2 1
footprint=0603
}
C 42500 54300 1 180 1 EMBEDDEDresistor-1.sym
[
T 42500 54300 8 10 0 1 180 6 1
class=DISCRETE
T 42500 54300 8 10 0 1 180 6 1
pins=2
T 42700 54000 8 10 0 1 180 6 1
refdes=R?
L 42701 54100 42650 54200 3 0 0 0 -1 -1
P 42500 54200 42652 54200 1 0 0
{
T 42600 54150 5 8 0 1 180 6 1
pinnumber=1
T 42600 54150 5 8 0 0 180 6 1
pinseq=1
T 42600 54150 5 8 0 1 180 6 1
pinlabel=1
T 42600 54150 5 8 0 1 180 6 1
pintype=pas
}
P 43400 54200 43250 54200 1 0 0
{
T 43300 54150 5 8 0 1 180 6 1
pinnumber=2
T 43300 54150 5 8 0 0 180 6 1
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T 43300 54150 5 8 0 1 180 6 1
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T 43300 54150 5 8 0 1 180 6 1
pintype=pas
}
L 43200 54300 43250 54200 3 0 0 0 -1 -1
L 43100 54100 43200 54300 3 0 0 0 -1 -1
T 42800 53900 5 10 0 0 180 6 1
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L 42800 54300 42700 54100 3 0 0 0 -1 -1
L 42900 54100 42800 54300 3 0 0 0 -1 -1
L 43000 54300 42900 54100 3 0 0 0 -1 -1
L 43100 54100 43000 54300 3 0 0 0 -1 -1
]
{
T 42800 53900 5 10 0 0 180 6 1
device=RESISTOR
T 42700 54300 5 10 1 1 0 6 1
refdes=R308
T 43500 54300 5 10 1 1 0 6 1
value=100
T 42500 54300 5 10 0 0 270 2 1
footprint=0603
}
N 42200 55100 42500 55100 4
N 42500 54800 42200 54800 4
N 42500 54200 42200 54200 4
N 42200 53600 42200 52100 4
N 42500 52300 42500 52100 4
C 42500 43000 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 41600 43200 5 10 0 0 90 0 1
symversion=0.1
T 41400 43200 5 10 0 0 90 0 1
numslots=0
T 41200 43200 5 10 0 0 90 0 1
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T 42000 43200 8 10 0 1 90 0 1
refdes=C?
T 41800 43200 5 10 0 0 90 0 1
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L 42300 43400 42300 43200 3 0 0 0 -1 -1
L 42300 43700 42300 43500 3 0 0 0 -1 -1
L 42100 43500 42500 43500 3 0 0 0 -1 -1
L 42100 43400 42500 43400 3 0 0 0 -1 -1
P 42300 43900 42300 43700 1 0 0
{
T 42250 43750 5 8 0 1 90 0 1
pinnumber=2
T 42350 43750 5 8 0 1 90 2 1
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T 42300 43700 9 8 0 1 90 6 1
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T 42300 43700 5 8 0 1 90 8 1
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}
P 42300 43000 42300 43200 1 0 0
{
T 42250 43150 5 8 0 1 90 6 1
pinnumber=1
T 42350 43150 5 8 0 1 90 8 1
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T 42300 43200 9 8 0 1 90 0 1
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T 42300 43200 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 41800 43200 5 10 0 0 90 0 1
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T 42100 43600 5 10 1 1 180 0 1
refdes=C301
T 41600 43200 5 10 0 0 90 0 1
symversion=0.1
T 41600 43200 5 10 1 1 0 0 1
value=0.1uf
T 42500 43000 5 10 0 0 0 0 1
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}
C 44300 43000 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 43400 43200 5 10 0 0 90 0 1
symversion=0.1
T 43200 43200 5 10 0 0 90 0 1
numslots=0
T 43000 43200 5 10 0 0 90 0 1
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T 43800 43200 8 10 0 1 90 0 1
refdes=C?
T 43600 43200 5 10 0 0 90 0 1
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L 44100 43400 44100 43200 3 0 0 0 -1 -1
L 44100 43700 44100 43500 3 0 0 0 -1 -1
L 43900 43500 44300 43500 3 0 0 0 -1 -1
L 43900 43400 44300 43400 3 0 0 0 -1 -1
P 44100 43900 44100 43700 1 0 0
{
T 44050 43750 5 8 0 1 90 0 1
pinnumber=2
T 44150 43750 5 8 0 1 90 2 1
pinseq=2
T 44100 43700 9 8 0 1 90 6 1
pinlabel=2
T 44100 43700 5 8 0 1 90 8 1
pintype=pas
}
P 44100 43000 44100 43200 1 0 0
{
T 44050 43150 5 8 0 1 90 6 1
pinnumber=1
T 44150 43150 5 8 0 1 90 8 1
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T 44100 43200 9 8 0 1 90 0 1
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T 44100 43200 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 43600 43200 5 10 0 0 90 0 1
device=CAPACITOR
T 43900 43600 5 10 1 1 180 0 1
refdes=C303
T 43400 43200 5 10 0 0 90 0 1
symversion=0.1
T 43400 43200 5 10 1 1 0 0 1
value=0.1uf
T 44300 43000 5 10 0 0 0 0 1
footprint=0603
}
C 43400 43000 1 90 0 EMBEDDEDcapacitor-1.sym
[
T 42500 43200 5 10 0 0 90 0 1
symversion=0.1
T 42300 43200 5 10 0 0 90 0 1
numslots=0
T 42100 43200 5 10 0 0 90 0 1
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T 42900 43200 8 10 0 1 90 0 1
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T 42700 43200 5 10 0 0 90 0 1
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L 43200 43400 43200 43200 3 0 0 0 -1 -1
L 43200 43700 43200 43500 3 0 0 0 -1 -1
L 43000 43500 43400 43500 3 0 0 0 -1 -1
L 43000 43400 43400 43400 3 0 0 0 -1 -1
P 43200 43900 43200 43700 1 0 0
{
T 43150 43750 5 8 0 1 90 0 1
pinnumber=2
T 43250 43750 5 8 0 1 90 2 1
pinseq=2
T 43200 43700 9 8 0 1 90 6 1
pinlabel=2
T 43200 43700 5 8 0 1 90 8 1
pintype=pas
}
P 43200 43000 43200 43200 1 0 0
{
T 43150 43150 5 8 0 1 90 6 1
pinnumber=1
T 43250 43150 5 8 0 1 90 8 1
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T 43200 43200 9 8 0 1 90 0 1
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T 43200 43200 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 42700 43200 5 10 0 0 90 0 1
device=CAPACITOR
T 43000 43600 5 10 1 1 180 0 1
refdes=C302
T 42500 43200 5 10 0 0 90 0 1
symversion=0.1
T 42500 43200 5 10 1 1 0 0 1
value=0.1uf
T 43400 43000 5 10 0 0 0 0 1
footprint=0603
}
N 42300 43000 45000 43000 4
N 43200 43000 43200 42500 4
C 43100 42200 1 0 0 EMBEDDEDgnd-1.sym
[
T 43400 42250 8 10 0 0 0 0 1
net=GND:1
L 43180 42210 43220 42210 3 0 0 0 -1 -1
L 43155 42250 43245 42250 3 0 0 0 -1 -1
L 43100 42300 43300 42300 3 0 0 0 -1 -1
P 43200 42300 43200 42500 1 0 1
{
T 43258 42361 5 4 0 1 0 0 1
pinnumber=1
T 43258 42361 5 4 0 0 0 0 1
pinseq=1
T 43258 42361 5 4 0 1 0 0 1
pinlabel=1
T 43258 42361 5 4 0 1 0 0 1
pintype=pwr
}
]
C 43000 43900 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 43300 43900 8 8 0 0 0 0 1
net=+3.3V:1
T 43075 44150 9 8 1 0 0 0 1
+3.3V
L 43050 44100 43350 44100 3 0 0 0 -1 -1
P 43200 43900 43200 44100 1 0 0
{
T 43250 43950 5 6 0 1 0 0 1
pinnumber=1
T 43250 43950 5 6 0 0 0 0 1
pinseq=1
T 43250 43950 5 6 0 1 0 0 1
pinlabel=1
T 43250 43950 5 6 0 1 0 0 1
pintype=pwr
}
]
N 42300 43900 46000 43900 4
T 54300 40400 9 10 1 0 0 0 1
Bone JTAG Programmer/Debugger
T 54600 39800 9 10 1 0 0 0 1
3
T 56100 39800 9 10 1 0 0 0 1
3
T 58400 40100 9 10 1 0 0 0 1
0.97
C 56000 49000 1 0 0 EMBEDDEDoutput-1.sym
[
L 56700 49000 56200 49000 3 0 0 0 -1 -1
L 56800 49100 56700 49000 3 0 0 0 -1 -1
L 56700 49200 56800 49100 3 0 0 0 -1 -1
L 56200 49200 56700 49200 3 0 0 0 -1 -1
L 56200 49200 56200 49000 3 0 0 0 -1 -1
P 56000 49100 56200 49100 1 0 0
{
T 56250 49050 5 6 0 0 0 0 1
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T 56250 49050 5 6 0 1 0 0 1
pinnumber=1
}
T 56100 49300 5 10 0 0 0 0 1
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]
{
T 56100 49300 5 10 0 0 0 0 1
device=OUTPUT
T 56800 49000 5 10 1 1 0 0 1
value=Target_TDI
T 56000 49000 5 10 0 1 180 0 1
net=JC7:1
}
C 47000 47700 1 180 0 EMBEDDEDoutput-1.sym
[
P 47000 47600 46800 47600 1 0 0
{
T 46750 47650 5 6 0 0 180 0 1
pinseq=1
T 46750 47650 5 6 0 1 180 0 1
pinnumber=1
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L 46800 47500 46800 47700 3 0 0 0 -1 -1
L 46800 47500 46300 47500 3 0 0 0 -1 -1
L 46300 47500 46200 47600 3 0 0 0 -1 -1
L 46200 47600 46300 47700 3 0 0 0 -1 -1
L 46300 47700 46800 47700 3 0 0 0 -1 -1
T 46900 47400 5 10 0 0 180 0 1
device=OUTPUT
]
{
T 46900 47400 5 10 0 0 180 0 1
device=OUTPUT
T 45400 47500 5 10 1 1 0 0 1
value=GPIO1_6
T 47000 47700 5 10 0 1 0 0 1
net=JC2:1
}
C 47000 48200 1 180 0 EMBEDDEDoutput-1.sym
[
P 47000 48100 46800 48100 1 0 0
{
T 46750 48150 5 6 0 0 180 0 1
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T 46750 48150 5 6 0 1 180 0 1
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L 46800 48000 46800 48200 3 0 0 0 -1 -1
L 46800 48000 46300 48000 3 0 0 0 -1 -1
L 46300 48000 46200 48100 3 0 0 0 -1 -1
L 46200 48100 46300 48200 3 0 0 0 -1 -1
L 46300 48200 46800 48200 3 0 0 0 -1 -1
T 46900 47900 5 10 0 0 180 0 1
device=OUTPUT
]
{
T 46900 47900 5 10 0 0 180 0 1
device=OUTPUT
T 45400 48000 5 10 1 1 0 0 1
value=GPIO1_7
T 47000 48200 5 10 0 1 0 0 1
net=JC3:1
}
C 51600 44200 1 0 0 EMBEDDEDgnd-1.sym
[
T 51900 44250 8 10 0 0 0 0 1
net=GND:1
L 51680 44210 51720 44210 3 0 0 0 -1 -1
L 51655 44250 51745 44250 3 0 0 0 -1 -1
L 51600 44300 51800 44300 3 0 0 0 -1 -1
P 51700 44300 51700 44500 1 0 1
{
T 51758 44361 5 4 0 1 0 0 1
pinnumber=1
T 51758 44361 5 4 0 0 0 0 1
pinseq=1
T 51758 44361 5 4 0 1 0 0 1
pinlabel=1
T 51758 44361 5 4 0 1 0 0 1
pintype=pwr
}
]
C 56000 49500 1 0 0 EMBEDDEDoutput-1.sym
[
P 56000 49600 56200 49600 1 0 0
{
T 56250 49550 5 6 0 0 0 0 1
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T 56250 49550 5 6 0 1 0 0 1
pinnumber=1
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L 56200 49700 56200 49500 3 0 0 0 -1 -1
L 56200 49700 56700 49700 3 0 0 0 -1 -1
L 56700 49700 56800 49600 3 0 0 0 -1 -1
L 56800 49600 56700 49500 3 0 0 0 -1 -1
L 56700 49500 56200 49500 3 0 0 0 -1 -1
T 56100 49800 5 10 0 0 0 0 1
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]
{
T 56100 49800 5 10 0 0 0 0 1
device=OUTPUT
T 56800 49500 5 10 1 1 0 0 1
value=Target_TMS
T 56000 49500 5 10 0 1 180 0 1
net=SPI0_SCLK:1
}
C 49300 44500 1 90 1 EMBEDDEDoutput-1.sym
[
L 49300 43800 49300 44300 3 0 0 0 -1 -1
L 49200 43700 49300 43800 3 0 0 0 -1 -1
L 49100 43800 49200 43700 3 0 0 0 -1 -1
L 49100 44300 49100 43800 3 0 0 0 -1 -1
L 49100 44300 49300 44300 3 0 0 0 -1 -1
P 49200 44500 49200 44300 1 0 0
{
T 49250 44250 5 6 0 0 90 6 1
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T 49250 44250 5 6 0 1 90 6 1
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}
T 49000 44400 5 10 0 0 90 6 1
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]
{
T 49000 44400 5 10 0 0 90 6 1
device=OUTPUT
T 49300 43600 5 10 1 1 90 6 1
value=PRU0_16_I
T 49300 44500 5 10 0 1 270 6 1
net=GPMC_WEN:1
}
C 47000 50500 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 50500 46800 50500 3 0 0 0 -1 -1
L 46200 50600 46300 50500 3 0 0 0 -1 -1
L 46300 50700 46200 50600 3 0 0 0 -1 -1
L 46800 50700 46300 50700 3 0 0 0 -1 -1
L 46800 50700 46800 50500 3 0 0 0 -1 -1
P 47000 50600 46800 50600 1 0 0
{
T 46750 50550 5 6 0 0 0 6 1
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T 46750 50550 5 6 0 1 0 6 1
pinnumber=1
}
T 46900 50800 5 10 0 0 0 6 1
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]
{
T 46900 50800 5 10 0 0 0 6 1
device=OUTPUT
T 46100 50500 5 10 1 1 0 6 1
value=PRU0_14_O
T 47000 50500 5 10 0 1 180 6 1
net=GPMC_AD12:1
}
C 47000 50000 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 50000 46800 50000 3 0 0 0 -1 -1
L 46200 50100 46300 50000 3 0 0 0 -1 -1
L 46300 50200 46200 50100 3 0 0 0 -1 -1
L 46800 50200 46300 50200 3 0 0 0 -1 -1
L 46800 50200 46800 50000 3 0 0 0 -1 -1
P 47000 50100 46800 50100 1 0 0
{
T 46750 50050 5 6 0 1 0 6 1
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T 46750 50050 5 6 0 0 0 6 1
pinseq=1
}
T 46900 50300 5 10 0 0 0 6 1
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]
{
T 46900 50300 5 10 0 0 0 6 1
device=OUTPUT
T 46100 50000 5 10 1 1 0 6 1
value=PRU0_15_O
T 47000 50000 5 10 0 1 180 6 1
net=GPMC_AD13:1
}
C 47000 48500 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 48500 46800 48500 3 0 0 0 -1 -1
L 46200 48600 46300 48500 3 0 0 0 -1 -1
L 46300 48700 46200 48600 3 0 0 0 -1 -1
L 46800 48700 46300 48700 3 0 0 0 -1 -1
L 46800 48700 46800 48500 3 0 0 0 -1 -1
P 47000 48600 46800 48600 1 0 0
{
T 46750 48550 5 6 0 1 0 6 1
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T 46750 48550 5 6 0 0 0 6 1
pinseq=1
}
T 46900 48800 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 46900 48800 5 10 0 0 0 6 1
device=OUTPUT
T 46100 48500 5 10 1 1 0 6 1
value=GPIO1_2
T 47000 48500 5 10 0 1 180 6 1
net=GPMC_AD9:1
}
C 47000 49000 1 0 1 EMBEDDEDoutput-1.sym
[
L 46300 49000 46800 49000 3 0 0 0 -1 -1
L 46200 49100 46300 49000 3 0 0 0 -1 -1
L 46300 49200 46200 49100 3 0 0 0 -1 -1
L 46800 49200 46300 49200 3 0 0 0 -1 -1
L 46800 49200 46800 49000 3 0 0 0 -1 -1
P 47000 49100 46800 49100 1 0 0
{
T 46750 49050 5 6 0 0 0 6 1
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T 46750 49050 5 6 0 1 0 6 1
pinnumber=1
}
T 46900 49300 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 46900 49300 5 10 0 0 0 6 1
device=OUTPUT
T 46100 49000 5 10 1 1 0 6 1
value=GPIO1_3
T 47000 49000 5 10 0 1 180 6 1
net=GPMC_AD6:1
}
C 56000 50000 1 0 0 EMBEDDEDoutput-1.sym
[
T 56100 50300 5 10 0 0 0 0 1
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P 56000 50100 56200 50100 1 0 0
{
T 56250 50050 5 6 0 1 0 0 1
pinnumber=1
T 56250 50050 5 6 0 0 0 0 1
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}
L 56200 50200 56200 50000 3 0 0 0 -1 -1
L 56200 50200 56700 50200 3 0 0 0 -1 -1
L 56700 50200 56800 50100 3 0 0 0 -1 -1
L 56800 50100 56700 50000 3 0 0 0 -1 -1
L 56700 50000 56200 50000 3 0 0 0 -1 -1
]
{
T 56100 50300 5 10 0 0 0 0 1
device=OUTPUT
T 56800 50000 5 10 1 1 0 0 1
value=Target_Trst