@@ -1160,9 +1160,9 @@ impl<T> (T,) {}
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///
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/// Note that most common platforms will not support `f16` in hardware without enabling extra target
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/// features, with the notable exception of Apple Silicon (also known as M1, M2, etc.) processors.
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- /// Hardware support on x86-64 requires the avx512fp16 feature , while RISC-V requires Zhf.
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- /// Usually the fallback implementation will be to use `f32` hardware if it exists, and convert
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- /// between `f16` and `f32` when performing math.
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+ /// Hardware support on x86/x86 -64 requires the avx512fp16 or avx10.1 features , while RISC-V requires
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+ /// Zfh, and Arm/AArch64 requires FEAT_FP16. Usually the fallback implementation will be to use `f32`
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+ /// hardware if it exists, and convert between `f16` and `f32` when performing math.
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///
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/// *[See also the `std::f16::consts` module](crate::f16::consts).*
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///
@@ -1344,10 +1344,10 @@ mod prim_f64 {}
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/// quad-precision values][wikipedia] for more information.
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///
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/// Note that no platforms have hardware support for `f128` without enabling target specific features,
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- /// as for all instruction set architectures `f128` is considered an optional feature.
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- /// Only Power ISA ("PowerPC") and RISC-V specify it, and only certain microarchitectures
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- /// actually implement it. For x86-64 and AArch64, ISA support is not even specified,
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- /// so it will always be a software implementation significantly slower than `f64`.
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+ /// as for all instruction set architectures `f128` is considered an optional feature. Only Power ISA
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+ /// ("PowerPC") and RISC-V (via the Q extension) specify it, and only certain microarchitectures
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+ /// actually implement it. For x86-64 and AArch64, ISA support is not even specified, so it will always
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+ /// be a software implementation significantly slower than `f64`.
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///
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/// _Note: `f128` support is incomplete. Many platforms will not be able to link math functions. On
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/// x86 in particular, these functions do link but their results are always incorrect._
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