Merge pull request #2 from jakubcabal/dev

Merge version 1.2 of UART module to master.

Author: jakubcabal

README.md

@@ -36,16 +36,16 @@ USE_DEBOUNCER : boolean := True    -- enable/disable debouncer
 
 ## Table of resource usage summary:
 
-Use debouncer | Parity type | LE (LUT+FF) | LUT | FF | BRAM | Fmax
+Use debouncer | Parity type | LE (LUT+FF) | LUT | FF | M9k | Fmax
 :---:|:---:|:---:|:---:|:---:|:---:|:---:
-True | none | 74 | 59 | 53 | 0 | 220.0 MHz
-True | even/odd | 81 | 70 | 56 | 0 | 193.3 MHz
-True | mark/space | 78 | 63 | 56 | 0 | 210.2 MHz
-False | none | 70 | 57 | 49 | 0 | 182.3 MHz
-False | even/odd | 78 | 68 | 52 | 0 | 183.5 MHz
-False | mark/space | 74 | 61 | 52 | 0 | 186.2 MHz
+True  | none       | 76 | 62 | 56 | 0 | 304.8 MHz
+True  | even/odd   | 86 | 73 | 59 | 0 | 277.3 MHz
+True  | mark/space | 80 | 66 | 59 | 0 | 292.3 MHz
+False | none       | 73 | 60 | 52 | 0 | 308.7 MHz
+False | even/odd   | 79 | 71 | 55 | 0 | 278.7 MHz
+False | mark/space | 77 | 64 | 55 | 0 | 338.0 MHz
 
-*Implementation was performed using Quartus Prime Lite Edition 17.0.0 for FPGA Altera Cyclone IV E EP4CE6E22C8. Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.*
+*Implementation was performed using Quartus Prime Lite Edition 18.1.0 for Intel Cyclone 10 FPGA (10CL025YU256C8G). Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.*
 
 ## Simulation:
 
@@ -57,8 +57,7 @@ vsim -do sim/sim.tcl
 
 ## UART loopback example:
 
-The UART loopback example design is for testing data transfer between FPGA and PC.
-I use it on my cheap FPGA board ([EP4CE6 Starter Board](http://www.ebay.com/itm/111975895262) with Altera FPGA Cyclone IV EP4CE6E22C8) together with external USB to UART Bridge.
+The UART loopback example design is for testing data transfer between FPGA and PC. I use it on my FPGA board [CYC1000](https://shop.trenz-electronic.de/en/TEI0003-02-CYC1000-with-Cyclone-10-FPGA-8-MByte-SDRAM) with Intel Cyclone 10 FPGA (10CL025YU256C8G) and FTDI USB to UART Bridge.
 
 ## License:
 

example/quartus/uart_loopback.qpf renamed to example/quartus/uart_loopback_cyc1000.qpf

@@ -1,10 +1,9 @@
 #-------------------------------------------------------------------------------
 # PROJECT: SIMPLE UART FOR FPGA
 #-------------------------------------------------------------------------------
-# NAME:    QUARTUS PROJECT FILE
 # AUTHORS: Jakub Cabal <[email protected]>
 # LICENSE: The MIT License (MIT), please read LICENSE file
 # WEBSITE: https://github.com/jakubcabal/uart-for-fpga
 #-------------------------------------------------------------------------------
 
-PROJECT_REVISION = "uart_loopback"
+PROJECT_REVISION = "UART_LOOPBACK_CYC1000"

example/quartus/uart_loopback.qsf renamed to example/quartus/uart_loopback_cyc1000.qsf

@@ -1,29 +1,31 @@
 #-------------------------------------------------------------------------------
 # PROJECT: SIMPLE UART FOR FPGA
 #-------------------------------------------------------------------------------
-# NAME:    QUARTUS SETTINGS FILE FOR EP4CE6 STARTER BOARD
 # AUTHORS: Jakub Cabal <[email protected]>
 # LICENSE: The MIT License (MIT), please read LICENSE file
 # WEBSITE: https://github.com/jakubcabal/uart-for-fpga
 #-------------------------------------------------------------------------------
 
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE6E22C8
-set_global_assignment -name TOP_LEVEL_ENTITY UART_LOOPBACK
+# QUARTUS SETTINGS FILE FOR CYC1000 BOARD
+set_global_assignment -name FAMILY "Cyclone 10 LP"
+set_global_assignment -name DEVICE 10CL025YU256C8G
+set_global_assignment -name TOP_LEVEL_ENTITY UART_LOOPBACK_CYC1000
 
 # PROJECT VHDL FILES
-set_global_assignment -name VHDL_FILE ../uart_loopback.vhd
-set_global_assignment -name VHDL_FILE ../../rtl/uart.vhd
-set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_tx.vhd
-set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_rx.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_clk_div.vhd
 set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_parity.vhd
 set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_debouncer.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_tx.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_rx.vhd
+set_global_assignment -name VHDL_FILE ../../rtl/uart.vhd
+set_global_assignment -name VHDL_FILE ../rst_sync.vhd
+set_global_assignment -name VHDL_FILE ../uart_loopback_cyc1000.vhd
 
 # TIMING CONSTRAINTS
-set_global_assignment -name SDC_FILE ../timing_constraints.sdc
+set_global_assignment -name SDC_FILE ./uart_loopback_cyc1000.sdc
 
-# FPGA PINS ASSIGNMENT FOR EP4CE6 STARTER BOARD
-set_location_assignment PIN_91  -to CLK
-set_location_assignment PIN_25  -to RST
-set_location_assignment PIN_85  -to UART_TXD
-set_location_assignment PIN_86  -to UART_RXD
+# FPGA PINS ASSIGNMENT
+set_location_assignment PIN_M2 -to CLK_12M
+set_location_assignment PIN_N6 -to RST_BTN_N
+set_location_assignment PIN_T7 -to UART_TXD
+set_location_assignment PIN_R7 -to UART_RXD

example/timing_constraints.sdc renamed to example/quartus/uart_loopback_cyc1000.sdc

@@ -1,10 +1,9 @@
 #-------------------------------------------------------------------------------
 # PROJECT: SIMPLE UART FOR FPGA
 #-------------------------------------------------------------------------------
-# MODULE:  TIMING CONSTRAINTS
 # AUTHORS: Jakub Cabal <[email protected]>
 # LICENSE: The MIT License (MIT), please read LICENSE file
 # WEBSITE: https://github.com/jakubcabal/uart-for-fpga
 #-------------------------------------------------------------------------------
 
-create_clock -name CLK50 -period 20.000 [get_ports {CLK}]
+create_clock -name CLK12M -period 12MHz [get_ports {CLK_12M}]

example/rst_sync.vhd

@@ -0,0 +1,50 @@
+--------------------------------------------------------------------------------
+-- PROJECT: SIMPLE UART FOR FPGA
+--------------------------------------------------------------------------------
+-- AUTHORS: Jakub Cabal <[email protected]>
+-- LICENSE: The MIT License (MIT), please read LICENSE file
+-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity RST_SYNC is
+    Port (
+        CLK        : in  std_logic;
+        ASYNC_RST  : in  std_logic;
+        SYNCED_RST : out std_logic
+    );
+end entity;
+
+architecture RTL of RST_SYNC is
+
+    attribute ALTERA_ATTRIBUTE : string;
+    attribute PRESERVE         : boolean;
+
+    signal meta_reg  : std_logic;
+    signal reset_reg : std_logic;
+
+    attribute ALTERA_ATTRIBUTE of RTL : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*RST_SYNC:*|meta_reg}] """;
+    attribute ALTERA_ATTRIBUTE of meta_reg  : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
+    attribute ALTERA_ATTRIBUTE of reset_reg : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
+    attribute PRESERVE of meta_reg  : signal is TRUE;
+    attribute PRESERVE of reset_reg : signal is TRUE;
+
+begin
+
+    process (CLK, ASYNC_RST)
+    begin
+        if (ASYNC_RST = '1') then
+            meta_reg  <= '1';
+            reset_reg <= '1';
+        elsif (rising_edge(CLK)) then
+            meta_reg  <= '0';
+            reset_reg <= meta_reg;
+        end if;
+    end process;
+
+    SYNCED_RST <= reset_reg;
+
+end architecture;

example/uart_loopback.vhd renamed to example/uart_loopback_cyc1000.vhd

@@ -1,7 +1,6 @@
 --------------------------------------------------------------------------------
 -- PROJECT: SIMPLE UART FOR FPGA
 --------------------------------------------------------------------------------
--- MODULE:  UART LOOPBACK EXAMPLE TOP MODULE
 -- AUTHORS: Jakub Cabal <[email protected]>
 -- LICENSE: The MIT License (MIT), please read LICENSE file
 -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
@@ -11,32 +10,45 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
+-- UART LOOPBACK EXAMPLE TOP MODULE FOR CYC1000 BOARD
+-- ==================================================
 -- UART FOR FPGA REQUIRES: 1 START BIT, 8 DATA BITS, 1 STOP BIT!!!
 -- OTHER PARAMETERS CAN BE SET USING GENERICS.
 
-entity UART_LOOPBACK is
+entity UART_LOOPBACK_CYC1000 is
     Generic (
-        CLK_FREQ      : integer := 50e6;   -- set system clock frequency in Hz
+        CLK_FREQ      : integer := 12e6;   -- set system clock frequency in Hz
         BAUD_RATE     : integer := 115200; -- baud rate value
         PARITY_BIT    : string  := "none"; -- legal values: "none", "even", "odd", "mark", "space"
         USE_DEBOUNCER : boolean := True    -- enable/disable debouncer
     );
     Port (
-        CLK      : in  std_logic; -- system clock
-        RST      : in  std_logic; -- high active synchronous reset
+        CLK_12M   : in  std_logic; -- system clock 12 MHz
+        RST_BTN_N : in  std_logic; -- low active reset button
         -- UART INTERFACE
-        UART_TXD : out std_logic;
-        UART_RXD : in  std_logic
+        UART_TXD  : out std_logic;
+        UART_RXD  : in  std_logic
     );
-end UART_LOOPBACK;
+end entity;
 
-architecture FULL of UART_LOOPBACK is
+architecture RTL of UART_LOOPBACK_CYC1000 is
 
-    signal data  : std_logic_vector(7 downto 0);
-    signal valid : std_logic;
+    signal rst_btn : std_logic;
+    signal reset   : std_logic;
+    signal data    : std_logic_vector(7 downto 0);
+    signal valid   : std_logic;
 
 begin
 
+    rst_btn <= not RST_BTN_N;
+
+    rst_sync_i : entity work.RST_SYNC
+    port map (
+        CLK        => CLK_12M,
+        ASYNC_RST  => rst_btn,
+        SYNCED_RST => reset
+    );
+
 	uart_i: entity work.UART
     generic map (
         CLK_FREQ      => CLK_FREQ,
@@ -45,8 +57,8 @@ begin
         USE_DEBOUNCER => USE_DEBOUNCER
     )
     port map (
-        CLK         => CLK,
-        RST         => RST,
+        CLK         => CLK_12M,
+        RST         => reset,
         -- UART INTERFACE
         UART_TXD    => UART_TXD,
         UART_RXD    => UART_RXD,
@@ -60,4 +72,4 @@ begin
         DIN_RDY     => open
     );
 
-end FULL;
+end architecture;