Fixed block2d load

For 32b_1r8x2c under simd16, its data size is 64 bytes in total.
But this function returns int2, which takes 128 bytes.

For this special function, don't change it to 1r16x1c. The result
is valid only for lower 8 lanes.

(cherry picked from commit 8e131ad)

Author: jgu222

IGC/Compiler/Optimizer/OpenCLPasses/LSCFuncs/LSCFuncsResolution.cpp

@@ -951,10 +951,9 @@ Instruction* LSCFuncsResolution::CreateSubGroup2DBlockOperation(llvm::CallInst&
             IGC_ASSERT_MESSAGE(funcName.consume_front("v2"), "Unrecognized v element in __builtin_IB_subgroup_block_read/write.");
         }
 
-        // Special handling of the following when GRF size = 64 bytes
+        // (1) Special handling of the following when GRF size = 64 bytes
         //    intel_sub_group_2d_block_read_8b_1r32x2c  (u8_m1k32v2)
         //    intel_sub_group_2d_block_read_16b_1r16x2c (u16_m1k16v2)
-        //    intel_sub_group_2d_block_read_32b_1r8x2c  (u32_m1k8v2)
         // They are defined to return 64 bytes, but the HW block read
         // returns 128 bytes (two GRFs, as a block size must be multiple
         // of GRF, unused part is zero-padded. Note that those APIs have
@@ -964,11 +963,17 @@ Instruction* LSCFuncsResolution::CreateSubGroup2DBlockOperation(llvm::CallInst&
         //
         // For those cases, instead of 2 blocks, using equivalent single-block
         // read to avoid those mov instructions by just doubling their width:
-        //   u8_m1k32v2  --> u8_m1k64v1
-        //   u16_m1k16v2 --> u16_m1k32v1
-        //   u32_m1k8v2  --> u32_m1k16v1
+        //   8b_m1k32v2  --> 8b_m1k64v1
+        //   16b_m1k16v2 --> 16b_m1k32v1
+        //
+        // (2) The following is an exception:
+        //    int2 = intel_sub_group_2d_block_read_32b_1r8x2c  (u32_m1k8v2)
+        // it is indeed defined as return 128 bytes. As this 2d read has
+        // 64 bytes, only lower 8 lanes have data and upper 8 lanes got zero.
+        // No change to this read!
         if (m_pCtx->platform.getGRFSize() == 64 && isRead && !isPrefetch &&
-            numBlocksV == 2 && tileHeight == 1 && (elemSize * tileWidth) == 256)
+            numBlocksV == 2 && tileHeight == 1 && (elemSize * tileWidth) == 256 &&
+            elemSize != 32 /* exception shown above in (2) */)
         {
             numBlocksV = 1;
             tileWidth *= 2;

IGC/ocloc_tests/Builtins/cl_intel_subgroup_2d_block_io/PVC/block_reads.cl

@@ -270,7 +270,7 @@ SPDX-License-Identifier: MIT
 // RUN: -DINPUT_TYPE=uint -DOUTPUT_TYPE=uint -DFUNCTION=intel_sub_group_2d_block_read_32b_1r8x2c -DDST_ARRAY_EL_TYPE=uint2 -DDST_ARRAY_EL_NUM=1" \
 // RUN: -internal_options "-cl-ext=-all,+cl_intel_subgroup_2d_block_io" | FileCheck %s --check-prefix=CHECK-VISAASM-32B-1R-8X2C
 
-// CHECK-VISAASM-32B-1R-8X2C: lsc_load_block2d.ugm (M1, 1)  V{{[0-9]+}}:d32.16x1nn  flat[{{.+}},0x1FF,0x2D,0x1FF,V{{[0-9]+}},V{{[0-9]+}}
+// CHECK-VISAASM-32B-1R-8X2C: lsc_load_block2d.ugm (M1, 1)  V{{[0-9]+}}:d32.2x8x1nn  flat[{{.+}},0x1FF,0x2D,0x1FF,V{{[0-9]+}},V{{[0-9]+}}
 
 // RUN: ocloc compile -file %s -device pvc -options "-igc_opts 'DumpVISAASMToConsole=1' \
 // RUN: -DINPUT_TYPE=uint -DOUTPUT_TYPE=uint -DFUNCTION=intel_sub_group_2d_block_read_32b_2r8x2c -DDST_ARRAY_EL_TYPE=uint2 -DDST_ARRAY_EL_NUM=1" \

IGC/ocloc_tests/SPIRV-extenstions/SPV_INTEL_2d_block_io/PVC/block_loads.ll

@@ -96,7 +96,7 @@ entry:
   call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32 4, i32 8, i32 16, i32 1, i8 addrspace(1)* %base_address, i32 512, i32 46, i32 512, <2 x i32> %0, i8* %dst_pointer)
 ; CHECK: lsc_load_block2d.ugm (M1, 1)  V{{[0-9]+}}:d32.8x32nn  flat[{{.+}},0x1FF,0x2D,0x1FF,V{{[0-9]+}},V{{[0-9]+}}
   call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32 4, i32 8, i32 32, i32 1, i8 addrspace(1)* %base_address, i32 512, i32 46, i32 512, <2 x i32> %0, i8* %dst_pointer)
-; CHECK: lsc_load_block2d.ugm (M1, 1)  V{{[0-9]+}}:d32.16x1nn  flat[{{.+}},0x1FF,0x2D,0x1FF,V{{[0-9]+}},V{{[0-9]+}}
+; CHECK: lsc_load_block2d.ugm (M1, 1)  V{{[0-9]+}}:d32.2x8x1nn  flat[{{.+}},0x1FF,0x2D,0x1FF,V{{[0-9]+}},V{{[0-9]+}}
   call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32 4, i32 8, i32 1,  i32 2, i8 addrspace(1)* %base_address, i32 512, i32 46, i32 512, <2 x i32> %0, i8* %dst_pointer)
 ; CHECK: lsc_load_block2d.ugm (M1, 1)  V{{[0-9]+}}:d32.2x8x2nn  flat[{{.+}},0x1FF,0x2D,0x1FF,V{{[0-9]+}},V{{[0-9]+}}
   call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32 4, i32 8, i32 2,  i32 2, i8 addrspace(1)* %base_address, i32 512, i32 46, i32 512, <2 x i32> %0, i8* %dst_pointer)