103.556MHz/1B00: Moved font, ++ VT100, test code

The VT100 terminal emulator has been much improved, and a new attribute
can be applied to the text (whilst not losing any current attributes).
Text can be blinked on and off (using a clock derived from the cursor
blink clock, divided by four), the cursor save and restore command has
been added, along with a few other miscellaneous commands, and a bug in
the relative cursor positioning routines has been fixed (a relative
move of 0 should be treated the same as 1 for those functions, it was
not being treated that way).

* UART baud initial value can be set by a generic, which is nice to
have, but not needed as it can be set from a control register. The other
options cannot be set at the moment and default to 8 bits, 1 stop bit,
no parity.
* Special cases for majority logic gates of 1, 2 and 3 have been added
to the 'majority' module.
* The font directory has moved.
* 'vga.vhd' converted to a UTF-8 file, fixed some invalid characters.
* Formatting changed 'port(' -> 'port ('
* Added extra VT100 terminal codes to simulator.
* Instead of commenting out code, generate functions are used.
  * This applies to the new VGA code.
  * And to adding a FIFO to the UART (which almost works).
* Some extra comments have been added.

The next major problems with the project will be:
* Making the UART more reliable, currently we get nonsense if we are not
processing received characters quick enough and we spend a lot of time
waiting around for transmission. There is a rate that we will not be
able to keep up with when it comes to processing text, however we should
never be receiving invalid data, which we are, if we cannot keep up.
* The UART RX module does not work with certain values for the baud
generator (specifically at 115200, the value that needs to go into the
clock register is '54', however it does not work when given that value,
50-53 and 55 have been tried and work, 54 does not). For TX, '54' works.
* Scrolling should be handled by the VT100 terminal, currently it just
erases everything on the screen. This is not optimal.

Author: howerj

fonts/.gitignore

@@ -0,0 +1 @@
+*.pbm

lat0.bin renamed to fonts/lat0.bin

@@ -0,0 +1,14 @@
+SOURCES:=$(wildcard *.bin)
+OBJFILES=$(SOURCES:%.bin=%.pbm)
+
+.PHONY: all clean
+
+all: ${OBJFILES}
+
+%.pbm: %.bin
+	echo "P1\n8" `wc $< | awk '{print $$1}'` > $@
+	cat $< >> $@
+
+clean:
+	rm -fv ${OBJFILES}
+

fonts/makefile

@@ -0,0 +1,27 @@
+# Font Directory
+
+This directory contains fonts which can used with the VGA terminal emulator
+component.
+
+All characters are 8 pixels wide, and 12 high. To ease editing and viewing of
+the font, they are stored in a text file as a pixel map, with a '1' character
+representing a switched on pixel. No prizes for guessing which character
+represents an off pixel.
+
+The format has two other advantages; it is easy for it to be read in by the HDL
+tool-chain, and it can be converted to a viewable [PBM][] file quite easily. The
+conversion just requires prepending a header.
+
+The [Terminus][] font used could do with some cleaning up - apart from the
+normal printable ASCII characters, the characters outside of that range were
+picked at random.
+
+## Copyright
+
+The fonts are under copyright. I believe the [Terminus][] font to be licensed under
+the 'SIL OPEN FONT LICENSE Version 1.1', the iso-8859-15 Latin-0 font I am 
+unsure of, it came with the original project and was generated from an open
+source font package.
+
+[PBM]: https://en.wikipedia.org/wiki/Netpbm_format
+[Terminus]: http://terminus-font.sourceforge.net/

fonts/readme.md

@@ -935,7 +935,7 @@ static void terminal_at_xy(vt100_t * const t, unsigned x, unsigned y, const bool
 	if (limit_not_wrap) {
 		x = MAX(x, 0);
 		y = MAX(y, 0);
-		x = MIN(x, t->width - 1);
+		x = MIN(x, t->width  - 1);
 		y = MIN(y, t->height - 1);
 	} else {
 		x %= t->width;
@@ -998,11 +998,15 @@ static int terminal_escape_sequences(vt100_t * const t, const uint8_t c) {
 	assert(t);
 	assert(t->state != TERMINAL_NORMAL_MODE);
 	switch (t->state) {
-	case TERMINAL_CSI:
-		if (c == '[')
-			t->state = TERMINAL_COMMAND;
-		else
-			goto fail;
+	case TERMINAL_CSI: /* process CSI and some non-CSI Escape Only commands */
+		switch (c) {
+		case '[': t->state = TERMINAL_COMMAND; break;
+		case 'c': goto eraser; /*reset display*/ break;
+		case '7': t->cursor_saved = t->cursor; t->attribute_saved = t->attribute; break;
+		case '8': t->cursor = t->cursor_saved; t->attribute = t->attribute_saved; break;
+		default: goto fail;
+		}
+
 		break;
 	case TERMINAL_COMMAND:
 		switch (c) {
@@ -1064,7 +1068,11 @@ static int terminal_escape_sequences(vt100_t * const t, const uint8_t c) {
 			if (t->n1 == 6)
 				goto success;
 			goto fail;
+eraser: /* HAHA: This is clearly the best way of doing things. */
+			t->command_index = 1;
+			t->n1 = 3; /* fall-through */
 		case 'J': /* reset */
+
 			switch (t->n1) {
 			case 3: /* fall-through */
 			case 2: t->cursor = 0; /* with cursor */ /* fall-through */

terminus.bin renamed to fonts/terminus.bin

@@ -615,7 +615,7 @@ location search-previous 0
 
 
 : 5u.r 5 u.r space ; hidden
-: dm+ 2/ for aft dup @ 5u.r cell+ then next ; ( a u -- a )
+: dm+ 2/ for aft dup @ 5u.r cell+ then next ; hidden ( a u -- a )
 : colon 58 emit ; hidden ( -- )
 
 \ It would be nice to colorize the dump output.
@@ -662,13 +662,14 @@ location search-previous 0
 : vt100 ' ps2? <key> ! ' vga! <emit> ! hand ;
 : interactive ' input <key> ! ' output <emit> ! hand ;
 : io! 
-	$36 oUartTxBaud  ! ( set TX baud rate )
-	$32 oUartRxBaud  ! ( set TX baud rate )
+	( 115200 9600 )
+	$36    ( $28B ) oUartTxBaud  ! ( set TX baud rate )
+	$35    ( $28A ) oUartRxBaud  ! ( set TX baud rate )
 	$8484 oUartControl ! ( set UART control register; 8 bits, 1 stop, no parity )
 	0 timer! 0 led! 0 segments!
 	0 ien! 0 oIrcMask ! interactive ; ( -- : initialize I/O )
-: ver $666 ;
-: hi io! ( save ) hex cr hi-string print ver <# # # 46 hold # #> type cr here . .free cr [ ;
+\ : ver $666 ;
+: hi io! ( save ) hex cr hi-string print cpu-id <# # # 46 hold # #> type cr here . .free cr [ ;
 : cold io! branch entry ;
 : bye cold ;
 

h2.c

@@ -200,7 +200,7 @@ typedef struct {
 	terminal_state_t state;
 	bool blinks;
 	bool cursor_on;
-	vt100_attribute_t attribute;
+	vt100_attribute_t attribute, attribute_saved;
 	vt100_attribute_t attributes[VT100_MAX_SIZE];
 	uint8_t m[VT100_MAX_SIZE];
 	uint8_t command_index;

h2.fth

@@ -176,9 +176,11 @@ viewer: simulation
 endif
 
 USB?=/dev/ttyUSB0
+BAUD?=115200
+#BAUD?=9600
 
 talk:
-	picocom --omap delbs -e b -b 115200 ${USB}
+	picocom --omap delbs -e b -b ${BAUD} ${USB}
 
 bitfile: design.bit
 

h2.h

@@ -252,7 +252,9 @@ The following peripherals have been implemented in the [VHDL][] SoC to
 interface with devices on the [Nexys3][] board:
 
 * [VGA][] output device, text mode only, 80 by 40 characters from
-  <http://www.javiervalcarce.eu/html/vhdl-vga80x40-en.html>
+  <http://www.javiervalcarce.eu/html/vhdl-vga80x40-en.html>. This has
+been heavily modified from the original, which now implements most of a VT100
+terminal emulator.
 * Timer
 * [UART][] (Rx/Tx) in [uart.vhd][].
 * [PS/2][] Keyboard

makefile

@@ -39,7 +39,7 @@ architecture testing of tb is
 	);
 
 	constant number_of_interrupts:    positive := 8;
-	constant uart_baud_rate:          positive := 115200;
+	constant uart_baud:          positive := 115200;
 	constant configuration_file_name: string   := "tb.cfg";
 	constant uart_tx_time:            time     := (10*1000 ms) / 115200;
 	constant uart_default_input:      std_ulogic_vector(7 downto 0) := x"AA";
@@ -138,7 +138,7 @@ begin
 	generic map(
 		g               => g,
 		reset_period_us => reset_period_us,
-		uart_baud_rate  => uart_baud_rate)
+		uart_baud  => uart_baud)
 	port map(
 		debug       => dbgi,
 		clk         => clk,
@@ -183,8 +183,8 @@ begin
 		signal uart_clock_rx_we, uart_clock_tx_we, uart_control_we: std_ulogic := '0';
 		signal uart_reg: std_ulogic_vector(15 downto 0);	
 	begin
-		uart_0: work.uart_pkg.uart_top
-			generic map (g => g)
+		uart_0: work.uart_pkg.uart_core
+			generic map (g => g, baud => uart_baud)
 			port map (
 				clk   => clk,
 				rst   => rst,
@@ -206,7 +206,7 @@ begin
 	end block;
 
 --	uut_uart: work.uart_pkg.uart_core
---		generic map(g => g, baud_rate =>  uart_baud_rate)
+--		generic map(g => g, baud_rate => uart_baud)
 --		port map(
 --			clk       =>  clk,
 --			rst       =>  rst,

readme.md

@@ -24,7 +24,7 @@ entity top is
 	generic(
 		g: common_generics         := default_settings;
 		reset_period_us:  natural  := 1;
-		uart_baud_rate:   positive := 115200;
+		uart_baud:        positive := 115200;
 		uart_fifo_depth:  positive := 8);
 	port
 	(
@@ -113,7 +113,6 @@ architecture behav of top is
 	signal rx_fifo_full:      std_ulogic := '0';
 	signal rx_data_re:        std_ulogic := '0';
 
-	signal tx_data:           std_ulogic_vector(7 downto 0) := (others => '0');
 	signal tx_fifo_full:      std_ulogic := '0';
 	signal tx_fifo_empty:     std_ulogic := '0';
 	signal tx_data_we:        std_ulogic := '0';
@@ -216,7 +215,6 @@ begin
 	assert not(io_wr = '1' and io_re = '1') report "IO Read/Write issued at same time" severity error;
 
 	vga_data <= io_dout(vga_data'range);
-	tx_data  <= io_dout(tx_data'range);
 
 	-- TODO: Raise trap (interrupt with bus error) on invalid memory access.
 	io_write: block
@@ -298,33 +296,66 @@ begin
 	--- UART ----------------------------------------------------------
 	uart_0_blk: block
 		signal tx_ok, rx_nd: std_ulogic;
+		signal tx_data:      std_ulogic_vector(7 downto 0) := (others => '0');
+		constant use_fifo_uart: boolean := false;
 	begin
-		tx_fifo_full  <= not tx_ok;
-		tx_fifo_empty <= tx_ok;
-
-		rx_fifo_full  <= rx_nd;
-		rx_fifo_empty <= not rx_nd;
-		uart_0: work.uart_pkg.uart_top
-			generic map (g => g)
-			port map (
-				clk   => clk,
-				rst   => rst,
-				tx_di => tx_data,
-				tx_we => tx_data_we,
-				tx_ok => tx_ok,
-				tx    => tx,
-			
-				rx    => rx,
-				rx_ok => open,
-				rx_nd => rx_nd,
-				rx_do => rx_data,
-				rx_re => rx_data_re,
-			
-				reg             => io_dout,
-				clock_reg_tx_we => uart_clock_tx_we,
-				clock_reg_rx_we => uart_clock_rx_we,
-				control_reg_we  => uart_control_we
-			);
+		tx_data  <= io_dout(tx_data'range);
+
+		ugen0: if not use_fifo_uart generate
+			tx_fifo_full  <= not tx_ok;
+			tx_fifo_empty <= tx_ok;
+
+			rx_fifo_full  <= rx_nd;
+			rx_fifo_empty <= not rx_nd;
+
+			uart_0: work.uart_pkg.uart_core
+				generic map (g => g, baud => uart_baud)
+				port map (
+					clk   => clk,
+					rst   => rst,
+					tx_di => tx_data,
+					tx_we => tx_data_we,
+					tx_ok => tx_ok,
+					tx    => tx,
+				
+					rx    => rx,
+					rx_ok => open,
+					rx_nd => rx_nd,
+					rx_do => rx_data,
+					rx_re => rx_data_re,
+				
+					reg             => io_dout,
+					clock_reg_tx_we => uart_clock_tx_we,
+					clock_reg_rx_we => uart_clock_rx_we,
+					control_reg_we  => uart_control_we);
+		end generate;
+
+		-- TEST CODE, TX is not quite working. This generate should
+		-- be moved into the core module.
+		ugen1: if use_fifo_uart generate
+			uart_fifo_0: work.uart_pkg.uart_top
+				generic map (g => g, baud => uart_baud)
+				port map (
+					clk => clk, 
+					rst => rst,
+
+					tx            => tx,
+					tx_fifo_full  => tx_fifo_full,
+					tx_fifo_empty => tx_fifo_empty,
+					tx_fifo_we    => tx_data_we,
+					tx_fifo_data  => tx_data,
+
+					rx            => rx,
+					rx_fifo_re    => rx_data_re,
+					rx_fifo_data  => rx_data,
+					rx_fifo_full  => rx_fifo_full,
+					rx_fifo_empty => rx_fifo_empty,
+
+					reg             => io_dout,
+					clock_reg_tx_we => uart_clock_tx_we,
+					clock_reg_rx_we => uart_clock_rx_we,
+					control_reg_we  => uart_control_we);
+		end generate;
 	end block;
 	--- UART ----------------------------------------------------------
 
@@ -352,44 +383,51 @@ begin
 	--- Timer ---------------------------------------------------------
 
 	--- VGA -----------------------------------------------------------
-	vt100_0: work.vga_pkg.vt100
-	generic map (g => g)
-	port map (
-		clk         =>  clk,
-		clk25MHz    =>  clk25MHz,
-		rst         =>  rst,
-		we          =>  vga_data_we,
-		char        =>  vga_data,
-		busy        =>  vga_data_busy,
-		o_vga       =>  o_vga
-	);
+	vga_selector: block
+		constant use_vt100: boolean := true;
+	begin
+		gen_vt100_0: if use_vt100 generate
+		vt100_0: work.vga_pkg.vt100
+			generic map (g => g)
+			port map (
+				clk         =>  clk,
+				clk25MHz    =>  clk25MHz,
+				rst         =>  rst,
+				we          =>  vga_data_we,
+				char        =>  vga_data,
+				busy        =>  vga_data_busy,
+				o_vga       =>  o_vga);
+		end generate;
 
-	-- Test code
-	-- NOTE: Timing is not the best, VGA monitor loses synchronization
-	-- every so often with this module.	
---	vga_c1: block
---		signal row, column: integer := 0;
---		signal h_blank, v_blank, draw: std_ulogic := '0';
---	begin
---		draw <= not h_blank and not v_blank;
---		vga_c: work.util.vga_controller
---		generic map (
---			g => g,
---			pixel_clock_frequency => 25_000_000,
---			cfg => work.util.vga_640x480)
---		port map (
---			clk    => clk25MHz,
---			rst    => rst,
---			row    => row,
---			column => column,
---			h_blank => h_blank,
---			v_blank => v_blank,
---			h_sync => o_vga.hsync,
---			v_sync => o_vga.vsync);
---		o_vga.red <= "111" when draw = '1' else "000";
---		o_vga.green <= "111" when (draw = '1' and row < 100 and column < 100) else "000";
---		o_vga.blue <= "11";
---	end block;
+		-- Test code
+		-- NOTE: Timing is not the best, VGA monitor loses synchronization
+		-- every so often with this module.
+		vga_gen_c1: if not use_vt100 generate
+		vga_c1: block 
+			signal row, column: integer := 0;
+			signal h_blank, v_blank, draw: std_ulogic := '0';
+		begin
+			draw <= not h_blank and not v_blank;
+			vga_c: work.util.vga_controller
+			generic map (
+				g => g,
+				pixel_clock_frequency => 25_000_000,
+				cfg => work.util.vga_640x480)
+			port map (
+				clk    => clk25MHz,
+				rst    => rst,
+				row    => row,
+				column => column,
+				h_blank => h_blank,
+				v_blank => v_blank,
+				h_sync => o_vga.hsync,
+				v_sync => o_vga.vsync);
+			o_vga.red <= "111" when draw = '1' else "000";
+			o_vga.green <= "111" when (draw = '1' and row < 100 and column < 100) else "000";
+			o_vga.blue <= "11";
+		end block;
+		end generate;
+	end block;
 	--- VGA -----------------------------------------------------------
 
 	--- Keyboard ------------------------------------------------------