synth: Make synthesize_rtl emit a VerilogInfo provider (#362)

* synth: Make synthesize_rtl emit a VerilogInfo provider Lets you do gate level sims easier if this rule can be passed as if it were a verilog_library Signed-off-by: Ethan Mahintorabi <[email protected]> * reformat bzl Signed-off-by: Ethan Mahintorabi <[email protected]> --------- Signed-off-by: Ethan Mahintorabi <[email protected]>
hdl · Nov 7, 2024 · ca650bf · ca650bf
1 parent 7d85930
commit ca650bf
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Showing 3 changed files with 19 additions and 2 deletions.
diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl
@@ -15,7 +15,7 @@
 """Rules for synthesizing (System)Verilog code."""
 
 load("@rules_hdl//pdk:build_defs.bzl", "StandardCellInfo")
-load("//verilog:defs.bzl", "VerilogInfo")
+load("//verilog:defs.bzl", "VerilogInfo", "make_dag_entry", "make_verilog_info")
 
 # There are no rules to generate this provider, but it does provide the mechansim to build
 # rules based on surelog in the open source world.
@@ -213,6 +213,16 @@ def _synthesize_design_impl(ctx):
             verilog_files = verilog_files,
             uhdm_files = uhdm_files,
         ),
+        make_verilog_info(
+            new_entries = [make_dag_entry(
+                label = ctx.label,
+                srcs = [output_file],
+                hdrs = [],
+                data = [],
+                deps = [],
+                tags = [],
+            )],
+        ),
     ]
 
 def _benchmark_synth(ctx, synth_log_file):

diff --git a/verilog/defs.bzl b/verilog/defs.bzl
@@ -3,8 +3,12 @@
 load(
     ":providers.bzl",
     _VerilogInfo = "VerilogInfo",
+    _make_dag_entry = "make_dag_entry",
+    _make_verilog_info = "make_verilog_info",
     _verilog_library = "verilog_library",
 )
 
 VerilogInfo = _VerilogInfo
 verilog_library = _verilog_library
+make_dag_entry = _make_dag_entry
+make_verilog_info = _make_verilog_info
diff --git a/verilog/providers.bzl b/verilog/providers.bzl
@@ -24,7 +24,7 @@ VerilogInfo = provider(
     },
 )
 
-def make_dag_entry(srcs, hdrs, data, deps, label):
+def make_dag_entry(srcs, hdrs, data, deps, label, tags):
     """Create a new DAG entry for use in VerilogInfo.
 
     As VerilogInfo should be created via 'merge_verilog_info' (rather than directly),
@@ -42,6 +42,7 @@ def make_dag_entry(srcs, hdrs, data, deps, label):
       data: A list of File that are `data`.
       deps: A list of Label that are deps of this entry.
       label: A Label to use as the name for this entry.
+      tags: A list of str. (Ideally) just the entry tags for later filelist filtering.
     Returns:
       struct with all these fields properly stored.
     """
@@ -50,6 +51,7 @@ def make_dag_entry(srcs, hdrs, data, deps, label):
         hdrs = tuple(hdrs),
         data = tuple(data),
         deps = tuple(deps),
+        tags = tuple(tags),
         label = label,
     )
 
@@ -97,6 +99,7 @@ def _verilog_library_impl(ctx):
             hdrs = ctx.files.hdrs,
             deps = ctx.attr.deps,
             label = ctx.label,
+            tags = [],
         )],
         old_infos = [dep[VerilogInfo] for dep in ctx.attr.deps],
     )