From 8890a4b008ed08eacf1e2a2fc629a0a7d29e9214 Mon Sep 17 00:00:00 2001
From: tcal-x <tcal@google.com>
Date: Mon, 16 Oct 2023 15:00:00 -0700
Subject: [PATCH] Add comment: why we're deleting $print cells.

Signed-off-by: tcal-x <tcal@google.com>
---
 synthesis/synth.tcl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
index ace891fb..62fcce61 100644
--- a/synthesis/synth.tcl
+++ b/synthesis/synth.tcl
@@ -52,7 +52,8 @@ yosys proc -nomux
 yosys proc_mux
 yosys flatten
 
-# Remove $print cells.
+# Remove $print cells.  These pass through Verilog $display() tasks.
+# Some place and route tools cannot parse these, so remove them here.
 yosys delete {*/t:$print}
 
 # Remove internal only aliases for public nets and then give created instances