@@ -335,7 +335,7 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
335335
336336 // EP0 is limited to one packet per xfer
337337 if (epnum == 0 ) {
338- total_bytes = tu_min16 (_dcd_data .ep0_pending [dir ], xfer -> max_size );
338+ total_bytes = tu_min16 (_dcd_data .ep0_pending [dir ], CFG_TUD_ENDPOINT0_SIZE );
339339 _dcd_data .ep0_pending [dir ] -= total_bytes ;
340340 num_packets = 1 ;
341341 } else {
@@ -373,12 +373,29 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
373373 }
374374 dep -> diepdma = (uintptr_t ) xfer -> buffer ;
375375 dep -> diepctl = depctl .value ; // enable endpoint
376+ // Advance buffer pointer for EP0
377+ if (epnum == 0 ) {
378+ xfer -> buffer += total_bytes ;
379+ }
376380 } else {
377381 dep -> diepctl = depctl .value ; // enable endpoint
378382
379383 // Enable tx fifo empty interrupt only if there is data. Note must after depctl enable
380384 if (dir == TUSB_DIR_IN && total_bytes != 0 ) {
381- dwc2 -> diepempmsk |= (1 << epnum );
385+ // For num_packets = 1 we write the packet directly
386+ if (num_packets == 1 ) {
387+ // Push packet to Tx-FIFO
388+ if (xfer -> ff ) {
389+ volatile uint32_t * tx_fifo = dwc2 -> fifo [epnum ];
390+ tu_fifo_read_n_const_addr_full_words (xfer -> ff , (void * )(uintptr_t )tx_fifo , total_bytes );
391+ } else {
392+ dfifo_write_packet (dwc2 , epnum , xfer -> buffer , total_bytes );
393+ xfer -> buffer += total_bytes ;
394+ }
395+ } else {
396+ // Enable TXFE interrupt for multi-packet transfer
397+ dwc2 -> diepempmsk |= (1 << epnum );
398+ }
382399 }
383400 }
384401}
@@ -820,7 +837,6 @@ static void handle_rxflvl_irq(uint8_t rhport) {
820837 const dwc2_ep_tsize_t tsiz = {.value = epout -> tsiz };
821838 xfer -> total_len -= tsiz .xfer_size ;
822839 if (epnum == 0 ) {
823- xfer -> total_len -= _dcd_data .ep0_pending [TUSB_DIR_OUT ];
824840 _dcd_data .ep0_pending [TUSB_DIR_OUT ] = 0 ;
825841 }
826842 }
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