in.txt

ALGORITHM:


//MRM writeback 
//MRM changes pointers of queue buffer - 3rd Priority
//MRM finds first non zero instruction (combinational logic) - 1st Priority
//MRM sends an instruction to DRAM for execution -2nd priority
//SEND TO MRM

Mem_req_manager() algorithm: (in order)
	1.) if there is a running instruction, execute one cycle of it (done by DRAM)
	2.) if writing a value into register or not doing anything, then pick apt row and start executing along with it.
			if row_buffer is -1, choose first non zero row, takes one cycle as done by combinational logic
	4.) else just continue
//maintain a hashmap row -> (first_index, last_index)
//for first non empty, row, maintain an array of prefix or's, and adjacent xor's-> JUST EXPLAIN THIS
DRAM , MRM, MAIN
//r0 check, and address divisibility by 4
While (true)

checkForWriteback(); //also returns the register 

For i ranging from 0 to n
	instruction is add 
		
		1.) checkForWriteback is true
			do not update PC of this

		2.) register is dependent of any ongoing or previous instruction
			(store last lw for each register) do not update PC of this (check all the three registers)
		3.) independent:
			execute in parallel

	instruction is lw

		1.) if offset register occurs as the first register of some previous lw(or current) ya fir writeback : PC not updated
		2.) if first register occurs previously.
				if just previous memory operation was lw and on same register:
					send to MRM (with a flag which is 1); (MRM starts an operation of Pointer updation)
					udpate PC;
				else:
					do not update PC
		3.) just push with flag(0),update PC
	
	instruction is sw

		1.) if any register is first register of previous lw : PC is not updated.
		2.) if jusr previous memory operation was on same memory and was sw:
			  send to MRM with flag as 1
			else
			  send flag(0)
			  update PC;

//print CPI
//total no. of instructions executed for each core
//total number of row buffer updates
//non zero-memory print
//ins no.: 		core :  , .....

//forwarding, forwarding + optimizations, lw,sw optimizations, dependent instructions, multiple register writes tried in the same cycle
//separate folder for each t.c, 4 cores minimal
// odd - Ishaan (forwarding,lw, dependent instructions)
// even - Aniket

To Check:
tc5 - t3.txt

lw/sw optimisation taking place when instruction is being pushed in just received.
forwarding taking place when instruction is pushed in mrmBuffer from just received.


sw $t1, 1900($zero)         $t1 = 200
we can perform reading of sw with writeback as writing will take the first half and sw read in second half.
Not in the case when $t1 is offset register since we will have to do base + offset_reg_value so it takes time

ERROR CASES
//add ERROR TEST CASES
//how to avoid MRAM, DRAM, FORWARDING printing to avoid taking erroneous file's instructions into account.