diff --git a/.github/workflows/modules-zstd.yml b/.github/workflows/modules-zstd.yml index 4272e4b91b..bdf61906f5 100644 --- a/.github/workflows/modules-zstd.yml +++ b/.github/workflows/modules-zstd.yml @@ -45,7 +45,9 @@ jobs: - name: Test ZSTD Module - DSLX Tests (opt) if: ${{ !cancelled() }} run: | - bazel test -c opt --test_output=errors -- $(bazel query 'filter("_dslx_test$", kind(rule, //xls/modules/zstd/...))') + bazel test -c opt --test_output=errors -- $(bazel query 'filter("_dslx_test$", kind(rule, //xls/modules/zstd/...)) except filter("zstd_dec_dslx_test$", kind(rule, //xls/modules/zstd/...))'); + # Run all tests except those ending with `_skip` + bazel test -c opt --test_strategy=exclusive --test_output=errors --test_filter='^(.*[^_]|.*_[^s]|.*_s[^k]|.*_sk[^i]|.*_ski[^p])$' //xls/modules/zstd:zstd_dec_dslx_test; - name: Build ZSTD verilog targets (opt) if: ${{ !cancelled() }} diff --git a/dependency_support/com_github_alexforencich_verilog_axi/BUILD.bazel b/dependency_support/com_github_alexforencich_verilog_axi/BUILD.bazel new file mode 100644 index 0000000000..4a24c1372f --- /dev/null +++ b/dependency_support/com_github_alexforencich_verilog_axi/BUILD.bazel @@ -0,0 +1,15 @@ +# Copyright 2025 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Needed to make this a package. diff --git a/dependency_support/com_github_alexforencich_verilog_axi/bundled.BUILD.bazel b/dependency_support/com_github_alexforencich_verilog_axi/bundled.BUILD.bazel new file mode 100644 index 0000000000..296e2bc0f6 --- /dev/null +++ b/dependency_support/com_github_alexforencich_verilog_axi/bundled.BUILD.bazel @@ -0,0 +1,45 @@ +# Copyright 2025 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +load("@xls_pip_deps//:requirements.bzl", "requirement") + +package(default_visibility = ["//visibility:public"]) + +exports_files( + glob(["rtl/*.v"]), +) + +py_binary( + name = "axi_crossbar_wrap", + srcs = ["rtl/axi_crossbar_wrap.py"], + deps = [requirement("Jinja2")], +) + +py_binary( + name = "axi_interconnect_wrap", + srcs = ["rtl/axi_interconnect_wrap.py"], + deps = [requirement("Jinja2")], +) + +py_binary( + name = "axil_crossbar_wrap", + srcs = ["rtl/axi_crossbar_wrap.py"], + deps = [requirement("Jinja2")], +) + +py_binary( + name = "axil_interconnect_wrap", + srcs = ["rtl/axil_interconnect_wrap.py"], + deps = [requirement("Jinja2")], +) diff --git a/dependency_support/load_external.bzl b/dependency_support/load_external.bzl index 73b6b7b9f0..aefbe77113 100644 --- a/dependency_support/load_external.bzl +++ b/dependency_support/load_external.bzl @@ -90,3 +90,11 @@ def load_external_repositories(): urls = ["https://github.com/facebook/zstd/archive/fdfb2aff39dc498372d8c9e5f2330b692fea9794.zip"], build_file = Label("//dependency_support/com_github_facebook_zstd:bundled.BUILD.bazel"), ) + + http_archive( + name = "com_github_alexforencich_verilog_axi", + sha256 = "f3b58406b51950584cc7b0c67b0710cef10cb14e1f5576e97a2f0b1c0b12fcbe", + strip_prefix = "verilog-axi-516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", + urls = ["https://github.com/alexforencich/verilog-axi/archive/516bd5dadc3365b7f9e225d2af8fe0b8d804fe53.zip"], + build_file = "//dependency_support/com_github_alexforencich_verilog_axi:bundled.BUILD.bazel", + ) diff --git a/dependency_support/pip_requirements.in b/dependency_support/pip_requirements.in index 804306558e..51ced9d019 100644 --- a/dependency_support/pip_requirements.in +++ b/dependency_support/pip_requirements.in @@ -13,6 +13,9 @@ pyyaml==6.0.1 # We build most of z3 ourselves but building python is really complicated. Just # use pypi version z3-solver==4.14.0.0 +cocotb==1.7.2 +cocotbext-axi==0.1.24 +cocotb_bus==0.2.1 # Note: numpy and scipy version availability seems to differ between Ubuntu # versions that we want to support (e.g. 18.04 vs 20.04), so we accept a diff --git a/dependency_support/pip_requirements_lock.txt b/dependency_support/pip_requirements_lock.txt index dc895c7f19..fc650abd8b 100644 --- a/dependency_support/pip_requirements_lock.txt +++ b/dependency_support/pip_requirements_lock.txt @@ -14,6 +14,51 @@ click==8.1.3 \ # via # -r dependency_support/pip_requirements.in # flask +cocotb==1.7.2 \ + --hash=sha256:0c1687ac78141724b8529e029ee6299698ecaa8a2c431b744eeff487a4bb18de \ + --hash=sha256:163e5262020cc21f6a0391fb4727c9ab3ecbf6ee12a1472c8f7320b3ba211a50 \ + --hash=sha256:170cf4d01c4d7c6c5b141ffc1824e846a6c8adbed553a50984cd522c1dddb111 \ + --hash=sha256:1851ac56eed7bb6c745aabfc0e417195cb4f08b5df50846c04eb77a868bfeaba \ + --hash=sha256:1abffb36183b07469c490836c66d8b9e24fc1bec7c27356818618a6719fabd4b \ + --hash=sha256:33be79f048f4072240668a079d2bcebd1a24611a0a1e55439b65ffa0ff077790 \ + --hash=sha256:34ab1bf3f18476724dd4e21dbcc0e060e813eb502abe155b800084fb6945360c \ + --hash=sha256:360019f74270661d14e9caa8103e740a070cb466ab08376a565ec0ef4c13dbbf \ + --hash=sha256:37ddb79f4ab60d2d2dc5a9db5bf767d226eb4978fd15b84dfb968d31ab2fcda5 \ + --hash=sha256:43f5af578803e5726b5c75421c0e35e54021ab423d3aa4efe930feb740d6479d \ + --hash=sha256:4738f36b9730cc05b74ccba3648dba0455cf9f237abf822ef307a274a29474c2 \ + --hash=sha256:4aa5d73ebdb59ef24cef36a1f8cca11dcecb3ee7b71a84df02751020bc67ea77 \ + --hash=sha256:574d21501ff1a3d36889397cd58a18d102d0e40391aa7a0274b600d1cc4c7dc3 \ + --hash=sha256:69f4e539dd308c9e169ab23135138ec397061b700f209803a6022ae9fbe08933 \ + --hash=sha256:6f289ac00f4884046ec64db7006e47b1c857a36dcd2a80ea0873cbff00248368 \ + --hash=sha256:707f795a17679b4653a50bd4094536a46fbfee5c6e3d951fac4320ee211ad13f \ + --hash=sha256:7828e22946f128aa59cb9254de4037b99e3bd5a51fe8f590cf64a3141d742a37 \ + --hash=sha256:82f694da656a699154b15ee28be3ac39c41a71d33985313deda12a3645f8b3db \ + --hash=sha256:959892eb94bd0b3ff40e0fca51d33a3936416deb853e2bac4f7f766b40002650 \ + --hash=sha256:a7ec6a2d212c27ec46bed17a15d60b7b29cd0f734f11cc16d2cb4d3f6136e133 \ + --hash=sha256:a90c77f4bbfdf73aa16093dfe95c68af1a1ca685ebfa525f3f150eab252f6728 \ + --hash=sha256:b288a59fa8dffc1cbc53105e71e2f8c82421081b17282e41319832654b309477 \ + --hash=sha256:c41cc8d4ece57f5e26076cd12f1e11d464d7f118fdb74b958269535185d99a30 \ + --hash=sha256:c8dce91d2a918ee63338d79b08e3d52f1d2797efd9c2bedd13c33d674f730db8 \ + --hash=sha256:d26a8a40cea61f295be04b1164a5dd9ec873f13a39814ad00efec7fd899320e0 \ + --hash=sha256:d80b3baafff1a8a91ac860023c448c603767bed502258160a5cb6029976fec4f \ + --hash=sha256:dcf5354268f16d9e11e05cf3616172ca5ef503b45567f75ebd96a0bfdb9832d1 \ + --hash=sha256:ded849360fb31746f1ba3a994f89c3bba2466ec2d0b4b5da0030645645f938d4 \ + --hash=sha256:e03df73573aec261447602904bd66927eeb2f00dd24370dc9a57f47fd42c4d70 \ + --hash=sha256:f97c2eb92cb68831f19b82ba0038ce40fa73c5edbffb7930745edac20c5358d1 \ + --hash=sha256:fa8abed5260baf4306fbfb997c8789fe24bc229cd762b12d7dba0b9c20147b1d + # via + # -r dependency_support/pip_requirements.in + # cocotb-bus + # cocotbext-axi +cocotb-bus==0.2.1 \ + --hash=sha256:a197aa4b0e0ad28469c8877b41b3fb2ec0206da9f491b9276d1578ce6dd8aa8d + # via + # -r dependency_support/pip_requirements.in + # cocotbext-axi +cocotbext-axi==0.1.24 \ + --hash=sha256:3ed62dcaf9448833176826507c5bc5c346431c4846a731e409d87c862d960593 \ + --hash=sha256:533ba6c7503c6302bdb9ef86e43a549ad5da876eafb1adce23d39751c54cced4 + # via -r dependency_support/pip_requirements.in contourpy==1.3.1 \ --hash=sha256:041b640d4ec01922083645a94bb3b2e777e6b626788f4095cf21abbe266413c1 \ --hash=sha256:05e806338bfeaa006acbdeba0ad681a10be63b26e1b17317bfac3c5d98f36cda \ @@ -74,6 +119,10 @@ cycler==0.12.1 \ --hash=sha256:85cef7cff222d8644161529808465972e51340599459b8ac3ccbac5a854e0d30 \ --hash=sha256:88bb128f02ba341da8ef447245a9e138fae777f6a23943da4540077d3601eb1c # via matplotlib +find-libpython==0.4.0 \ + --hash=sha256:034a4253bd57da3408aefc59aeac1650150f6c1f42e10fdd31615cf1df0842e3 \ + --hash=sha256:46f9cdcd397ddb563b2d7592ded3796a41c1df5222443bd9d981721c906c03e6 + # via cocotb flask==2.3.2 \ --hash=sha256:77fd4e1249d8c9923de34907236b747ced06e5467ecac1a7bb7115ae0e9670b0 \ --hash=sha256:8c2f9abd47a9e8df7f0c3f091ce9497d011dc3b31effcf4c85a6e2b50f4114ef diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index fcd076ae01..1a05177799 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -14,9 +14,11 @@ # Build rules for XLS ZSTD codec implementation. -load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route") +# pytype binary, library +load("@rules_hdl//place_and_route:build_defs.bzl", "collect_benchmark_reports", "place_and_route") load("@rules_hdl//synthesis:build_defs.bzl", "benchmark_synth", "synthesize_rtl") load("@rules_hdl//verilog:providers.bzl", "verilog_library") +load("@xls_pip_deps//:requirements.bzl", "requirement") load( "//xls/build_rules:xls_build_defs.bzl", "xls_benchmark_ir", @@ -837,7 +839,7 @@ SEQUENCE_EXECUTOR_CODEGEN_ARGS = COMMON_CODEGEN_ARGS | { "delay_model": "asap7", "ram_configurations": ",".join([ "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, + latency = 1, ram_name = "ram{}".format(num), rd_req = "sequence_executor__rd_req_m{}_s".format(num), rd_resp = "sequence_executor__rd_resp_m{}_r".format(num), @@ -1184,7 +1186,7 @@ xls_dslx_verilog( "delay_model": "asap7", # FIXME: update ram rewrite #"ram_configurations": "ram:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - # latency = 5, + # latency = 1, # rd_req = "fse_proba_freq_dec__rd_req_s", # rd_resp = "fse_proba_freq_dec__rd_resp_r", # wr_req = "fse_proba_freq_dec__wr_req_s", @@ -1210,7 +1212,7 @@ xls_benchmark_ir( "reset": "rst", # FIXME: update ram rewrite #"ram_configurations": "ram:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - # latency = 5, + # latency = 1, # rd_req = "fse_proba_freq_dec__rd_req_s", # rd_resp = "fse_proba_freq_dec__rd_resp_r", # wr_req = "fse_proba_freq_dec__wr_req_s", @@ -1444,6 +1446,28 @@ xls_dslx_test( ], ) +py_binary( + name = "zstd_test_frames_generator", + srcs = ["zstd_frame_dslx.py"], + imports = ["."], + main = "zstd_frame_dslx.py", + tags = ["manual"], + visibility = ["//xls:xls_users"], + deps = [ + "//xls/common:runfiles", + "//xls/modules/zstd/cocotb:data_generator", + "@com_google_protobuf//:protobuf_python", + ], +) + +genrule( + name = "zstd_test_frames_generate", + srcs = [], + outs = ["zstd_frame_testcases.x"], + cmd = "$(location :zstd_test_frames_generator) --seed 36 -n 1 --btype COMPRESSED -o $@", + tools = [":zstd_test_frames_generator"], +) + zstd_dec_deps = [ ":axi_csr_accessor_dslx", ":block_header_dec_dslx", @@ -1475,7 +1499,7 @@ xls_dslx_library( xls_dslx_test( name = "zstd_dec_dslx_test", - size = "large", + size = "enormous", srcs = [ "data/comp_frame.x", "data/comp_frame_fse_comp.x", @@ -1492,6 +1516,169 @@ xls_dslx_test( deps = zstd_dec_deps, ) +ZSTD_DEC_CODEGEN_ARGS = COMMON_CODEGEN_ARGS | { + "module_name": "ZstdDecoder", + "clock_period_ps": "0", + "pipeline_stages": "16", + "worst_case_throughput": "6", + # "flop_inputs_kind": "skid", + # "flop_outputs_kind": "skid", + "materialize_internal_fifos": "false", # TODO: remove once this option works with loopback channels + "ram_configurations": ",".join([ + ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "history_buffer_ram{}".format(num), + rd_req = "zstd_dec__ram_rd_req_{}_s".format(num), + rd_resp = "zstd_dec__ram_rd_resp_{}_r".format(num), + wr_req = "zstd_dec__ram_wr_req_{}_s".format(num), + wr_resp = "zstd_dec__ram_wr_resp_{}_r".format(num), + ) + for num in range(8) + ]), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "dpd_ram", + rd_req = "zstd_dec__dpd_rd_req_s", + rd_resp = "zstd_dec__dpd_rd_resp_r", + wr_req = "zstd_dec__dpd_wr_req_s", + wr_resp = "zstd_dec__dpd_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "fse_tmp_ram", + rd_req = "zstd_dec__tmp_rd_req_s", + rd_resp = "zstd_dec__tmp_rd_resp_r", + wr_req = "zstd_dec__tmp_wr_req_s", + wr_resp = "zstd_dec__tmp_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "fse_tmp2_ram", + rd_req = "zstd_dec__tmp2_rd_req_s", + rd_resp = "zstd_dec__tmp2_rd_resp_r", + wr_req = "zstd_dec__tmp2_wr_req_s", + wr_resp = "zstd_dec__tmp2_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "ll_def_fse_ram", + rd_req = "zstd_dec__ll_def_fse_rd_req_s", + rd_resp = "zstd_dec__ll_def_fse_rd_resp_r", + wr_req = "zstd_dec__ll_def_fse_wr_req_s", + wr_resp = "zstd_dec__ll_def_fse_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "ll_fse_ram", + rd_req = "zstd_dec__ll_fse_rd_req_s", + rd_resp = "zstd_dec__ll_fse_rd_resp_r", + wr_req = "zstd_dec__ll_fse_wr_req_s", + wr_resp = "zstd_dec__ll_fse_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "ml_def_fse_ram", + rd_req = "zstd_dec__ml_def_fse_rd_req_s", + rd_resp = "zstd_dec__ml_def_fse_rd_resp_r", + wr_req = "zstd_dec__ml_def_fse_wr_req_s", + wr_resp = "zstd_dec__ml_def_fse_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "ml_fse_ram", + rd_req = "zstd_dec__ml_fse_rd_req_s", + rd_resp = "zstd_dec__ml_fse_rd_resp_r", + wr_req = "zstd_dec__ml_fse_wr_req_s", + wr_resp = "zstd_dec__ml_fse_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "of_def_fse_ram", + rd_req = "zstd_dec__of_def_fse_rd_req_s", + rd_resp = "zstd_dec__of_def_fse_rd_resp_r", + wr_req = "zstd_dec__of_def_fse_wr_req_s", + wr_resp = "zstd_dec__of_def_fse_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "of_fse_ram", + rd_req = "zstd_dec__of_fse_rd_req_s", + rd_resp = "zstd_dec__of_fse_rd_resp_r", + wr_req = "zstd_dec__of_fse_wr_req_s", + wr_resp = "zstd_dec__of_fse_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "huffman_literals_prescan_ram", + rd_req = "zstd_dec__huffman_lit_prescan_mem_rd_req_s", + rd_resp = "zstd_dec__huffman_lit_prescan_mem_rd_resp_r", + wr_req = "zstd_dec__huffman_lit_prescan_mem_wr_req_s", + wr_resp = "zstd_dec__huffman_lit_prescan_mem_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "huffman_literals_weights_dpd_ram", + rd_req = "zstd_dec__huffman_lit_weights_dpd_rd_req_s", + rd_resp = "zstd_dec__huffman_lit_weights_dpd_rd_resp_r", + wr_req = "zstd_dec__huffman_lit_weights_dpd_wr_req_s", + wr_resp = "zstd_dec__huffman_lit_weights_dpd_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "huffman_literals_weights_tmp_ram", + rd_req = "zstd_dec__huffman_lit_weights_tmp_rd_req_s", + rd_resp = "zstd_dec__huffman_lit_weights_tmp_rd_resp_r", + wr_req = "zstd_dec__huffman_lit_weights_tmp_wr_req_s", + wr_resp = "zstd_dec__huffman_lit_weights_tmp_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "huffman_literals_weights_tmp2_ram", + rd_req = "zstd_dec__huffman_lit_weights_tmp2_rd_req_s", + rd_resp = "zstd_dec__huffman_lit_weights_tmp2_rd_resp_r", + wr_req = "zstd_dec__huffman_lit_weights_tmp2_wr_req_s", + wr_resp = "zstd_dec__huffman_lit_weights_tmp2_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "huffman_literals_weights_fse_ram", + rd_req = "zstd_dec__huffman_lit_weights_fse_rd_req_s", + rd_resp = "zstd_dec__huffman_lit_weights_fse_rd_resp_r", + wr_req = "zstd_dec__huffman_lit_weights_fse_wr_req_s", + wr_resp = "zstd_dec__huffman_lit_weights_fse_wr_resp_r", + ), + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "huffman_literals_weights_mem_ram", + rd_req = "zstd_dec__huffman_lit_weights_mem_rd_req_s", + rd_resp = "zstd_dec__huffman_lit_weights_mem_rd_resp_r", + wr_req = "zstd_dec__huffman_lit_weights_mem_wr_req_s", + wr_resp = "zstd_dec__huffman_lit_weights_mem_wr_resp_r", + ), + ",".join([ + "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( + latency = 1, + ram_name = "literals_buffer_ram{}".format(num), + rd_req = "zstd_dec__litbuf_rd_req_s__{}".format(num), + rd_resp = "zstd_dec__litbuf_rd_resp_r__{}".format(num), + wr_req = "zstd_dec__litbuf_wr_req_s__{}".format(num), + wr_resp = "zstd_dec__litbuf_wr_resp_r__{}".format(num), + ) + for num in range(8) + ]), + ]), +} + +xls_dslx_verilog( + name = "zstd_dec_verilog", + codegen_args = ZSTD_DEC_CODEGEN_ARGS, + dslx_top = "ZstdDecoderInst", + library = ":zstd_dec_dslx", + tags = ["manual"], + verilog_file = "zstd_dec.v", +) + ZSTD_DEC_INTERNAL_CODEGEN_ARGS = COMMON_CODEGEN_ARGS | { "module_name": "ZstdDecoderInternal", "pipeline_stages": "2", @@ -1551,6 +1738,138 @@ place_and_route( target_die_utilization_percentage = "10", ) +verilog_library( + name = "zstd_dec_verilog_lib", + srcs = [ + ":zstd_dec.v", + ], + tags = ["manual"], +) + +synthesize_rtl( + name = "zstd_dec_synth_asap7", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", + tags = ["manual"], + top_module = "ZstdDecoder", + deps = [ + ":zstd_dec_verilog_lib", + "//xls/modules/zstd/rtl:xls_fifo_wrapper_verilog_lib", + ], +) + +benchmark_synth( + name = "zstd_dec_benchmark_synth", + synth_target = ":zstd_dec_synth_asap7", + tags = ["manual"], +) + +#place_and_route( +# name = "zstd_dec_place_and_route", +# clock_period = CLOCK_PERIOD_PS, +# core_padding_microns = 2, +# min_pin_distance = "0.4", +# placement_density = "0.1", +# stop_after_step = "global_routing", +# synthesized_rtl = ":zstd_dec_synth_asap7", +# tags = ["manual"], +# target_die_utilization_percentage = "1", +#) + +filegroup( + name = "zstd_dec_xx_fse_default", + srcs = [ + "zstd_dec_ll_fse_default.mem", + "zstd_dec_ml_fse_default.mem", + "zstd_dec_of_fse_default.mem", + ], +) + +genrule( + name = "axi_crossbar_wrapper", + outs = ["axi_crossbar_wrapper.v"], + cmd = "$(location @com_github_alexforencich_verilog_axi//:axi_crossbar_wrap) -p 15 1 -n axi_crossbar_wrapper -o $(OUTS)", + tools = [ + "@com_github_alexforencich_verilog_axi//:axi_crossbar_wrap", + ], +) + +py_test( + name = "zstd_dec_cocotb_test", + srcs = ["zstd_dec_cocotb_test.py"], + data = [ + "data/comp_frame.zst", + "data/comp_frame_fse_comp.zst", + "data/comp_frame_fse_repeated.zst", + "data/comp_frame_huffman.zst", + "data/comp_frame_huffman_fse.zst", + "data/fse_huffman_literals_predefined_sequences_seed_107958.zst", + "data/fse_huffman_literals_predefined_sequences_seed_204626.zst", + "data/fse_huffman_literals_predefined_sequences_seed_210872.zst", + "data/fse_huffman_literals_predefined_sequences_seed_299289.zst", + "data/fse_huffman_literals_predefined_sequences_seed_319146.zst", + "data/fse_huffman_literals_predefined_sequences_seed_331938.zst", + "data/fse_huffman_literals_predefined_sequences_seed_333824.zst", + "data/pregenerated_compressed_minimal.zst", + "data/pregenerated_compressed_random_1.zst", + "data/pregenerated_compressed_random_2.zst", + "data/pregenerated_compressed_raw_1.zst", + "data/pregenerated_compressed_raw_2.zst", + "data/pregenerated_compressed_rle_1.zst", + "data/pregenerated_compressed_rle_2.zst", + "data/pregenerated_uncompressed.zst", + "data/raw_literals_compressed_sequences_seed_903062.zst", + "data/raw_literals_predefined_sequences_seed_422473.zst", + "data/raw_literals_predefined_sequences_seed_436965.zst", + "data/raw_literals_predefined_sequences_seed_462302.zst", + "data/raw_literals_rle_sequences_seed_700216.zst", + "data/rle_literals_compressed_sequences_seed_701326.zst", + "data/rle_literals_predefined_sequences_seed_406229.zst", + "data/rle_literals_predefined_sequences_seed_411034.zst", + "data/rle_literals_predefined_sequences_seed_413015.zst", + "data/rle_literals_predefined_sequences_seed_436165.zst", + "data/rle_literals_predefined_sequences_seed_464057.zst", + "data/rle_literals_predefined_sequences_seed_466803.zst", + "data/rle_literals_rle_sequences_seed_2.zst", + "data/rle_raw_literals_predefined_sequences_seed_408158.zst", + "data/rle_raw_literals_predefined_sequences_seed_499212.zst", + "data/treeless_huffman_literals_compressed_sequences_seed_400077.zst", + "data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.zst", + "data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.zst", + "data/treeless_huffman_literals_rle_sequences_seed_403927.zst", + ":axi_crossbar_wrapper.v", + ":zstd_dec.v", + ":zstd_dec_xx_fse_default", + "//xls/modules/zstd/rtl:ram_1r1w.v", + "//xls/modules/zstd/rtl:xls_fifo_wrapper.sv", + "//xls/modules/zstd/rtl:zstd_dec_wrapper.sv", + "@com_github_alexforencich_verilog_axi//:rtl/arbiter.v", + "@com_github_alexforencich_verilog_axi//:rtl/axi_crossbar.v", + "@com_github_alexforencich_verilog_axi//:rtl/axi_crossbar_addr.v", + "@com_github_alexforencich_verilog_axi//:rtl/axi_crossbar_rd.v", + "@com_github_alexforencich_verilog_axi//:rtl/axi_crossbar_wr.v", + "@com_github_alexforencich_verilog_axi//:rtl/axi_register_rd.v", + "@com_github_alexforencich_verilog_axi//:rtl/axi_register_wr.v", + "@com_github_alexforencich_verilog_axi//:rtl/priority_encoder.v", + "@com_icarus_iverilog//:iverilog", + "@com_icarus_iverilog//:vvp", + ], + tags = ["manual"], + visibility = ["//xls:xls_users"], + deps = [ + requirement("cocotb"), + requirement("cocotbext-axi"), + "//xls/common:runfiles", + "//xls/modules/zstd/cocotb:channel", + "//xls/modules/zstd/cocotb:data_generator", + "//xls/modules/zstd/cocotb:memory", + "//xls/modules/zstd/cocotb:utils", + "//xls/modules/zstd/cocotb:xlsstruct", + "@abseil-py//absl:app", + "@abseil-py//absl/flags", + "@com_google_protobuf//:protobuf_python", + ], +) + xls_dslx_library( name = "comp_lookup_dec_dslx", srcs = [ @@ -1883,7 +2202,7 @@ RAM_DEMUX_CODEGEN_ARGS = { "worst_case_throughput": "6", "ram_configurations": ",".join([ "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, + latency = 1, ram_name = "ram{}".format(num), rd_req = "ram_demux__rd_req{}_s".format(num), rd_resp = "ram_demux__rd_resp{}_r".format(num), @@ -1895,6 +2214,7 @@ RAM_DEMUX_CODEGEN_ARGS = { "clock_period_ps": "750", "reset": "rst", "use_system_verilog": "false", + "streaming_channel_data_suffix": "_data", "materialize_internal_fifos": "true", } @@ -1972,6 +2292,34 @@ ram_demux_naive_codegen_args = { "materialize_internal_fifos": "true", } +py_test( + name = "ram_demux_cocotb_test", + srcs = ["ram_demux_cocotb_test.py"], + data = [ + "//xls/modules/zstd:ram_demux.v", + "//xls/modules/zstd/rtl:ram_1r1w.v", + "//xls/modules/zstd/rtl:ram_demux_wrapper.v", + "@com_icarus_iverilog//:iverilog", + "@com_icarus_iverilog//:vvp", + ], + env = { + "PYTHONUNBUFFERED": "1", + }, + imports = ["."], + tags = ["manual"], + visibility = ["//xls:xls_users"], + deps = [ + requirement("cocotb"), + requirement("cocotbext-axi"), + "//xls/common:runfiles", + "//xls/modules/zstd/cocotb:channel", + "//xls/modules/zstd/cocotb:data_generator", + "//xls/modules/zstd/cocotb:memory", + "//xls/modules/zstd/cocotb:utils", + "//xls/modules/zstd/cocotb:xlsstruct", + ], +) + xls_dslx_verilog( name = "ram_demux_naive_verilog", codegen_args = ram_demux_naive_codegen_args, @@ -2174,7 +2522,7 @@ xls_dslx_verilog( "delay_model": "asap7", "ram_configurations": ",".join([ "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, + latency = 1, ram_name = "ram{}".format(num), rd_req = "ram_demux3__rd_req{}_s".format(num), rd_resp = "ram_demux3__rd_resp{}_r".format(num), @@ -2585,7 +2933,7 @@ xls_dslx_verilog( "delay_model": "asap7", "ram_configurations": ",".join([ "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, + latency = 1, ram_name = "ram{}".format(num), rd_req = "literals_buffer__rd_req_m{}_s".format(num), rd_resp = "literals_buffer__rd_resp_m{}_r".format(num), @@ -2752,7 +3100,7 @@ LITERALS_DECODER_CODEGEN_ARGS = { "delay_model": "asap7", "ram_configurations": ",".join([ "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( - latency = 5, + latency = 1, ram_name = "ram{}".format(num), rd_req = "literals_decoder__rd_req_m{}_s".format(num), rd_resp = "literals_decoder__rd_resp_m{}_r".format(num), @@ -3005,7 +3353,7 @@ benchmark_synth( ) place_and_route( - name = "huffman_code_builder_place_and_route", + name = "huffman_code_builder_place_and_route_skip", clock_period = CLOCK_PERIOD_PS, core_padding_microns = 2, min_pin_distance = "0.5", @@ -3528,3 +3876,46 @@ xls_dslx_test( name = "refilling_shift_buffer_mux_dslx_test", library = ":refilling_shift_buffer_mux_dslx", ) + +collect_benchmark_reports( + name = "all_banchmark_reports", + srcs = [ + ":window_buffer_place_and_route", + ":shift_buffer_aligner_place_and_route", + ":shift_buffer_storage_place_and_route", + ":shift_buffer_place_and_route", + ":frame_header_dec_place_and_route", + ":block_header_dec_place_and_route", + ":raw_block_dec_place_and_route", + ":rle_block_dec_place_and_route", + ":dec_mux_place_and_route", + ":sequence_executor_place_and_route", + ":axi_csr_accessor_place_and_route", + ":csr_config_place_and_route", + ":ram_rw_handler_place_and_route", + ":fse_proba_freq_dec_place_and_route", + ":refilling_shift_buffer_internal_place_and_route", + ":zstd_dec_internal_place_and_route", + ":fse_table_iterator_place_and_route", + ":fse_table_creator_place_and_route", + ":command_constructor_place_and_route", + ":ram_demux_place_and_route", + ":ram_demux_naive_place_and_route", + ":fse_dec_place_and_route", + ":ram_demux3_place_and_route", + ":rle_literals_dec_place_and_route", + ":raw_literals_dec_place_and_route", + ":literals_buffer_place_and_route", + ":literals_decoder_ctrl_place_and_route", + # ":literals_decoder_place_and_route", + ":huffman_prescan_place_and_route", + # ":huffman_code_builder_place_and_route", + ":huffman_axi_reader_place_and_route", + # ":huffman_data_preprocessor_place_and_route", + # ":huffman_decoder_place_and_route", + ":huffman_ctrl_place_and_route", + ":huffman_weights_dec_place_and_route", + # ":huffman_literals_dec_place_and_route", + # ":zstd_dec_place_and_route", + ], +) diff --git a/xls/modules/zstd/README.md b/xls/modules/zstd/README.md index fb079592e3..c0785c1fc7 100644 --- a/xls/modules/zstd/README.md +++ b/xls/modules/zstd/README.md @@ -10,7 +10,7 @@ the diagram below. The decoder comprises: * Control and Status Registers, * Frame Header Decoder, * Block Header Decoder, -* 3 types of processing units: RAW-, RLE-, and Compressed Block Decoders[^1], +* 3 types of processing units: RAW-, RLE-, and Compressed Block Decoders, * Command Aggregator, The Decoder interacts with the environment through a set of ports: @@ -39,7 +39,7 @@ Once the decoding process is started, the decoder: updates the history, 7. Prepares the final output of the decoder and writes it to the memory, 8. (Optional) Calculates checksum and compares it against the checksum read - from the frame.[^2] + from the frame.[^1] ![brief data flow diagram of ZstdDecoder](img/ZSTD_decoder.png) @@ -220,7 +220,7 @@ processing request to the `RleBlockDecoder`. The proc produces `N*s` repeats of the given symbol. This step preserves the block ID and attaches the literals tag to all its outputs. -#### CompressedBlockDecoder[^1] +#### CompressedBlockDecoder This part of the design is responsible for decoding the compressed data blocks. It ingests the bytes stream, and internally translates and interprets incoming @@ -262,7 +262,7 @@ will show the following behavior, depending on the tag: * Copy `copy_length` literals starting `offset _length` from the newest in history buffer to the history buffer as the newest. -### Compressed block decoder architecture[^1] {#compressed-block-decoder-architecture1} +### Compressed block decoder architecture {#compressed-block-decoder-architecture1} This part of the design is responsible for processing the compressed blocks up to the `literals`/`copy` command sequence. This sequence is then processed by @@ -278,7 +278,7 @@ Treeless blocks. #### Compressed block dispatcher This proc parses literals section headers to calculate block compression format, -Huffmman tree size (if applicable based on compression format), compressed and +Huffman tree size (if applicable based on compression format), compressed and regenerated sizes for literals. If compressed block format is `Compressed_Literals_Block`, dispatcher reads Huffman tree header byte from Huffman bitstream, and directs expected number of bytes to the Huffman tree @@ -452,6 +452,9 @@ results against the decoding of the reference library. Currently, due to the restrictions from the ZSTD frame generator, it is possible to test only the positive cases (decoding valid ZSTD frames). +Verilog tests are written in Python as +[cocotb](https://github.com/cocotb/cocotb) testbench. + ZstdDecoder's main communication interfaces are the AXI buses. Due to the way XLS handles the codegen of DSLX channels that model the AXI channels, the particular ports of the AXI channels are not represented correctly. This @@ -465,6 +468,33 @@ Crossbar](https://github.com/alexforencich/verilog-axi). ![diagram of interfaces of decoder and its wrapper](img/ZSTD_decoder_wrapper.png) +**Figure: Zstd decoder wrapper connection diagram.** + +Cocotb testbench interacts with the decoder with the help of a +[cocotbext-axi](https://github.com/alexforencich/cocotbext-axi) extension that +provides AXI bus models, drivers, monitors and RAM model accessible through AXI +interface. Cocotb AXI Manager is connected to the decoder's `CSR Interface` and +is used to simulate the software's interaction with the decoder. + +The Basic test case for the ZstdDecoder is composed of the following steps: + +1. The testbench generates a ZSTD frame using the + [decodecorpus](https://github.com/facebook/zstd/blob/dev/tests/decodecorpus.c) + utility from the [zstd reference library](https://github.com/facebook/zstd). +2. The encoded frame is placed in an AXI RAM model that is connected to the + decoder's `Memory Interface`. +3. The encoded frame is decoded with the zstd reference library and the results + are represented in the decoder's output format as the expected data from the + simulation. +4. AXI Manager performs a series of writes to the ZstdDecoder CSRs to configure + it and start the decoding process. +5. Testbench waits for the signal on the `Notify` channel and checks the output + of the decoder stored in the memory against the expected output data. +6. Test case succeeds once `Notify` is asserted, all expected data is received + and the decoder lands in `IDLE` state with status `OKAY` in the `Status` CSR. + +Additionally, pregenerated test cases are provided in the [data](data/) subdirectory. `*.zst` files contain frames encoded using the ZSTD library. Supplementary `*.log` files provide additional info regarding the contents of each frame. Among the aforementioned test cases, those generated using `decodecorpus` follow the `__seed_` naming convention. + ### Failure points #### User-facing decoder errors @@ -478,6 +508,10 @@ The design will fail the tests under the following conditions: results from the reference library * The decoding result from the simulation has different contents than the results from the reference library +* Failures caused by incorrect intermediate results (only in the selected tests): + * Incorrect decoding of the FSE table + * Incorrect Huffman weights + * Incorrect Huffman codebook Currently, all mentioned conditions lead to an eventual test failure. @@ -537,3 +571,49 @@ This is done for example in: * Frame header decoder * SequenceExecutor + +#### Positive test cases + +If the results of decoding with `libzstd` are valid, the test runs the same +encoded frame through the simulation of DSLX design. The output of the +simulation is gathered and compared with the results of `libzstd` in terms of +its size and contents. + +Encoded ZSTD frame is generated with the function `GenerateFrame(seed, btype, +output_path)` from +[data_generator](https://github.com/antmicro/xls/blob/main/xls/modules/zstd/cocotb/data_generator.py) +library. This function takes as arguments the seed for the generator, an enum +that codes the type of blocks that should be generated in a given frame and the +output path to write the generated frame into a file. The available block types +are: + +* RAW +* RLE +* COMPRESSED +* RANDOM + +The function returns a vector of bytes representing a valid encoded ZSTD frame. +Such generated frame can be passed to DSLX and cocotb testbenches to be decoded +in the simulation and compared against the results from the reference library. + +Verilog tests are available in the `zstd_dec_cocotb_test.py` file and can be +launched with the following Bazel command: + +```shell +bazel run -c opt -- //xls/modules/zstd:zstd_dec_cocotb_test --logtostderr +``` + +#### Negative test cases + +Currently, `decodecorpus` does not support generating ZSTD frames with subtle +errors that trigger failure points provided in the ZSTD Decoder. Because of +that, it is not possible to efficiently provide valuable negative tests for the +integrated ZSTD Decoder. + +The alternatives for writing negative tests include: + +* Generating a well-known valid ZSTD frame from a specific generator seed and +then tweaking the raw bits in this frame to trigger the error response from the +decoder + +[^1]: Checksum verification is currently unsupported. diff --git a/xls/modules/zstd/cocotb/BUILD b/xls/modules/zstd/cocotb/BUILD new file mode 100644 index 0000000000..6c08efa697 --- /dev/null +++ b/xls/modules/zstd/cocotb/BUILD @@ -0,0 +1,76 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +load("@xls_pip_deps//:requirements.bzl", "requirement") + +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//xls:xls_users"], + licenses = ["notice"], +) + +py_library( + name = "channel", + srcs = ["channel.py"], + deps = [ + ":xlsstruct", + requirement("cocotb"), + requirement("cocotb_bus"), + ], +) + +py_library( + name = "memory", + srcs = ["memory.py"], + deps = [ + requirement("cocotbext-axi"), + ], +) + +py_library( + name = "scoreboard", + srcs = ["scoreboard.py"], + deps = [ + ":channel", + ":xlsstruct", + requirement("cocotb"), + ], +) + +py_library( + name = "utils", + srcs = ["utils.py"], + deps = [ + requirement("cocotb"), + "//xls/common:runfiles", + ], +) + +py_library( + name = "xlsstruct", + srcs = ["xlsstruct.py"], + deps = [ + requirement("cocotb"), + ], +) + +py_library( + name = "data_generator", + srcs = ["data_generator.py"], + deps = [ + "//xls/common:runfiles", + "@zstd//:decodecorpus", + "@zstd//:zstd_cli", + ], +) diff --git a/xls/modules/zstd/cocotb/channel.py b/xls/modules/zstd/cocotb/channel.py new file mode 100644 index 0000000000..6b6e546e86 --- /dev/null +++ b/xls/modules/zstd/cocotb/channel.py @@ -0,0 +1,122 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Cocotb interfaces for XLS channels using data, valid, and ready signals.""" + +from typing import Any, Sequence, Type, Union + +import cocotb +from cocotb.handle import SimHandleBase +from cocotb.triggers import RisingEdge +from cocotb_bus.bus import Bus +from cocotb_bus.drivers import BusDriver +from cocotb_bus.monitors import BusMonitor + +from xls.modules.zstd.cocotb.xlsstruct import XLSStruct + +Transaction = Union[XLSStruct, Sequence[XLSStruct]] + +XLS_CHANNEL_SIGNALS = ["data", "rdy", "vld"] +XLS_CHANNEL_OPTIONAL_SIGNALS = [] + + +class XLSChannel(Bus): + """Represents an XLS- channel with ready/valid handshake.""" + _signals = XLS_CHANNEL_SIGNALS + _optional_signals = XLS_CHANNEL_OPTIONAL_SIGNALS + + def __init__(self, entity, name, clk, *, start_now=False, **kwargs: Any): + super().__init__( + entity, name, self._signals, self._optional_signals, **kwargs + ) + self.clk = clk + if start_now: + self.start_recv_loop() + + @cocotb.coroutine + async def recv_channel(self): + """Cocotb coroutine that acts as a proc receiving data from a channel.""" + self.rdy.setimmediatevalue(1) + while True: + await RisingEdge(self.clk) + + def start_recv_loop(self): + cocotb.start_soon(self.recv_channel()) + + +class XLSChannelDriver(BusDriver): + """Drives transactions on an XLS channel.""" + _signals = XLS_CHANNEL_SIGNALS + _optional_signals = XLS_CHANNEL_OPTIONAL_SIGNALS + + def __init__( + self, + entity: SimHandleBase, + name: str, + clock: SimHandleBase, + **kwargs: Any + ): + BusDriver.__init__(self, entity, name, clock, **kwargs) + + self.bus.data.setimmediatevalue(0) + self.bus.vld.setimmediatevalue(0) + + async def _driver_send( + self, + transaction: Transaction, + sync: bool = True, + **kwargs: Any + ) -> None: + if sync: + await RisingEdge(self.clock) + + data_to_send = ( + transaction if isinstance(transaction, Sequence) else [transaction] + ) + + for word in data_to_send: + self.bus.vld.value = 1 + self.bus.data.value = word.binaryvalue + + while True: + await RisingEdge(self.clock) + if self.bus.rdy.value: + break + + self.bus.vld.value = 0 + + +class XLSChannelMonitor(BusMonitor): + """Monitors and decodes transactions on an XLS channel.""" + _signals = XLS_CHANNEL_SIGNALS + _optional_signals = XLS_CHANNEL_OPTIONAL_SIGNALS + + def __init__( + self, + entity: SimHandleBase, + name: str, + clock: SimHandleBase, + struct: Type[XLSStruct], + **kwargs: Any + ): + BusMonitor.__init__(self, entity, name, clock, **kwargs) + self.struct = struct + + @cocotb.coroutine + async def _monitor_recv(self) -> None: + while True: + await RisingEdge(self.clock) + if self.bus.rdy.value and self.bus.vld.value: + vec = self.struct.from_int(self.bus.data.value.integer) + self._recv(vec) diff --git a/xls/modules/zstd/cocotb/data_generator.py b/xls/modules/zstd/cocotb/data_generator.py new file mode 100644 index 0000000000..d0c5cc0495 --- /dev/null +++ b/xls/modules/zstd/cocotb/data_generator.py @@ -0,0 +1,96 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Module for generating and decompressing test frames.""" + +import pathlib +import enum + +from xls.common import runfiles +import subprocess +import tempfile + +class BlockType(enum.Enum): + """Enum encoding of ZSTD block types.""" + + RAW = 0 + RLE = 1 + COMPRESSED = 2 + RANDOM = 3 + + def __str__(self): + return self.name + + @staticmethod + def from_string(s): + try: + return BlockType[s] + except KeyError as e: + raise ValueError(str(e)) from e + +class LiteralType(enum.Enum): + """Enum encoding of ZSTD literal types.""" + + RAW = 0 + RLE = 1 + COMPRESSED = 2 + RANDOM = 3 + + def __str__(self): + return self.name + + @staticmethod + def from_string(s): + try: + return BlockType[s] + except KeyError as e: + raise ValueError(str(e)) from e + +def CallDecodecorpus(args): + decodecorpus = pathlib.Path( + runfiles.get_path("decodecorpus", repository = "zstd") + ) + cmd = args + cmd.insert(0, str(decodecorpus)) + cmd_concat = " ".join(cmd) + subprocess.run(cmd_concat, shell=True, check=True) + +def DecompressFrame(data): + zstd_cli = pathlib.Path(runfiles.get_path("zstd_cli", repository = "zstd")) + with tempfile.NamedTemporaryFile(mode='wb') as input_data, \ + tempfile.NamedTemporaryFile(mode='wb') as output_data: + input_data.write(data) + input_data.flush() + cmd = f"{str(zstd_cli)} -f -d {input_data.name} -o {output_data.name}" + output_data.close() + subprocess.run(cmd, shell=True, check=True) + with open(output_data.name, "rb") as output_data: + return output_data.read() + +def GenerateFrame(seed, btype, output_path, ltype=LiteralType.RANDOM): + args = [] + args.append("-s" + str(seed)) + if (btype != BlockType.RANDOM): + args.append("--block-type=" + str(btype.value)) + + if (ltype != LiteralType.RANDOM): + args.append("--literal-type=" + str(ltype.value)) + + args.append("--content-size") + # Test payloads up to 16KB + args.append("--max-content-size-log=14") + args.append("-p" + output_path) + args.append("-vvvvvvv") + + CallDecodecorpus(args) diff --git a/xls/modules/zstd/cocotb/memory.py b/xls/modules/zstd/cocotb/memory.py new file mode 100644 index 0000000000..a07ef33923 --- /dev/null +++ b/xls/modules/zstd/cocotb/memory.py @@ -0,0 +1,49 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Extensions of the cocotb AXI RAM models to memory contents from a binary file. +""" + +import os + +from cocotbext.axi.axi_ram import AxiRam +from cocotbext.axi.axi_ram import AxiRamRead +from cocotbext.axi.axi_ram import AxiRamWrite +from cocotbext.axi.sparse_memory import SparseMemory + + +def init_axi_mem(path: os.PathLike[str], kwargs): + with open(path, "rb") as f: + sparse_mem = SparseMemory(size=kwargs["size"]) + sparse_mem.write(0x0, f.read()) + kwargs["mem"] = sparse_mem + + +class AxiRamReadFromFile(AxiRamRead): + def __init__(self, *args, path: os.PathLike[str], **kwargs): + init_axi_mem(path, kwargs) + super().__init__(*args, **kwargs) + + +class AxiRamFromFile(AxiRam): + def __init__(self, *args, path: os.PathLike[str], **kwargs): + init_axi_mem(path, kwargs) + super().__init__(*args, **kwargs) + + +class AxiRamWriteFromFile(AxiRamWrite): + def __init__(self, *args, path: os.PathLike[str], **kwargs): + init_axi_mem(path, kwargs) + super().__init__(*args, **kwargs) diff --git a/xls/modules/zstd/cocotb/scoreboard.py b/xls/modules/zstd/cocotb/scoreboard.py new file mode 100644 index 0000000000..b3dfca1e3a --- /dev/null +++ b/xls/modules/zstd/cocotb/scoreboard.py @@ -0,0 +1,82 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Scoreboard creator for measuring request-response latency. + +Tracks transactions from channel monitors, computes cycle-based latency, +and logs results. +""" + +import dataclasses +import queue + +from cocotb.clock import Clock +from cocotb.log import SimLog +from cocotb.utils import get_sim_time + +from xls.modules.zstd.cocotb.channel import XLSChannelMonitor +from xls.modules.zstd.cocotb.xlsstruct import XLSStruct + + +@dataclasses.dataclass +class LatencyQueueItem: + """ + Data container for items in a latency queue. + """ + + transaction: XLSStruct + timestamp: int + + +class LatencyScoreboard: + """Tracks and reports latency between request and response transactions.""" + + def __init__(self, dut, clock: Clock, req_monitor: XLSChannelMonitor, resp_monitor: XLSChannelMonitor): + self.dut = dut + self.log = SimLog(f"zstd.cocotb.scoreboard.{self.dut._name}") + self.clock = clock + self.req_monitor = req_monitor + self.resp_monitor = resp_monitor + self.pending_req = queue.Queue() + self.results = [] + + self.req_monitor.add_callback(self._req_callback) + self.resp_monitor.add_callback(self._resp_callback) + + def _current_cycle(self): + return get_sim_time(units='step') / self.clock.period + + def _req_callback(self, transaction: XLSStruct): + self.pending_req.put(LatencyQueueItem(transaction, self._current_cycle())) + + def _resp_callback(self, unused_transaction: XLSStruct): + latency_item = self.pending_req.get() + self.results.append(self._current_cycle() - latency_item.timestamp) + + def average_latency(self): + return sum(self.results)/len(self.results) + + def report_result(self): + """Logs a summary of latency measurements and any unfulfilled requests.""" + if not self.pending_req.empty(): + self.log.warning(f"There are unfulfilled requests from channel {self.req_monitor.name}") + while not self.pending_req.empty(): + self.log.warning(f"Unfulfilled request: {self.pending_req.get()}") + if self.results: + self.log.info(f"Latency report - 1st latency: {self.results[0]}") + if len(self.results) > 1: + self.log.info(f"Latency report - 2nd latency: {self.results[1]}") + if len(self.results) > 2: + avg = sum(self.results[2:])/len(self.results[2:]) + self.log.info(f"Latency report - rest of the latencies (average): {avg}") diff --git a/xls/modules/zstd/cocotb/utils.py b/xls/modules/zstd/cocotb/utils.py new file mode 100644 index 0000000000..43f9ca16bc --- /dev/null +++ b/xls/modules/zstd/cocotb/utils.py @@ -0,0 +1,85 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Helpers for setting up and running simulations using Icarus Verilog with Cocotb.""" + +import os +import pathlib + +import cocotb +from cocotb.runner import check_results_file +from cocotb.runner import get_runner +from cocotb.triggers import ClockCycles + +from xls.common import runfiles + + +def setup_com_iverilog(): + iverilog_path = pathlib.Path( + runfiles.get_path("iverilog", repository = "com_icarus_iverilog") + ) + vvp_path = pathlib.Path( + runfiles.get_path("vvp", repository = "com_icarus_iverilog") + ) + os.environ["PATH"] += os.pathsep + str(iverilog_path.parent) + os.environ["PATH"] += os.pathsep + str(vvp_path.parent) + build_dir = pathlib.Path("sim_build").absolute() + return build_dir + + +def run_test(toplevel, test_module, verilog_sources, timescale=("1ns", "1ps")): + """Builds and runs a Cocotb testbench using Icarus Verilog.""" + build_dir = setup_com_iverilog() + runner = get_runner("icarus")() + build_args = [] + + cmds_file = build_dir / pathlib.Path("cmds.f") + cmds_file.parent.mkdir(parents=True, exist_ok=True) + with open(cmds_file, "w") as f: + f.write("+timescale+{}/{}\n".format(*timescale)) + build_args += ["-f", str(cmds_file)] + + dump_file = build_dir / pathlib.Path("cocotb_iverilog_dump.v") + wave_file = build_dir / pathlib.Path(f"{toplevel}.fst") + with open(dump_file, "w") as f: + f.write("module cocotb_iverilog_dump();\n") + f.write("initial begin\n") + f.write(f' $dumpfile("{wave_file}");\n') + f.write(f" $dumpvars(0, {toplevel});\n") + f.write("end\n") + f.write("endmodule\n") + wave_file.parent.mkdir(parents=True, exist_ok=True) + + runner.build( + verilog_sources=(verilog_sources + [str(dump_file)]), + toplevel=toplevel, + build_dir=build_dir, + extra_args=build_args, + defines={"SIMULATION": "1"}, + ) + + try: + results_xml = runner.test( + toplevel=toplevel, + py_module=test_module, + ) + finally: + check_results_file(results_xml) + +@cocotb.coroutine +async def reset(clk, rst, cycles=1): + """Cocotb coroutine that performs the reset.""" + rst.value = 1 + await ClockCycles(clk, cycles) + rst.value = 0 diff --git a/xls/modules/zstd/cocotb/xlsstruct.py b/xls/modules/zstd/cocotb/xlsstruct.py new file mode 100644 index 0000000000..131be8e663 --- /dev/null +++ b/xls/modules/zstd/cocotb/xlsstruct.py @@ -0,0 +1,174 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Provides utilities for defining Python representations of XLS structs. +""" + +import random +import dataclasses + +from cocotb.binary import BinaryValue + + +class TruncationError(Exception): + pass + +def xls_dataclass(cls): + """Class decorator for XLS structs. + + Usage: + + @xls_dataclass + class MyStruct(XLSStruct): + ... + Args: + cls (type): The class to decorate. + + Returns: + type: The dataclass-decorated class with repr disabled. + """ + return dataclasses.dataclass(cls, repr=False) + +@dataclasses.dataclass +class XLSStruct: + """Represents XLS struct on the Python side. + + Allows serialization/deserialization to/from common formats and usage with + XLS{Driver, Monitor}. + + The intended way to use this class is to inherit from it, specify the fields + with : [= ] syntax and decorate the inheriting + class with @XLSDataclass. Objects of this class can be instantiated and used + like usual dataclass objects, with a few extra methods and properties + available. They can also be passed as arguments to XLSChannelDriver.send and + will be serialized to expected bit vector. Class can be passed to + XLSChannelMonitor ``struct`` constructor argument to automatically + deserialize all transfers to the provided struct. + + Example: + + from xlsstruct import XLSDataclass, XLSStruct + + @XLSDataclass + class MyStruct(XLSStruct): + data: 32 + ok: 1 + id: 4 = 0 + + monitor = XLSChannelMonitor(dut, CHANNEL_PREFIX, dut.clk, MyStruct) + + driver = XLSChannelDriver(dut, CHANNEL_PREFIX, dut.clk) + driver.send(MyStruct( + data = 0xdeadbeef, + ok = 1, + id = 3, + )) + # struct fields can also be randomized + driver.send(MyStruct.randomize()) + """ + + @classmethod + def _masks(cls): + """Returns a list of field-sized bitmasks. + + For example for fields of widths 2, 3, 4 + returns [2'b11, 3'b111, 4'b1111]. + """ + masks = [] + for field in dataclasses.fields(cls): + width = field.type + masks += [(1 << width) - 1] + return masks + + @classmethod + def _positions(cls): + """Returns a list of start positions in a bit vector for struct's fields. + + For example for fields of widths 1, 2, 3, 4, 5, 6 + returns [20, 18, 15, 11, 6, 0] + """ + positions = [] + for i, field in enumerate(dataclasses.fields(cls)): + width = field.type + if i == 0: + positions += [cls.total_width - width] + else: + positions += [positions[i-1] - width] + return positions + + @classmethod + @property + def total_width(cls): + """Returns total bit width of the struct.""" + return sum(field.type for field in dataclasses.fields(cls)) + + @property + def value(self): + """Returns struct's value as a Python integer.""" + value = 0 + masks = self._masks() + positions = self._positions() + for field_val, mask, pos in zip( + dataclasses.astuple(self), masks, positions): + if field_val > mask: + raise TruncationError("Signal value is wider than its bit width") + value |= (field_val & mask) << pos + return value + + @property + def binaryvalue(self): + """Returns struct's value as a cocotb.binary.BinaryValue.""" + return BinaryValue(self.binstr) + + @property + def binstr(self): + """Returns struct's value as a string with its binary representation.""" + return f"{self.value:>0{self.total_width}b}" + + @property + def hexstr(self): + """Returns struct's value as a string with its hex representation. + + The result does NOT have leading "0x". + """ + return f"{self.value:>0{self.total_width // 4}x}" + + @classmethod + def from_int(cls, value): + """Returns an instance of the struct from Python integer.""" + instance = {} + masks = cls._masks() + positions = cls._positions() + for field, mask, pos in zip(dataclasses.fields(cls), masks, positions): + instance[field.name] = (value >> pos) & mask + return cls(**instance) + + @classmethod + def randomize(cls): + """Returns an instance of the struct with all fields' values randomized.""" + instance = {} + for field in dataclasses.fields(cls): + instance[field.name] = random.randrange(0, 2**field.type) + return cls(**instance) + + def __str__(self): + return self.__repr__() + + def __repr__(self): + classname = self.__class__.__name__ + class_fields = [ + f"{name}={hex(value)}" for name, value in dataclasses.asdict(self).items() + ] + return f"{classname}({', '.join(class_fields)})" diff --git a/xls/modules/zstd/data/comp_frame.zst b/xls/modules/zstd/data/comp_frame.zst new file mode 100644 index 0000000000..800a7bdca9 Binary files /dev/null and b/xls/modules/zstd/data/comp_frame.zst differ diff --git a/xls/modules/zstd/data/comp_frame_fse_comp.zst b/xls/modules/zstd/data/comp_frame_fse_comp.zst new file mode 100644 index 0000000000..f9cf4a5d1f Binary files /dev/null and b/xls/modules/zstd/data/comp_frame_fse_comp.zst differ diff --git a/xls/modules/zstd/data/comp_frame_fse_repeated.zst b/xls/modules/zstd/data/comp_frame_fse_repeated.zst new file mode 100644 index 0000000000..8fed4b3fbe Binary files /dev/null and b/xls/modules/zstd/data/comp_frame_fse_repeated.zst differ diff --git a/xls/modules/zstd/data/comp_frame_huffman.zst b/xls/modules/zstd/data/comp_frame_huffman.zst new file mode 100644 index 0000000000..7f21a9f870 Binary files /dev/null and b/xls/modules/zstd/data/comp_frame_huffman.zst differ diff --git a/xls/modules/zstd/data/comp_frame_huffman_fse.zst b/xls/modules/zstd/data/comp_frame_huffman_fse.zst new file mode 100644 index 0000000000..4be6a40cbb Binary files /dev/null and b/xls/modules/zstd/data/comp_frame_huffman_fse.zst differ diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_107958.log b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_107958.log new file mode 100644 index 0000000000..74008be9c2 --- /dev/null +++ b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_107958.log @@ -0,0 +1,30 @@ +seed: 107958 +frame seed: 107958 + frame content size: 100 + frame window size: 1536 + content size flag: 1 + single segment flag: 0 + block: + block content size: 100 + last block: yes + compressed block: + compressed literals + distribution weight: 81% + huffman log: 10 + regenerated size: 45 + compressed size: 22 + literals size: 45 + total match lengths: 55 + LL: 13 OF: 9 ML: 4 srcPos: 17 seqNb: 0 + LL: 12 OF: 6 ML: 9 srcPos: 38 seqNb: 1 + LL: 3 OF: 36 ML: 25 srcPos: 66 seqNb: 2 + LL: 0 OF: 42 ML: 5 srcPos: 71 seqNb: 3 + LL: 14 OF: 2 ML: 5 srcPos: 90 seqNb: 4 + LL: 0 OF: 27 ML: 3 srcPos: 93 seqNb: 5 + LL: 1 OF: 67 ML: 4 srcPos: 98 seqNb: 6 + excess literals: 2 srcPos: 100 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 7 + block type: compressed + block size field: 44 + checksum: 61c6e5a0 diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_107958.zst b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_107958.zst new file mode 100644 index 0000000000..b44e0191ea Binary files /dev/null and b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_107958.zst differ diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_204626.log b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_204626.log new file mode 100644 index 0000000000..6a11616659 --- /dev/null +++ b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_204626.log @@ -0,0 +1,25 @@ +seed: 204626 +frame seed: 204626 + frame content size: 89 + frame window size: 1152 + content size flag: 1 + single segment flag: 0 + block: + block content size: 89 + last block: yes + compressed block: + compressed literals + distribution weight: 64% + huffman log: 9 + regenerated size: 66 + compressed size: 36 + literals size: 66 + total match lengths: 23 + LL: 42 OF: 16 ML: 9 srcPos: 51 seqNb: 0 + LL: 24 OF: 6 ML: 14 srcPos: 89 seqNb: 1 + excess literals: 0 srcPos: 89 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 2 + block type: compressed + block size field: 47 + checksum: 9834e3da diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_204626.zst b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_204626.zst new file mode 100644 index 0000000000..cc5812eb6a Binary files /dev/null and b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_204626.zst differ diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_210872.log b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_210872.log new file mode 100644 index 0000000000..3ef449b1fe --- /dev/null +++ b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_210872.log @@ -0,0 +1,28 @@ +seed: 210872 +frame seed: 210872 + frame content size: 76 + frame window size: 76 + content size flag: 1 + single segment flag: 1 + block: + block content size: 76 + last block: yes + compressed block: + compressed literals + distribution weight: 57% + huffman log: 10 + regenerated size: 59 + compressed size: 45 + literals size: 59 + total match lengths: 17 + LL: 2 OF: 1 ML: 4 srcPos: 6 seqNb: 0 + LL: 7 OF: 1 ML: 3 srcPos: 16 seqNb: 1 + LL: 3 OF: 1 ML: 4 srcPos: 23 seqNb: 2 + LL: 0 OF: 1 ML: 3 srcPos: 26 seqNb: 3 + LL: 42 OF: 14 ML: 3 srcPos: 71 seqNb: 4 + excess literals: 5 srcPos: 76 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 5 + block type: compressed + block size field: 64 + checksum: 6f916f12 diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_210872.zst b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_210872.zst new file mode 100644 index 0000000000..292089888e Binary files /dev/null and b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_210872.zst differ diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_299289.log b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_299289.log new file mode 100644 index 0000000000..f2f01bd94a --- /dev/null +++ b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_299289.log @@ -0,0 +1,39 @@ +seed: 299289 +frame seed: 299289 + frame content size: 68 + frame window size: 294912 + content size flag: 1 + single segment flag: 0 + block: + block content size: 68 + last block: yes + compressed block: + compressed literals + distribution weight: 24% + huffman log: 11 + regenerated size: 60 + compressed size: 74 + trying again + distribution weight: 44% + huffman log: 9 + regenerated size: 41 + compressed size: 45 + trying again + distribution weight: 86% + huffman log: 11 + regenerated size: 46 + compressed size: 26 + literals size: 46 + total match lengths: 22 + LL: 7 OF: 6 ML: 5 srcPos: 12 seqNb: 0 + LL: 5 OF: 8 ML: 4 srcPos: 21 seqNb: 1 + LL: 18 OF: 1 ML: 6 srcPos: 45 seqNb: 2 + repeat offset: 2 + LL: 0 OF: 16 ML: 4 srcPos: 49 seqNb: 3 + LL: 16 OF: 29 ML: 3 srcPos: 68 seqNb: 4 + excess literals: 0 srcPos: 68 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 5 + block type: compressed + block size field: 43 + checksum: 28ab4e28 diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_299289.zst b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_299289.zst new file mode 100644 index 0000000000..c19b07faf2 Binary files /dev/null and b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_299289.zst differ diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_319146.log b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_319146.log new file mode 100644 index 0000000000..dc4eaae5ff --- /dev/null +++ b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_319146.log @@ -0,0 +1,26 @@ +seed: 319146 +frame seed: 319146 + frame content size: 114 + frame window size: 720896 + content size flag: 1 + single segment flag: 0 + block: + block content size: 114 + last block: yes + compressed block: + compressed literals + distribution weight: 23% + huffman log: 10 + regenerated size: 105 + compressed size: 91 + literals size: 105 + total match lengths: 9 + LL: 90 OF: 16 ML: 4 srcPos: 94 seqNb: 0 + LL: 15 OF: 1 ML: 5 srcPos: 114 seqNb: 1 + repeat offset: 1 + excess literals: 0 srcPos: 114 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 2 + block type: compressed + block size field: 104 + checksum: 9a966cac diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_319146.zst b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_319146.zst new file mode 100644 index 0000000000..f5b2d6c157 Binary files /dev/null and b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_319146.zst differ diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_331938.log b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_331938.log new file mode 100644 index 0000000000..557c6176f1 --- /dev/null +++ b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_331938.log @@ -0,0 +1,25 @@ +seed: 331938 +frame seed: 331938 + frame content size: 104 + frame window size: 36864 + content size flag: 1 + single segment flag: 0 + block: + block content size: 104 + last block: yes + compressed block: + compressed literals + distribution weight: 37% + huffman log: 9 + regenerated size: 67 + compressed size: 60 + literals size: 67 + total match lengths: 37 + LL: 31 OF: 31 ML: 23 srcPos: 54 seqNb: 0 + LL: 19 OF: 13 ML: 14 srcPos: 87 seqNb: 1 + excess literals: 17 srcPos: 104 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 2 + block type: compressed + block size field: 72 + checksum: d76a8c9e diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_331938.zst b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_331938.zst new file mode 100644 index 0000000000..943fafbf00 Binary files /dev/null and b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_331938.zst differ diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_333824.log b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_333824.log new file mode 100644 index 0000000000..025dfe3f63 --- /dev/null +++ b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_333824.log @@ -0,0 +1,27 @@ +seed: 333824 +frame seed: 333824 + frame content size: 109 + frame window size: 109 + content size flag: 1 + single segment flag: 1 + block: + block content size: 109 + last block: yes + compressed block: + compressed literals + distribution weight: 74% + huffman log: 9 + regenerated size: 86 + compressed size: 30 + literals size: 86 + total match lengths: 23 + LL: 10 OF: 5 ML: 3 srcPos: 13 seqNb: 0 + LL: 45 OF: 40 ML: 10 srcPos: 68 seqNb: 1 + LL: 21 OF: 5 ML: 10 srcPos: 99 seqNb: 2 + repeat offset: 1 + excess literals: 10 srcPos: 109 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 3 + block type: compressed + block size field: 43 + checksum: 5905f5bb diff --git a/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_333824.zst b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_333824.zst new file mode 100644 index 0000000000..51b18d62b8 Binary files /dev/null and b/xls/modules/zstd/data/fse_huffman_literals_predefined_sequences_seed_333824.zst differ diff --git a/xls/modules/zstd/data/pregenerated_compressed_minimal.zst b/xls/modules/zstd/data/pregenerated_compressed_minimal.zst new file mode 100644 index 0000000000..e41f9a9c2e Binary files /dev/null and b/xls/modules/zstd/data/pregenerated_compressed_minimal.zst differ diff --git a/xls/modules/zstd/data/pregenerated_compressed_random_1.log b/xls/modules/zstd/data/pregenerated_compressed_random_1.log new file mode 100644 index 0000000000..5a0377c884 --- /dev/null +++ b/xls/modules/zstd/data/pregenerated_compressed_random_1.log @@ -0,0 +1,189 @@ +seed: 1 +frame seed: 1 + frame content size: 1019 + frame window size: 294912 + content size flag: 1 + single segment flag: 0 + block: + block content size: 181 + last block: no + compressed block: + compressed literals + distribution weight: 49% + huffman log: 8 + regenerated size: 126 + compressed size: 63 + literals size: 126 + total match lengths: 55 + LL: 7 OF: 7 ML: 10 srcPos: 17 seqNb: 0 + LL: 9 OF: 15 ML: 7 srcPos: 33 seqNb: 1 + LL: 18 OF: 43 ML: 4 srcPos: 55 seqNb: 2 + LL: 4 OF: 12 ML: 6 srcPos: 65 seqNb: 3 + LL: 0 OF: 22 ML: 6 srcPos: 71 seqNb: 4 + LL: 20 OF: 78 ML: 5 srcPos: 96 seqNb: 5 + LL: 24 OF: 102 ML: 8 srcPos: 128 seqNb: 6 + LL: 0 OF: 40 ML: 4 srcPos: 132 seqNb: 7 + LL: 44 OF: 167 ML: 5 srcPos: 181 seqNb: 8 + excess literals: 0 srcPos: 181 + LL type: 2 OF type: 2 ML type: 2 + number of sequences: 9 + block type: compressed + block size field: 105 + block: + block content size: 838 + last block: yes + compressed block: + compressed literals + distribution weight: 94% + huffman log: 11 + regenerated size: 426 + compressed size: 75 + literals size: 426 + total match lengths: 412 + LL: 1 OF: 16 ML: 3 srcPos: 185 seqNb: 0 + LL: 2 OF: 2 ML: 3 srcPos: 190 seqNb: 1 + LL: 5 OF: 88 ML: 3 srcPos: 198 seqNb: 2 + LL: 0 OF: 44 ML: 4 srcPos: 202 seqNb: 3 + LL: 3 OF: 151 ML: 4 srcPos: 209 seqNb: 4 + LL: 4 OF: 12 ML: 3 srcPos: 216 seqNb: 5 + LL: 0 OF: 93 ML: 4 srcPos: 220 seqNb: 6 + LL: 3 OF: 217 ML: 4 srcPos: 227 seqNb: 7 + LL: 1 OF: 68 ML: 3 srcPos: 231 seqNb: 8 + LL: 0 OF: 42 ML: 3 srcPos: 234 seqNb: 9 + LL: 4 OF: 3 ML: 3 srcPos: 241 seqNb: 10 + LL: 0 OF: 233 ML: 3 srcPos: 244 seqNb: 11 + LL: 2 OF: 203 ML: 3 srcPos: 249 seqNb: 12 + LL: 1 OF: 235 ML: 3 srcPos: 253 seqNb: 13 + LL: 2 OF: 196 ML: 3 srcPos: 258 seqNb: 14 + LL: 6 OF: 225 ML: 3 srcPos: 267 seqNb: 15 + LL: 0 OF: 98 ML: 3 srcPos: 270 seqNb: 16 + LL: 1 OF: 79 ML: 4 srcPos: 275 seqNb: 17 + LL: 10 OF: 220 ML: 3 srcPos: 288 seqNb: 18 + LL: 12 OF: 161 ML: 3 srcPos: 303 seqNb: 19 + LL: 0 OF: 141 ML: 3 srcPos: 306 seqNb: 20 + LL: 7 OF: 161 ML: 3 srcPos: 316 seqNb: 21 + repeat offset: 1 + LL: 5 OF: 270 ML: 3 srcPos: 324 seqNb: 22 + LL: 3 OF: 83 ML: 4 srcPos: 331 seqNb: 23 + LL: 1 OF: 33 ML: 4 srcPos: 336 seqNb: 24 + LL: 3 OF: 118 ML: 3 srcPos: 342 seqNb: 25 + LL: 1 OF: 83 ML: 3 srcPos: 346 seqNb: 26 + LL: 6 OF: 159 ML: 3 srcPos: 355 seqNb: 27 + LL: 4 OF: 118 ML: 3 srcPos: 362 seqNb: 28 + repeat offset: 2 + LL: 0 OF: 59 ML: 3 srcPos: 365 seqNb: 29 + LL: 0 OF: 106 ML: 3 srcPos: 368 seqNb: 30 + LL: 1 OF: 47 ML: 4 srcPos: 373 seqNb: 31 + LL: 4 OF: 19 ML: 3 srcPos: 380 seqNb: 32 + LL: 1 OF: 165 ML: 3 srcPos: 384 seqNb: 33 + LL: 1 OF: 270 ML: 4 srcPos: 389 seqNb: 34 + LL: 6 OF: 60 ML: 3 srcPos: 398 seqNb: 35 + LL: 2 OF: 224 ML: 3 srcPos: 403 seqNb: 36 + LL: 7 OF: 296 ML: 3 srcPos: 413 seqNb: 37 + LL: 8 OF: 125 ML: 3 srcPos: 424 seqNb: 38 + LL: 1 OF: 382 ML: 3 srcPos: 428 seqNb: 39 + LL: 6 OF: 45 ML: 3 srcPos: 437 seqNb: 40 + LL: 0 OF: 257 ML: 3 srcPos: 440 seqNb: 41 + LL: 7 OF: 49 ML: 3 srcPos: 450 seqNb: 42 + LL: 7 OF: 257 ML: 3 srcPos: 460 seqNb: 43 + repeat offset: 1 + LL: 1 OF: 279 ML: 3 srcPos: 464 seqNb: 44 + LL: 0 OF: 108 ML: 4 srcPos: 468 seqNb: 45 + LL: 3 OF: 458 ML: 4 srcPos: 475 seqNb: 46 + LL: 4 OF: 180 ML: 4 srcPos: 483 seqNb: 47 + LL: 0 OF: 366 ML: 3 srcPos: 486 seqNb: 48 + LL: 0 OF: 228 ML: 3 srcPos: 489 seqNb: 49 + LL: 2 OF: 228 ML: 3 srcPos: 494 seqNb: 50 + repeat offset: 0 + LL: 0 OF: 43 ML: 4 srcPos: 498 seqNb: 51 + LL: 9 OF: 43 ML: 4 srcPos: 511 seqNb: 52 + repeat offset: 0 + LL: 1 OF: 240 ML: 4 srcPos: 516 seqNb: 53 + LL: 0 OF: 360 ML: 3 srcPos: 519 seqNb: 54 + LL: 4 OF: 392 ML: 5 srcPos: 528 seqNb: 55 + LL: 2 OF: 49 ML: 3 srcPos: 533 seqNb: 56 + LL: 10 OF: 381 ML: 3 srcPos: 546 seqNb: 57 + LL: 0 OF: 278 ML: 4 srcPos: 550 seqNb: 58 + LL: 3 OF: 380 ML: 3 srcPos: 556 seqNb: 59 + LL: 1 OF: 118 ML: 3 srcPos: 560 seqNb: 60 + LL: 0 OF: 116 ML: 3 srcPos: 563 seqNb: 61 + LL: 7 OF: 16 ML: 3 srcPos: 573 seqNb: 62 + LL: 2 OF: 203 ML: 3 srcPos: 578 seqNb: 63 + LL: 2 OF: 56 ML: 3 srcPos: 583 seqNb: 64 + LL: 3 OF: 203 ML: 3 srcPos: 589 seqNb: 65 + repeat offset: 1 + LL: 2 OF: 16 ML: 4 srcPos: 595 seqNb: 66 + repeat offset: 2 + LL: 11 OF: 203 ML: 3 srcPos: 609 seqNb: 67 + repeat offset: 1 + LL: 9 OF: 524 ML: 4 srcPos: 622 seqNb: 68 + LL: 1 OF: 452 ML: 3 srcPos: 626 seqNb: 69 + LL: 3 OF: 381 ML: 4 srcPos: 633 seqNb: 70 + LL: 5 OF: 381 ML: 4 srcPos: 642 seqNb: 71 + repeat offset: 0 + LL: 6 OF: 44 ML: 3 srcPos: 651 seqNb: 72 + LL: 3 OF: 44 ML: 3 srcPos: 657 seqNb: 73 + repeat offset: 0 + LL: 0 OF: 247 ML: 3 srcPos: 660 seqNb: 74 + LL: 0 OF: 621 ML: 3 srcPos: 663 seqNb: 75 + LL: 9 OF: 16 ML: 3 srcPos: 675 seqNb: 76 + LL: 0 OF: 15 ML: 3 srcPos: 678 seqNb: 77 + repeat offset: 2 + LL: 1 OF: 16 ML: 3 srcPos: 682 seqNb: 78 + repeat offset: 1 + LL: 0 OF: 55 ML: 4 srcPos: 686 seqNb: 79 + LL: 1 OF: 32 ML: 3 srcPos: 690 seqNb: 80 + LL: 3 OF: 500 ML: 4 srcPos: 697 seqNb: 81 + LL: 6 OF: 218 ML: 3 srcPos: 706 seqNb: 82 + LL: 0 OF: 637 ML: 3 srcPos: 709 seqNb: 83 + LL: 0 OF: 647 ML: 3 srcPos: 712 seqNb: 84 + LL: 13 OF: 103 ML: 3 srcPos: 728 seqNb: 85 + LL: 0 OF: 326 ML: 3 srcPos: 731 seqNb: 86 + LL: 0 OF: 488 ML: 3 srcPos: 734 seqNb: 87 + LL: 6 OF: 103 ML: 3 srcPos: 743 seqNb: 88 + repeat offset: 2 + LL: 11 OF: 67 ML: 4 srcPos: 758 seqNb: 89 + LL: 3 OF: 488 ML: 3 srcPos: 764 seqNb: 90 + repeat offset: 2 + LL: 2 OF: 25 ML: 3 srcPos: 769 seqNb: 91 + LL: 3 OF: 277 ML: 4 srcPos: 776 seqNb: 92 + LL: 1 OF: 132 ML: 4 srcPos: 781 seqNb: 93 + LL: 3 OF: 425 ML: 3 srcPos: 787 seqNb: 94 + LL: 2 OF: 135 ML: 3 srcPos: 792 seqNb: 95 + LL: 8 OF: 534 ML: 3 srcPos: 803 seqNb: 96 + LL: 3 OF: 550 ML: 3 srcPos: 809 seqNb: 97 + LL: 1 OF: 666 ML: 3 srcPos: 813 seqNb: 98 + LL: 5 OF: 64 ML: 3 srcPos: 821 seqNb: 99 + LL: 1 OF: 195 ML: 3 srcPos: 825 seqNb: 100 + LL: 1 OF: 713 ML: 3 srcPos: 829 seqNb: 101 + LL: 5 OF: 64 ML: 3 srcPos: 837 seqNb: 102 + repeat offset: 2 + LL: 0 OF: 571 ML: 3 srcPos: 840 seqNb: 103 + LL: 2 OF: 184 ML: 5 srcPos: 847 seqNb: 104 + LL: 2 OF: 475 ML: 3 srcPos: 852 seqNb: 105 + LL: 3 OF: 741 ML: 3 srcPos: 858 seqNb: 106 + LL: 2 OF: 664 ML: 4 srcPos: 864 seqNb: 107 + LL: 5 OF: 196 ML: 3 srcPos: 872 seqNb: 108 + LL: 6 OF: 326 ML: 4 srcPos: 882 seqNb: 109 + LL: 1 OF: 522 ML: 4 srcPos: 887 seqNb: 110 + LL: 1 OF: 429 ML: 4 srcPos: 892 seqNb: 111 + LL: 4 OF: 235 ML: 4 srcPos: 900 seqNb: 112 + LL: 0 OF: 817 ML: 3 srcPos: 903 seqNb: 113 + LL: 8 OF: 403 ML: 4 srcPos: 915 seqNb: 114 + LL: 9 OF: 835 ML: 3 srcPos: 927 seqNb: 115 + LL: 1 OF: 609 ML: 3 srcPos: 931 seqNb: 116 + LL: 2 OF: 840 ML: 3 srcPos: 936 seqNb: 117 + LL: 19 OF: 231 ML: 3 srcPos: 958 seqNb: 118 + LL: 2 OF: 758 ML: 3 srcPos: 963 seqNb: 119 + LL: 10 OF: 268 ML: 3 srcPos: 976 seqNb: 120 + LL: 6 OF: 568 ML: 3 srcPos: 985 seqNb: 121 + LL: 2 OF: 675 ML: 4 srcPos: 991 seqNb: 122 + LL: 21 OF: 28 ML: 3 srcPos: 1015 seqNb: 123 + LL: 0 OF: 27 ML: 4 srcPos: 1019 seqNb: 124 + repeat offset: 2 + excess literals: 0 srcPos: 1019 + LL type: 2 OF type: 2 ML type: 0 + number of sequences: 125 + block type: compressed + block size field: 376 + checksum: d28997be diff --git a/xls/modules/zstd/data/pregenerated_compressed_random_1.zst b/xls/modules/zstd/data/pregenerated_compressed_random_1.zst new file mode 100644 index 0000000000..8673b024e0 Binary files /dev/null and b/xls/modules/zstd/data/pregenerated_compressed_random_1.zst differ diff --git a/xls/modules/zstd/data/pregenerated_compressed_random_2.log b/xls/modules/zstd/data/pregenerated_compressed_random_2.log new file mode 100644 index 0000000000..e120ce7b47 --- /dev/null +++ b/xls/modules/zstd/data/pregenerated_compressed_random_2.log @@ -0,0 +1,70 @@ +seed: 2 +frame seed: 2 + frame content size: 152 + frame window size: 114688 + content size flag: 1 + single segment flag: 0 + block: + block content size: 91 + last block: no + compressed block: + compressed literals + distribution weight: 33% + huffman log: 10 + regenerated size: 44 + compressed size: 49 + trying again + distribution weight: 64% + huffman log: 8 + regenerated size: 35 + compressed size: 30 + literals size: 35 + total match lengths: 56 + LL: 14 OF: 12 ML: 6 srcPos: 20 seqNb: 0 + LL: 1 OF: 9 ML: 9 srcPos: 30 seqNb: 1 + LL: 5 OF: 12 ML: 10 srcPos: 45 seqNb: 2 + LL: 0 OF: 39 ML: 3 srcPos: 48 seqNb: 3 + LL: 5 OF: 3 ML: 13 srcPos: 66 seqNb: 4 + LL: 10 OF: 24 ML: 15 srcPos: 91 seqNb: 5 + excess literals: 0 srcPos: 91 + LL type: 2 OF type: 2 ML type: 2 + number of sequences: 6 + block type: compressed + block size field: 61 + block: + block content size: 53 + last block: no + compressed block: + rle literals: 0xf8 + literals size: 19 + total match lengths: 34 + LL: 2 OF: 56 ML: 3 srcPos: 96 seqNb: 0 + LL: 1 OF: 56 ML: 3 srcPos: 100 seqNb: 1 + repeat offset: 0 + LL: 0 OF: 40 ML: 4 srcPos: 104 seqNb: 2 + LL: 0 OF: 48 ML: 4 srcPos: 108 seqNb: 3 + LL: 6 OF: 53 ML: 3 srcPos: 117 seqNb: 4 + LL: 5 OF: 81 ML: 3 srcPos: 125 seqNb: 5 + LL: 2 OF: 111 ML: 4 srcPos: 131 seqNb: 6 + LL: 3 OF: 79 ML: 3 srcPos: 137 seqNb: 7 + LL: 0 OF: 78 ML: 3 srcPos: 140 seqNb: 8 + LL: 0 OF: 87 ML: 4 srcPos: 144 seqNb: 9 + excess literals: 0 srcPos: 144 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 10 + block type: compressed + block size field: 29 + block: + block content size: 8 + last block: yes + compressed block: + raw literals + literals size: 0 + total match lengths: 8 + LL: 0 OF: 58 ML: 8 srcPos: 152 seqNb: 0 + excess literals: 0 srcPos: 152 + LL type: 3 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 7 + checksum: e7ab4be9 diff --git a/xls/modules/zstd/data/pregenerated_compressed_random_2.zst b/xls/modules/zstd/data/pregenerated_compressed_random_2.zst new file mode 100644 index 0000000000..014359109f Binary files /dev/null and b/xls/modules/zstd/data/pregenerated_compressed_random_2.zst differ diff --git a/xls/modules/zstd/data/pregenerated_compressed_raw_1.log b/xls/modules/zstd/data/pregenerated_compressed_raw_1.log new file mode 100644 index 0000000000..15e8ef895b --- /dev/null +++ b/xls/modules/zstd/data/pregenerated_compressed_raw_1.log @@ -0,0 +1,347 @@ +seed: 1 +frame seed: 1 + frame content size: 1019 + frame window size: 294912 + content size flag: 1 + single segment flag: 0 + block: + block content size: 181 + last block: no + compressed block: + raw literals + literals size: 139 + total match lengths: 42 + LL: 37 OF: 31 ML: 13 srcPos: 50 seqNb: 0 + LL: 25 OF: 16 ML: 29 srcPos: 104 seqNb: 1 + excess literals: 77 srcPos: 181 + LL type: 2 OF type: 2 ML type: 2 + number of sequences: 2 + block type: compressed + block size field: 168 + block: + block content size: 0 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 181 + number of sequences: 0 + block type: compressed + block size field: 2 + block: + block content size: 63 + last block: no + compressed block: + raw literals + literals size: 7 + total match lengths: 56 + LL: 0 OF: 70 ML: 3 srcPos: 184 seqNb: 0 + LL: 0 OF: 56 ML: 3 srcPos: 187 seqNb: 1 + LL: 0 OF: 55 ML: 3 srcPos: 190 seqNb: 2 + repeat offset: 2 + LL: 0 OF: 23 ML: 3 srcPos: 193 seqNb: 3 + LL: 0 OF: 4 ML: 3 srcPos: 196 seqNb: 4 + LL: 0 OF: 136 ML: 3 srcPos: 199 seqNb: 5 + LL: 0 OF: 23 ML: 3 srcPos: 202 seqNb: 6 + LL: 0 OF: 28 ML: 3 srcPos: 205 seqNb: 7 + LL: 0 OF: 2 ML: 3 srcPos: 208 seqNb: 8 + LL: 1 OF: 5 ML: 3 srcPos: 212 seqNb: 9 + LL: 0 OF: 4 ML: 3 srcPos: 215 seqNb: 10 + repeat offset: 2 + LL: 0 OF: 2 ML: 3 srcPos: 218 seqNb: 11 + repeat offset: 2 + LL: 0 OF: 56 ML: 3 srcPos: 221 seqNb: 12 + LL: 2 OF: 209 ML: 3 srcPos: 226 seqNb: 13 + LL: 0 OF: 24 ML: 4 srcPos: 230 seqNb: 14 + LL: 0 OF: 14 ML: 3 srcPos: 233 seqNb: 15 + LL: 0 OF: 112 ML: 4 srcPos: 237 seqNb: 16 + LL: 0 OF: 233 ML: 3 srcPos: 240 seqNb: 17 + excess literals: 4 srcPos: 244 + LL type: 2 OF type: 2 ML type: 2 + number of sequences: 18 + block type: compressed + block size field: 39 + block: + block content size: 59 + last block: no + compressed block: + raw literals + literals size: 19 + total match lengths: 40 + LL: 2 OF: 90 ML: 6 srcPos: 252 seqNb: 0 + LL: 2 OF: 153 ML: 5 srcPos: 259 seqNb: 1 + LL: 10 OF: 76 ML: 10 srcPos: 279 seqNb: 2 + LL: 1 OF: 226 ML: 5 srcPos: 285 seqNb: 3 + LL: 2 OF: 5 ML: 4 srcPos: 291 seqNb: 4 + LL: 2 OF: 33 ML: 7 srcPos: 300 seqNb: 5 + LL: 0 OF: 262 ML: 3 srcPos: 303 seqNb: 6 + excess literals: 0 srcPos: 303 + LL type: 2 OF type: 2 ML type: 0 + number of sequences: 7 + block type: compressed + block size field: 45 + block: + block content size: 614 + last block: no + compressed block: + raw literals + literals size: 159 + total match lengths: 455 + LL: 2 OF: 128 ML: 3 srcPos: 308 seqNb: 0 + LL: 3 OF: 96 ML: 3 srcPos: 314 seqNb: 1 + LL: 0 OF: 123 ML: 3 srcPos: 317 seqNb: 2 + LL: 0 OF: 225 ML: 3 srcPos: 320 seqNb: 3 + LL: 1 OF: 172 ML: 3 srcPos: 324 seqNb: 4 + LL: 2 OF: 56 ML: 3 srcPos: 329 seqNb: 5 + LL: 2 OF: 13 ML: 3 srcPos: 334 seqNb: 6 + LL: 1 OF: 327 ML: 3 srcPos: 338 seqNb: 7 + LL: 0 OF: 264 ML: 3 srcPos: 341 seqNb: 8 + LL: 0 OF: 13 ML: 3 srcPos: 344 seqNb: 9 + repeat offset: 2 + LL: 0 OF: 340 ML: 3 srcPos: 347 seqNb: 10 + LL: 0 OF: 95 ML: 3 srcPos: 350 seqNb: 11 + LL: 0 OF: 221 ML: 3 srcPos: 353 seqNb: 12 + LL: 0 OF: 95 ML: 3 srcPos: 356 seqNb: 13 + repeat offset: 1 + LL: 0 OF: 94 ML: 3 srcPos: 359 seqNb: 14 + repeat offset: 2 + LL: 0 OF: 95 ML: 3 srcPos: 362 seqNb: 15 + repeat offset: 1 + LL: 0 OF: 294 ML: 3 srcPos: 365 seqNb: 16 + LL: 0 OF: 250 ML: 3 srcPos: 368 seqNb: 17 + LL: 3 OF: 310 ML: 3 srcPos: 374 seqNb: 18 + LL: 0 OF: 59 ML: 3 srcPos: 377 seqNb: 19 + LL: 0 OF: 17 ML: 3 srcPos: 380 seqNb: 20 + LL: 1 OF: 59 ML: 3 srcPos: 384 seqNb: 21 + repeat offset: 1 + LL: 0 OF: 372 ML: 3 srcPos: 387 seqNb: 22 + LL: 1 OF: 203 ML: 3 srcPos: 391 seqNb: 23 + LL: 1 OF: 251 ML: 3 srcPos: 395 seqNb: 24 + LL: 0 OF: 203 ML: 3 srcPos: 398 seqNb: 25 + repeat offset: 1 + LL: 1 OF: 363 ML: 3 srcPos: 402 seqNb: 26 + LL: 0 OF: 321 ML: 3 srcPos: 405 seqNb: 27 + LL: 1 OF: 395 ML: 3 srcPos: 409 seqNb: 28 + LL: 1 OF: 381 ML: 3 srcPos: 413 seqNb: 29 + LL: 3 OF: 99 ML: 3 srcPos: 419 seqNb: 30 + LL: 1 OF: 116 ML: 3 srcPos: 423 seqNb: 31 + LL: 0 OF: 293 ML: 3 srcPos: 426 seqNb: 32 + LL: 0 OF: 292 ML: 3 srcPos: 429 seqNb: 33 + repeat offset: 2 + LL: 1 OF: 127 ML: 3 srcPos: 433 seqNb: 34 + LL: 0 OF: 219 ML: 3 srcPos: 436 seqNb: 35 + LL: 0 OF: 236 ML: 3 srcPos: 439 seqNb: 36 + LL: 1 OF: 353 ML: 3 srcPos: 443 seqNb: 37 + LL: 1 OF: 46 ML: 3 srcPos: 447 seqNb: 38 + LL: 3 OF: 404 ML: 3 srcPos: 453 seqNb: 39 + LL: 0 OF: 267 ML: 3 srcPos: 456 seqNb: 40 + LL: 0 OF: 421 ML: 3 srcPos: 459 seqNb: 41 + LL: 1 OF: 201 ML: 3 srcPos: 463 seqNb: 42 + LL: 1 OF: 12 ML: 3 srcPos: 467 seqNb: 43 + LL: 0 OF: 438 ML: 3 srcPos: 470 seqNb: 44 + LL: 1 OF: 136 ML: 3 srcPos: 474 seqNb: 45 + LL: 2 OF: 126 ML: 3 srcPos: 479 seqNb: 46 + LL: 0 OF: 400 ML: 3 srcPos: 482 seqNb: 47 + LL: 0 OF: 130 ML: 3 srcPos: 485 seqNb: 48 + LL: 2 OF: 206 ML: 3 srcPos: 490 seqNb: 49 + LL: 0 OF: 302 ML: 3 srcPos: 493 seqNb: 50 + LL: 0 OF: 206 ML: 3 srcPos: 496 seqNb: 51 + LL: 1 OF: 420 ML: 3 srcPos: 500 seqNb: 52 + LL: 1 OF: 131 ML: 3 srcPos: 504 seqNb: 53 + LL: 1 OF: 172 ML: 3 srcPos: 508 seqNb: 54 + LL: 0 OF: 131 ML: 3 srcPos: 511 seqNb: 55 + repeat offset: 1 + LL: 2 OF: 438 ML: 3 srcPos: 516 seqNb: 56 + LL: 0 OF: 453 ML: 3 srcPos: 519 seqNb: 57 + LL: 0 OF: 248 ML: 3 srcPos: 522 seqNb: 58 + LL: 0 OF: 438 ML: 3 srcPos: 525 seqNb: 59 + repeat offset: 2 + LL: 1 OF: 326 ML: 3 srcPos: 529 seqNb: 60 + LL: 0 OF: 248 ML: 3 srcPos: 532 seqNb: 61 + repeat offset: 2 + LL: 1 OF: 46 ML: 3 srcPos: 536 seqNb: 62 + LL: 2 OF: 139 ML: 3 srcPos: 541 seqNb: 63 + LL: 1 OF: 139 ML: 3 srcPos: 545 seqNb: 64 + repeat offset: 0 + LL: 0 OF: 508 ML: 4 srcPos: 549 seqNb: 65 + LL: 2 OF: 482 ML: 3 srcPos: 554 seqNb: 66 + LL: 1 OF: 127 ML: 3 srcPos: 558 seqNb: 67 + LL: 3 OF: 485 ML: 3 srcPos: 564 seqNb: 68 + LL: 0 OF: 300 ML: 3 srcPos: 567 seqNb: 69 + LL: 2 OF: 338 ML: 3 srcPos: 572 seqNb: 70 + LL: 1 OF: 285 ML: 3 srcPos: 576 seqNb: 71 + LL: 0 OF: 300 ML: 3 srcPos: 579 seqNb: 72 + repeat offset: 2 + LL: 1 OF: 60 ML: 3 srcPos: 583 seqNb: 73 + LL: 2 OF: 304 ML: 3 srcPos: 588 seqNb: 74 + LL: 2 OF: 106 ML: 3 srcPos: 593 seqNb: 75 + LL: 4 OF: 106 ML: 3 srcPos: 600 seqNb: 76 + repeat offset: 0 + LL: 2 OF: 106 ML: 3 srcPos: 605 seqNb: 77 + repeat offset: 0 + LL: 5 OF: 60 ML: 3 srcPos: 613 seqNb: 78 + repeat offset: 2 + LL: 2 OF: 594 ML: 3 srcPos: 618 seqNb: 79 + LL: 1 OF: 234 ML: 3 srcPos: 622 seqNb: 80 + LL: 1 OF: 227 ML: 3 srcPos: 626 seqNb: 81 + LL: 0 OF: 235 ML: 3 srcPos: 629 seqNb: 82 + LL: 1 OF: 311 ML: 3 srcPos: 633 seqNb: 83 + LL: 0 OF: 253 ML: 3 srcPos: 636 seqNb: 84 + LL: 1 OF: 286 ML: 3 srcPos: 640 seqNb: 85 + LL: 0 OF: 175 ML: 3 srcPos: 643 seqNb: 86 + LL: 1 OF: 395 ML: 3 srcPos: 647 seqNb: 87 + LL: 2 OF: 544 ML: 3 srcPos: 652 seqNb: 88 + LL: 0 OF: 278 ML: 3 srcPos: 655 seqNb: 89 + LL: 1 OF: 450 ML: 3 srcPos: 659 seqNb: 90 + LL: 4 OF: 469 ML: 3 srcPos: 666 seqNb: 91 + LL: 5 OF: 192 ML: 3 srcPos: 674 seqNb: 92 + LL: 0 OF: 492 ML: 3 srcPos: 677 seqNb: 93 + LL: 2 OF: 192 ML: 3 srcPos: 682 seqNb: 94 + repeat offset: 1 + LL: 2 OF: 597 ML: 3 srcPos: 687 seqNb: 95 + LL: 1 OF: 501 ML: 3 srcPos: 691 seqNb: 96 + LL: 0 OF: 148 ML: 3 srcPos: 694 seqNb: 97 + LL: 1 OF: 513 ML: 3 srcPos: 698 seqNb: 98 + LL: 0 OF: 143 ML: 3 srcPos: 701 seqNb: 99 + LL: 2 OF: 89 ML: 3 srcPos: 706 seqNb: 100 + LL: 1 OF: 513 ML: 3 srcPos: 710 seqNb: 101 + repeat offset: 2 + LL: 0 OF: 35 ML: 3 srcPos: 713 seqNb: 102 + LL: 0 OF: 218 ML: 3 srcPos: 716 seqNb: 103 + LL: 1 OF: 140 ML: 3 srcPos: 720 seqNb: 104 + LL: 2 OF: 465 ML: 3 srcPos: 725 seqNb: 105 + LL: 0 OF: 183 ML: 3 srcPos: 728 seqNb: 106 + LL: 0 OF: 704 ML: 4 srcPos: 732 seqNb: 107 + LL: 2 OF: 361 ML: 3 srcPos: 737 seqNb: 108 + LL: 1 OF: 460 ML: 3 srcPos: 741 seqNb: 109 + LL: 3 OF: 554 ML: 3 srcPos: 747 seqNb: 110 + LL: 3 OF: 544 ML: 3 srcPos: 753 seqNb: 111 + LL: 0 OF: 19 ML: 3 srcPos: 756 seqNb: 112 + LL: 2 OF: 539 ML: 3 srcPos: 761 seqNb: 113 + LL: 0 OF: 557 ML: 3 srcPos: 764 seqNb: 114 + LL: 3 OF: 501 ML: 3 srcPos: 770 seqNb: 115 + LL: 2 OF: 557 ML: 3 srcPos: 775 seqNb: 116 + repeat offset: 1 + LL: 0 OF: 683 ML: 3 srcPos: 778 seqNb: 117 + LL: 0 OF: 362 ML: 3 srcPos: 781 seqNb: 118 + LL: 1 OF: 723 ML: 4 srcPos: 786 seqNb: 119 + LL: 1 OF: 526 ML: 4 srcPos: 791 seqNb: 120 + LL: 0 OF: 653 ML: 3 srcPos: 794 seqNb: 121 + LL: 0 OF: 572 ML: 3 srcPos: 797 seqNb: 122 + LL: 1 OF: 572 ML: 3 srcPos: 801 seqNb: 123 + repeat offset: 0 + LL: 0 OF: 383 ML: 4 srcPos: 805 seqNb: 124 + LL: 4 OF: 383 ML: 4 srcPos: 813 seqNb: 125 + repeat offset: 0 + LL: 1 OF: 46 ML: 4 srcPos: 818 seqNb: 126 + LL: 0 OF: 742 ML: 3 srcPos: 821 seqNb: 127 + LL: 2 OF: 84 ML: 4 srcPos: 827 seqNb: 128 + LL: 1 OF: 793 ML: 3 srcPos: 831 seqNb: 129 + LL: 4 OF: 277 ML: 3 srcPos: 838 seqNb: 130 + LL: 0 OF: 312 ML: 3 srcPos: 841 seqNb: 131 + LL: 1 OF: 306 ML: 3 srcPos: 845 seqNb: 132 + LL: 0 OF: 706 ML: 3 srcPos: 848 seqNb: 133 + LL: 0 OF: 244 ML: 3 srcPos: 851 seqNb: 134 + LL: 4 OF: 301 ML: 3 srcPos: 858 seqNb: 135 + LL: 1 OF: 53 ML: 3 srcPos: 862 seqNb: 136 + LL: 1 OF: 313 ML: 3 srcPos: 866 seqNb: 137 + LL: 1 OF: 53 ML: 3 srcPos: 870 seqNb: 138 + repeat offset: 1 + LL: 1 OF: 301 ML: 4 srcPos: 875 seqNb: 139 + repeat offset: 2 + LL: 6 OF: 53 ML: 3 srcPos: 884 seqNb: 140 + repeat offset: 1 + LL: 3 OF: 295 ML: 3 srcPos: 890 seqNb: 141 + LL: 0 OF: 363 ML: 3 srcPos: 893 seqNb: 142 + LL: 1 OF: 742 ML: 4 srcPos: 898 seqNb: 143 + LL: 2 OF: 742 ML: 4 srcPos: 904 seqNb: 144 + repeat offset: 0 + LL: 2 OF: 728 ML: 3 srcPos: 909 seqNb: 145 + LL: 1 OF: 728 ML: 3 srcPos: 913 seqNb: 146 + repeat offset: 0 + LL: 0 OF: 597 ML: 3 srcPos: 916 seqNb: 147 + excess literals: 1 srcPos: 917 + LL type: 0 OF type: 0 ML type: 3 + number of sequences: 148 + block type: compressed + block size field: 550 + block: + block content size: 24 + last block: no + compressed block: + raw literals + literals size: 21 + total match lengths: 3 + LL: 9 OF: 905 ML: 3 srcPos: 929 seqNb: 0 + excess literals: 12 srcPos: 941 + LL type: 1 OF type: 1 ML type: 3 + number of sequences: 1 + block type: compressed + block size field: 28 + block: + block content size: 0 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 941 + number of sequences: 0 + block type: compressed + block size field: 2 + block: + block content size: 24 + last block: no + compressed block: + raw literals + literals size: 14 + total match lengths: 10 + LL: 11 OF: 506 ML: 10 srcPos: 962 seqNb: 0 + excess literals: 3 srcPos: 965 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 22 + block: + block content size: 47 + last block: no + compressed block: + raw literals + literals size: 40 + total match lengths: 7 + LL: 40 OF: 833 ML: 4 srcPos: 1009 seqNb: 0 + LL: 0 OF: 832 ML: 3 srcPos: 1012 seqNb: 1 + repeat offset: 2 + excess literals: 0 srcPos: 1012 + LL type: 0 OF type: 0 ML type: 2 + number of sequences: 2 + block type: compressed + block size field: 53 + block: + block content size: 4 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 4 + LL: 0 OF: 92 ML: 4 srcPos: 1016 seqNb: 0 + excess literals: 0 srcPos: 1016 + LL type: 3 OF type: 1 ML type: 3 + number of sequences: 1 + block type: compressed + block size field: 7 + block: + block content size: 3 + last block: yes + compressed block: + raw literals + literals size: 0 + total match lengths: 3 + LL: 0 OF: 280 ML: 3 srcPos: 1019 seqNb: 0 + excess literals: 0 srcPos: 1019 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 8 + checksum: 20a07047 diff --git a/xls/modules/zstd/data/pregenerated_compressed_raw_1.zst b/xls/modules/zstd/data/pregenerated_compressed_raw_1.zst new file mode 100644 index 0000000000..bea909ee30 Binary files /dev/null and b/xls/modules/zstd/data/pregenerated_compressed_raw_1.zst differ diff --git a/xls/modules/zstd/data/pregenerated_compressed_raw_2.log b/xls/modules/zstd/data/pregenerated_compressed_raw_2.log new file mode 100644 index 0000000000..b30d8f1ce6 --- /dev/null +++ b/xls/modules/zstd/data/pregenerated_compressed_raw_2.log @@ -0,0 +1,100 @@ +seed: 2 +frame seed: 2 + frame content size: 152 + frame window size: 114688 + content size flag: 1 + single segment flag: 0 + block: + block content size: 91 + last block: no + compressed block: + raw literals + literals size: 68 + total match lengths: 23 + LL: 38 OF: 4 ML: 23 srcPos: 61 seqNb: 0 + repeat offset: 1 + excess literals: 30 srcPos: 91 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 76 + block: + block content size: 32 + last block: no + compressed block: + raw literals + literals size: 15 + total match lengths: 17 + LL: 7 OF: 1 ML: 3 srcPos: 101 seqNb: 0 + repeat offset: 1 + LL: 0 OF: 36 ML: 5 srcPos: 106 seqNb: 1 + LL: 0 OF: 9 ML: 9 srcPos: 115 seqNb: 2 + excess literals: 8 srcPos: 123 + LL type: 2 OF type: 0 ML type: 2 + number of sequences: 3 + block type: compressed + block size field: 36 + block: + block content size: 23 + last block: no + compressed block: + raw literals + literals size: 8 + total match lengths: 15 + LL: 3 OF: 55 ML: 4 srcPos: 130 seqNb: 0 + LL: 2 OF: 36 ML: 5 srcPos: 137 seqNb: 1 + repeat offset: 2 + LL: 0 OF: 27 ML: 3 srcPos: 140 seqNb: 2 + LL: 3 OF: 113 ML: 3 srcPos: 146 seqNb: 3 + excess literals: 0 srcPos: 146 + LL type: 2 OF type: 2 ML type: 0 + number of sequences: 4 + block type: compressed + block size field: 31 + block: + block content size: 4 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 4 + LL: 0 OF: 52 ML: 4 srcPos: 150 seqNb: 0 + excess literals: 0 srcPos: 150 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 7 + block: + block content size: 0 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 150 + number of sequences: 0 + block type: compressed + block size field: 2 + block: + block content size: 1 + last block: no + compressed block: + raw literals + literals size: 1 + total match lengths: 0 + excess literals: 1 srcPos: 151 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 1 + last block: yes + compressed block: + raw literals + literals size: 1 + total match lengths: 0 + excess literals: 1 srcPos: 152 + number of sequences: 0 + block type: compressed + block size field: 3 + checksum: abf90678 diff --git a/xls/modules/zstd/data/pregenerated_compressed_raw_2.zst b/xls/modules/zstd/data/pregenerated_compressed_raw_2.zst new file mode 100644 index 0000000000..9d5d81af90 Binary files /dev/null and b/xls/modules/zstd/data/pregenerated_compressed_raw_2.zst differ diff --git a/xls/modules/zstd/data/pregenerated_compressed_rle_1.log b/xls/modules/zstd/data/pregenerated_compressed_rle_1.log new file mode 100644 index 0000000000..6758c747f2 --- /dev/null +++ b/xls/modules/zstd/data/pregenerated_compressed_rle_1.log @@ -0,0 +1,179 @@ +seed: 1 +frame seed: 1 + frame content size: 1019 + frame window size: 294912 + content size flag: 1 + single segment flag: 0 + block: + block content size: 181 + last block: no + compressed block: + rle literals: 0xed + literals size: 139 + total match lengths: 42 + LL: 139 OF: 97 ML: 42 srcPos: 181 seqNb: 0 + excess literals: 0 srcPos: 181 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 10 + block: + block content size: 178 + last block: no + compressed block: + rle literals: 0xc6 + literals size: 21 + total match lengths: 157 + LL: 0 OF: 53 ML: 4 srcPos: 185 seqNb: 0 + LL: 0 OF: 155 ML: 3 srcPos: 188 seqNb: 1 + LL: 0 OF: 7 ML: 3 srcPos: 191 seqNb: 2 + LL: 2 OF: 124 ML: 4 srcPos: 197 seqNb: 3 + LL: 0 OF: 138 ML: 4 srcPos: 201 seqNb: 4 + LL: 0 OF: 92 ML: 4 srcPos: 205 seqNb: 5 + LL: 0 OF: 1 ML: 5 srcPos: 210 seqNb: 6 + LL: 0 OF: 93 ML: 3 srcPos: 213 seqNb: 7 + LL: 1 OF: 144 ML: 5 srcPos: 219 seqNb: 8 + LL: 1 OF: 183 ML: 4 srcPos: 224 seqNb: 9 + LL: 0 OF: 140 ML: 3 srcPos: 227 seqNb: 10 + LL: 1 OF: 42 ML: 5 srcPos: 233 seqNb: 11 + LL: 0 OF: 118 ML: 4 srcPos: 237 seqNb: 12 + LL: 1 OF: 47 ML: 4 srcPos: 242 seqNb: 13 + LL: 0 OF: 232 ML: 5 srcPos: 247 seqNb: 14 + LL: 0 OF: 24 ML: 4 srcPos: 251 seqNb: 15 + LL: 1 OF: 24 ML: 5 srcPos: 257 seqNb: 16 + repeat offset: 0 + LL: 0 OF: 2 ML: 3 srcPos: 260 seqNb: 17 + LL: 0 OF: 212 ML: 4 srcPos: 264 seqNb: 18 + LL: 1 OF: 66 ML: 4 srcPos: 269 seqNb: 19 + LL: 0 OF: 65 ML: 5 srcPos: 274 seqNb: 20 + repeat offset: 2 + LL: 0 OF: 212 ML: 5 srcPos: 279 seqNb: 21 + repeat offset: 2 + LL: 0 OF: 119 ML: 4 srcPos: 283 seqNb: 22 + LL: 1 OF: 245 ML: 4 srcPos: 288 seqNb: 23 + LL: 0 OF: 152 ML: 5 srcPos: 293 seqNb: 24 + LL: 0 OF: 219 ML: 3 srcPos: 296 seqNb: 25 + LL: 0 OF: 107 ML: 5 srcPos: 301 seqNb: 26 + LL: 0 OF: 157 ML: 4 srcPos: 305 seqNb: 27 + LL: 1 OF: 30 ML: 6 srcPos: 312 seqNb: 28 + LL: 1 OF: 44 ML: 5 srcPos: 318 seqNb: 29 + LL: 0 OF: 151 ML: 4 srcPos: 322 seqNb: 30 + LL: 1 OF: 30 ML: 4 srcPos: 327 seqNb: 31 + repeat offset: 2 + LL: 1 OF: 8 ML: 4 srcPos: 332 seqNb: 32 + LL: 1 OF: 238 ML: 4 srcPos: 337 seqNb: 33 + LL: 6 OF: 244 ML: 5 srcPos: 348 seqNb: 34 + LL: 0 OF: 290 ML: 3 srcPos: 351 seqNb: 35 + LL: 1 OF: 271 ML: 3 srcPos: 355 seqNb: 36 + LL: 0 OF: 111 ML: 4 srcPos: 359 seqNb: 37 + excess literals: 0 srcPos: 359 + LL type: 0 OF type: 2 ML type: 2 + number of sequences: 38 + block type: compressed + block size field: 80 + block: + block content size: 419 + last block: no + compressed block: + rle literals: 0xc1 + literals size: 282 + total match lengths: 137 + LL: 0 OF: 353 ML: 5 srcPos: 364 seqNb: 0 + LL: 1 OF: 111 ML: 3 srcPos: 368 seqNb: 1 + repeat offset: 1 + LL: 18 OF: 65 ML: 4 srcPos: 390 seqNb: 2 + LL: 3 OF: 213 ML: 6 srcPos: 399 seqNb: 3 + LL: 0 OF: 249 ML: 6 srcPos: 405 seqNb: 4 + LL: 11 OF: 285 ML: 11 srcPos: 427 seqNb: 5 + LL: 4 OF: 297 ML: 5 srcPos: 436 seqNb: 6 + LL: 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ML: 5 srcPos: 750 seqNb: 27 + LL: 1 OF: 141 ML: 4 srcPos: 755 seqNb: 28 + LL: 0 OF: 667 ML: 5 srcPos: 760 seqNb: 29 + excess literals: 18 srcPos: 778 + LL type: 2 OF type: 0 ML type: 2 + number of sequences: 30 + block type: compressed + block size field: 80 + block: + block content size: 7 + last block: no + compressed block: + rle literals: 0x3a + literals size: 1 + total match lengths: 6 + LL: 1 OF: 282 ML: 6 srcPos: 785 seqNb: 0 + excess literals: 0 srcPos: 785 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 9 + block: + block content size: 129 + last block: no + compressed block: + rle literals: 0xcf + literals size: 60 + total match lengths: 69 + LL: 0 OF: 455 ML: 69 srcPos: 854 seqNb: 0 + excess literals: 60 srcPos: 914 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 10 + block: + block content size: 85 + last block: no + compressed block: + rle literals: 0xf1 + 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--git a/xls/modules/zstd/data/pregenerated_compressed_rle_2.log b/xls/modules/zstd/data/pregenerated_compressed_rle_2.log new file mode 100644 index 0000000000..ed2a1dbb00 --- /dev/null +++ b/xls/modules/zstd/data/pregenerated_compressed_rle_2.log @@ -0,0 +1,103 @@ +seed: 2 +frame seed: 2 + frame content size: 152 + frame window size: 114688 + content size flag: 1 + single segment flag: 0 + block: + block content size: 91 + last block: no + compressed block: + rle literals: 0xda + literals size: 68 + total match lengths: 23 + LL: 2 OF: 1 ML: 3 srcPos: 5 seqNb: 0 + LL: 8 OF: 2 ML: 3 srcPos: 16 seqNb: 1 + LL: 5 OF: 10 ML: 4 srcPos: 25 seqNb: 2 + LL: 8 OF: 10 ML: 3 srcPos: 36 seqNb: 3 + repeat offset: 0 + LL: 4 OF: 7 ML: 3 srcPos: 43 seqNb: 4 + LL: 38 OF: 27 ML: 4 srcPos: 85 seqNb: 5 + LL: 2 OF: 68 ML: 3 srcPos: 90 seqNb: 6 + excess literals: 1 srcPos: 91 + LL type: 2 OF type: 0 ML type: 2 + number of sequences: 7 + block type: compressed + block size field: 26 + block: + block content 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0 OF: 3 ML: 3 srcPos: 7 seqNb: 1 + LL: 0 OF: 4 ML: 4 srcPos: 11 seqNb: 2 + LL: 0 OF: 10 ML: 3 srcPos: 14 seqNb: 3 + excess literals: 0 srcPos: 14 + LL type: 2 OF type: 2 ML type: 2 + number of sequences: 4 + block type: compressed + block size field: 20 + checksum: 0b0ba282 diff --git a/xls/modules/zstd/data/raw_literals_compressed_sequences_seed_903062.zst b/xls/modules/zstd/data/raw_literals_compressed_sequences_seed_903062.zst new file mode 100644 index 0000000000..33d75db742 Binary files /dev/null and b/xls/modules/zstd/data/raw_literals_compressed_sequences_seed_903062.zst differ diff --git a/xls/modules/zstd/data/raw_literals_predefined_sequences_seed_422473.log b/xls/modules/zstd/data/raw_literals_predefined_sequences_seed_422473.log new file mode 100644 index 0000000000..a785b43a08 --- /dev/null +++ b/xls/modules/zstd/data/raw_literals_predefined_sequences_seed_422473.log @@ -0,0 +1,25 @@ +seed: 422473 +frame seed: 422473 + frame content size: 25 + frame window size: 5632 + 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sequences: 1 + block type: compressed + block size field: 25 + checksum: 46d2ac93 diff --git a/xls/modules/zstd/data/raw_literals_rle_sequences_seed_700216.zst b/xls/modules/zstd/data/raw_literals_rle_sequences_seed_700216.zst new file mode 100644 index 0000000000..541f7860ab Binary files /dev/null and b/xls/modules/zstd/data/raw_literals_rle_sequences_seed_700216.zst differ diff --git a/xls/modules/zstd/data/rle_literals_compressed_sequences_seed_701326.log b/xls/modules/zstd/data/rle_literals_compressed_sequences_seed_701326.log new file mode 100644 index 0000000000..ddd13d1a38 --- /dev/null +++ b/xls/modules/zstd/data/rle_literals_compressed_sequences_seed_701326.log @@ -0,0 +1,87 @@ +seed: 701326 +frame seed: 701326 + frame content size: 28 + frame window size: 11264 + content size flag: 1 + single segment flag: 0 + block: + block content size: 1 + last block: no + compressed block: + rle literals: 0xf3 + literals size: 1 + total match lengths: 0 + excess literals: 1 srcPos: 1 + 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block content size: 7 + last block: yes + compressed block: + rle literals: 0x27 + literals size: 7 + total match lengths: 0 + excess literals: 7 srcPos: 83 + number of sequences: 0 + block type: compressed + block size field: 3 + checksum: e20e662f diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_406229.zst b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_406229.zst new file mode 100644 index 0000000000..5886d2796c Binary files /dev/null and b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_406229.zst differ diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_411034.log b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_411034.log new file mode 100644 index 0000000000..8bc1fedfa2 --- /dev/null +++ b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_411034.log @@ -0,0 +1,28 @@ +seed: 411034 +frame seed: 411034 + frame content size: 31 + frame window size: 31 + content size flag: 1 + single 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type: compressed + block size field: 3 + block: + block content size: 38 + last block: yes + compressed block: + rle literals: 0x25 + literals size: 12 + total match lengths: 26 + LL: 0 OF: 24 ML: 3 srcPos: 51 seqNb: 0 + LL: 1 OF: 40 ML: 3 srcPos: 55 seqNb: 1 + LL: 11 OF: 37 ML: 4 srcPos: 70 seqNb: 2 + LL: 0 OF: 5 ML: 3 srcPos: 73 seqNb: 3 + LL: 0 OF: 40 ML: 3 srcPos: 76 seqNb: 4 + LL: 0 OF: 70 ML: 3 srcPos: 79 seqNb: 5 + LL: 0 OF: 74 ML: 3 srcPos: 82 seqNb: 6 + LL: 0 OF: 40 ML: 4 srcPos: 86 seqNb: 7 + repeat offset: 2 + excess literals: 0 srcPos: 86 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 8 + block type: compressed + block size field: 24 + checksum: 9f8a30e7 diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_413015.zst b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_413015.zst new file mode 100644 index 0000000000..209ef66178 Binary files /dev/null and b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_413015.zst differ diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_436165.log b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_436165.log new file mode 100644 index 0000000000..adcc599156 --- /dev/null +++ b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_436165.log @@ -0,0 +1,34 @@ +seed: 436165 +frame seed: 436165 + frame content size: 90 + frame window size: 589824 + content size flag: 1 + single segment flag: 0 + block: + block content size: 1 + last block: no + compressed block: + rle literals: 0x88 + literals size: 1 + total match lengths: 0 + excess literals: 1 srcPos: 1 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 89 + last block: yes + compressed block: + rle literals: 0x65 + literals size: 51 + total match lengths: 38 + LL: 4 OF: 1 ML: 5 srcPos: 10 seqNb: 0 + LL: 23 OF: 3 ML: 5 srcPos: 38 seqNb: 1 + LL: 2 OF: 4 ML: 6 srcPos: 46 seqNb: 2 + LL: 9 OF: 33 ML: 22 srcPos: 77 seqNb: 3 + excess literals: 13 srcPos: 90 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 4 + block type: compressed + block size field: 15 + checksum: 391cc8a2 diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_436165.zst b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_436165.zst new file mode 100644 index 0000000000..1eb90bcec4 Binary files /dev/null and b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_436165.zst differ diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_464057.log b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_464057.log new file mode 100644 index 0000000000..4db9a9c6a6 --- /dev/null +++ b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_464057.log @@ -0,0 +1,21 @@ +seed: 464057 +frame seed: 464057 + frame content size: 46 + frame window size: 3072 + content size flag: 1 + single segment flag: 0 + block: + block content size: 46 + last block: yes + compressed block: + rle literals: 0x84 + literals size: 31 + total match lengths: 15 + LL: 22 OF: 4 ML: 12 srcPos: 34 seqNb: 0 + LL: 9 OF: 35 ML: 3 srcPos: 46 seqNb: 1 + excess literals: 0 srcPos: 46 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 2 + block type: compressed + block size field: 10 + checksum: e24bcde2 diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_464057.zst b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_464057.zst new file mode 100644 index 0000000000..414a0fdc1c Binary files /dev/null and b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_464057.zst differ diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_466803.log b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_466803.log new file mode 100644 index 0000000000..3e90c84fe2 --- /dev/null +++ b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_466803.log @@ -0,0 +1,24 @@ +seed: 466803 +frame seed: 466803 + frame content size: 19 + frame window size: 1152 + content size flag: 1 + single segment flag: 0 + block: + block content size: 19 + last block: yes + compressed block: + rle literals: 0xac + literals size: 7 + total match lengths: 12 + LL: 1 OF: 1 ML: 4 srcPos: 5 seqNb: 0 + repeat offset: 0 + LL: 4 OF: 7 ML: 5 srcPos: 14 seqNb: 1 + LL: 2 OF: 1 ML: 3 srcPos: 19 seqNb: 2 + repeat offset: 1 + excess literals: 0 srcPos: 19 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 3 + block type: compressed + block size field: 11 + checksum: 6f34981f diff --git a/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_466803.zst b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_466803.zst new file mode 100644 index 0000000000..2550a15af8 Binary files /dev/null and b/xls/modules/zstd/data/rle_literals_predefined_sequences_seed_466803.zst differ diff --git a/xls/modules/zstd/data/rle_literals_rle_sequences_seed_2.log b/xls/modules/zstd/data/rle_literals_rle_sequences_seed_2.log new file mode 100644 index 0000000000..bf6b092bbe --- /dev/null +++ b/xls/modules/zstd/data/rle_literals_rle_sequences_seed_2.log @@ -0,0 +1,42 @@ +seed: 2 +frame seed: 2 + frame content size: 152 + frame window size: 114688 + content size flag: 1 + single segment flag: 0 + block: + block content size: 91 + last block: no + compressed block: + compressed literals + distribution weight: 41% + huffman log: 10 + regenerated size: 64 + compressed size: 63 + literals size: 64 + total match lengths: 27 + LL: 1 OF: 1 ML: 4 srcPos: 5 seqNb: 0 + LL: 5 OF: 5 ML: 3 srcPos: 13 seqNb: 1 + LL: 12 OF: 25 ML: 5 srcPos: 30 seqNb: 2 + LL: 17 OF: 14 ML: 4 srcPos: 51 seqNb: 3 + LL: 2 OF: 19 ML: 4 srcPos: 57 seqNb: 4 + LL: 13 OF: 32 ML: 4 srcPos: 74 seqNb: 5 + LL: 12 OF: 59 ML: 3 srcPos: 89 seqNb: 6 + excess literals: 2 srcPos: 91 + LL type: 2 OF type: 0 ML type: 2 + number of sequences: 7 + block type: raw + block size field: 91 + block: + block content size: 61 + last block: yes + compressed block: + rle literals: 0xce + literals size: 41 + total match lengths: 20 + LL: 34 OF: 47 ML: 20 srcPos: 145 seqNb: 0 + excess literals: 7 srcPos: 152 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 10 diff --git a/xls/modules/zstd/data/rle_literals_rle_sequences_seed_2.zst b/xls/modules/zstd/data/rle_literals_rle_sequences_seed_2.zst new file mode 100644 index 0000000000..91284f5bd2 Binary files /dev/null and b/xls/modules/zstd/data/rle_literals_rle_sequences_seed_2.zst differ diff --git a/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_408158.log b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_408158.log new file mode 100644 index 0000000000..d80c261dc5 --- /dev/null +++ b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_408158.log @@ -0,0 +1,111 @@ +seed: 408158 +frame seed: 408158 + frame content size: 44 + frame window size: 90112 + content size flag: 1 + single segment flag: 0 + block: + block content size: 43 + last block: no + compressed block: + raw literals + literals size: 15 + total match lengths: 28 + LL: 7 OF: 3 ML: 9 srcPos: 16 seqNb: 0 + LL: 0 OF: 2 ML: 4 srcPos: 20 seqNb: 1 + LL: 0 OF: 12 ML: 3 srcPos: 23 seqNb: 2 + LL: 8 OF: 6 ML: 12 srcPos: 43 seqNb: 3 + excess literals: 0 srcPos: 43 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 4 + block type: compressed + block size field: 27 + block: + block content size: 1 + last block: no + compressed block: + raw literals + literals size: 1 + total match lengths: 0 + excess literals: 1 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 0 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 2 + block: + block content size: 0 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 2 + block: + block content size: 0 + last block: no + compressed block: + raw literals + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 2 + block: + block content size: 0 + last block: no + compressed block: + rle literals: 0x57 + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 0 + last block: no + compressed block: + rle literals: 0x02 + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 0 + last block: no + compressed block: + rle literals: 0x96 + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 0 + last block: yes + compressed block: + rle literals: 0x40 + literals size: 0 + total match lengths: 0 + excess literals: 0 srcPos: 44 + number of sequences: 0 + block type: compressed + block size field: 3 + checksum: 975ba214 diff --git a/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_408158.zst b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_408158.zst new file mode 100644 index 0000000000..ddb555d1ec Binary files /dev/null and b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_408158.zst differ diff --git a/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_499212.log b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_499212.log new file mode 100644 index 0000000000..5528ebd698 --- /dev/null +++ b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_499212.log @@ -0,0 +1,44 @@ +seed: 499212 +frame seed: 499212 + frame content size: 39 + frame window size: 2304 + content size flag: 1 + single segment flag: 0 + block: + block content size: 35 + last block: no + compressed block: + raw literals + literals size: 17 + total match lengths: 18 + LL: 1 OF: 1 ML: 5 srcPos: 6 seqNb: 0 + LL: 2 OF: 6 ML: 5 srcPos: 13 seqNb: 1 + LL: 0 OF: 3 ML: 8 srcPos: 21 seqNb: 2 + excess literals: 14 srcPos: 35 + LL type: 0 OF type: 0 ML type: 0 + number of sequences: 3 + block type: compressed + block size field: 27 + block: + block content size: 3 + last block: no + compressed block: + rle literals: 0xe4 + literals size: 3 + total match lengths: 0 + excess literals: 3 srcPos: 38 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 1 + last block: yes + compressed block: + raw literals + literals size: 1 + total match lengths: 0 + excess literals: 1 srcPos: 39 + number of sequences: 0 + block type: compressed + block size field: 3 + checksum: fea5e563 diff --git a/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_499212.zst b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_499212.zst new file mode 100644 index 0000000000..ac03f4a85d Binary files /dev/null and b/xls/modules/zstd/data/rle_raw_literals_predefined_sequences_seed_499212.zst differ diff --git a/xls/modules/zstd/data/treeless_huffman_literals_compressed_sequences_seed_400077.log b/xls/modules/zstd/data/treeless_huffman_literals_compressed_sequences_seed_400077.log new file mode 100644 index 0000000000..c47dd6d2d3 --- /dev/null +++ b/xls/modules/zstd/data/treeless_huffman_literals_compressed_sequences_seed_400077.log @@ -0,0 +1,80 @@ +seed: 400077 +frame seed: 400077 + frame content size: 233 + frame window size: 26624 + content size flag: 1 + single segment flag: 0 + block: + block content size: 109 + last block: no + compressed block: + compressed literals + distribution weight: 56% + huffman log: 11 + regenerated size: 44 + compressed size: 44 + trying again + distribution weight: 16% + huffman log: 11 + regenerated size: 40 + compressed size: 72 + trying again + distribution weight: 87% + huffman log: 10 + regenerated size: 32 + compressed size: 27 + literals size: 32 + total match lengths: 77 + LL: 3 OF: 3 ML: 12 srcPos: 15 seqNb: 0 + LL: 3 OF: 15 ML: 37 srcPos: 55 seqNb: 1 + LL: 19 OF: 67 ML: 4 srcPos: 78 seqNb: 2 + LL: 7 OF: 23 ML: 4 srcPos: 89 seqNb: 3 + LL: 0 OF: 21 ML: 20 srcPos: 109 seqNb: 4 + excess literals: 0 srcPos: 109 + LL type: 2 OF type: 2 ML type: 2 + number of sequences: 5 + block type: compressed + block size field: 60 + block: + block content size: 16 + last block: no + compressed block: + rle literals: 0x31 + literals size: 16 + total match lengths: 0 + excess literals: 16 srcPos: 125 + number of sequences: 0 + block type: compressed + block size field: 3 + block: + block content size: 100 + last block: no + compressed block: + compressed literals + huffman repeat stats + regenerated size: 63 + compressed size: 18 + literals size: 63 + total match lengths: 37 + LL: 4 OF: 127 ML: 3 srcPos: 132 seqNb: 0 + LL: 11 OF: 36 ML: 5 srcPos: 148 seqNb: 1 + LL: 48 OF: 30 ML: 11 srcPos: 207 seqNb: 2 + LL: 0 OF: 1 ML: 15 srcPos: 222 seqNb: 3 + LL: 0 OF: 11 ML: 3 srcPos: 225 seqNb: 4 + excess literals: 0 srcPos: 225 + LL type: 2 OF type: 2 ML type: 2 + number of sequences: 5 + block type: compressed + block size field: 50 + block: + block content size: 8 + last block: yes + compressed block: + rle literals: 0xd8 + literals size: 8 + total match lengths: 0 + excess literals: 8 srcPos: 233 + number of sequences: 0 + block type: compressed + block size field: 3 + checksum: 9e8dd98a diff --git a/xls/modules/zstd/data/treeless_huffman_literals_compressed_sequences_seed_400077.zst b/xls/modules/zstd/data/treeless_huffman_literals_compressed_sequences_seed_400077.zst new file mode 100644 index 0000000000..534fd3079c Binary files /dev/null and b/xls/modules/zstd/data/treeless_huffman_literals_compressed_sequences_seed_400077.zst differ diff --git a/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.log b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.log new file mode 100644 index 0000000000..2e7d1110a7 --- /dev/null +++ b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.log @@ -0,0 +1,46 @@ +seed: 400025 +frame seed: 400025 + frame content size: 142 + frame window size: 40960 + content size flag: 1 + single segment flag: 0 + block: + block content size: 78 + last block: no + compressed block: + compressed literals + small range literals + huffman log: 4 + regenerated size: 66 + compressed size: 50 + literals size: 66 + total match lengths: 12 + LL: 66 OF: 45 ML: 12 srcPos: 78 seqNb: 0 + excess literals: 0 srcPos: 78 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 60 + block: + block content size: 64 + last block: yes + compressed block: + compressed literals + huffman repeat stats + regenerated size: 43 + compressed size: 30 + literals size: 43 + total match lengths: 21 + LL: 12 OF: 17 ML: 3 srcPos: 93 seqNb: 0 + LL: 0 OF: 65 ML: 5 srcPos: 98 seqNb: 1 + LL: 23 OF: 7 ML: 3 srcPos: 124 seqNb: 2 + LL: 4 OF: 65 ML: 4 srcPos: 132 seqNb: 3 + repeat offset: 1 + LL: 0 OF: 69 ML: 3 srcPos: 135 seqNb: 4 + LL: 1 OF: 75 ML: 3 srcPos: 139 seqNb: 5 + excess literals: 3 srcPos: 142 + LL type: 2 OF type: 2 ML type: 0 + number of sequences: 6 + block type: compressed + block size field: 60 + checksum: 29af0a62 diff --git a/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.zst b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.zst new file mode 100644 index 0000000000..884f540c77 Binary files /dev/null and b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.zst differ diff --git a/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.log b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.log new file mode 100644 index 0000000000..6f5e6bf708 --- /dev/null +++ b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.log @@ -0,0 +1,81 @@ +seed: 400061 +frame seed: 400061 + frame content size: 241 + frame window size: 2048 + content size flag: 1 + single segment flag: 0 + block: + block content size: 60 + last block: no + compressed block: + raw literals + literals size: 60 + total match lengths: 0 + excess literals: 60 srcPos: 60 + number of sequences: 0 + block type: compressed + block size field: 63 + block: + block content size: 91 + last block: no + compressed block: + compressed literals + small range literals + huffman log: 10 + regenerated size: 44 + compressed size: 39 + literals size: 44 + total match lengths: 47 + LL: 1 OF: 40 ML: 3 srcPos: 64 seqNb: 0 + LL: 0 OF: 12 ML: 3 srcPos: 67 seqNb: 1 + LL: 2 OF: 13 ML: 3 srcPos: 72 seqNb: 2 + LL: 0 OF: 70 ML: 3 srcPos: 75 seqNb: 3 + LL: 8 OF: 71 ML: 3 srcPos: 86 seqNb: 4 + LL: 17 OF: 17 ML: 3 srcPos: 106 seqNb: 5 + LL: 0 OF: 39 ML: 3 srcPos: 109 seqNb: 6 + LL: 0 OF: 56 ML: 3 srcPos: 112 seqNb: 7 + LL: 1 OF: 78 ML: 5 srcPos: 118 seqNb: 8 + LL: 1 OF: 48 ML: 3 srcPos: 122 seqNb: 9 + LL: 0 OF: 122 ML: 3 srcPos: 125 seqNb: 10 + LL: 1 OF: 1 ML: 3 srcPos: 129 seqNb: 11 + LL: 7 OF: 31 ML: 4 srcPos: 140 seqNb: 12 + LL: 3 OF: 19 ML: 5 srcPos: 148 seqNb: 13 + excess literals: 3 srcPos: 151 + LL type: 2 OF type: 0 ML type: 2 + number of sequences: 14 + block type: compressed + block size field: 74 + block: + block content size: 11 + last block: no + compressed block: + rle literals: 0x9c + literals size: 8 + total match lengths: 3 + LL: 4 OF: 1 ML: 3 srcPos: 158 seqNb: 0 + repeat offset: 2 + excess literals: 4 srcPos: 162 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 8 + block: + block content size: 79 + last block: yes + compressed block: + compressed literals + huffman repeat stats + regenerated size: 57 + compressed size: 37 + literals size: 57 + total match lengths: 22 + LL: 22 OF: 18 ML: 3 srcPos: 187 seqNb: 0 + LL: 7 OF: 168 ML: 5 srcPos: 199 seqNb: 1 + LL: 28 OF: 48 ML: 5 srcPos: 232 seqNb: 2 + LL: 0 OF: 176 ML: 9 srcPos: 241 seqNb: 3 + excess literals: 0 srcPos: 241 + LL type: 2 OF type: 0 ML type: 2 + number of sequences: 4 + block type: compressed + block size field: 69 + checksum: 1d05f549 diff --git a/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.zst b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.zst new file mode 100644 index 0000000000..b0fe4849b3 Binary files /dev/null and b/xls/modules/zstd/data/treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.zst differ diff --git a/xls/modules/zstd/data/treeless_huffman_literals_rle_sequences_seed_403927.log b/xls/modules/zstd/data/treeless_huffman_literals_rle_sequences_seed_403927.log new file mode 100644 index 0000000000..9962123a00 --- /dev/null +++ b/xls/modules/zstd/data/treeless_huffman_literals_rle_sequences_seed_403927.log @@ -0,0 +1,53 @@ +seed: 403927 +frame seed: 403927 + frame content size: 224 + frame window size: 229376 + content size flag: 1 + single segment flag: 0 + block: + block content size: 100 + last block: no + compressed block: + compressed literals + distribution weight: 46% + huffman log: 8 + regenerated size: 67 + compressed size: 56 + literals size: 67 + total match lengths: 33 + LL: 67 OF: 46 ML: 33 srcPos: 100 seqNb: 0 + excess literals: 0 srcPos: 100 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 68 + block: + block content size: 23 + last block: no + compressed block: + rle literals: 0x46 + literals size: 14 + total match lengths: 9 + LL: 14 OF: 27 ML: 9 srcPos: 123 seqNb: 0 + excess literals: 0 srcPos: 123 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 8 + block: + block content size: 101 + last block: yes + compressed block: + compressed literals + huffman repeat stats + regenerated size: 96 + compressed size: 29 + literals size: 96 + total match lengths: 5 + LL: 0 OF: 4 ML: 5 srcPos: 128 seqNb: 0 + excess literals: 96 srcPos: 224 + LL type: 1 OF type: 1 ML type: 1 + number of sequences: 1 + block type: compressed + block size field: 38 + checksum: d06e892b diff --git a/xls/modules/zstd/data/treeless_huffman_literals_rle_sequences_seed_403927.zst b/xls/modules/zstd/data/treeless_huffman_literals_rle_sequences_seed_403927.zst new file mode 100644 index 0000000000..d5cfe6c706 Binary files /dev/null and b/xls/modules/zstd/data/treeless_huffman_literals_rle_sequences_seed_403927.zst differ diff --git a/xls/modules/zstd/huffman_decoder.x b/xls/modules/zstd/huffman_decoder.x index 5652a64da6..50895ac4e2 100644 --- a/xls/modules/zstd/huffman_decoder.x +++ b/xls/modules/zstd/huffman_decoder.x @@ -223,7 +223,7 @@ pub proc HuffmanDecoder { trace_fmt!("[HuffmanDecoder] Received codes:"); for (i, ()) in u32:0..SYMBOLS_N { if symbol_valid[i] { - trace_fmt!("[HuffmanDecoder] {:#b} (len {}) -> {:#x}", symbol_code[i], symbol_code_len[i], i); + trace_fmt!("[HuffmanDecoder] {:#x} (len {}) -> {:#x}", symbol_code[i], symbol_code_len[i], i); } else {}; }(()); FSM::READ_DATA diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index ba29c3a453..b0d7312393 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -12,9 +12,11 @@ # See the License for the specific language governing permissions and # limitations under the License. +# pytype binary, library load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route") load("@rules_hdl//synthesis:build_defs.bzl", "benchmark_synth", "synthesize_rtl") load("@rules_hdl//verilog:providers.bzl", "verilog_library") +load("@xls_pip_deps//:requirements.bzl", "requirement") load( "//xls/build_rules:xls_build_defs.bzl", "xls_benchmark_ir", @@ -546,6 +548,31 @@ place_and_route( target_die_utilization_percentage = "10", ) +py_test( + name = "mem_reader_cocotb_test", + srcs = ["mem_reader_cocotb_test.py"], + data = [ + ":mem_reader_adv.v", + "//xls/modules/zstd/memory/rtl:mem_reader_wrapper.v", + "@com_icarus_iverilog//:iverilog", + "@com_icarus_iverilog//:vvp", + ], + tags = ["manual"], + visibility = ["//xls:xls_users"], + deps = [ + requirement("cocotb"), + requirement("cocotbext-axi"), + "//xls/common:runfiles", + "//xls/modules/zstd/cocotb:channel", + "//xls/modules/zstd/cocotb:memory", + "//xls/modules/zstd/cocotb:utils", + "//xls/modules/zstd/cocotb:xlsstruct", + "@abseil-py//absl:app", + "@abseil-py//absl/flags", + "@com_google_protobuf//:protobuf_python", + ], +) + xls_dslx_library( name = "axi_writer_dslx", srcs = ["axi_writer.x"], @@ -615,6 +642,30 @@ place_and_route( target_die_utilization_percentage = "10", ) +py_test( + name = "axi_writer_cocotb_test", + srcs = ["axi_writer_cocotb_test.py"], + data = [ + ":axi_writer.v", + "//xls/modules/zstd/memory/rtl:axi_writer_wrapper.v", + "@com_icarus_iverilog//:iverilog", + "@com_icarus_iverilog//:vvp", + ], + tags = ["manual"], + visibility = ["//xls:xls_users"], + deps = [ + requirement("cocotb"), + requirement("cocotbext-axi"), + "//xls/common:runfiles", + "//xls/modules/zstd/cocotb:channel", + "//xls/modules/zstd/cocotb:utils", + "//xls/modules/zstd/cocotb:xlsstruct", + "@abseil-py//absl:app", + "@abseil-py//absl/flags", + "@com_google_protobuf//:protobuf_python", + ], +) + xls_dslx_library( name = "axi_stream_add_empty_dslx", srcs = ["axi_stream_add_empty.x"], @@ -753,3 +804,27 @@ place_and_route( tags = ["manual"], target_die_utilization_percentage = "10", ) + +py_test( + name = "mem_writer_cocotb_test", + srcs = ["mem_writer_cocotb_test.py"], + data = [ + ":mem_writer.v", + "//xls/modules/zstd/memory/rtl:mem_writer_wrapper.v", + "@com_icarus_iverilog//:iverilog", + "@com_icarus_iverilog//:vvp", + ], + tags = ["manual"], + visibility = ["//xls:xls_users"], + deps = [ + requirement("cocotb"), + requirement("cocotbext-axi"), + "//xls/common:runfiles", + "//xls/modules/zstd/cocotb:channel", + "//xls/modules/zstd/cocotb:utils", + "//xls/modules/zstd/cocotb:xlsstruct", + "@abseil-py//absl:app", + "@abseil-py//absl/flags", + "@com_google_protobuf//:protobuf_python", + ], +) diff --git a/xls/modules/zstd/memory/README.md b/xls/modules/zstd/memory/README.md index 37c20c45a3..ad7d874218 100644 --- a/xls/modules/zstd/memory/README.md +++ b/xls/modules/zstd/memory/README.md @@ -89,3 +89,44 @@ The list below shows the usage of the `MemWriter` proc: 3. Wait for the response submitted on the `resp_s` channel, which indicates if the write operation was successful or an error occurred. + +## Cocotb Simulation + +This directory also contains Verilog simulations of the created modules, +which test their interaction with RAM attached to the AXI bus. These Verilog +simulations provide insight into the design's latency and achievable throughput. + +The simulation interacts with verilog file generated from the particular DSLX +proc through a verilog wrapper. The wrapper is used to create an interface that +is compliant with the AXI specification so that the cocotb testbench can +interact with the DUT with the help of an extension tailored for handling the +AXI bus. + +### Usage + +1. Run the simulation with the following command: + +``` +bazel run -c opt //xls/modules/zstd/memory:_cocotb_test -- --logtostderr +``` + +2. Observe simulation results, e.g. for `mem_writer_cocotb_test`: + +``` +************************************************************************************************************************************************************* +** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) ** +************************************************************************************************************************************************************* +** mem_writer_cocotb_test.ram_test_single_burst_1_transfer PASS 1970000.00 0.05 40004933.01 ** +** mem_writer_cocotb_test.ram_test_single_burst_2_transfers PASS 2140000.00 0.04 52208013.80 ** +** mem_writer_cocotb_test.ram_test_single_burst_almost_max_burst_transfer PASS 42620000.00 1.00 42734572.11 ** +** mem_writer_cocotb_test.ram_test_single_burst_max_burst_transfer PASS 43380000.00 1.03 42245987.95 ** +** mem_writer_cocotb_test.ram_test_multiburst_2_full_bursts PASS 85940000.00 2.00 42978720.13 ** +** mem_writer_cocotb_test.ram_test_multiburst_1_full_burst_and_single_transfer PASS 44510000.00 1.02 43487911.16 ** +** mem_writer_cocotb_test.ram_test_multiburst_crossing_4kb_boundary PASS 3740000.00 0.06 60190612.91 ** +** mem_writer_cocotb_test.ram_test_multiburst_crossing_4kb_boundary_with_perfectly_aligned_full_bursts PASS 21440000.00 0.50 42469371.00 ** +** mem_writer_cocotb_test.ram_test_multiburst_crossing_4kb_boundary_with_2_full_bursts_and_1_transfer PASS 87070000.00 2.01 43348812.05 ** +** mem_writer_cocotb_test.ram_test_random PASS 4491230000.00 109.05 41184670.96 ** +************************************************************************************************************************************************************* +** TESTS=10 PASS=10 FAIL=0 SKIP=0 4824040000.01 116.82 41296261.92 ** +************************************************************************************************************************************************************* +``` diff --git a/xls/modules/zstd/memory/axi_writer_cocotb_test.py b/xls/modules/zstd/memory/axi_writer_cocotb_test.py new file mode 100644 index 0000000000..270a390416 --- /dev/null +++ b/xls/modules/zstd/memory/axi_writer_cocotb_test.py @@ -0,0 +1,312 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +import random +import logging +import pathlib +import sys + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import Event +from cocotb_bus.scoreboard import Scoreboard + +from cocotbext.axi import axis +from cocotbext.axi import axi_channels +from cocotbext.axi.axi_ram import AxiRamWrite +from cocotbext.axi.sparse_memory import SparseMemory + +import xls.modules.zstd.cocotb.channel as xlschannel +from xls.modules.zstd.cocotb import utils +from xls.modules.zstd.cocotb import xlsstruct + +ID_WIDTH = 4 +ADDR_WIDTH = 16 + +# Override default widths of AXI response signals +signal_widths = {"bresp": 3} +axi_channels.AxiBBus._signal_widths = signal_widths +axi_channels.AxiBTransaction._signal_widths = signal_widths +axi_channels.AxiBSource._signal_widths = signal_widths +axi_channels.AxiBSink._signal_widths = signal_widths +axi_channels.AxiBMonitor._signal_widths = signal_widths + +@xlsstruct.xls_dataclass +class AxiWriterRespStruct(xlsstruct.XLSStruct): + status: 1 + +@xlsstruct.xls_dataclass +class WriteRequestStruct(xlsstruct.XLSStruct): + address: ADDR_WIDTH + length: ADDR_WIDTH + +def set_termination_event(monitor, event, transactions): + def terminate_cb(_): + if monitor.stats.received_transactions == transactions: + event.set() + monitor.add_callback(terminate_cb) + +@cocotb.test(timeout_time=20000, timeout_unit="ms") +async def ram_test(dut): + generic_addr_req_channel = "write_req" + generic_addr_resp_channel = "write_resp" + axi_stream_channel = "axi_st_read" + axi_aw_channel = "axi_aw" + axi_w_channel = "axi_w" + axi_b_channel = "axi_b" + + terminate = Event() + + mem_size = 2**ADDR_WIDTH + test_count = 200 + + ( + addr_req_input, + axi_st_input, + addr_resp_expect, + memory_verification, + expected_memory + ) = generate_test_data_random(test_count, mem_size) + + dut.rst.setimmediatevalue(0) + + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + # prefix unused objects with unused_ + # to suppress linter and keep the objects alive + unused_resp_bus = xlschannel.XLSChannel( + dut, generic_addr_resp_channel, dut.clk, start_now=True + ) + + driver_addr_req = xlschannel.XLSChannelDriver( + dut, generic_addr_req_channel, dut.clk + ) + driver_axi_st = axis.AxiStreamSource( + axis.AxiStreamBus.from_prefix(dut, axi_stream_channel), + dut.clk, + dut.rst + ) + + bus_axi_aw = axi_channels.AxiAWBus.from_prefix(dut, axi_aw_channel) + bus_axi_w = axi_channels.AxiWBus.from_prefix(dut, axi_w_channel) + bus_axi_b = axi_channels.AxiBBus.from_prefix(dut, axi_b_channel) + bus_axi_write = axi_channels.AxiWriteBus(bus_axi_aw, bus_axi_w, bus_axi_b) + + unused_monitor_addr_req = xlschannel.XLSChannelMonitor( + dut, generic_addr_req_channel, dut.clk, WriteRequestStruct + ) + monitor_addr_resp = xlschannel.XLSChannelMonitor( + dut, generic_addr_resp_channel, dut.clk, AxiWriterRespStruct + ) + unused_monitor_axi_aw = axi_channels.AxiAWMonitor( + bus_axi_aw, dut.clk, dut.rst + ) + unused_monitor_axi_w = axi_channels.AxiWMonitor(bus_axi_w, dut.clk, dut.rst) + unused_monitor_axi_b = axi_channels.AxiBMonitor(bus_axi_b, dut.clk, dut.rst) + + set_termination_event(monitor_addr_resp, terminate, test_count) + + memory = AxiRamWrite(bus_axi_write, dut.clk, dut.rst, size=mem_size) + + log = logging.getLogger("cocotb.tb") + log.setLevel(logging.WARNING) + memory.log.setLevel(logging.WARNING) + driver_axi_st.log.setLevel(logging.WARNING) + + scoreboard = Scoreboard(dut) + scoreboard.add_interface(monitor_addr_resp, addr_resp_expect) + + await utils.reset(dut.clk, dut.rst, cycles=10) + await cocotb.start(driver_addr_req.send(addr_req_input)) + await cocotb.start(drive_axi_st(driver_axi_st, axi_st_input)) + await terminate.wait() + + for bundle in memory_verification: + memory_contents = bytearray( + memory.read(bundle["base_address"], bundle["length"]) + ) + expected_memory_contents = bytearray( + expected_memory.read(bundle["base_address"], bundle["length"]) + ) + assert memory_contents == expected_memory_contents, ( + ( + "{} bytes of memory contents at base address {}:\n" + "{}\nvs\n{}" + "\nHEXDUMP:\n{}" + "\nvs\n{}" + ).format( + hex(bundle["length"]), + hex(bundle["base_address"]), + memory_contents, + expected_memory_contents, + memory.hexdump(bundle["base_address"], bundle["length"]), + expected_memory.hexdump(bundle["base_address"], bundle["length"]) + ) + ) + +@cocotb.coroutine +async def drive_axi_st(driver, inputs): + for axi_st_input in inputs: + await driver.send(axi_st_input) + +def generate_test_data_random(test_count, mem_size): + addr_req_input = [] + axi_st_input = [] + addr_resp_expect = [] + memory_verification = [] + memory = SparseMemory(mem_size) + + random.seed(1234) + + for i in range(test_count): + xfer_addr = random.randrange(0, mem_size) + # Don't allow unaligned writes + xfer_addr_aligned = (xfer_addr // 4) * 4 + # Make sure we don't write beyond available memory + memory_size_max_xfer_len = mem_size - xfer_addr_aligned + arbitrary_max_xfer_len = 0x5000 # 20kB + xfer_max_len = min(arbitrary_max_xfer_len, memory_size_max_xfer_len) + xfer_len = random.randrange(1, xfer_max_len) + transfer_req = WriteRequestStruct( + address = xfer_addr_aligned, + length = xfer_len, + ) + addr_req_input.append(transfer_req) + + data_to_write = random.randbytes(xfer_len) + axi_st_frame = axis.AxiStreamFrame( + tdata=data_to_write, + tkeep=[15]*xfer_len, + tid=i % (1 << ID_WIDTH), + tdest=(i % (1 << ID_WIDTH)) + ) + axi_st_input.append(axi_st_frame) + + write_expected_memory(transfer_req, axi_st_frame.tdata, memory) + + memory_bundle = { + "base_address": transfer_req.address, + "length": transfer_req.length, + } + memory_verification.append(memory_bundle) + + addr_resp_expect = [AxiWriterRespStruct(status=False)] * test_count + + return ( + addr_req_input, + axi_st_input, + addr_resp_expect, + memory_verification, + memory + ) + +def bytes_to_4k_boundary(addr): + axi_4k_boundary = 0x1000 + return axi_4k_boundary - (addr % axi_4k_boundary) + +def write_expected_memory(transfer_req, data_to_write, memory): + """Write test data to reference memory keeping the AXI 4kb boundary. + + Split the write requests into smaller ones as needed. + + Args: + transfer_req: The transfer request object containing address and length + information. + data_to_write: A bytes-like object or list of data that needs to be + written. + memory: SparseMemory object simulating memory storage, where the data will + be written. + """ + prev_id = 0 + address = transfer_req.address + length = transfer_req.length + + bytes_in_transfer = 4 + max_axi_burst_bytes = 256 * bytes_in_transfer + + while (length > 0): + bytes_to_4k = bytes_to_4k_boundary(address) + new_len = min(length, min(bytes_to_4k, max_axi_burst_bytes)) + new_data = data_to_write[prev_id:prev_id+new_len] + memory.write(address, new_data) + address = address + new_len + length = length - new_len + prev_id = prev_id + new_len + +def generate_test_data_arbitrary(mem_size): + addr_req_input = [] + axi_st_input = [] + addr_resp_expect = [] + memory_verification = [] + memory = SparseMemory(mem_size) + + xfer_addr_begin = [0, 8, 512, 1000, 0x1234, 256] + xfer_len = [1, 2, 4, 8, 0x48d, 4] + assert len(xfer_len) == len(xfer_addr_begin) + testcase_num = len(xfer_addr_begin) # test cases to execute + for i in range(testcase_num): + transfer_req = WriteRequestStruct( + address = xfer_addr_begin[i], + length = xfer_len[i] * 4, # xfer_len[i] transfers per 4 bytes + ) + addr_req_input.append(transfer_req) + + data_chunks = [] + data_bytes = [ + [(0xEF + j) & 0xFF, 0xBE, 0xAD, 0xDE] for j in range(xfer_len[i]) + ] + unused_data_words = [ + int.from_bytes(data_bytes[j]) for j in range(xfer_len[i]) + ] + for j in range(xfer_len[i]): + data_chunks += data_bytes[j] + data_to_write = bytearray(data_chunks) + axi_st_frame = axis.AxiStreamFrame( + tdata=data_to_write, + tkeep=[15]*xfer_len[i], + tid=i, + tdest=i + ) + axi_st_input.append(axi_st_frame) + + write_expected_memory(transfer_req, axi_st_frame.tdata, memory) + + memory_bundle = { + "base_address": transfer_req.address, + "length": transfer_req.length, # 4 byte words + } + memory_verification.append(memory_bundle) + + addr_resp_expect = [AxiWriterRespStruct(status=False)] * testcase_num + + return ( + addr_req_input, + axi_st_input, + addr_resp_expect, + memory_verification, + memory + ) + +if __name__ == "__main__": + sys.path.append(str(pathlib.Path(__file__).parent)) + + toplevel = "axi_writer_wrapper" + verilog_sources = [ + "xls/modules/zstd/memory/axi_writer.v", + "xls/modules/zstd/memory/rtl/axi_writer_wrapper.v", + ] + test_module=[pathlib.Path(__file__).stem] + utils.run_test(toplevel, test_module, verilog_sources) diff --git a/xls/modules/zstd/memory/mem_reader_cocotb_test.py b/xls/modules/zstd/memory/mem_reader_cocotb_test.py new file mode 100644 index 0000000000..8f862bc5ca --- /dev/null +++ b/xls/modules/zstd/memory/mem_reader_cocotb_test.py @@ -0,0 +1,282 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +import pathlib +import random +import sys +import warnings + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import Event +from cocotb_bus.scoreboard import Scoreboard +from cocotbext.axi import axi_channels +from cocotbext.axi.axi_ram import AxiRamRead +from cocotbext.axi.sparse_memory import SparseMemory + +import xls.modules.zstd.cocotb.channel as xlschannel +from xls.modules.zstd.cocotb import utils +from xls.modules.zstd.cocotb import xlsstruct + +# to disable warnings from hexdiff used by cocotb's Scoreboard +warnings.filterwarnings("ignore", category=DeprecationWarning) + +DSLX_DATA_W = 64 +DSLX_ADDR_W = 16 + +AXI_DATA_W = 128 +AXI_ADDR_W = 16 + +LAST_W = 1 +STATUS_W = 1 +ERROR_W = 1 +ID_W = 4 +DEST_W = 4 + +# AXI +AXI_AR_PREFIX = "axi_ar" +AXI_R_PREFIX = "axi_r" + +# MemReader +MEM_READER_REQ_CHANNEL = "req" +MEM_READER_RESP_CHANNEL = "resp" + +# Override default widths of AXI response signals +signal_widths = {"rresp": 3, "rlast": 1} +axi_channels.AxiRBus._signal_widths = signal_widths +axi_channels.AxiRTransaction._signal_widths = signal_widths +axi_channels.AxiRSource._signal_widths = signal_widths +axi_channels.AxiRSink._signal_widths = signal_widths +axi_channels.AxiRMonitor._signal_widths = signal_widths + +@xlsstruct.xls_dataclass +class MemReaderReq(xlsstruct.XLSStruct): + addr: DSLX_ADDR_W + length: DSLX_ADDR_W + + +@xlsstruct.xls_dataclass +class MemReaderResp(xlsstruct.XLSStruct): + status: STATUS_W + data: DSLX_DATA_W + length: DSLX_ADDR_W + last: LAST_W + + +@xlsstruct.xls_dataclass +class AxiReaderReq(xlsstruct.XLSStruct): + addr: AXI_ADDR_W + len: AXI_ADDR_W + + +@xlsstruct.xls_dataclass +class AxiStream(xlsstruct.XLSStruct): + data: AXI_DATA_W + str: AXI_DATA_W // 8 + keep: AXI_DATA_W // 8 = 0 + last: LAST_W = 0 + id: ID_W = 0 + dest: DEST_W = 0 + + +@xlsstruct.xls_dataclass +class AxiReaderError(xlsstruct.XLSStruct): + error: ERROR_W + + +@xlsstruct.xls_dataclass +class AxiAr(xlsstruct.XLSStruct): + id: ID_W + addr: AXI_ADDR_W + region: 4 + len: 8 + size: 3 + burst: 2 + cache: 4 + prot: 3 + qos: 4 + + +@xlsstruct.xls_dataclass +class AxiR(xlsstruct.XLSStruct): + id: ID_W + data: AXI_DATA_W + resp: 3 + last: 1 + + +def print_callback(name: str = "monitor"): + def _print_callback(transaction): + print(f" [{name}]: {transaction}") + + return _print_callback + + +def set_termination_event(monitor, event, transactions): + def terminate_cb(_): + if monitor.stats.received_transactions == transactions: + print("all transactions received") + event.set() + + monitor.add_callback(terminate_cb) + + +def generate_test_data(test_cases, xfer_base=0x0, seed=1234): + random.seed(seed) + mem_size = 2**AXI_ADDR_W + data_w_div8 = DSLX_DATA_W // 8 + + assert xfer_base < mem_size, "Base address outside the memory span" + + req = [] + resp = [] + mem_writes = {} + + for xfer_offset, xfer_length in test_cases: + xfer_addr = xfer_base + xfer_offset + xfer_max_addr = xfer_addr + xfer_length + + if xfer_length == 0: + req += [MemReaderReq(addr=xfer_addr, length=0)] + resp += [MemReaderResp(status=0, data=0, length=0, last=1)] + + assert xfer_max_addr < mem_size, "Max address outside the memory span" + req += [MemReaderReq(addr=xfer_addr, length=xfer_length)] + + rem = xfer_length % data_w_div8 + range_end = xfer_max_addr - (data_w_div8 - 1) + for addr in range(xfer_addr, range_end, data_w_div8): + last = ((addr + data_w_div8) >= xfer_max_addr) & (rem == 0) + data = random.randint(0, 1 << (data_w_div8 * 8)) + mem_writes.update({addr: data}) + resp += [ + MemReaderResp(status=0, data=data, length=data_w_div8, last=last) + ] + + if rem > 0: + addr = xfer_max_addr - rem + mask = (1 << (rem * 8)) - 1 + data = random.randint(0, 1 << (data_w_div8 * 8)) + mem_writes.update({addr: data}) + resp += [MemReaderResp(status=0, data=data & mask, length=rem, last=1)] + + return (req, resp, mem_writes) + + +async def test_mem_reader(dut, req_input, resp_output, mem_contents=None): + if mem_contents is None: + mem_contents = {} + + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + # prefix unused objects with unused_ + # to suppress linter and keep the objects alive + unused_mem_reader_resp_bus = xlschannel.XLSChannel( + dut, MEM_READER_RESP_CHANNEL, dut.clk, start_now=True + ) + mem_reader_req_driver = xlschannel.XLSChannelDriver( + dut, MEM_READER_REQ_CHANNEL, dut.clk + ) + mem_reader_resp_monitor = xlschannel.XLSChannelMonitor( + dut, + MEM_READER_RESP_CHANNEL, + dut.clk, + MemReaderResp, + callback=print_callback() + ) + + terminate = Event() + set_termination_event(mem_reader_resp_monitor, terminate, len(resp_output)) + + scoreboard = Scoreboard(dut) + scoreboard.add_interface(mem_reader_resp_monitor, resp_output) + + ar_bus = axi_channels.AxiARBus.from_prefix(dut, AXI_AR_PREFIX) + r_bus = axi_channels.AxiRBus.from_prefix(dut, AXI_R_PREFIX) + axi_read_bus = axi_channels.AxiReadBus(ar=ar_bus, r=r_bus) + + mem_size = 2**AXI_ADDR_W + sparse_mem = SparseMemory(mem_size) + for addr, data in mem_contents.items(): + sparse_mem.write(addr, (data).to_bytes(8, "little")) + + unused_memory = AxiRamRead( + axi_read_bus, dut.clk, dut.rst, size=mem_size, mem=sparse_mem + ) + + await utils.reset(dut.clk, dut.rst, cycles=10) + await mem_reader_req_driver.send(req_input) + await terminate.wait() + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def mem_reader_zero_length_req(dut): + req, resp, _ = generate_test_data( + xfer_base=0xFFF, test_cases=[(0x101, 0)] + ) + await test_mem_reader(dut, req, resp) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def mem_reader_aligned_transfer_shorter_than_bus(dut): + req, resp, mem_contents = generate_test_data( + xfer_base=0xFFF, test_cases=[(0x101, 1)] + ) + await test_mem_reader(dut, req, resp, mem_contents) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def mem_reader_aligned_transfer_shorter_than_bus1(dut): + req, resp, mem_contents = generate_test_data( + xfer_base=0xFFF, test_cases=[(0x2, 1)] + ) + await test_mem_reader(dut, req, resp, mem_contents) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def mem_reader_aligned_transfer_shorter_than_bus2(dut): + req, resp, mem_contents = generate_test_data( + xfer_base=0xFFF, test_cases=[(0x2, 17)] + ) + await test_mem_reader(dut, req, resp, mem_contents) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def mem_reader_aligned_transfer_shorter_than_bus3(dut): + req, resp, mem_contents = generate_test_data( + xfer_base=0xFFF, test_cases=[(0x0, 0x1000)] + ) + await test_mem_reader(dut, req, resp, mem_contents) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def mem_reader_aligned_transfer_shorter_than_bus4(dut): + req, resp, mem_contents = generate_test_data( + xfer_base=0x1, test_cases=[(0x0, 0xFFF), (0x1000, 0x1)] + ) + await test_mem_reader(dut, req, resp, mem_contents) + + +if __name__ == "__main__": + sys.path.append(str(pathlib.Path(__file__).parent)) + + toplevel = "mem_reader_wrapper" + verilog_sources = [ + "xls/modules/zstd/memory/mem_reader_adv.v", + "xls/modules/zstd/memory/rtl/mem_reader_wrapper.v", + ] + test_module = [pathlib.Path(__file__).stem] + utils.run_test(toplevel, test_module, verilog_sources) diff --git a/xls/modules/zstd/memory/mem_writer_cocotb_test.py b/xls/modules/zstd/memory/mem_writer_cocotb_test.py new file mode 100644 index 0000000000..a74a5db2e7 --- /dev/null +++ b/xls/modules/zstd/memory/mem_writer_cocotb_test.py @@ -0,0 +1,949 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +import random +import logging +import enum +import pathlib +import sys + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import Event +from cocotb_bus.scoreboard import Scoreboard + +from cocotbext.axi import axi_channels +from cocotbext.axi.axi_ram import AxiRamWrite +from cocotbext.axi.sparse_memory import SparseMemory + +import xls.modules.zstd.cocotb.channel as xlschannel +from xls.modules.zstd.cocotb import utils +from xls.modules.zstd.cocotb import xlsstruct + +DATA_WIDTH = 32 +ADDR_WIDTH = 16 + +# Override default widths of AXI response signals +signal_widths = {"bresp": 3} +axi_channels.AxiBBus._signal_widths = signal_widths +axi_channels.AxiBTransaction._signal_widths = signal_widths +axi_channels.AxiBSource._signal_widths = signal_widths +axi_channels.AxiBSink._signal_widths = signal_widths +axi_channels.AxiBMonitor._signal_widths = signal_widths + +@xlsstruct.xls_dataclass +class DataInStruct(xlsstruct.XLSStruct): + data: DATA_WIDTH + length: ADDR_WIDTH + last: 1 + +@xlsstruct.xls_dataclass +class WriteReqStruct(xlsstruct.XLSStruct): + offset: ADDR_WIDTH + length: ADDR_WIDTH + +@xlsstruct.xls_dataclass +class MemWriterRespStruct(xlsstruct.XLSStruct): + status: 1 + +class MemWriterRespStatus(enum.Enum): + OKAY = 0 + ERROR = 1 + +@xlsstruct.xls_dataclass +class WriteRequestStruct(xlsstruct.XLSStruct): + address: ADDR_WIDTH + length: ADDR_WIDTH + +def set_termination_event(monitor, event, transactions): + def terminate_cb(_): + if monitor.stats.received_transactions == transactions: + event.set() + monitor.add_callback(terminate_cb) + +async def test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt +): + generic_write_req_channel = "req" + generic_write_resp_channel = "resp" + generic_data_in_channel = "data_in" + axi_aw_channel = "axi_aw" + axi_w_channel = "axi_w" + axi_b_channel = "axi_b" + + terminate = Event() + + dut.rst.setimmediatevalue(0) + + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + # prefix unused objects with unused_ + # to suppress linter and keep the objects alive + unused_resp_bus = xlschannel.XLSChannel( + dut, generic_write_resp_channel, dut.clk, start_now=True + ) + + driver_write_req = xlschannel.XLSChannelDriver( + dut, generic_write_req_channel, dut.clk + ) + driver_data_in = xlschannel.XLSChannelDriver( + dut, generic_data_in_channel, dut.clk + ) + + bus_axi_aw = axi_channels.AxiAWBus.from_prefix(dut, axi_aw_channel) + bus_axi_w = axi_channels.AxiWBus.from_prefix(dut, axi_w_channel) + bus_axi_b = axi_channels.AxiBBus.from_prefix(dut, axi_b_channel) + bus_axi_write = axi_channels.AxiWriteBus(bus_axi_aw, bus_axi_w, bus_axi_b) + + unused_monitor_write_req = xlschannel.XLSChannelMonitor( + dut, generic_write_req_channel, dut.clk, WriteRequestStruct + ) + unused_monitor_data_in = xlschannel.XLSChannelMonitor( + dut, generic_data_in_channel, dut.clk, WriteRequestStruct + ) + monitor_write_resp = xlschannel.XLSChannelMonitor( + dut, generic_write_resp_channel, dut.clk, MemWriterRespStruct + ) + unused_monitor_axi_aw = axi_channels.AxiAWMonitor( + bus_axi_aw, dut.clk, dut.rst + ) + unused_monitor_axi_w = axi_channels.AxiWMonitor(bus_axi_w, dut.clk, dut.rst) + unused_monitor_axi_b = axi_channels.AxiBMonitor(bus_axi_b, dut.clk, dut.rst) + + set_termination_event(monitor_write_resp, terminate, resp_cnt) + + memory = AxiRamWrite(bus_axi_write, dut.clk, dut.rst, size=mem_size) + + log = logging.getLogger("cocotb.tb") + log.setLevel(logging.WARNING) + memory.log.setLevel(logging.WARNING) + + scoreboard = Scoreboard(dut) + scoreboard.add_interface(monitor_write_resp, write_resp_expect) + + await utils.reset(dut.clk, dut.rst, cycles=10) + await cocotb.start(driver_write_req.send(write_req_input)) + await cocotb.start(driver_data_in.send(data_in_input)) + + await terminate.wait() + + for bundle in memory_verification: + memory_contents = bytearray( + memory.read(bundle["base_address"], bundle["length"]) + ) + expected_memory_contents = bytearray( + expected_memory.read(bundle["base_address"], bundle["length"]) + ) + assert memory_contents == expected_memory_contents, ( + ( + "{} bytes of memory contents at base address {}:\n" + "{}\nvs\n{}" + "\nHEXDUMP:\n{}" + "\nvs\n{}" + ).format( + hex(bundle["length"]), + hex(bundle["base_address"]), + memory_contents, + expected_memory_contents, + memory.hexdump(bundle["base_address"], bundle["length"]), + expected_memory.hexdump(bundle["base_address"], bundle["length"]) + ) + ) + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_single_burst_1_transfer(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary(mem_size, test_cases_single_burst_1_transfer) + + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_single_burst_2_transfers(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, test_cases_single_burst_2_transfers + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_single_burst_almost_max_burst_transfer(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, test_cases_single_burst_almost_max_burst_transfer + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_single_burst_max_burst_transfer(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, test_cases_single_burst_max_burst_transfer + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_multiburst_2_full_bursts(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, test_cases_multiburst_2_full_bursts + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_multiburst_1_full_burst_and_single_transfer(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, test_cases_multiburst_1_full_burst_and_single_transfer + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_multiburst_crossing_4kb_boundary(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, test_cases_multiburst_crossing_4kb_boundary + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_multiburst_crossing_4kb_boundary_with_perfectly_aligned_full_bursts( + dut, +): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, + test_cases_multiburst_crossing_4kb_boundary_with_perfectly_aligned_full_bursts, + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def ram_test_multiburst_crossing_4kb_boundary_with_2_full_bursts_and_1_transfer( + dut, +): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_test_data_arbitrary( + mem_size, + test_cases_multiburst_crossing_4kb_boundary_with_2_full_bursts_and_1_transfer, + ) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=5000, timeout_unit="ms") +async def ram_test_not_full_packets(dut): + mem_size = 2**ADDR_WIDTH + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) = generate_padded_test_data_arbitrary(mem_size, test_cases_not_full_packets) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt, + ) + + +@cocotb.test(timeout_time=5000, timeout_unit="ms") +async def ram_test_random(dut): + mem_size = 2**ADDR_WIDTH + test_count = 50 + + ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt + ) = generate_test_data_random(test_count, mem_size) + await test_writer( + dut, + mem_size, + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + expected_memory, + resp_cnt + ) + +def generate_test_data_random(test_count, mem_size): + write_req_input = [] + data_in_input = [] + write_resp_expect = [] + memory_verification = [] + memory = SparseMemory(mem_size) + + random.seed(1234) + + xfer_baseaddr = 0 + + for _ in range(test_count): + # Generate offset from the absolute address + max_xfer_offset = mem_size - xfer_baseaddr + xfer_offset = random.randrange(0, max_xfer_offset) + xfer_addr = xfer_baseaddr + xfer_offset + # Make sure we don't write beyond available memory + memory_size_max_xfer_len = mem_size - xfer_addr + arbitrary_max_xfer_len = 0x5000 # 20kB + xfer_max_len = min(arbitrary_max_xfer_len, memory_size_max_xfer_len) + xfer_len = random.randrange(1, xfer_max_len) + + write_req = WriteReqStruct( + offset = xfer_offset, + length = xfer_len, + ) + write_req_input.append(write_req) + + data_to_write = random.randbytes(xfer_len) + rem = xfer_len % 4 + for j in list(range(0, xfer_len-3, 4)): + last = ((j + 4) >= xfer_len) & (rem == 0) + data_in = DataInStruct( + data = int.from_bytes(data_to_write[j:j+4], byteorder='little'), + length = 4, + last = last + ) + data_in_input.append(data_in) + if (rem > 0): + data_in = DataInStruct( + data = int.from_bytes(data_to_write[-rem:], byteorder='little'), + length = rem, + last = True + ) + data_in_input.append(data_in) + + + transfer_req = WriteRequestStruct( + address = xfer_addr, + length = xfer_len, + ) + write_expected_memory(transfer_req, data_to_write, memory) + + memory_bundle = { + "base_address": transfer_req.address, + "length": transfer_req.length, + } + memory_verification.append(memory_bundle) + + write_resp_expect = [ + MemWriterRespStruct(status=MemWriterRespStatus.OKAY.value) + ] * test_count + + return ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + memory, + test_count + ) + +def bytes_to_4k_boundary(addr): + axi_4k_boundary = 0x1000 + return axi_4k_boundary - (addr % axi_4k_boundary) + +def write_expected_memory(transfer_req, data_to_write, memory): + """ + Write test data to reference memory keeping the AXI 4kb boundary. + + Split the write requests into smaller ones as needed. + + Args: + transfer_req: The transfer request object containing address and length information. + data_to_write: A bytes-like object or list of data that needs to be written. + memory: SparseMemory object simulating memory storage, where the data will be written. + """ + prev_id = 0 + address = transfer_req.address + length = transfer_req.length + + bytes_in_transfer = 4 + max_axi_burst_bytes = 256 * bytes_in_transfer + + while (length > 0): + bytes_to_4k = bytes_to_4k_boundary(address) + new_len = min(length, min(bytes_to_4k, max_axi_burst_bytes)) + new_data = data_to_write[prev_id:prev_id+new_len] + memory.write(address, new_data) + address = address + new_len + length = length - new_len + prev_id = prev_id + new_len + +def generate_test_data_arbitrary(mem_size, test_cases): + test_count = len(test_cases) + + random.seed(1234) + + write_req_input = [] + data_in_input = [] + write_resp_expect = [] + memory_verification = [] + memory = SparseMemory(mem_size) + + xfer_baseaddr = 0x0 + assert xfer_baseaddr < mem_size + + max_xfer_offset = mem_size - xfer_baseaddr + + for xfer_offset, xfer_len in test_cases: + assert xfer_offset <= max_xfer_offset + xfer_addr = xfer_baseaddr + xfer_offset + # Make sure we don't write beyond available memory + memory_size_max_xfer_len = mem_size - xfer_addr + arbitrary_max_xfer_len = 0x5000 # 20kB + xfer_max_len = min(arbitrary_max_xfer_len, memory_size_max_xfer_len) + assert xfer_len <= xfer_max_len + + write_req = WriteReqStruct( + offset = xfer_offset, + length = xfer_len, + ) + write_req_input.append(write_req) + + data_to_write = random.randbytes(xfer_len) + rem = xfer_len % 4 + for j in list(range(0, xfer_len-3, 4)): + last = ((j + 4) >= xfer_len) & (rem == 0) + data_in = DataInStruct( + data = int.from_bytes(data_to_write[j:j+4], byteorder='little'), + length = 4, + last = last + ) + data_in_input.append(data_in) + if (rem > 0): + data_in = DataInStruct( + data = int.from_bytes(data_to_write[-rem:], byteorder='little'), + length = rem, + last = True + ) + data_in_input.append(data_in) + + + transfer_req = WriteRequestStruct( + address = xfer_addr, + length = xfer_len, + ) + write_expected_memory(transfer_req, data_to_write, memory) + + memory_bundle = { + "base_address": transfer_req.address, + "length": transfer_req.length, + } + memory_verification.append(memory_bundle) + + write_resp_expect = [ + MemWriterRespStruct(status=MemWriterRespStatus.OKAY.value) + ] * test_count + + return ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + memory, + test_count + ) + +def generate_padded_test_data_arbitrary(mem_size, test_cases): + test_count = len(test_cases) + + random.seed(1234) + + write_req_input = [] + data_in_input = [] + write_resp_expect = [] + memory_verification = [] + memory = SparseMemory(mem_size) + + xfer_baseaddr = 0x0 + assert xfer_baseaddr < mem_size + + max_xfer_offset = mem_size - xfer_baseaddr + + for xfer_offset, xfer_len in test_cases: + assert xfer_offset <= max_xfer_offset + xfer_addr = xfer_baseaddr + xfer_offset + # Make sure we don't write beyond available memory + memory_size_max_xfer_len = mem_size - xfer_addr + arbitrary_max_xfer_len = 0x5000 # 20kB + xfer_max_len = min(arbitrary_max_xfer_len, memory_size_max_xfer_len) + assert xfer_len <= xfer_max_len + + write_req = WriteReqStruct( + offset = xfer_offset, + length = xfer_len, + ) + write_req_input.append(write_req) + + data_to_write = random.randbytes(xfer_len) + bytes_to_packetize = xfer_len + packetized_bytes = 0 + while(bytes_to_packetize): + packet_len = random.randint(1, 4) + + if (bytes_to_packetize < packet_len): + packet_len = bytes_to_packetize + + last = packet_len == bytes_to_packetize + + data_in = DataInStruct( + data=int.from_bytes( + data_to_write[packetized_bytes:packetized_bytes+packet_len], + byteorder='little' + ), + length=packet_len, + last=last + ) + data_in_input.append(data_in) + + bytes_to_packetize -= packet_len + packetized_bytes += packet_len + assert xfer_len == packetized_bytes + + + transfer_req = WriteRequestStruct( + address = xfer_addr, + length = xfer_len, + ) + write_expected_memory(transfer_req, data_to_write, memory) + + memory_bundle = { + "base_address": transfer_req.address, + "length": transfer_req.length, + } + memory_verification.append(memory_bundle) + + write_resp_expect = [ + MemWriterRespStruct(status=MemWriterRespStatus.OKAY.value) + ] * test_count + + return ( + write_req_input, + data_in_input, + write_resp_expect, + memory_verification, + memory, + test_count + ) + +if __name__ == "__main__": + sys.path.append(str(pathlib.Path(__file__).parent)) + + toplevel = "mem_writer_wrapper" + verilog_sources = [ + "xls/modules/zstd/memory/mem_writer.v", + "xls/modules/zstd/memory/rtl/mem_writer_wrapper.v", + ] + test_module=[pathlib.Path(__file__).stem] + utils.run_test(toplevel, test_module, verilog_sources) + +test_cases_single_burst_1_transfer = [ + # Aligned Address; Aligned Length + (0x0, 0x4), + # Aligned Address; Unaligned Length + (0x10, 0x1), + (0x24, 0x2), + (0x38, 0x3), + # Unaligned Address; Aligned Length + (0x41, 0x4), + (0x52, 0x4), + (0x63, 0x4), + # Unaligned Address; Unaligned Length + (0x71, 0x1), + (0x81, 0x2), + (0x91, 0x3), + (0xa2, 0x1), + (0xb2, 0x2), + (0xc2, 0x3), + (0xd3, 0x1), + (0xe3, 0x2), + (0xf3, 0x3) +] + +test_cases_single_burst_2_transfers = [ + # Aligned Address; Aligned Length + (0x100, 0x8), + # Aligned Address; Unaligned Length + (0x110, 0x5), + (0x120, 0x6), + (0x130, 0x7), + # Unaligned Address; Aligned Length + (0x141, 0x8), + (0x152, 0x8), + (0x163, 0x8), + # Unaligned Address; Unaligned Length + (0x171, 0x5), + (0x182, 0x5), + (0x193, 0x5), + (0x1A1, 0x6), + (0x1B2, 0x6), + (0x1C3, 0x6), + (0x1D1, 0x7), + (0x1E2, 0x7), + (0x1F3, 0x7) +] + +test_cases_single_burst_almost_max_burst_transfer = [ + # Aligned Address; Aligned Length + (0x200, 0x3FC), + # Aligned Address; Unaligned Length + (0x600, 0x3F9), + (0xA00, 0x3FA), + (0x1000, 0x3FB), + # Unaligned Address; Aligned Length + (0x1401, 0x3FC), + (0x1802, 0x3FC), + (0x2003, 0x3FC), + # Unaligned Address; Unaligned Length + (0x2401, 0x3F9), + (0x2802, 0x3F9), + (0x2C03, 0x3F9), + (0x3001, 0x3FA), + (0x3402, 0x3FA), + (0x3803, 0x3FA), + (0x3C01, 0x3FB), + (0x4002, 0x3FB), + (0x4403, 0x3FB) +] + +test_cases_single_burst_max_burst_transfer = [ + # Aligned Address; Aligned Length + (0x4800, 0x400), + # Aligned Address; Unaligned Length + (0x4C00, 0x3FD), + (0x5000, 0x3FE), + (0x5400, 0x3FF), + # Unaligned Address; Aligned Length + (0x5801, 0x400), + (0x6002, 0x400), + (0x6803, 0x400), + # Unaligned Address; Unaligned Length + (0x7001, 0x3FD), + (0x7802, 0x3FD), + (0x8003, 0x3FD), + (0x8801, 0x3FE), + (0x9002, 0x3FE), + (0x9803, 0x3FE), + (0xA001, 0x3FF), + (0xA802, 0x3FF), + (0xB003, 0x3FF) +] + +test_cases_multiburst_2_full_bursts = [ + # Aligned Address; Aligned Length + (0x0400, 0x800), + # Aligned Address; Unaligned Length + (0x1000, 0x7FD), + (0x1800, 0x7FE), + (0x2000, 0x7FF), + # Unaligned Address; Aligned Length + (0x2801, 0x800), + (0x3002, 0x800), + (0x3803, 0x800), + # Unaligned Address; Unaligned Length + (0x4001, 0x7FD), + (0x5002, 0x7FD), + (0x6003, 0x7FD), + (0x7001, 0x7FE), + (0x8002, 0x7FE), + (0x9003, 0x7FE), + (0xA001, 0x7FF), + (0xB002, 0x7FF), + (0xF003, 0x7FF) +] + +test_cases_multiburst_1_full_burst_and_single_transfer = [ + # Aligned Address; Aligned Length; Multi-Burst + (0x0000, 0x404), + # Aligned Address; Unaligned Length; Multi-Burst + (0x0800, 0x401), + (0x1000, 0x402), + (0x1800, 0x403), + # Unaligned Address; Aligned Length; Multi-Burst + (0x2000, 0x404), + (0x2800, 0x404), + (0x3000, 0x404), + # Unaligned Address; Unaligned Length; Multi-Burst + (0x3801, 0x401), + (0x5002, 0x401), + (0x5803, 0x401), + (0x6001, 0x402), + (0x6802, 0x402), + (0x7003, 0x402), + (0x7801, 0x403), + (0x8002, 0x403), + (0x8803, 0x403) +] + +test_cases_multiburst_crossing_4kb_boundary = [ + # Aligned Address; Aligned Length + (0x0FFC, 0x8), + # Aligned Address; Unaligned Length + (0x1FFC, 0x5), + (0x2FFC, 0x6), + (0x3FFC, 0x7), + # Unaligned Address; Aligned Length + (0x4FFD, 0x8), + (0x5FFE, 0x8), + (0x6FFF, 0x8), + # Unaligned Address; Unaligned Length + (0x7FFD, 0x5), + (0x8FFD, 0x6), + (0x9FFD, 0x7), + (0xAFFE, 0x5), + (0xBFFE, 0x6), + (0xCFFE, 0x7), + (0xDFFF, 0x5), + (0xEFFF, 0x6), + # End of address space - wrap around + (0x0FFF, 0x7), +] + +test_cases_multiburst_crossing_4kb_boundary_with_perfectly_aligned_full_bursts = [ + # Aligned Address; Aligned Length; Multi-Burst; + # crossing 4kB boundary with perfectly aligned full bursts + (0x0C00, 0x800), + # Unaligned Address; Unaligned Length; Multi-Burst; + # crossing 4kB boundary with perfectly aligned full bursts + (0x1C01, 0x7FF), + (0x2C02, 0x7FE), + (0x3C03, 0x7FD), +] + +test_cases_multiburst_crossing_4kb_boundary_with_2_full_bursts_and_1_transfer = [ + # Aligned Address; Aligned Length + (0x0C04, 0x800), + # Aligned Address; Unaligned Length + (0x1C04, 0x801), + (0x2C04, 0x802), + (0x3C04, 0x803), + # Unaligned Address; Aligned Length + (0x4C01, 0x800), + (0x5C02, 0x800), + (0x6C03, 0x800), + # Unaligned Address; Unaligned Length + (0x7C01, 0x801), + (0x8C02, 0x802), + (0x9C03, 0x803), + (0xAC01, 0x802), + (0xBC02, 0x802), + (0xCC03, 0x802), + (0xDC01, 0x803), + (0xEC02, 0x803), + # End of address space - wrap around + (0x0C03, 0x803), +] + +test_cases_not_full_packets = [ + # Aligned Address; Aligned Length + (0x0000, 0x20), + # Aligned Address; Unaligned Length + (0x100, 0x21), + (0x200, 0x22), + (0x300, 0x23), + # Unaligned Address; Aligned Length + (0x401, 0x20), + (0x502, 0x20), + (0x603, 0x20), + # Unaligned Address; Unaligned Length + (0x701, 0x21), + (0x802, 0x22), + (0x903, 0x23), + (0xA01, 0x22), + (0xB02, 0x22), + (0xC03, 0x22), + (0xD01, 0x23), + (0xE02, 0x23), + (0xF03, 0x23), +] diff --git a/xls/modules/zstd/memory/rtl/BUILD b/xls/modules/zstd/memory/rtl/BUILD new file mode 100644 index 0000000000..96029da06d --- /dev/null +++ b/xls/modules/zstd/memory/rtl/BUILD @@ -0,0 +1,39 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Collection of simulation sources + +This package exports verilog sources required by the Memory Writer and Read +in the verilog tests. + +The sources contain: + * Wrapper for the MemReader used in the verilog tests + * Wrapper for the MemWriter used in the verilog tests + * Wrapper for the AxiWriter used in the verilog tests + +""" + +package( + default_applicable_licenses = ["//:license"], + default_visibility = ["//xls:xls_users"], + licenses = ["notice"], +) + +exports_files( + [ + "mem_reader_wrapper.v", + "mem_writer_wrapper.v", + "axi_writer_wrapper.v", + ], +) diff --git a/xls/modules/zstd/memory/rtl/axi_writer_wrapper.v b/xls/modules/zstd/memory/rtl/axi_writer_wrapper.v new file mode 100644 index 0000000000..15788cd41d --- /dev/null +++ b/xls/modules/zstd/memory/rtl/axi_writer_wrapper.v @@ -0,0 +1,122 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This module wraps the AXI Writer verilog sources generated from DSLX to +// form a DUT for verilog tests with consistent IO. + +`default_nettype none + +module axi_writer_wrapper ( + input wire clk, + input wire rst, + + output wire write_resp_data, + output wire write_resp_vld, + input wire write_resp_rdy, + + input wire [31:0] write_req_data, + input wire write_req_vld, + output wire write_req_rdy, + + input wire [31:0] axi_st_read_tdata, + input wire [3:0] axi_st_read_tstr, + input wire [3:0] axi_st_read_tkeep, + input wire [0:0] axi_st_read_tlast, + input wire [3:0] axi_st_read_tid, + input wire [3:0] axi_st_read_tdest, + input wire axi_st_read_tvalid, + output wire axi_st_read_tready, + + output wire [3:0] axi_aw_awid, + output wire [15:0] axi_aw_awaddr, + output wire [2:0] axi_aw_awsize, + output wire [7:0] axi_aw_awlen, + output wire [1:0] axi_aw_awburst, + output wire axi_aw_awvalid, + input wire axi_aw_awready, + + output wire [31:0] axi_w_wdata, + output wire [3:0] axi_w_wstrb, + output wire [0:0] axi_w_wlast, + output wire axi_w_wvalid, + input wire axi_w_wready, + + input wire [2:0] axi_b_bresp, + input wire [3:0] axi_b_bid, + input wire axi_b_bvalid, + output wire axi_b_bready + +); + + wire [32:0] axi_writer__ch_axi_aw_data; + wire [36:0] axi_writer__ch_axi_w_data; + wire [ 6:0] axi_writer__ch_axi_b_data; + + wire [15:0] write_req_data_address; + wire [15:0] write_req_data_length; + + wire [48:0] axi_st_read_data; + + assign {write_req_data_address, write_req_data_length} = write_req_data; + + assign { axi_aw_awid, + axi_aw_awaddr, + axi_aw_awsize, + axi_aw_awlen, + axi_aw_awburst } = axi_writer__ch_axi_aw_data; + + assign {axi_w_wdata, axi_w_wstrb, axi_w_wlast} = axi_writer__ch_axi_w_data; + + assign axi_writer__ch_axi_b_data = {axi_b_bresp, axi_b_bid}; + + assign axi_st_read_data = { + axi_st_read_tdata, + axi_st_read_tstr, + axi_st_read_tkeep, + axi_st_read_tlast, + axi_st_read_tid, + axi_st_read_tdest + }; + + axi_writer axi_writer ( + .clk(clk), + .rst(rst), + + .axi_writer__ch_write_req_data(write_req_data), + .axi_writer__ch_write_req_rdy (write_req_rdy), + .axi_writer__ch_write_req_vld (write_req_vld), + + .axi_writer__ch_write_resp_rdy (write_resp_rdy), + .axi_writer__ch_write_resp_vld (write_resp_vld), + .axi_writer__ch_write_resp_data(write_resp_data), + + .axi_writer__ch_axi_aw_data(axi_writer__ch_axi_aw_data), + .axi_writer__ch_axi_aw_rdy (axi_aw_awready), + .axi_writer__ch_axi_aw_vld (axi_aw_awvalid), + + .axi_writer__ch_axi_w_data(axi_writer__ch_axi_w_data), + .axi_writer__ch_axi_w_rdy (axi_w_wready), + .axi_writer__ch_axi_w_vld (axi_w_wvalid), + + .axi_writer__ch_axi_b_data(axi_writer__ch_axi_b_data), + .axi_writer__ch_axi_b_rdy (axi_b_bready), + .axi_writer__ch_axi_b_vld (axi_b_bvalid), + + .axi_writer__ch_axi_st_read_data(axi_st_read_data), + .axi_writer__ch_axi_st_read_rdy (axi_st_read_tready), + .axi_writer__ch_axi_st_read_vld (axi_st_read_tvalid) + ); + + +endmodule : axi_writer_wrapper diff --git a/xls/modules/zstd/memory/rtl/mem_reader_wrapper.v b/xls/modules/zstd/memory/rtl/mem_reader_wrapper.v new file mode 100644 index 0000000000..12e1fe4478 --- /dev/null +++ b/xls/modules/zstd/memory/rtl/mem_reader_wrapper.v @@ -0,0 +1,114 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This module wraps the Memory Reader verilog sources generated from DSLX to +// form a DUT for verilog tests with consistent IO. + +`default_nettype none + +module mem_reader_wrapper #( + parameter int DSLX_DATA_W = 64, + parameter int DSLX_ADDR_W = 16, + parameter int AXI_DATA_W = 128, + parameter int AXI_ADDR_W = 16, + parameter int AXI_DEST_W = 8, + parameter int AXI_ID_W = 8, + + parameter int CTRL_W = (DSLX_ADDR_W), + parameter int REQ_W = (2 * DSLX_ADDR_W), + parameter int RESP_W = (1 + DSLX_DATA_W + DSLX_ADDR_W + 1), + parameter int AXI_AR_W = (AXI_ID_W + AXI_ADDR_W + 28), + parameter int AXI_R_W = (AXI_ID_W + AXI_DATA_W + 4) +) ( + input wire clk, + input wire rst, + + output wire req_rdy, + input wire req_vld, + input wire [REQ_W-1:0] req_data, + + output wire resp_vld, + input wire resp_rdy, + output wire [RESP_W-1:0] resp_data, + + output wire axi_ar_arvalid, + input wire axi_ar_arready, + output wire [ AXI_ID_W-1:0] axi_ar_arid, + output wire [AXI_ADDR_W-1:0] axi_ar_araddr, + output wire [ 3:0] axi_ar_arregion, + output wire [ 7:0] axi_ar_arlen, + output wire [ 2:0] axi_ar_arsize, + output wire [ 1:0] axi_ar_arburst, + output wire [ 3:0] axi_ar_arcache, + output wire [ 2:0] axi_ar_arprot, + output wire [ 3:0] axi_ar_arqos, + + input wire axi_r_rvalid, + output wire axi_r_rready, + input wire [ AXI_ID_W-1:0] axi_r_rid, + input wire [AXI_DATA_W-1:0] axi_r_rdata, + input wire [ 2:0] axi_r_rresp, + input wire axi_r_rlast +); + + wire [AXI_AR_W-1:0] axi_ar_data; + wire axi_ar_rdy; + wire axi_ar_vld; + + assign axi_ar_rdy = axi_ar_arready; + + assign axi_ar_arvalid = axi_ar_vld; + assign { + axi_ar_arid, + axi_ar_araddr, + axi_ar_arregion, + axi_ar_arlen, + axi_ar_arsize, + axi_ar_arburst, + axi_ar_arcache, + axi_ar_arprot, + axi_ar_arqos +} = axi_ar_data; + + wire [AXI_R_W-1:0] axi_r_data; + wire axi_r_vld; + wire axi_r_rdy; + + assign axi_r_data = {axi_r_rid, axi_r_rdata, axi_r_rresp, axi_r_rlast}; + assign axi_r_vld = axi_r_rvalid; + + assign axi_r_rready = axi_r_rdy; + + mem_reader_adv mem_reader_adv ( + .clk(clk), + .rst(rst), + + .mem_reader__req_r_data(req_data), + .mem_reader__req_r_rdy (req_rdy), + .mem_reader__req_r_vld (req_vld), + + .mem_reader__resp_s_data(resp_data), + .mem_reader__resp_s_rdy (resp_rdy), + .mem_reader__resp_s_vld (resp_vld), + + .mem_reader__axi_ar_s_data(axi_ar_data), + .mem_reader__axi_ar_s_rdy (axi_ar_rdy), + .mem_reader__axi_ar_s_vld (axi_ar_vld), + + .mem_reader__axi_r_r_data(axi_r_data), + .mem_reader__axi_r_r_vld (axi_r_vld), + .mem_reader__axi_r_r_rdy (axi_r_rdy) + ); + +endmodule diff --git a/xls/modules/zstd/memory/rtl/mem_writer_wrapper.v b/xls/modules/zstd/memory/rtl/mem_writer_wrapper.v new file mode 100644 index 0000000000..6b53dbd805 --- /dev/null +++ b/xls/modules/zstd/memory/rtl/mem_writer_wrapper.v @@ -0,0 +1,226 @@ +// Copyright 2024 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This module wraps the Memory Writer verilog sources generated from DSLX to +// form a DUT for verilog tests with consistent IO. + +`default_nettype none + +module mem_writer_wrapper ( + input wire clk, + input wire rst, + + input wire [31:0] req_data, + input wire req_vld, + output wire req_rdy, + + input wire [48:0] data_in_data, + input wire data_in_vld, + output wire data_in_rdy, + + output wire resp_data, + output wire resp_vld, + input wire resp_rdy, + + output wire [3:0] axi_aw_awid, + output wire [15:0] axi_aw_awaddr, + output wire [2:0] axi_aw_awsize, + output wire [7:0] axi_aw_awlen, + output wire [1:0] axi_aw_awburst, + output wire axi_aw_awvalid, + input wire axi_aw_awready, + + output wire [31:0] axi_w_wdata, + output wire [3:0] axi_w_wstrb, + output wire [0:0] axi_w_wlast, + output wire axi_w_wvalid, + input wire axi_w_wready, + + input wire [2:0] axi_b_bresp, + input wire [3:0] axi_b_bid, + input wire axi_b_bvalid, + output wire axi_b_bready +); + + wire [15:0] req_f_addr; + wire [15:0] req_f_length; + + wire [31:0] data_in_f_data; + wire [15:0] data_in_f_length; + wire [0:0] data_in_f_last; + + wire [36:0] axi_w_data; + wire axi_w_vld; + wire axi_w_rdy; + + wire [32:0] axi_aw_data; + wire axi_aw_vld; + wire axi_aw_rdy; + + wire [6:0] axi_b_data; + wire axi_b_rdy; + wire axi_b_vld; + + assign {req_f_addr, req_f_length} = req_data; + + assign {data_in_f_data, data_in_f_length, data_in_f_last} = data_in_data; + + assign {axi_aw_awid, axi_aw_awaddr, axi_aw_awsize, axi_aw_awlen, axi_aw_awburst} = axi_aw_data; + assign axi_aw_awvalid = axi_aw_vld; + assign axi_aw_rdy = axi_aw_awready; + + assign {axi_w_wdata, axi_w_wstrb, axi_w_wlast} = axi_w_data; + assign axi_w_wvalid = axi_w_vld; + assign axi_w_rdy = axi_w_wready; + + assign axi_b_data = {axi_b_bresp, axi_b_bid}; + assign axi_b_vld = axi_b_bvalid; + assign axi_b_bready = axi_b_rdy; + + wire [15:0] axi_writer_write_req_address; + wire [15:0] axi_writer_write_req_length; + wire [ 0:0] axi_writer_write_req_valid; + wire [ 0:0] axi_writer_write_req_ready; + + wire [15:0] padding_write_req_address; + wire [15:0] padding_write_req_length; + wire [ 0:0] padding_write_req_valid; + wire [ 0:0] padding_write_req_ready; + + wire [31:0] axi_stream_raw_tdata; + wire [ 3:0] axi_stream_raw_tstr; + wire [ 3:0] axi_stream_raw_tkeep; + wire [ 0:0] axi_stream_raw_tlast; + wire [ 3:0] axi_stream_raw_tid; + wire [ 3:0] axi_stream_raw_tdest; + wire [ 0:0] axi_stream_raw_tvalid; + wire [ 0:0] axi_stream_raw_tready; + + wire [31:0] axi_stream_clean_tdata; + wire [ 3:0] axi_stream_clean_tstr; + wire [ 3:0] axi_stream_clean_tkeep; + wire [ 0:0] axi_stream_clean_tlast; + wire [ 3:0] axi_stream_clean_tid; + wire [ 3:0] axi_stream_clean_tdest; + wire [ 0:0] axi_stream_clean_tvalid; + wire [ 0:0] axi_stream_clean_tready; + + wire [31:0] axi_stream_padded_tdata; + wire [ 3:0] axi_stream_padded_tstr; + wire [ 3:0] axi_stream_padded_tkeep; + wire [ 0:0] axi_stream_padded_tlast; + wire [ 3:0] axi_stream_padded_tid; + wire [ 3:0] axi_stream_padded_tdest; + wire [ 0:0] axi_stream_padded_tvalid; + wire [ 0:0] axi_stream_padded_tready; + + assign {axi_writer_write_req_address, axi_writer_write_req_length} = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__axi_writer_req_data; + assign axi_writer_write_req_valid = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__axi_writer_req_vld; + assign axi_writer_write_req_ready = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__axi_writer_req_rdy; + + assign {padding_write_req_address, padding_write_req_length} = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__padding_req_data; + assign padding_write_req_valid = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__padding_req_vld; + assign padding_write_req_ready = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__padding_req_rdy; + + assign { axi_stream_raw_tdata, + axi_stream_raw_tstr, + axi_stream_raw_tkeep, + axi_stream_raw_tid, + axi_stream_raw_tdest, + axi_stream_raw_tlast} = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__axi_st_raw_data; + assign axi_stream_raw_tvalid = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__axi_st_raw_vld; + assign axi_stream_raw_tready = mem_writer + .__mem_writer__MemWriterInst__MemWriter_0__MemWriterInternal_0__16_32_4_4_4_2_next_inst0 + .mem_writer__axi_st_raw_rdy; + + assign { axi_stream_clean_tdata, + axi_stream_clean_tstr, + axi_stream_clean_tkeep, + axi_stream_clean_tid, + axi_stream_clean_tdest, + axi_stream_clean_tlast} = mem_writer + .__xls_modules_zstd_memory_axi_stream_add_empty__MemWriterInst__MemWriter_0__AxiStreamAddEmpty_0__16_32_4_2_4_4_next_inst1 // verilog_lint: waive line-length + .mem_writer__axi_st_clean_data; + assign axi_stream_clean_tvalid = mem_writer + .__xls_modules_zstd_memory_axi_stream_add_empty__MemWriterInst__MemWriter_0__AxiStreamAddEmpty_0__16_32_4_2_4_4_next_inst1 // verilog_lint: waive line-length + .mem_writer__axi_st_clean_vld; + assign axi_stream_clean_tready = mem_writer + .__xls_modules_zstd_memory_axi_stream_add_empty__MemWriterInst__MemWriter_0__AxiStreamAddEmpty_0__16_32_4_2_4_4_next_inst1 // verilog_lint: waive line-length + .mem_writer__axi_st_clean_rdy; + + assign { axi_stream_padded_tdata, + axi_stream_padded_tstr, + axi_stream_padded_tkeep, + axi_stream_padded_tid, + axi_stream_padded_tdest, + axi_stream_padded_tlast} = mem_writer + .__xls_modules_zstd_memory_axi_writer__MemWriterInst__MemWriter_0__AxiWriter_0__16_32_4_4_4_2_next_inst4 // verilog_lint: waive line-length + .mem_writer__axi_st_padded_data; + assign axi_stream_padded_tvalid = mem_writer + .__xls_modules_zstd_memory_axi_writer__MemWriterInst__MemWriter_0__AxiWriter_0__16_32_4_4_4_2_next_inst4 // verilog_lint: waive line-length + .mem_writer__axi_st_padded_vld; + assign axi_stream_padded_tready = mem_writer + .__xls_modules_zstd_memory_axi_writer__MemWriterInst__MemWriter_0__AxiWriter_0__16_32_4_4_4_2_next_inst4 // verilog_lint: waive line-length + .mem_writer__axi_st_padded_rdy; + + mem_writer mem_writer ( + .clk(clk), + .rst(rst), + + // MemWriter Write Request + .mem_writer__req_in_r_data(req_data), + .mem_writer__req_in_r_vld (req_vld), + .mem_writer__req_in_r_rdy (req_rdy), + + // Data to write + .mem_writer__data_in_r_data(data_in_data), + .mem_writer__data_in_r_vld (data_in_vld), + .mem_writer__data_in_r_rdy (data_in_rdy), + + // Response channel + .mem_writer__resp_s_data(resp_data), + .mem_writer__resp_s_rdy (resp_rdy), + .mem_writer__resp_s_vld (resp_vld), + + // Memory AXI + .mem_writer__axi_w_s_data(axi_w_data), + .mem_writer__axi_w_s_vld (axi_w_vld), + .mem_writer__axi_w_s_rdy (axi_w_rdy), + + .mem_writer__axi_aw_s_data(axi_aw_data), + .mem_writer__axi_aw_s_vld (axi_aw_vld), + .mem_writer__axi_aw_s_rdy (axi_aw_rdy), + + .mem_writer__axi_b_r_data(axi_b_data), + .mem_writer__axi_b_r_vld (axi_b_vld), + .mem_writer__axi_b_r_rdy (axi_b_rdy) + ); + +endmodule : mem_writer_wrapper diff --git a/xls/modules/zstd/ram_demux_cocotb_test.py b/xls/modules/zstd/ram_demux_cocotb_test.py new file mode 100644 index 0000000000..5e75c6abce --- /dev/null +++ b/xls/modules/zstd/ram_demux_cocotb_test.py @@ -0,0 +1,173 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +import pathlib +import random +import sys +import warnings + +import cocotb +from cocotb.binary import BinaryValue +from cocotb.clock import Clock +from cocotb.triggers import Event, ClockCycles, RisingEdge +from cocotb_bus.scoreboard import Scoreboard +from cocotbext.axi import axi_channels +from cocotbext.axi.axi_ram import AxiRamRead +from cocotbext.axi.sparse_memory import SparseMemory + +import xls.modules.zstd.cocotb.channel as xlschannel +from xls.modules.zstd.cocotb import utils +from xls.modules.zstd.cocotb import xlsstruct + +warnings.filterwarnings("ignore", category=DeprecationWarning) + +ADDR_W = 10 +DATA_W = 64 +NUM_PARTITIONS = 64 +SEL_W = 1 + + +@xlsstruct.xls_dataclass +class SelReq(xlsstruct.XLSStruct): + sel: SEL_W + + +@xlsstruct.xls_dataclass +class ReadReq(xlsstruct.XLSStruct): + addr: ADDR_W + mask: NUM_PARTITIONS + + +@xlsstruct.xls_dataclass +class ReadResp(xlsstruct.XLSStruct): + data: DATA_W + + +@xlsstruct.xls_dataclass +class WriteReq(xlsstruct.XLSStruct): + addr: ADDR_W + data: DATA_W + mask: NUM_PARTITIONS + + +@xlsstruct.xls_dataclass +class WriteResp(xlsstruct.XLSStruct): + pass + + +def print_callback(name: str = "monitor"): + def _print_callback(transaction): + print(f" [{name}]: {transaction}") + + return _print_callback + + +def set_termination_event(monitor, event, transactions): + def terminate_cb(_): + if monitor.stats.received_transactions == transactions: + print("all transactions received") + event.set() + + monitor.add_callback(terminate_cb) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def test_mem_reader(dut): + + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + sel_resp_channel = xlschannel.XLSChannel(dut, "ram_demux__sel_resp_s", dut.clk) + rd_resp_channel = xlschannel.XLSChannel(dut, "ram_demux__rd_resp_s", dut.clk) + wr_resp_channel = xlschannel.XLSChannel( + dut, "ram_demux__wr_resp_s", dut.clk, start_now=True + ) + + sel_driver = xlschannel.XLSChannelDriver(dut, "ram_demux__sel_req_r", dut.clk) + rd_req_driver = xlschannel.XLSChannelDriver(dut, "ram_demux__rd_req_r", dut.clk) + wr_req_driver = xlschannel.XLSChannelDriver(dut, "ram_demux__wr_req_r", dut.clk) + + dut.rst.setimmediatevalue(0) + await ClockCycles(dut.clk, 10) + dut.rst.setimmediatevalue(1) + await ClockCycles(dut.clk, 10) + dut.rst.setimmediatevalue(0) + + sel_resp_channel.rdy.setimmediatevalue(1) + rd_resp_channel.rdy.setimmediatevalue(1) + wr_resp_channel.rdy.setimmediatevalue(1) + + await sel_driver.send(SelReq(0)) + while True: + await RisingEdge(dut.clk) + if sel_resp_channel.rdy.value and sel_resp_channel.vld.value: + break + + await wr_req_driver.send(WriteReq(addr=123, data=0x10, mask=0xFFFF_FFFF_FFFF_FFFF)) + while True: + await RisingEdge(dut.clk) + if wr_resp_channel.rdy.value and wr_resp_channel.vld.value: + break + + await sel_driver.send(SelReq(1)) + while True: + await RisingEdge(dut.clk) + if sel_resp_channel.rdy.value and sel_resp_channel.vld.value: + break + + await wr_req_driver.send(WriteReq(addr=256, data=0x3, mask=0xFFFF_FFFF_FFFF_FFFF)) + while True: + await RisingEdge(dut.clk) + if wr_resp_channel.rdy.value and wr_resp_channel.vld.value: + break + + await sel_driver.send(SelReq(0)) + while True: + await RisingEdge(dut.clk) + if sel_resp_channel.rdy.value and sel_resp_channel.vld.value: + break + + await rd_req_driver.send(ReadReq(addr=123, mask=0xFFFF_FFFF_FFFF_FFFF)) + while True: + await RisingEdge(dut.clk) + if rd_resp_channel.rdy.value and rd_resp_channel.vld.value: + assert rd_resp_channel.data.value == 0x10 + break + + await sel_driver.send(SelReq(1)) + while True: + await RisingEdge(dut.clk) + if sel_resp_channel.rdy.value and sel_resp_channel.vld.value: + break + + await rd_req_driver.send(ReadReq(addr=256, mask=0xFFFF_FFFF_FFFF_FFFF)) + while True: + await RisingEdge(dut.clk) + if rd_resp_channel.rdy.value and rd_resp_channel.vld.value: + assert rd_resp_channel.data.value == 0x3 + break + + +if __name__ == "__main__": + sys.path.append(str(pathlib.Path(__file__).parent)) + + toplevel = "ram_demux_wrapper" + verilog_sources = [ + "xls/modules/zstd/ram_demux.v", + "xls/modules/zstd/rtl/ram_1r1w.v", + "xls/modules/zstd/rtl/ram_demux_wrapper.v", + ] + test_module = [pathlib.Path(__file__).stem] + utils.run_test(toplevel, test_module, verilog_sources) diff --git a/xls/modules/zstd/rtl/BUILD b/xls/modules/zstd/rtl/BUILD index 4447877821..1a6c5f1592 100644 --- a/xls/modules/zstd/rtl/BUILD +++ b/xls/modules/zstd/rtl/BUILD @@ -23,6 +23,7 @@ The sources contain: """ +# pytype binary, library load("@rules_hdl//verilog:providers.bzl", "verilog_library") package( @@ -35,6 +36,8 @@ exports_files( [ "zstd_dec_wrapper.sv", "xls_fifo_wrapper.sv", + "ram_demux_wrapper.v", + "ram_1r1w.v", ], ) diff --git a/xls/modules/zstd/rtl/ram_1r1w.v b/xls/modules/zstd/rtl/ram_1r1w.v new file mode 100644 index 0000000000..cbcbfe55f6 --- /dev/null +++ b/xls/modules/zstd/rtl/ram_1r1w.v @@ -0,0 +1,88 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module ram_1r1w # ( + parameter DATA_WIDTH = 4, + parameter SIZE = 32, + parameter NUM_PARTITIONS = 1, + parameter ADDR_WIDTH = $clog(SIZE), + parameter INIT_FILE = "" +) ( + input wire clk, + input wire rst, + + input wire [ DATA_WIDTH -1:0 ] wr_data, + input wire [ ADDR_WIDTH -1:0 ] wr_addr, + input wire wr_en, + input wire [ NUM_PARTITIONS -1:0 ] wr_mask, + + output reg [ DATA_WIDTH -1:0 ] rd_data, + input wire [ ADDR_WIDTH -1:0 ] rd_addr, + input wire rd_en, + input wire [ NUM_PARTITIONS -1:0 ] rd_mask +); + +localparam PARTITION_WIDTH = (DATA_WIDTH / NUM_PARTITIONS); + +reg [DATA_WIDTH-1:0] mem [SIZE]; + +integer i; + +always @(rst) begin + if (INIT_FILE != "") begin + $readmemh(INIT_FILE, mem); + end + else begin + for (i = 0; i < SIZE; i++) begin + mem[i] <= {DATA_WIDTH{1'b0}}; + end + end +end + +reg [DATA_WIDTH-1:0] wr_exp_mask; +reg [DATA_WIDTH-1:0] rd_exp_mask; + +genvar j; +generate +for (j = 0; j < NUM_PARTITIONS; j = j + 1) begin + always @(*) begin + if (wr_mask[j]) begin + wr_exp_mask[((j+1)*PARTITION_WIDTH)-1 : j*PARTITION_WIDTH] <= {PARTITION_WIDTH{1'b1}}; + end else begin + wr_exp_mask[((j+1)*PARTITION_WIDTH)-1 : j*PARTITION_WIDTH] <= {PARTITION_WIDTH{1'b0}}; + end + + if (rd_mask[j]) begin + rd_exp_mask[((j+1)*PARTITION_WIDTH)-1:j*PARTITION_WIDTH] <= {PARTITION_WIDTH{1'b1}}; + end else begin + rd_exp_mask[((j+1)*PARTITION_WIDTH)-1:j*PARTITION_WIDTH] <= {PARTITION_WIDTH{1'b0}}; + end + end +end +endgenerate + +wire [DATA_WIDTH-1:0] rd_data_masked; +wire [DATA_WIDTH-1:0] wr_data_masked; + +assign rd_data_masked = mem[rd_addr] & rd_exp_mask; +assign wr_data_masked = (mem[wr_addr] & ~wr_exp_mask) | (wr_data & wr_exp_mask); + +always @(posedge clk) begin + if (rd_en) begin + rd_data <= rd_data_masked; + end else if (wr_en) begin + mem[wr_addr] <= wr_data_masked; + end +end +endmodule diff --git a/xls/modules/zstd/rtl/ram_demux_wrapper.v b/xls/modules/zstd/rtl/ram_demux_wrapper.v new file mode 100644 index 0000000000..973b0b18a4 --- /dev/null +++ b/xls/modules/zstd/rtl/ram_demux_wrapper.v @@ -0,0 +1,155 @@ +// Copyright 2025 The XLS Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module ram_demux_wrapper #( + parameter DATA_WIDTH = 64, + parameter SIZE = 1024, + parameter ADDR_WIDTH = $clog2(SIZE), + parameter NUM_PARTITIONS = 64 +) ( + input wire clk, + input wire rst, + + input wire ram_demux__sel_req_r_data, + input wire ram_demux__sel_req_r_vld, + output wire ram_demux__sel_req_r_rdy, + + input wire ram_demux__sel_resp_s_rdy, + output wire ram_demux__sel_resp_s_vld, + + input wire [ NUM_PARTITIONS + ADDR_WIDTH - 1:0 ] ram_demux__rd_req_r_data, + input wire ram_demux__rd_req_r_vld, + output wire ram_demux__rd_req_r_rdy, + + output wire [ DATA_WIDTH -1:0 ] ram_demux__rd_resp_s_data, + output wire ram_demux__rd_resp_s_vld, + input wire ram_demux__rd_resp_s_rdy, + + input wire [ DATA_WIDTH + NUM_PARTITIONS + ADDR_WIDTH -1:0 ] ram_demux__wr_req_r_data, + input wire ram_demux__wr_req_r_vld, + output wire ram_demux__wr_req_r_rdy, + + input wire ram_demux__wr_resp_s_rdy, + output wire ram_demux__wr_resp_s_vld +); + +wire [ DATA_WIDTH -1:0 ] ram0_wr_data; +wire [ ADDR_WIDTH -1:0 ] ram0_wr_addr; +wire ram0_wr_en; +wire [ NUM_PARTITIONS -1:0 ] ram0_wr_mask; + +wire [ DATA_WIDTH -1:0 ] ram0_rd_data; +wire [ ADDR_WIDTH -1:0 ] ram0_rd_addr; +wire ram0_rd_en; +wire [ NUM_PARTITIONS -1:0 ] ram0_rd_mask; + +ram_1r1w # ( + .DATA_WIDTH(DATA_WIDTH), + .SIZE(SIZE), + .NUM_PARTITIONS(NUM_PARTITIONS), + .ADDR_WIDTH(ADDR_WIDTH) +) ram0 ( + .clk (clk), + .rst (rst), + + .wr_data (ram0_wr_data), + .wr_addr (ram0_wr_addr), + .wr_en (ram0_wr_en), + .wr_mask (ram0_wr_mask), + + .rd_data (ram0_rd_data), + .rd_addr (ram0_rd_addr), + .rd_en (ram0_rd_en), + .rd_mask (ram0_rd_mask) +); + +wire [ DATA_WIDTH -1:0 ] ram1_wr_data; +wire [ ADDR_WIDTH -1:0 ] ram1_wr_addr; +wire ram1_wr_en; +wire [ NUM_PARTITIONS -1:0 ] ram1_wr_mask; + +wire [ DATA_WIDTH -1:0 ] ram1_rd_data; +wire [ ADDR_WIDTH -1:0 ] ram1_rd_addr; +wire ram1_rd_en; +wire [ NUM_PARTITIONS -1:0 ] ram1_rd_mask; + + +ram_1r1w # ( + .DATA_WIDTH(DATA_WIDTH), + .SIZE(SIZE), + .NUM_PARTITIONS(NUM_PARTITIONS), + .ADDR_WIDTH(ADDR_WIDTH) +) ram1 ( + .clk (clk), + .rst (rst), + + .wr_data (ram1_wr_data), + .wr_addr (ram1_wr_addr), + .wr_en (ram1_wr_en), + .wr_mask (ram1_wr_mask), + + .rd_data (ram1_rd_data), + .rd_addr (ram1_rd_addr), + .rd_en (ram1_rd_en), + .rd_mask (ram1_rd_mask) +); + +RamDemux demux ( + .clk(clk), + .rst(rst), + + .ram_demux__rd_req_r_data(ram_demux__rd_req_r_data), + .ram_demux__rd_req_r_vld(ram_demux__rd_req_r_vld), + .ram_demux__rd_req_r_rdy(ram_demux__rd_req_r_rdy), + + .ram_demux__sel_req_r_data(ram_demux__sel_req_r_data), + .ram_demux__sel_req_r_rdy(ram_demux__sel_req_r_rdy), + .ram_demux__sel_req_r_vld(ram_demux__sel_req_r_vld), + + .ram_demux__sel_resp_s_rdy(ram_demux__sel_resp_s_rdy), + .ram_demux__sel_resp_s_vld(ram_demux__sel_resp_s_vld), + + .ram_demux__wr_req_r_vld(ram_demux__wr_req_r_vld), + .ram_demux__wr_req_r_rdy(ram_demux__wr_req_r_rdy), + .ram_demux__wr_req_r_data(ram_demux__wr_req_r_data), + + .ram_demux__wr_resp_s_rdy(ram_demux__wr_resp_s_rdy), + .ram_demux__wr_resp_s_vld(ram_demux__wr_resp_s_vld), + + .ram_demux__rd_resp_s_rdy(ram_demux__rd_resp_s_rdy), + .ram_demux__rd_resp_s_data(ram_demux__rd_resp_s_data), + .ram_demux__rd_resp_s_vld(ram_demux__rd_resp_s_vld), + + .ram0_rd_data (ram0_rd_data), + .ram0_rd_addr (ram0_rd_addr), + .ram0_rd_mask (ram0_rd_mask), + .ram0_rd_en (ram0_rd_en), + + .ram0_wr_addr (ram0_wr_addr), + .ram0_wr_data (ram0_wr_data), + .ram0_wr_mask (ram0_wr_mask), + .ram0_wr_en (ram0_wr_en), + + .ram1_rd_data (ram1_rd_data), + .ram1_rd_addr (ram1_rd_addr), + .ram1_rd_mask (ram1_rd_mask), + .ram1_rd_en (ram1_rd_en), + + .ram1_wr_addr (ram1_wr_addr), + .ram1_wr_data (ram1_wr_data), + .ram1_wr_mask (ram1_wr_mask), + .ram1_wr_en (ram1_wr_en) +); + +endmodule diff --git a/xls/modules/zstd/rtl/zstd_dec_wrapper.sv b/xls/modules/zstd/rtl/zstd_dec_wrapper.sv index 8a616f3f23..79a6199810 100644 --- a/xls/modules/zstd/rtl/zstd_dec_wrapper.sv +++ b/xls/modules/zstd/rtl/zstd_dec_wrapper.sv @@ -22,9 +22,9 @@ module zstd_dec_wrapper #( parameter int AXI_DATA_W = 64, - parameter int AXI_ADDR_W = 16, + parameter int AXI_ADDR_W = 32, parameter int S_AXI_ID_W = 4, - parameter int M_AXI_ID_W = 6, + parameter int M_AXI_ID_W = 8, parameter int AXI_STRB_W = 8, parameter int AWUSER_WIDTH = 1, parameter int WUSER_WIDTH = 1, @@ -426,68 +426,1854 @@ module zstd_dec_wrapper #( assign csr_axi_r_ruser = 1'b0; assign notify_data = notify_vld; + // Axi Subordinate Interface for axi_ram_s__0 + wire axi_ram_s__0_axi_ar_arvalid; + wire axi_ram_s__0_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__0_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__0_axi_ar_araddr; + wire [ 3:0] axi_ram_s__0_axi_ar_arregion; + wire [ 7:0] axi_ram_s__0_axi_ar_arlen; + wire [ 2:0] axi_ram_s__0_axi_ar_arsize; + wire [ 1:0] axi_ram_s__0_axi_ar_arburst; + wire [ 3:0] axi_ram_s__0_axi_ar_arcache; + wire [ 2:0] axi_ram_s__0_axi_ar_arprot; + wire [ 3:0] axi_ram_s__0_axi_ar_arqos; + + wire axi_ram_s__0_axi_r_rvalid; + wire axi_ram_s__0_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__0_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__0_axi_r_rdata; + wire [ 2:0] axi_ram_s__0_axi_r_rresp; + wire axi_ram_s__0_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__0; + wire zstd_dec__axi_ram_ar_s__0_rdy; + wire zstd_dec__axi_ram_ar_s__0_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__0; + wire zstd_dec__axi_ram_r_r__0_rdy; + wire zstd_dec__axi_ram_r_r__0_vld; + + assign { + axi_ram_s__0_axi_ar_arid, + axi_ram_s__0_axi_ar_araddr, + axi_ram_s__0_axi_ar_arregion, + axi_ram_s__0_axi_ar_arlen, + axi_ram_s__0_axi_ar_arsize, + axi_ram_s__0_axi_ar_arburst, + axi_ram_s__0_axi_ar_arcache, + axi_ram_s__0_axi_ar_arprot, + axi_ram_s__0_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__0; + assign axi_ram_s__0_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__0_vld; + assign zstd_dec__axi_ram_ar_s__0_rdy = axi_ram_s__0_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__0 = { + axi_ram_s__0_axi_r_rid, + axi_ram_s__0_axi_r_rdata, + axi_ram_s__0_axi_r_rresp, + axi_ram_s__0_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__0_vld = axi_ram_s__0_axi_r_rvalid; + assign axi_ram_s__0_axi_r_rready = zstd_dec__axi_ram_r_r__0_rdy; + assign axi_ram_s__0_axi_r_rresp[2] = '0; + + // Axi Subordinate Interface for axi_ram_s__1 + wire axi_ram_s__1_axi_ar_arvalid; + wire axi_ram_s__1_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__1_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__1_axi_ar_araddr; + wire [ 3:0] axi_ram_s__1_axi_ar_arregion; + wire [ 7:0] axi_ram_s__1_axi_ar_arlen; + wire [ 2:0] axi_ram_s__1_axi_ar_arsize; + wire [ 1:0] axi_ram_s__1_axi_ar_arburst; + wire [ 3:0] axi_ram_s__1_axi_ar_arcache; + wire [ 2:0] axi_ram_s__1_axi_ar_arprot; + wire [ 3:0] axi_ram_s__1_axi_ar_arqos; + + wire axi_ram_s__1_axi_r_rvalid; + wire axi_ram_s__1_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__1_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__1_axi_r_rdata; + wire [ 2:0] axi_ram_s__1_axi_r_rresp; + wire axi_ram_s__1_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__1; + wire zstd_dec__axi_ram_ar_s__1_rdy; + wire zstd_dec__axi_ram_ar_s__1_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__1; + wire zstd_dec__axi_ram_r_r__1_rdy; + wire zstd_dec__axi_ram_r_r__1_vld; + + assign { + axi_ram_s__1_axi_ar_arid, + axi_ram_s__1_axi_ar_araddr, + axi_ram_s__1_axi_ar_arregion, + axi_ram_s__1_axi_ar_arlen, + axi_ram_s__1_axi_ar_arsize, + axi_ram_s__1_axi_ar_arburst, + axi_ram_s__1_axi_ar_arcache, + axi_ram_s__1_axi_ar_arprot, + axi_ram_s__1_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__1; + assign axi_ram_s__1_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__1_vld; + assign zstd_dec__axi_ram_ar_s__1_rdy = axi_ram_s__1_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__1 = { + axi_ram_s__1_axi_r_rid, + axi_ram_s__1_axi_r_rdata, + axi_ram_s__1_axi_r_rresp, + axi_ram_s__1_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__1_vld = axi_ram_s__1_axi_r_rvalid; + assign axi_ram_s__1_axi_r_rready = zstd_dec__axi_ram_r_r__1_rdy; + assign axi_ram_s__1_axi_r_rresp[2] = '0; + + + // Axi Subordinate Interface for axi_ram_s__2 + wire axi_ram_s__2_axi_ar_arvalid; + wire axi_ram_s__2_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__2_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__2_axi_ar_araddr; + wire [ 3:0] axi_ram_s__2_axi_ar_arregion; + wire [ 7:0] axi_ram_s__2_axi_ar_arlen; + wire [ 2:0] axi_ram_s__2_axi_ar_arsize; + wire [ 1:0] axi_ram_s__2_axi_ar_arburst; + wire [ 3:0] axi_ram_s__2_axi_ar_arcache; + wire [ 2:0] axi_ram_s__2_axi_ar_arprot; + wire [ 3:0] axi_ram_s__2_axi_ar_arqos; + + wire axi_ram_s__2_axi_r_rvalid; + wire axi_ram_s__2_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__2_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__2_axi_r_rdata; + wire [ 2:0] axi_ram_s__2_axi_r_rresp; + wire axi_ram_s__2_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__2; + wire zstd_dec__axi_ram_ar_s__2_rdy; + wire zstd_dec__axi_ram_ar_s__2_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__2; + wire zstd_dec__axi_ram_r_r__2_rdy; + wire zstd_dec__axi_ram_r_r__2_vld; + + assign { + axi_ram_s__2_axi_ar_arid, + axi_ram_s__2_axi_ar_araddr, + axi_ram_s__2_axi_ar_arregion, + axi_ram_s__2_axi_ar_arlen, + axi_ram_s__2_axi_ar_arsize, + axi_ram_s__2_axi_ar_arburst, + axi_ram_s__2_axi_ar_arcache, + axi_ram_s__2_axi_ar_arprot, + axi_ram_s__2_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__2; + assign axi_ram_s__2_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__2_vld; + assign zstd_dec__axi_ram_ar_s__2_rdy = axi_ram_s__2_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__2 = { + axi_ram_s__2_axi_r_rid, + axi_ram_s__2_axi_r_rdata, + axi_ram_s__2_axi_r_rresp, + axi_ram_s__2_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__2_vld = axi_ram_s__2_axi_r_rvalid; + assign axi_ram_s__2_axi_r_rready = zstd_dec__axi_ram_r_r__2_rdy; + assign axi_ram_s__2_axi_r_rresp[2] = '0; + + + // Axi Subordinate Interface for axi_ram_s__3 + wire axi_ram_s__3_axi_ar_arvalid; + wire axi_ram_s__3_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__3_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__3_axi_ar_araddr; + wire [ 3:0] axi_ram_s__3_axi_ar_arregion; + wire [ 7:0] axi_ram_s__3_axi_ar_arlen; + wire [ 2:0] axi_ram_s__3_axi_ar_arsize; + wire [ 1:0] axi_ram_s__3_axi_ar_arburst; + wire [ 3:0] axi_ram_s__3_axi_ar_arcache; + wire [ 2:0] axi_ram_s__3_axi_ar_arprot; + wire [ 3:0] axi_ram_s__3_axi_ar_arqos; + + wire axi_ram_s__3_axi_r_rvalid; + wire axi_ram_s__3_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__3_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__3_axi_r_rdata; + wire [ 2:0] axi_ram_s__3_axi_r_rresp; + wire axi_ram_s__3_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__3; + wire zstd_dec__axi_ram_ar_s__3_rdy; + wire zstd_dec__axi_ram_ar_s__3_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__3; + wire zstd_dec__axi_ram_r_r__3_rdy; + wire zstd_dec__axi_ram_r_r__3_vld; + + assign { + axi_ram_s__3_axi_ar_arid, + axi_ram_s__3_axi_ar_araddr, + axi_ram_s__3_axi_ar_arregion, + axi_ram_s__3_axi_ar_arlen, + axi_ram_s__3_axi_ar_arsize, + axi_ram_s__3_axi_ar_arburst, + axi_ram_s__3_axi_ar_arcache, + axi_ram_s__3_axi_ar_arprot, + axi_ram_s__3_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__3; + assign axi_ram_s__3_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__3_vld; + assign zstd_dec__axi_ram_ar_s__3_rdy = axi_ram_s__3_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__3 = { + axi_ram_s__3_axi_r_rid, + axi_ram_s__3_axi_r_rdata, + axi_ram_s__3_axi_r_rresp, + axi_ram_s__3_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__3_vld = axi_ram_s__3_axi_r_rvalid; + assign axi_ram_s__3_axi_r_rready = zstd_dec__axi_ram_r_r__3_rdy; + assign axi_ram_s__3_axi_r_rresp[2] = '0; + + + // Axi Subordinate Interface for axi_ram_s__4 + wire axi_ram_s__4_axi_ar_arvalid; + wire axi_ram_s__4_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__4_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__4_axi_ar_araddr; + wire [ 3:0] axi_ram_s__4_axi_ar_arregion; + wire [ 7:0] axi_ram_s__4_axi_ar_arlen; + wire [ 2:0] axi_ram_s__4_axi_ar_arsize; + wire [ 1:0] axi_ram_s__4_axi_ar_arburst; + wire [ 3:0] axi_ram_s__4_axi_ar_arcache; + wire [ 2:0] axi_ram_s__4_axi_ar_arprot; + wire [ 3:0] axi_ram_s__4_axi_ar_arqos; + + wire axi_ram_s__4_axi_r_rvalid; + wire axi_ram_s__4_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__4_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__4_axi_r_rdata; + wire [ 2:0] axi_ram_s__4_axi_r_rresp; + wire axi_ram_s__4_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__4; + wire zstd_dec__axi_ram_ar_s__4_rdy; + wire zstd_dec__axi_ram_ar_s__4_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__4; + wire zstd_dec__axi_ram_r_r__4_rdy; + wire zstd_dec__axi_ram_r_r__4_vld; + + assign { + axi_ram_s__4_axi_ar_arid, + axi_ram_s__4_axi_ar_araddr, + axi_ram_s__4_axi_ar_arregion, + axi_ram_s__4_axi_ar_arlen, + axi_ram_s__4_axi_ar_arsize, + axi_ram_s__4_axi_ar_arburst, + axi_ram_s__4_axi_ar_arcache, + axi_ram_s__4_axi_ar_arprot, + axi_ram_s__4_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__4; + assign axi_ram_s__4_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__4_vld; + assign zstd_dec__axi_ram_ar_s__4_rdy = axi_ram_s__4_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__4 = { + axi_ram_s__4_axi_r_rid, + axi_ram_s__4_axi_r_rdata, + axi_ram_s__4_axi_r_rresp, + axi_ram_s__4_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__4_vld = axi_ram_s__4_axi_r_rvalid; + assign axi_ram_s__4_axi_r_rready = zstd_dec__axi_ram_r_r__4_rdy; + assign axi_ram_s__4_axi_r_rresp[2] = '0; + + // Axi Subordinate Interface for axi_ram_s__5 + wire axi_ram_s__5_axi_ar_arvalid; + wire axi_ram_s__5_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__5_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__5_axi_ar_araddr; + wire [ 3:0] axi_ram_s__5_axi_ar_arregion; + wire [ 7:0] axi_ram_s__5_axi_ar_arlen; + wire [ 2:0] axi_ram_s__5_axi_ar_arsize; + wire [ 1:0] axi_ram_s__5_axi_ar_arburst; + wire [ 3:0] axi_ram_s__5_axi_ar_arcache; + wire [ 2:0] axi_ram_s__5_axi_ar_arprot; + wire [ 3:0] axi_ram_s__5_axi_ar_arqos; + + wire axi_ram_s__5_axi_r_rvalid; + wire axi_ram_s__5_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__5_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__5_axi_r_rdata; + wire [ 2:0] axi_ram_s__5_axi_r_rresp; + wire axi_ram_s__5_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__5; + wire zstd_dec__axi_ram_ar_s__5_rdy; + wire zstd_dec__axi_ram_ar_s__5_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__5; + wire zstd_dec__axi_ram_r_r__5_rdy; + wire zstd_dec__axi_ram_r_r__5_vld; + + assign { + axi_ram_s__5_axi_ar_arid, + axi_ram_s__5_axi_ar_araddr, + axi_ram_s__5_axi_ar_arregion, + axi_ram_s__5_axi_ar_arlen, + axi_ram_s__5_axi_ar_arsize, + axi_ram_s__5_axi_ar_arburst, + axi_ram_s__5_axi_ar_arcache, + axi_ram_s__5_axi_ar_arprot, + axi_ram_s__5_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__5; + assign axi_ram_s__5_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__5_vld; + assign zstd_dec__axi_ram_ar_s__5_rdy = axi_ram_s__5_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__5 = { + axi_ram_s__5_axi_r_rid, + axi_ram_s__5_axi_r_rdata, + axi_ram_s__5_axi_r_rresp, + axi_ram_s__5_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__5_vld = axi_ram_s__5_axi_r_rvalid; + assign axi_ram_s__5_axi_r_rready = zstd_dec__axi_ram_r_r__5_rdy; + assign axi_ram_s__5_axi_r_rresp[2] = '0; + + // Axi Subordinate Interface for axi_ram_s__6 + wire axi_ram_s__6_axi_ar_arvalid; + wire axi_ram_s__6_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__6_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__6_axi_ar_araddr; + wire [ 3:0] axi_ram_s__6_axi_ar_arregion; + wire [ 7:0] axi_ram_s__6_axi_ar_arlen; + wire [ 2:0] axi_ram_s__6_axi_ar_arsize; + wire [ 1:0] axi_ram_s__6_axi_ar_arburst; + wire [ 3:0] axi_ram_s__6_axi_ar_arcache; + wire [ 2:0] axi_ram_s__6_axi_ar_arprot; + wire [ 3:0] axi_ram_s__6_axi_ar_arqos; + + wire axi_ram_s__6_axi_r_rvalid; + wire axi_ram_s__6_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__6_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__6_axi_r_rdata; + wire [ 2:0] axi_ram_s__6_axi_r_rresp; + wire axi_ram_s__6_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__6; + wire zstd_dec__axi_ram_ar_s__6_rdy; + wire zstd_dec__axi_ram_ar_s__6_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__6; + wire zstd_dec__axi_ram_r_r__6_rdy; + wire zstd_dec__axi_ram_r_r__6_vld; + + assign { + axi_ram_s__6_axi_ar_arid, + axi_ram_s__6_axi_ar_araddr, + axi_ram_s__6_axi_ar_arregion, + axi_ram_s__6_axi_ar_arlen, + axi_ram_s__6_axi_ar_arsize, + axi_ram_s__6_axi_ar_arburst, + axi_ram_s__6_axi_ar_arcache, + axi_ram_s__6_axi_ar_arprot, + axi_ram_s__6_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__6; + assign axi_ram_s__6_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__6_vld; + assign zstd_dec__axi_ram_ar_s__6_rdy = axi_ram_s__6_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__6 = { + axi_ram_s__6_axi_r_rid, + axi_ram_s__6_axi_r_rdata, + axi_ram_s__6_axi_r_rresp, + axi_ram_s__6_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__6_vld = axi_ram_s__6_axi_r_rvalid; + assign axi_ram_s__6_axi_r_rready = zstd_dec__axi_ram_r_r__6_rdy; + assign axi_ram_s__6_axi_r_rresp[2] = '0; + + // Axi Subordinate Interface for axi_ram_s__7 + wire axi_ram_s__7_axi_ar_arvalid; + wire axi_ram_s__7_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__7_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__7_axi_ar_araddr; + wire [ 3:0] axi_ram_s__7_axi_ar_arregion; + wire [ 7:0] axi_ram_s__7_axi_ar_arlen; + wire [ 2:0] axi_ram_s__7_axi_ar_arsize; + wire [ 1:0] axi_ram_s__7_axi_ar_arburst; + wire [ 3:0] axi_ram_s__7_axi_ar_arcache; + wire [ 2:0] axi_ram_s__7_axi_ar_arprot; + wire [ 3:0] axi_ram_s__7_axi_ar_arqos; + + wire axi_ram_s__7_axi_r_rvalid; + wire axi_ram_s__7_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__7_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__7_axi_r_rdata; + wire [ 2:0] axi_ram_s__7_axi_r_rresp; + wire axi_ram_s__7_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__7; + wire zstd_dec__axi_ram_ar_s__7_rdy; + wire zstd_dec__axi_ram_ar_s__7_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__7; + wire zstd_dec__axi_ram_r_r__7_rdy; + wire zstd_dec__axi_ram_r_r__7_vld; + + assign { + axi_ram_s__7_axi_ar_arid, + axi_ram_s__7_axi_ar_araddr, + axi_ram_s__7_axi_ar_arregion, + axi_ram_s__7_axi_ar_arlen, + axi_ram_s__7_axi_ar_arsize, + axi_ram_s__7_axi_ar_arburst, + axi_ram_s__7_axi_ar_arcache, + axi_ram_s__7_axi_ar_arprot, + axi_ram_s__7_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__7; + assign axi_ram_s__7_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__7_vld; + assign zstd_dec__axi_ram_ar_s__7_rdy = axi_ram_s__7_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__7 = { + axi_ram_s__7_axi_r_rid, + axi_ram_s__7_axi_r_rdata, + axi_ram_s__7_axi_r_rresp, + axi_ram_s__7_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__7_vld = axi_ram_s__7_axi_r_rvalid; + assign axi_ram_s__7_axi_r_rready = zstd_dec__axi_ram_r_r__7_rdy; + assign axi_ram_s__7_axi_r_rresp[2] = '0; + + // Axi Subordinate Interface for axi_ram_s__8 + wire axi_ram_s__8_axi_ar_arvalid; + wire axi_ram_s__8_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__8_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__8_axi_ar_araddr; + wire [ 3:0] axi_ram_s__8_axi_ar_arregion; + wire [ 7:0] axi_ram_s__8_axi_ar_arlen; + wire [ 2:0] axi_ram_s__8_axi_ar_arsize; + wire [ 1:0] axi_ram_s__8_axi_ar_arburst; + wire [ 3:0] axi_ram_s__8_axi_ar_arcache; + wire [ 2:0] axi_ram_s__8_axi_ar_arprot; + wire [ 3:0] axi_ram_s__8_axi_ar_arqos; + + wire axi_ram_s__8_axi_r_rvalid; + wire axi_ram_s__8_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__8_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__8_axi_r_rdata; + wire [ 2:0] axi_ram_s__8_axi_r_rresp; + wire axi_ram_s__8_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__8; + wire zstd_dec__axi_ram_ar_s__8_rdy; + wire zstd_dec__axi_ram_ar_s__8_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__8; + wire zstd_dec__axi_ram_r_r__8_rdy; + wire zstd_dec__axi_ram_r_r__8_vld; + + assign { + axi_ram_s__8_axi_ar_arid, + axi_ram_s__8_axi_ar_araddr, + axi_ram_s__8_axi_ar_arregion, + axi_ram_s__8_axi_ar_arlen, + axi_ram_s__8_axi_ar_arsize, + axi_ram_s__8_axi_ar_arburst, + axi_ram_s__8_axi_ar_arcache, + axi_ram_s__8_axi_ar_arprot, + axi_ram_s__8_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__8; + assign axi_ram_s__8_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__8_vld; + assign zstd_dec__axi_ram_ar_s__8_rdy = axi_ram_s__8_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__8 = { + axi_ram_s__8_axi_r_rid, + axi_ram_s__8_axi_r_rdata, + axi_ram_s__8_axi_r_rresp, + axi_ram_s__8_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__8_vld = axi_ram_s__8_axi_r_rvalid; + assign axi_ram_s__8_axi_r_rready = zstd_dec__axi_ram_r_r__8_rdy; + assign axi_ram_s__8_axi_r_rresp[2] = '0; + + // Axi Subordinate Interface for axi_ram_s__9 + wire axi_ram_s__9_axi_ar_arvalid; + wire axi_ram_s__9_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__9_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__9_axi_ar_araddr; + wire [ 3:0] axi_ram_s__9_axi_ar_arregion; + wire [ 7:0] axi_ram_s__9_axi_ar_arlen; + wire [ 2:0] axi_ram_s__9_axi_ar_arsize; + wire [ 1:0] axi_ram_s__9_axi_ar_arburst; + wire [ 3:0] axi_ram_s__9_axi_ar_arcache; + wire [ 2:0] axi_ram_s__9_axi_ar_arprot; + wire [ 3:0] axi_ram_s__9_axi_ar_arqos; + + wire axi_ram_s__9_axi_r_rvalid; + wire axi_ram_s__9_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__9_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__9_axi_r_rdata; + wire [ 2:0] axi_ram_s__9_axi_r_rresp; + wire axi_ram_s__9_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__9; + wire zstd_dec__axi_ram_ar_s__9_rdy; + wire zstd_dec__axi_ram_ar_s__9_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__9; + wire zstd_dec__axi_ram_r_r__9_rdy; + wire zstd_dec__axi_ram_r_r__9_vld; + + assign { + axi_ram_s__9_axi_ar_arid, + axi_ram_s__9_axi_ar_araddr, + axi_ram_s__9_axi_ar_arregion, + axi_ram_s__9_axi_ar_arlen, + axi_ram_s__9_axi_ar_arsize, + axi_ram_s__9_axi_ar_arburst, + axi_ram_s__9_axi_ar_arcache, + axi_ram_s__9_axi_ar_arprot, + axi_ram_s__9_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__9; + assign axi_ram_s__9_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__9_vld; + assign zstd_dec__axi_ram_ar_s__9_rdy = axi_ram_s__9_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__9 = { + axi_ram_s__9_axi_r_rid, + axi_ram_s__9_axi_r_rdata, + axi_ram_s__9_axi_r_rresp, + axi_ram_s__9_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__9_vld = axi_ram_s__9_axi_r_rvalid; + assign axi_ram_s__9_axi_r_rready = zstd_dec__axi_ram_r_r__9_rdy; + assign axi_ram_s__9_axi_r_rresp[2] = '0; + + + // Axi Subordinate Interface for axi_ram_s__10 + wire axi_ram_s__10_axi_ar_arvalid; + wire axi_ram_s__10_axi_ar_arready; + wire [S_AXI_ID_W-1:0] axi_ram_s__10_axi_ar_arid; + wire [AXI_ADDR_W-1:0] axi_ram_s__10_axi_ar_araddr; + wire [ 3:0] axi_ram_s__10_axi_ar_arregion; + wire [ 7:0] axi_ram_s__10_axi_ar_arlen; + wire [ 2:0] axi_ram_s__10_axi_ar_arsize; + wire [ 1:0] axi_ram_s__10_axi_ar_arburst; + wire [ 3:0] axi_ram_s__10_axi_ar_arcache; + wire [ 2:0] axi_ram_s__10_axi_ar_arprot; + wire [ 3:0] axi_ram_s__10_axi_ar_arqos; + + wire axi_ram_s__10_axi_r_rvalid; + wire axi_ram_s__10_axi_r_rready; + wire [S_AXI_ID_W-1:0] axi_ram_s__10_axi_r_rid; + wire [AXI_DATA_W-1:0] axi_ram_s__10_axi_r_rdata; + wire [ 2:0] axi_ram_s__10_axi_r_rresp; + wire axi_ram_s__10_axi_r_rlast; + + wire [XlsAxiArW-1:0] zstd_dec__axi_ram_ar_s__10; + wire zstd_dec__axi_ram_ar_s__10_rdy; + wire zstd_dec__axi_ram_ar_s__10_vld; + wire [ XlsAxiRW-1:0] zstd_dec__axi_ram_r_r__10; + wire zstd_dec__axi_ram_r_r__10_rdy; + wire zstd_dec__axi_ram_r_r__10_vld; + + assign { + axi_ram_s__10_axi_ar_arid, + axi_ram_s__10_axi_ar_araddr, + axi_ram_s__10_axi_ar_arregion, + axi_ram_s__10_axi_ar_arlen, + axi_ram_s__10_axi_ar_arsize, + axi_ram_s__10_axi_ar_arburst, + axi_ram_s__10_axi_ar_arcache, + axi_ram_s__10_axi_ar_arprot, + axi_ram_s__10_axi_ar_arqos + } = zstd_dec__axi_ram_ar_s__10; + assign axi_ram_s__10_axi_ar_arvalid = zstd_dec__axi_ram_ar_s__10_vld; + assign zstd_dec__axi_ram_ar_s__10_rdy = axi_ram_s__10_axi_ar_arready; + + assign zstd_dec__axi_ram_r_r__10 = { + axi_ram_s__10_axi_r_rid, + axi_ram_s__10_axi_r_rdata, + axi_ram_s__10_axi_r_rresp, + axi_ram_s__10_axi_r_rlast}; + assign zstd_dec__axi_ram_r_r__10_vld = axi_ram_s__10_axi_r_rvalid; + assign axi_ram_s__10_axi_r_rready = zstd_dec__axi_ram_r_r__10_rdy; + assign axi_ram_s__10_axi_r_rresp[2] = '0; + + + // RAM instance for history_buffer_ram0 + logic [7:0] history_buffer_ram0_wr_data; + logic [12:0] history_buffer_ram0_wr_addr; + logic history_buffer_ram0_wr_en; + logic history_buffer_ram0_wr_mask; + logic [7:0] history_buffer_ram0_rd_data; + logic [12:0] history_buffer_ram0_rd_addr; + logic history_buffer_ram0_rd_en; + logic history_buffer_ram0_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram0_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram0_wr_data), + .wr_addr(history_buffer_ram0_wr_addr), + .wr_en(history_buffer_ram0_wr_en), + .wr_mask(history_buffer_ram0_wr_mask), + .rd_data(history_buffer_ram0_rd_data), + .rd_addr(history_buffer_ram0_rd_addr), + .rd_en(history_buffer_ram0_rd_en), + .rd_mask(history_buffer_ram0_rd_mask) + ); + + // RAM instance for history_buffer_ram1 + logic [7:0] history_buffer_ram1_wr_data; + logic [12:0] history_buffer_ram1_wr_addr; + logic history_buffer_ram1_wr_en; + logic history_buffer_ram1_wr_mask; + logic [7:0] history_buffer_ram1_rd_data; + logic [12:0] history_buffer_ram1_rd_addr; + logic history_buffer_ram1_rd_en; + logic history_buffer_ram1_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram1_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram1_wr_data), + .wr_addr(history_buffer_ram1_wr_addr), + .wr_en(history_buffer_ram1_wr_en), + .wr_mask(history_buffer_ram1_wr_mask), + .rd_data(history_buffer_ram1_rd_data), + .rd_addr(history_buffer_ram1_rd_addr), + .rd_en(history_buffer_ram1_rd_en), + .rd_mask(history_buffer_ram1_rd_mask) + ); + + // RAM instance for history_buffer_ram2 + logic [7:0] history_buffer_ram2_wr_data; + logic [12:0] history_buffer_ram2_wr_addr; + logic history_buffer_ram2_wr_en; + logic history_buffer_ram2_wr_mask; + logic [7:0] history_buffer_ram2_rd_data; + logic [12:0] history_buffer_ram2_rd_addr; + logic history_buffer_ram2_rd_en; + logic history_buffer_ram2_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram2_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram2_wr_data), + .wr_addr(history_buffer_ram2_wr_addr), + .wr_en(history_buffer_ram2_wr_en), + .wr_mask(history_buffer_ram2_wr_mask), + .rd_data(history_buffer_ram2_rd_data), + .rd_addr(history_buffer_ram2_rd_addr), + .rd_en(history_buffer_ram2_rd_en), + .rd_mask(history_buffer_ram2_rd_mask) + ); + + // RAM instance for history_buffer_ram3 + logic [7:0] history_buffer_ram3_wr_data; + logic [12:0] history_buffer_ram3_wr_addr; + logic history_buffer_ram3_wr_en; + logic history_buffer_ram3_wr_mask; + logic [7:0] history_buffer_ram3_rd_data; + logic [12:0] history_buffer_ram3_rd_addr; + logic history_buffer_ram3_rd_en; + logic history_buffer_ram3_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram3_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram3_wr_data), + .wr_addr(history_buffer_ram3_wr_addr), + .wr_en(history_buffer_ram3_wr_en), + .wr_mask(history_buffer_ram3_wr_mask), + .rd_data(history_buffer_ram3_rd_data), + .rd_addr(history_buffer_ram3_rd_addr), + .rd_en(history_buffer_ram3_rd_en), + .rd_mask(history_buffer_ram3_rd_mask) + ); + + // RAM instance for history_buffer_ram4 + logic [7:0] history_buffer_ram4_wr_data; + logic [12:0] history_buffer_ram4_wr_addr; + logic history_buffer_ram4_wr_en; + logic history_buffer_ram4_wr_mask; + logic [7:0] history_buffer_ram4_rd_data; + logic [12:0] history_buffer_ram4_rd_addr; + logic history_buffer_ram4_rd_en; + logic history_buffer_ram4_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram4_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram4_wr_data), + .wr_addr(history_buffer_ram4_wr_addr), + .wr_en(history_buffer_ram4_wr_en), + .wr_mask(history_buffer_ram4_wr_mask), + .rd_data(history_buffer_ram4_rd_data), + .rd_addr(history_buffer_ram4_rd_addr), + .rd_en(history_buffer_ram4_rd_en), + .rd_mask(history_buffer_ram4_rd_mask) + ); + + // RAM instance for history_buffer_ram5 + logic [7:0] history_buffer_ram5_wr_data; + logic [12:0] history_buffer_ram5_wr_addr; + logic history_buffer_ram5_wr_en; + logic history_buffer_ram5_wr_mask; + logic [7:0] history_buffer_ram5_rd_data; + logic [12:0] history_buffer_ram5_rd_addr; + logic history_buffer_ram5_rd_en; + logic history_buffer_ram5_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram5_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram5_wr_data), + .wr_addr(history_buffer_ram5_wr_addr), + .wr_en(history_buffer_ram5_wr_en), + .wr_mask(history_buffer_ram5_wr_mask), + .rd_data(history_buffer_ram5_rd_data), + .rd_addr(history_buffer_ram5_rd_addr), + .rd_en(history_buffer_ram5_rd_en), + .rd_mask(history_buffer_ram5_rd_mask) + ); + + // RAM instance for history_buffer_ram6 + logic [7:0] history_buffer_ram6_wr_data; + logic [12:0] history_buffer_ram6_wr_addr; + logic history_buffer_ram6_wr_en; + logic history_buffer_ram6_wr_mask; + logic [7:0] history_buffer_ram6_rd_data; + logic [12:0] history_buffer_ram6_rd_addr; + logic history_buffer_ram6_rd_en; + logic history_buffer_ram6_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram6_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram6_wr_data), + .wr_addr(history_buffer_ram6_wr_addr), + .wr_en(history_buffer_ram6_wr_en), + .wr_mask(history_buffer_ram6_wr_mask), + .rd_data(history_buffer_ram6_rd_data), + .rd_addr(history_buffer_ram6_rd_addr), + .rd_en(history_buffer_ram6_rd_en), + .rd_mask(history_buffer_ram6_rd_mask) + ); + + // RAM instance for history_buffer_ram7 + logic [7:0] history_buffer_ram7_wr_data; + logic [12:0] history_buffer_ram7_wr_addr; + logic history_buffer_ram7_wr_en; + logic history_buffer_ram7_wr_mask; + logic [7:0] history_buffer_ram7_rd_data; + logic [12:0] history_buffer_ram7_rd_addr; + logic history_buffer_ram7_rd_en; + logic history_buffer_ram7_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) history_buffer_ram7_ram ( + .clk(clk), + .rst(rst), + .wr_data(history_buffer_ram7_wr_data), + .wr_addr(history_buffer_ram7_wr_addr), + .wr_en(history_buffer_ram7_wr_en), + .wr_mask(history_buffer_ram7_wr_mask), + .rd_data(history_buffer_ram7_rd_data), + .rd_addr(history_buffer_ram7_rd_addr), + .rd_en(history_buffer_ram7_rd_en), + .rd_mask(history_buffer_ram7_rd_mask) + ); + + // RAM instance for dpd_ram + logic [15:0] dpd_ram_wr_data; + logic [7:0] dpd_ram_wr_addr; + logic dpd_ram_wr_en; + logic dpd_ram_wr_mask; + logic [15:0] dpd_ram_rd_data; + logic [7:0] dpd_ram_rd_addr; + logic dpd_ram_rd_en; + logic dpd_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(16), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(8) + ) dpd_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(dpd_ram_wr_data), + .wr_addr(dpd_ram_wr_addr), + .wr_en(dpd_ram_wr_en), + .wr_mask(dpd_ram_wr_mask), + .rd_data(dpd_ram_rd_data), + .rd_addr(dpd_ram_rd_addr), + .rd_en(dpd_ram_rd_en), + .rd_mask(dpd_ram_rd_mask) + ); + + // RAM instance for fse_tmp_ram + logic [15:0] fse_tmp_ram_wr_data; + logic [7:0] fse_tmp_ram_wr_addr; + logic fse_tmp_ram_wr_en; + logic fse_tmp_ram_wr_mask; + logic [15:0] fse_tmp_ram_rd_data; + logic [7:0] fse_tmp_ram_rd_addr; + logic fse_tmp_ram_rd_en; + logic fse_tmp_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(16), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(8) + ) fse_tmp_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(fse_tmp_ram_wr_data), + .wr_addr(fse_tmp_ram_wr_addr), + .wr_en(fse_tmp_ram_wr_en), + .wr_mask(fse_tmp_ram_wr_mask), + .rd_data(fse_tmp_ram_rd_data), + .rd_addr(fse_tmp_ram_rd_addr), + .rd_en(fse_tmp_ram_rd_en), + .rd_mask(fse_tmp_ram_rd_mask) + ); + + // RAM instance for fse_tmp2_ram + logic [7:0] fse_tmp2_ram_wr_data; + logic [8:0] fse_tmp2_ram_wr_addr; + logic fse_tmp2_ram_wr_en; + logic fse_tmp2_ram_wr_mask; + logic [7:0] fse_tmp2_ram_rd_data; + logic [8:0] fse_tmp2_ram_rd_addr; + logic fse_tmp2_ram_rd_en; + logic fse_tmp2_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(512), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(9) + ) fse_tmp2_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(fse_tmp2_ram_wr_data), + .wr_addr(fse_tmp2_ram_wr_addr), + .wr_en(fse_tmp2_ram_wr_en), + .wr_mask(fse_tmp2_ram_wr_mask), + .rd_data(fse_tmp2_ram_rd_data), + .rd_addr(fse_tmp2_ram_rd_addr), + .rd_en(fse_tmp2_ram_rd_en), + .rd_mask(fse_tmp2_ram_rd_mask) + ); + + // RAM instance for ll_def_fse_ram + logic [31:0] ll_def_fse_ram_wr_data; + logic [14:0] ll_def_fse_ram_wr_addr; + logic ll_def_fse_ram_wr_en; + logic ll_def_fse_ram_wr_mask; + logic [31:0] ll_def_fse_ram_rd_data; + logic [14:0] ll_def_fse_ram_rd_addr; + logic ll_def_fse_ram_rd_en; + logic ll_def_fse_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(15), + .INIT_FILE("../xls/modules/zstd/zstd_dec_ll_fse_default.mem") + ) ll_def_fse_ram ( + .clk(clk), + .rst(rst), + .wr_data(ll_def_fse_ram_wr_data), + .wr_addr(ll_def_fse_ram_wr_addr), + .wr_en(ll_def_fse_ram_wr_en), + .wr_mask(ll_def_fse_ram_wr_mask), + .rd_data(ll_def_fse_ram_rd_data), + .rd_addr(ll_def_fse_ram_rd_addr), + .rd_en(ll_def_fse_ram_rd_en), + .rd_mask(ll_def_fse_ram_rd_mask) + ); + + // RAM instance for ll_fse_ram + logic [31:0] ll_fse_ram_wr_data; + logic [14:0] ll_fse_ram_wr_addr; + logic ll_fse_ram_wr_en; + logic ll_fse_ram_wr_mask; + logic [31:0] ll_fse_ram_rd_data; + logic [14:0] ll_fse_ram_rd_addr; + logic ll_fse_ram_rd_en; + logic ll_fse_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(32768), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(15) + ) ll_fse_ram ( + .clk(clk), + .rst(rst), + .wr_data(ll_fse_ram_wr_data), + .wr_addr(ll_fse_ram_wr_addr), + .wr_en(ll_fse_ram_wr_en), + .wr_mask(ll_fse_ram_wr_mask), + .rd_data(ll_fse_ram_rd_data), + .rd_addr(ll_fse_ram_rd_addr), + .rd_en(ll_fse_ram_rd_en), + .rd_mask(ll_fse_ram_rd_mask) + ); + + // RAM instance for ml_def_fse_ram + logic [31:0] ml_def_fse_ram_wr_data; + logic [14:0] ml_def_fse_ram_wr_addr; + logic ml_def_fse_ram_wr_en; + logic ml_def_fse_ram_wr_mask; + logic [31:0] ml_def_fse_ram_rd_data; + logic [14:0] ml_def_fse_ram_rd_addr; + logic ml_def_fse_ram_rd_en; + logic ml_def_fse_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(15), + .INIT_FILE("../xls/modules/zstd/zstd_dec_ml_fse_default.mem") + ) ml_def_fse_ram ( + .clk(clk), + .rst(rst), + .wr_data(ml_def_fse_ram_wr_data), + .wr_addr(ml_def_fse_ram_wr_addr), + .wr_en(ml_def_fse_ram_wr_en), + .wr_mask(ml_def_fse_ram_wr_mask), + .rd_data(ml_def_fse_ram_rd_data), + .rd_addr(ml_def_fse_ram_rd_addr), + .rd_en(ml_def_fse_ram_rd_en), + .rd_mask(ml_def_fse_ram_rd_mask) + ); + + // RAM instance for ml_fse_ram + logic [31:0] ml_fse_ram_wr_data; + logic [14:0] ml_fse_ram_wr_addr; + logic ml_fse_ram_wr_en; + logic ml_fse_ram_wr_mask; + logic [31:0] ml_fse_ram_rd_data; + logic [14:0] ml_fse_ram_rd_addr; + logic ml_fse_ram_rd_en; + logic ml_fse_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(32768), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(15) + ) ml_fse_ram ( + .clk(clk), + .rst(rst), + .wr_data(ml_fse_ram_wr_data), + .wr_addr(ml_fse_ram_wr_addr), + .wr_en(ml_fse_ram_wr_en), + .wr_mask(ml_fse_ram_wr_mask), + .rd_data(ml_fse_ram_rd_data), + .rd_addr(ml_fse_ram_rd_addr), + .rd_en(ml_fse_ram_rd_en), + .rd_mask(ml_fse_ram_rd_mask) + ); + + // RAM instance for of_def_fse_ram + logic [31:0] of_def_fse_ram_wr_data; + logic [14:0] of_def_fse_ram_wr_addr; + logic of_def_fse_ram_wr_en; + logic of_def_fse_ram_wr_mask; + logic [31:0] of_def_fse_ram_rd_data; + logic [14:0] of_def_fse_ram_rd_addr; + logic of_def_fse_ram_rd_en; + logic of_def_fse_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(15), + .INIT_FILE("../xls/modules/zstd/zstd_dec_of_fse_default.mem") + ) of_def_fse_ram ( + .clk(clk), + .rst(rst), + .wr_data(of_def_fse_ram_wr_data), + .wr_addr(of_def_fse_ram_wr_addr), + .wr_en(of_def_fse_ram_wr_en), + .wr_mask(of_def_fse_ram_wr_mask), + .rd_data(of_def_fse_ram_rd_data), + .rd_addr(of_def_fse_ram_rd_addr), + .rd_en(of_def_fse_ram_rd_en), + .rd_mask(of_def_fse_ram_rd_mask) + ); + + // RAM instance for of_fse_ram + logic [31:0] of_fse_ram_wr_data; + logic [14:0] of_fse_ram_wr_addr; + logic of_fse_ram_wr_en; + logic of_fse_ram_wr_mask; + logic [31:0] of_fse_ram_rd_data; + logic [14:0] of_fse_ram_rd_addr; + logic of_fse_ram_rd_en; + logic of_fse_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(32768), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(15) + ) of_fse_ram ( + .clk(clk), + .rst(rst), + .wr_data(of_fse_ram_wr_data), + .wr_addr(of_fse_ram_wr_addr), + .wr_en(of_fse_ram_wr_en), + .wr_mask(of_fse_ram_wr_mask), + .rd_data(of_fse_ram_rd_data), + .rd_addr(of_fse_ram_rd_addr), + .rd_en(of_fse_ram_rd_en), + .rd_mask(of_fse_ram_rd_mask) + ); + + // RAM instance for huffman_literals_prescan_ram + logic [91:0] huffman_literals_prescan_ram_wr_data; + logic [5:0] huffman_literals_prescan_ram_wr_addr; + logic huffman_literals_prescan_ram_wr_en; + logic huffman_literals_prescan_ram_wr_mask; + logic [91:0] huffman_literals_prescan_ram_rd_data; + logic [5:0] huffman_literals_prescan_ram_rd_addr; + logic huffman_literals_prescan_ram_rd_en; + logic huffman_literals_prescan_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(92), + .SIZE(64), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(6) + ) huffman_literals_prescan_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(huffman_literals_prescan_ram_wr_data), + .wr_addr(huffman_literals_prescan_ram_wr_addr), + .wr_en(huffman_literals_prescan_ram_wr_en), + .wr_mask(huffman_literals_prescan_ram_wr_mask), + .rd_data(huffman_literals_prescan_ram_rd_data), + .rd_addr(huffman_literals_prescan_ram_rd_addr), + .rd_en(huffman_literals_prescan_ram_rd_en), + .rd_mask(huffman_literals_prescan_ram_rd_mask) + ); + + // RAM instance for huffman_literals_weights_mem_ram + logic [31:0] huffman_literals_weights_mem_ram_wr_data; + logic [5:0] huffman_literals_weights_mem_ram_wr_addr; + logic huffman_literals_weights_mem_ram_wr_en; + logic [7:0] huffman_literals_weights_mem_ram_wr_mask; + logic [31:0] huffman_literals_weights_mem_ram_rd_data; + logic [5:0] huffman_literals_weights_mem_ram_rd_addr; + logic huffman_literals_weights_mem_ram_rd_en; + logic [7:0] huffman_literals_weights_mem_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(64), + .NUM_PARTITIONS(8), + .ADDR_WIDTH(6) + ) huffman_literals_weights_mem_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(huffman_literals_weights_mem_ram_wr_data), + .wr_addr(huffman_literals_weights_mem_ram_wr_addr), + .wr_en(huffman_literals_weights_mem_ram_wr_en), + .wr_mask(huffman_literals_weights_mem_ram_wr_mask), + .rd_data(huffman_literals_weights_mem_ram_rd_data), + .rd_addr(huffman_literals_weights_mem_ram_rd_addr), + .rd_en(huffman_literals_weights_mem_ram_rd_en), + .rd_mask(huffman_literals_weights_mem_ram_rd_mask) + ); + + // RAM instance for literals_buffer_ram0 + logic [8:0] literals_buffer_ram0_wr_data; + logic [12:0] literals_buffer_ram0_wr_addr; + logic literals_buffer_ram0_wr_en; + logic literals_buffer_ram0_wr_mask; + logic [8:0] literals_buffer_ram0_rd_data; + logic [12:0] literals_buffer_ram0_rd_addr; + logic literals_buffer_ram0_rd_en; + logic literals_buffer_ram0_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram0_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram0_wr_data), + .wr_addr(literals_buffer_ram0_wr_addr), + .wr_en(literals_buffer_ram0_wr_en), + .wr_mask(literals_buffer_ram0_wr_mask), + .rd_data(literals_buffer_ram0_rd_data), + .rd_addr(literals_buffer_ram0_rd_addr), + .rd_en(literals_buffer_ram0_rd_en), + .rd_mask(literals_buffer_ram0_rd_mask) + ); + + // RAM instance for literals_buffer_ram1 + logic [8:0] literals_buffer_ram1_wr_data; + logic [12:0] literals_buffer_ram1_wr_addr; + logic literals_buffer_ram1_wr_en; + logic literals_buffer_ram1_wr_mask; + logic [8:0] literals_buffer_ram1_rd_data; + logic [12:0] literals_buffer_ram1_rd_addr; + logic literals_buffer_ram1_rd_en; + logic literals_buffer_ram1_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram1_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram1_wr_data), + .wr_addr(literals_buffer_ram1_wr_addr), + .wr_en(literals_buffer_ram1_wr_en), + .wr_mask(literals_buffer_ram1_wr_mask), + .rd_data(literals_buffer_ram1_rd_data), + .rd_addr(literals_buffer_ram1_rd_addr), + .rd_en(literals_buffer_ram1_rd_en), + .rd_mask(literals_buffer_ram1_rd_mask) + ); + + // RAM instance for literals_buffer_ram2 + logic [8:0] literals_buffer_ram2_wr_data; + logic [12:0] literals_buffer_ram2_wr_addr; + logic literals_buffer_ram2_wr_en; + logic literals_buffer_ram2_wr_mask; + logic [8:0] literals_buffer_ram2_rd_data; + logic [12:0] literals_buffer_ram2_rd_addr; + logic literals_buffer_ram2_rd_en; + logic literals_buffer_ram2_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram2_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram2_wr_data), + .wr_addr(literals_buffer_ram2_wr_addr), + .wr_en(literals_buffer_ram2_wr_en), + .wr_mask(literals_buffer_ram2_wr_mask), + .rd_data(literals_buffer_ram2_rd_data), + .rd_addr(literals_buffer_ram2_rd_addr), + .rd_en(literals_buffer_ram2_rd_en), + .rd_mask(literals_buffer_ram2_rd_mask) + ); + + // RAM instance for literals_buffer_ram3 + logic [8:0] literals_buffer_ram3_wr_data; + logic [12:0] literals_buffer_ram3_wr_addr; + logic literals_buffer_ram3_wr_en; + logic literals_buffer_ram3_wr_mask; + logic [8:0] literals_buffer_ram3_rd_data; + logic [12:0] literals_buffer_ram3_rd_addr; + logic literals_buffer_ram3_rd_en; + logic literals_buffer_ram3_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram3_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram3_wr_data), + .wr_addr(literals_buffer_ram3_wr_addr), + .wr_en(literals_buffer_ram3_wr_en), + .wr_mask(literals_buffer_ram3_wr_mask), + .rd_data(literals_buffer_ram3_rd_data), + .rd_addr(literals_buffer_ram3_rd_addr), + .rd_en(literals_buffer_ram3_rd_en), + .rd_mask(literals_buffer_ram3_rd_mask) + ); + + // RAM instance for literals_buffer_ram4 + logic [8:0] literals_buffer_ram4_wr_data; + logic [12:0] literals_buffer_ram4_wr_addr; + logic literals_buffer_ram4_wr_en; + logic literals_buffer_ram4_wr_mask; + logic [8:0] literals_buffer_ram4_rd_data; + logic [12:0] literals_buffer_ram4_rd_addr; + logic literals_buffer_ram4_rd_en; + logic literals_buffer_ram4_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram4_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram4_wr_data), + .wr_addr(literals_buffer_ram4_wr_addr), + .wr_en(literals_buffer_ram4_wr_en), + .wr_mask(literals_buffer_ram4_wr_mask), + .rd_data(literals_buffer_ram4_rd_data), + .rd_addr(literals_buffer_ram4_rd_addr), + .rd_en(literals_buffer_ram4_rd_en), + .rd_mask(literals_buffer_ram4_rd_mask) + ); + + // RAM instance for literals_buffer_ram5 + logic [8:0] literals_buffer_ram5_wr_data; + logic [12:0] literals_buffer_ram5_wr_addr; + logic literals_buffer_ram5_wr_en; + logic literals_buffer_ram5_wr_mask; + logic [8:0] literals_buffer_ram5_rd_data; + logic [12:0] literals_buffer_ram5_rd_addr; + logic literals_buffer_ram5_rd_en; + logic literals_buffer_ram5_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram5_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram5_wr_data), + .wr_addr(literals_buffer_ram5_wr_addr), + .wr_en(literals_buffer_ram5_wr_en), + .wr_mask(literals_buffer_ram5_wr_mask), + .rd_data(literals_buffer_ram5_rd_data), + .rd_addr(literals_buffer_ram5_rd_addr), + .rd_en(literals_buffer_ram5_rd_en), + .rd_mask(literals_buffer_ram5_rd_mask) + ); + + // RAM instance for literals_buffer_ram6 + logic [8:0] literals_buffer_ram6_wr_data; + logic [12:0] literals_buffer_ram6_wr_addr; + logic literals_buffer_ram6_wr_en; + logic literals_buffer_ram6_wr_mask; + logic [8:0] literals_buffer_ram6_rd_data; + logic [12:0] literals_buffer_ram6_rd_addr; + logic literals_buffer_ram6_rd_en; + logic literals_buffer_ram6_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram6_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram6_wr_data), + .wr_addr(literals_buffer_ram6_wr_addr), + .wr_en(literals_buffer_ram6_wr_en), + .wr_mask(literals_buffer_ram6_wr_mask), + .rd_data(literals_buffer_ram6_rd_data), + .rd_addr(literals_buffer_ram6_rd_addr), + .rd_en(literals_buffer_ram6_rd_en), + .rd_mask(literals_buffer_ram6_rd_mask) + ); + + // RAM instance for literals_buffer_ram7 + logic [8:0] literals_buffer_ram7_wr_data; + logic [12:0] literals_buffer_ram7_wr_addr; + logic literals_buffer_ram7_wr_en; + logic literals_buffer_ram7_wr_mask; + logic [8:0] literals_buffer_ram7_rd_data; + logic [12:0] literals_buffer_ram7_rd_addr; + logic literals_buffer_ram7_rd_en; + logic literals_buffer_ram7_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(9), + .SIZE(8192), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(13) + ) literals_buffer_ram7_ram ( + .clk(clk), + .rst(rst), + .wr_data(literals_buffer_ram7_wr_data), + .wr_addr(literals_buffer_ram7_wr_addr), + .wr_en(literals_buffer_ram7_wr_en), + .wr_mask(literals_buffer_ram7_wr_mask), + .rd_data(literals_buffer_ram7_rd_data), + .rd_addr(literals_buffer_ram7_rd_addr), + .rd_en(literals_buffer_ram7_rd_en), + .rd_mask(literals_buffer_ram7_rd_mask) + ); + + // RAM instance for huffman_literals_weights_dpd_ram + logic [15:0] huffman_literals_weights_dpd_ram_wr_data; + logic [7:0] huffman_literals_weights_dpd_ram_wr_addr; + logic huffman_literals_weights_dpd_ram_wr_en; + logic huffman_literals_weights_dpd_ram_wr_mask; + logic [15:0] huffman_literals_weights_dpd_ram_rd_data; + logic [7:0] huffman_literals_weights_dpd_ram_rd_addr; + logic huffman_literals_weights_dpd_ram_rd_en; + logic huffman_literals_weights_dpd_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(16), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(8) + ) huffman_literals_weights_dpd_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(huffman_literals_weights_dpd_ram_wr_data), + .wr_addr(huffman_literals_weights_dpd_ram_wr_addr), + .wr_en(huffman_literals_weights_dpd_ram_wr_en), + .wr_mask(huffman_literals_weights_dpd_ram_wr_mask), + .rd_data(huffman_literals_weights_dpd_ram_rd_data), + .rd_addr(huffman_literals_weights_dpd_ram_rd_addr), + .rd_en(huffman_literals_weights_dpd_ram_rd_en), + .rd_mask(huffman_literals_weights_dpd_ram_rd_mask) + ); + + // RAM instance for huffman_literals_weights_tmp_ram + logic [15:0] huffman_literals_weights_tmp_ram_wr_data; + logic [7:0] huffman_literals_weights_tmp_ram_wr_addr; + logic huffman_literals_weights_tmp_ram_wr_en; + logic huffman_literals_weights_tmp_ram_wr_mask; + logic [15:0] huffman_literals_weights_tmp_ram_rd_data; + logic [7:0] huffman_literals_weights_tmp_ram_rd_addr; + logic huffman_literals_weights_tmp_ram_rd_en; + logic huffman_literals_weights_tmp_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(16), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(8) + ) huffman_literals_weights_tmp_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(huffman_literals_weights_tmp_ram_wr_data), + .wr_addr(huffman_literals_weights_tmp_ram_wr_addr), + .wr_en(huffman_literals_weights_tmp_ram_wr_en), + .wr_mask(huffman_literals_weights_tmp_ram_wr_mask), + .rd_data(huffman_literals_weights_tmp_ram_rd_data), + .rd_addr(huffman_literals_weights_tmp_ram_rd_addr), + .rd_en(huffman_literals_weights_tmp_ram_rd_en), + .rd_mask(huffman_literals_weights_tmp_ram_rd_mask) + ); + + // RAM instance for huffman_literals_weights_tmp2_ram + logic [7:0] huffman_literals_weights_tmp2_ram_wr_data; + logic [8:0] huffman_literals_weights_tmp2_ram_wr_addr; + logic huffman_literals_weights_tmp2_ram_wr_en; + logic huffman_literals_weights_tmp2_ram_wr_mask; + logic [7:0] huffman_literals_weights_tmp2_ram_rd_data; + logic [8:0] huffman_literals_weights_tmp2_ram_rd_addr; + logic huffman_literals_weights_tmp2_ram_rd_en; + logic huffman_literals_weights_tmp2_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(8), + .SIZE(512), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(9) + ) huffman_literals_weights_tmp2_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(huffman_literals_weights_tmp2_ram_wr_data), + .wr_addr(huffman_literals_weights_tmp2_ram_wr_addr), + .wr_en(huffman_literals_weights_tmp2_ram_wr_en), + .wr_mask(huffman_literals_weights_tmp2_ram_wr_mask), + .rd_data(huffman_literals_weights_tmp2_ram_rd_data), + .rd_addr(huffman_literals_weights_tmp2_ram_rd_addr), + .rd_en(huffman_literals_weights_tmp2_ram_rd_en), + .rd_mask(huffman_literals_weights_tmp2_ram_rd_mask) + ); + + // RAM instance for huffman_literals_weights_fse_ram + logic [31:0] huffman_literals_weights_fse_ram_wr_data; + logic [7:0] huffman_literals_weights_fse_ram_wr_addr; + logic huffman_literals_weights_fse_ram_wr_en; + logic huffman_literals_weights_fse_ram_wr_mask; + logic [31:0] huffman_literals_weights_fse_ram_rd_data; + logic [7:0] huffman_literals_weights_fse_ram_rd_addr; + logic huffman_literals_weights_fse_ram_rd_en; + logic huffman_literals_weights_fse_ram_rd_mask; + + ram_1r1w #( + .DATA_WIDTH(32), + .SIZE(256), + .NUM_PARTITIONS(1), + .ADDR_WIDTH(8) + ) huffman_literals_weights_fse_ram_ram ( + .clk(clk), + .rst(rst), + .wr_data(huffman_literals_weights_fse_ram_wr_data), + .wr_addr(huffman_literals_weights_fse_ram_wr_addr), + .wr_en(huffman_literals_weights_fse_ram_wr_en), + .wr_mask(huffman_literals_weights_fse_ram_wr_mask), + .rd_data(huffman_literals_weights_fse_ram_rd_data), + .rd_addr(huffman_literals_weights_fse_ram_rd_addr), + .rd_en(huffman_literals_weights_fse_ram_rd_en), + .rd_mask(huffman_literals_weights_fse_ram_rd_mask) + ); + /* * ZSTD Decoder instance */ + + ZstdDecoder ZstdDecoder ( - .clk(clk), - .rst(rst), + .clk(clk), + .rst(rst), - // CSR Interface - .zstd_dec__csr_axi_aw_r(zstd_dec__csr_axi_aw), - .zstd_dec__csr_axi_aw_r_vld(zstd_dec__csr_axi_aw_vld), - .zstd_dec__csr_axi_aw_r_rdy(zstd_dec__csr_axi_aw_rdy), - .zstd_dec__csr_axi_w_r(zstd_dec__csr_axi_w), - .zstd_dec__csr_axi_w_r_vld(zstd_dec__csr_axi_w_vld), - .zstd_dec__csr_axi_w_r_rdy(zstd_dec__csr_axi_w_rdy), - .zstd_dec__csr_axi_b_s(zstd_dec__csr_axi_b), - .zstd_dec__csr_axi_b_s_vld(zstd_dec__csr_axi_b_vld), - .zstd_dec__csr_axi_b_s_rdy(zstd_dec__csr_axi_b_rdy), - .zstd_dec__csr_axi_ar_r(zstd_dec__csr_axi_ar), - .zstd_dec__csr_axi_ar_r_vld(zstd_dec__csr_axi_ar_vld), - .zstd_dec__csr_axi_ar_r_rdy(zstd_dec__csr_axi_ar_rdy), - .zstd_dec__csr_axi_r_s(zstd_dec__csr_axi_r), - .zstd_dec__csr_axi_r_s_vld(zstd_dec__csr_axi_r_vld), - .zstd_dec__csr_axi_r_s_rdy(zstd_dec__csr_axi_r_rdy), + .zstd_dec__axi_ram_ar_s__0(zstd_dec__axi_ram_ar_s__0), + .zstd_dec__axi_ram_ar_s__0_vld(zstd_dec__axi_ram_ar_s__0_vld), + .zstd_dec__axi_ram_ar_s__0_rdy(zstd_dec__axi_ram_ar_s__0_rdy), + .zstd_dec__axi_ram_r_r__0(zstd_dec__axi_ram_r_r__0), + .zstd_dec__axi_ram_r_r__0_vld(zstd_dec__axi_ram_r_r__0_vld), + .zstd_dec__axi_ram_r_r__0_rdy(zstd_dec__axi_ram_r_r__0_rdy), - // FrameHeaderDecoder - .zstd_dec__fh_axi_ar_s(zstd_dec__fh_axi_ar), - .zstd_dec__fh_axi_ar_s_vld(zstd_dec__fh_axi_ar_vld), - .zstd_dec__fh_axi_ar_s_rdy(zstd_dec__fh_axi_ar_rdy), - .zstd_dec__fh_axi_r_r(zstd_dec__fh_axi_r), - .zstd_dec__fh_axi_r_r_vld(zstd_dec__fh_axi_r_vld), - .zstd_dec__fh_axi_r_r_rdy(zstd_dec__fh_axi_r_rdy), + .zstd_dec__axi_ram_ar_s__1(zstd_dec__axi_ram_ar_s__1), + .zstd_dec__axi_ram_ar_s__1_vld(zstd_dec__axi_ram_ar_s__1_vld), + .zstd_dec__axi_ram_ar_s__1_rdy(zstd_dec__axi_ram_ar_s__1_rdy), + .zstd_dec__axi_ram_r_r__1(zstd_dec__axi_ram_r_r__1), + .zstd_dec__axi_ram_r_r__1_vld(zstd_dec__axi_ram_r_r__1_vld), + .zstd_dec__axi_ram_r_r__1_rdy(zstd_dec__axi_ram_r_r__1_rdy), - // BlockHeaderDecoder - .zstd_dec__bh_axi_ar_s(zstd_dec__bh_axi_ar), - .zstd_dec__bh_axi_ar_s_vld(zstd_dec__bh_axi_ar_vld), - .zstd_dec__bh_axi_ar_s_rdy(zstd_dec__bh_axi_ar_rdy), - .zstd_dec__bh_axi_r_r(zstd_dec__bh_axi_r), - .zstd_dec__bh_axi_r_r_vld(zstd_dec__bh_axi_r_vld), - .zstd_dec__bh_axi_r_r_rdy(zstd_dec__bh_axi_r_rdy), + .zstd_dec__axi_ram_ar_s__2(zstd_dec__axi_ram_ar_s__2), + .zstd_dec__axi_ram_ar_s__2_vld(zstd_dec__axi_ram_ar_s__2_vld), + .zstd_dec__axi_ram_ar_s__2_rdy(zstd_dec__axi_ram_ar_s__2_rdy), + .zstd_dec__axi_ram_r_r__2(zstd_dec__axi_ram_r_r__2), + .zstd_dec__axi_ram_r_r__2_vld(zstd_dec__axi_ram_r_r__2_vld), + .zstd_dec__axi_ram_r_r__2_rdy(zstd_dec__axi_ram_r_r__2_rdy), - // RawBlockDecoder - .zstd_dec__raw_axi_ar_s(zstd_dec__raw_axi_ar), - .zstd_dec__raw_axi_ar_s_vld(zstd_dec__raw_axi_ar_vld), - .zstd_dec__raw_axi_ar_s_rdy(zstd_dec__raw_axi_ar_rdy), - .zstd_dec__raw_axi_r_r(zstd_dec__raw_axi_r), - .zstd_dec__raw_axi_r_r_vld(zstd_dec__raw_axi_r_vld), - .zstd_dec__raw_axi_r_r_rdy(zstd_dec__raw_axi_r_rdy), - - // Output Writer - .zstd_dec__output_axi_aw_s(zstd_dec__output_axi_aw), - .zstd_dec__output_axi_aw_s_vld(zstd_dec__output_axi_aw_vld), - .zstd_dec__output_axi_aw_s_rdy(zstd_dec__output_axi_aw_rdy), - .zstd_dec__output_axi_w_s(zstd_dec__output_axi_w), - .zstd_dec__output_axi_w_s_vld(zstd_dec__output_axi_w_vld), - .zstd_dec__output_axi_w_s_rdy(zstd_dec__output_axi_w_rdy), - .zstd_dec__output_axi_b_r(zstd_dec__output_axi_b), - .zstd_dec__output_axi_b_r_vld(zstd_dec__output_axi_b_vld), - .zstd_dec__output_axi_b_r_rdy(zstd_dec__output_axi_b_rdy), - - // Other ports - .zstd_dec__notify_s_vld(notify_vld), - .zstd_dec__notify_s_rdy(notify_rdy) + .zstd_dec__axi_ram_ar_s__3(zstd_dec__axi_ram_ar_s__3), + .zstd_dec__axi_ram_ar_s__3_vld(zstd_dec__axi_ram_ar_s__3_vld), + .zstd_dec__axi_ram_ar_s__3_rdy(zstd_dec__axi_ram_ar_s__3_rdy), + .zstd_dec__axi_ram_r_r__3(zstd_dec__axi_ram_r_r__3), + .zstd_dec__axi_ram_r_r__3_vld(zstd_dec__axi_ram_r_r__3_vld), + .zstd_dec__axi_ram_r_r__3_rdy(zstd_dec__axi_ram_r_r__3_rdy), + + .zstd_dec__axi_ram_ar_s__4(zstd_dec__axi_ram_ar_s__4), + .zstd_dec__axi_ram_ar_s__4_vld(zstd_dec__axi_ram_ar_s__4_vld), + .zstd_dec__axi_ram_ar_s__4_rdy(zstd_dec__axi_ram_ar_s__4_rdy), + .zstd_dec__axi_ram_r_r__4(zstd_dec__axi_ram_r_r__4), + .zstd_dec__axi_ram_r_r__4_vld(zstd_dec__axi_ram_r_r__4_vld), + .zstd_dec__axi_ram_r_r__4_rdy(zstd_dec__axi_ram_r_r__4_rdy), + + .zstd_dec__axi_ram_ar_s__5(zstd_dec__axi_ram_ar_s__5), + .zstd_dec__axi_ram_ar_s__5_vld(zstd_dec__axi_ram_ar_s__5_vld), + .zstd_dec__axi_ram_ar_s__5_rdy(zstd_dec__axi_ram_ar_s__5_rdy), + .zstd_dec__axi_ram_r_r__5(zstd_dec__axi_ram_r_r__5), + .zstd_dec__axi_ram_r_r__5_vld(zstd_dec__axi_ram_r_r__5_vld), + .zstd_dec__axi_ram_r_r__5_rdy(zstd_dec__axi_ram_r_r__5_rdy), + + .zstd_dec__axi_ram_ar_s__6(zstd_dec__axi_ram_ar_s__6), + .zstd_dec__axi_ram_ar_s__6_vld(zstd_dec__axi_ram_ar_s__6_vld), + .zstd_dec__axi_ram_ar_s__6_rdy(zstd_dec__axi_ram_ar_s__6_rdy), + .zstd_dec__axi_ram_r_r__6(zstd_dec__axi_ram_r_r__6), + .zstd_dec__axi_ram_r_r__6_vld(zstd_dec__axi_ram_r_r__6_vld), + .zstd_dec__axi_ram_r_r__6_rdy(zstd_dec__axi_ram_r_r__6_rdy), + + .zstd_dec__axi_ram_ar_s__7(zstd_dec__axi_ram_ar_s__7), + .zstd_dec__axi_ram_ar_s__7_vld(zstd_dec__axi_ram_ar_s__7_vld), + .zstd_dec__axi_ram_ar_s__7_rdy(zstd_dec__axi_ram_ar_s__7_rdy), + .zstd_dec__axi_ram_r_r__7(zstd_dec__axi_ram_r_r__7), + .zstd_dec__axi_ram_r_r__7_vld(zstd_dec__axi_ram_r_r__7_vld), + .zstd_dec__axi_ram_r_r__7_rdy(zstd_dec__axi_ram_r_r__7_rdy), + + .zstd_dec__axi_ram_ar_s__8(zstd_dec__axi_ram_ar_s__8), + .zstd_dec__axi_ram_ar_s__8_vld(zstd_dec__axi_ram_ar_s__8_vld), + .zstd_dec__axi_ram_ar_s__8_rdy(zstd_dec__axi_ram_ar_s__8_rdy), + .zstd_dec__axi_ram_r_r__8(zstd_dec__axi_ram_r_r__8), + .zstd_dec__axi_ram_r_r__8_vld(zstd_dec__axi_ram_r_r__8_vld), + .zstd_dec__axi_ram_r_r__8_rdy(zstd_dec__axi_ram_r_r__8_rdy), + + .zstd_dec__axi_ram_ar_s__9(zstd_dec__axi_ram_ar_s__9), + .zstd_dec__axi_ram_ar_s__9_vld(zstd_dec__axi_ram_ar_s__9_vld), + .zstd_dec__axi_ram_ar_s__9_rdy(zstd_dec__axi_ram_ar_s__9_rdy), + .zstd_dec__axi_ram_r_r__9(zstd_dec__axi_ram_r_r__9), + .zstd_dec__axi_ram_r_r__9_vld(zstd_dec__axi_ram_r_r__9_vld), + .zstd_dec__axi_ram_r_r__9_rdy(zstd_dec__axi_ram_r_r__9_rdy), + + .zstd_dec__axi_ram_ar_s__10(zstd_dec__axi_ram_ar_s__10), + .zstd_dec__axi_ram_ar_s__10_vld(zstd_dec__axi_ram_ar_s__10_vld), + .zstd_dec__axi_ram_ar_s__10_rdy(zstd_dec__axi_ram_ar_s__10_rdy), + .zstd_dec__axi_ram_r_r__10(zstd_dec__axi_ram_r_r__10), + .zstd_dec__axi_ram_r_r__10_vld(zstd_dec__axi_ram_r_r__10_vld), + .zstd_dec__axi_ram_r_r__10_rdy(zstd_dec__axi_ram_r_r__10_rdy), + + // Huffman literals memories + .huffman_literals_weights_dpd_ram_rd_data(huffman_literals_weights_dpd_ram_rd_data), + .huffman_literals_weights_dpd_ram_rd_addr(huffman_literals_weights_dpd_ram_rd_addr), + .huffman_literals_weights_dpd_ram_rd_mask(huffman_literals_weights_dpd_ram_rd_mask), + .huffman_literals_weights_dpd_ram_rd_en(huffman_literals_weights_dpd_ram_rd_en), + .huffman_literals_weights_dpd_ram_wr_addr(huffman_literals_weights_dpd_ram_wr_addr), + .huffman_literals_weights_dpd_ram_wr_data(huffman_literals_weights_dpd_ram_wr_data), + .huffman_literals_weights_dpd_ram_wr_mask(huffman_literals_weights_dpd_ram_wr_mask), + .huffman_literals_weights_dpd_ram_wr_en(huffman_literals_weights_dpd_ram_wr_en), + + .huffman_literals_weights_tmp_ram_rd_data(huffman_literals_weights_tmp_ram_rd_data), + .huffman_literals_weights_tmp_ram_rd_addr(huffman_literals_weights_tmp_ram_rd_addr), + .huffman_literals_weights_tmp_ram_rd_mask(huffman_literals_weights_tmp_ram_rd_mask), + .huffman_literals_weights_tmp_ram_rd_en(huffman_literals_weights_tmp_ram_rd_en), + .huffman_literals_weights_tmp_ram_wr_addr(huffman_literals_weights_tmp_ram_wr_addr), + .huffman_literals_weights_tmp_ram_wr_data(huffman_literals_weights_tmp_ram_wr_data), + .huffman_literals_weights_tmp_ram_wr_mask(huffman_literals_weights_tmp_ram_wr_mask), + .huffman_literals_weights_tmp_ram_wr_en(huffman_literals_weights_tmp_ram_wr_en), + + .huffman_literals_weights_tmp2_ram_rd_data(huffman_literals_weights_tmp2_ram_rd_data), + .huffman_literals_weights_tmp2_ram_rd_addr(huffman_literals_weights_tmp2_ram_rd_addr), + .huffman_literals_weights_tmp2_ram_rd_mask(huffman_literals_weights_tmp2_ram_rd_mask), + .huffman_literals_weights_tmp2_ram_rd_en(huffman_literals_weights_tmp2_ram_rd_en), + .huffman_literals_weights_tmp2_ram_wr_addr(huffman_literals_weights_tmp2_ram_wr_addr), + .huffman_literals_weights_tmp2_ram_wr_data(huffman_literals_weights_tmp2_ram_wr_data), + .huffman_literals_weights_tmp2_ram_wr_mask(huffman_literals_weights_tmp2_ram_wr_mask), + .huffman_literals_weights_tmp2_ram_wr_en(huffman_literals_weights_tmp2_ram_wr_en), + + .huffman_literals_weights_fse_ram_rd_data(huffman_literals_weights_fse_ram_rd_data), + .huffman_literals_weights_fse_ram_rd_addr(huffman_literals_weights_fse_ram_rd_addr), + .huffman_literals_weights_fse_ram_rd_mask(huffman_literals_weights_fse_ram_rd_mask), + .huffman_literals_weights_fse_ram_rd_en(huffman_literals_weights_fse_ram_rd_en), + .huffman_literals_weights_fse_ram_wr_addr(huffman_literals_weights_fse_ram_wr_addr), + .huffman_literals_weights_fse_ram_wr_data(huffman_literals_weights_fse_ram_wr_data), + .huffman_literals_weights_fse_ram_wr_mask(huffman_literals_weights_fse_ram_wr_mask), + .huffman_literals_weights_fse_ram_wr_en(huffman_literals_weights_fse_ram_wr_en), + + // History buffers memories + .history_buffer_ram0_rd_data(history_buffer_ram0_rd_data), + .history_buffer_ram0_rd_addr(history_buffer_ram0_rd_addr), + .history_buffer_ram0_rd_mask(history_buffer_ram0_rd_mask), + .history_buffer_ram0_rd_en(history_buffer_ram0_rd_en), + .history_buffer_ram0_wr_addr(history_buffer_ram0_wr_addr), + .history_buffer_ram0_wr_data(history_buffer_ram0_wr_data), + .history_buffer_ram0_wr_mask(history_buffer_ram0_wr_mask), + .history_buffer_ram0_wr_en(history_buffer_ram0_wr_en), + + .history_buffer_ram1_rd_data(history_buffer_ram1_rd_data), + .history_buffer_ram1_rd_addr(history_buffer_ram1_rd_addr), + .history_buffer_ram1_rd_mask(history_buffer_ram1_rd_mask), + .history_buffer_ram1_rd_en(history_buffer_ram1_rd_en), + .history_buffer_ram1_wr_addr(history_buffer_ram1_wr_addr), + .history_buffer_ram1_wr_data(history_buffer_ram1_wr_data), + .history_buffer_ram1_wr_mask(history_buffer_ram1_wr_mask), + .history_buffer_ram1_wr_en(history_buffer_ram1_wr_en), + + .history_buffer_ram2_rd_data(history_buffer_ram2_rd_data), + .history_buffer_ram2_rd_addr(history_buffer_ram2_rd_addr), + .history_buffer_ram2_rd_mask(history_buffer_ram2_rd_mask), + .history_buffer_ram2_rd_en(history_buffer_ram2_rd_en), + .history_buffer_ram2_wr_addr(history_buffer_ram2_wr_addr), + .history_buffer_ram2_wr_data(history_buffer_ram2_wr_data), + .history_buffer_ram2_wr_mask(history_buffer_ram2_wr_mask), + .history_buffer_ram2_wr_en(history_buffer_ram2_wr_en), + + .history_buffer_ram3_rd_data(history_buffer_ram3_rd_data), + .history_buffer_ram3_rd_addr(history_buffer_ram3_rd_addr), + .history_buffer_ram3_rd_mask(history_buffer_ram3_rd_mask), + .history_buffer_ram3_rd_en(history_buffer_ram3_rd_en), + .history_buffer_ram3_wr_addr(history_buffer_ram3_wr_addr), + .history_buffer_ram3_wr_data(history_buffer_ram3_wr_data), + .history_buffer_ram3_wr_mask(history_buffer_ram3_wr_mask), + .history_buffer_ram3_wr_en(history_buffer_ram3_wr_en), + + .history_buffer_ram4_rd_data(history_buffer_ram4_rd_data), + .history_buffer_ram4_rd_addr(history_buffer_ram4_rd_addr), + .history_buffer_ram4_rd_mask(history_buffer_ram4_rd_mask), + .history_buffer_ram4_rd_en(history_buffer_ram4_rd_en), + .history_buffer_ram4_wr_addr(history_buffer_ram4_wr_addr), + .history_buffer_ram4_wr_data(history_buffer_ram4_wr_data), + .history_buffer_ram4_wr_mask(history_buffer_ram4_wr_mask), + .history_buffer_ram4_wr_en(history_buffer_ram4_wr_en), + + .history_buffer_ram5_rd_data(history_buffer_ram5_rd_data), + .history_buffer_ram5_rd_addr(history_buffer_ram5_rd_addr), + .history_buffer_ram5_rd_mask(history_buffer_ram5_rd_mask), + .history_buffer_ram5_rd_en(history_buffer_ram5_rd_en), + .history_buffer_ram5_wr_addr(history_buffer_ram5_wr_addr), + .history_buffer_ram5_wr_data(history_buffer_ram5_wr_data), + .history_buffer_ram5_wr_mask(history_buffer_ram5_wr_mask), + .history_buffer_ram5_wr_en(history_buffer_ram5_wr_en), + + .history_buffer_ram6_rd_data(history_buffer_ram6_rd_data), + .history_buffer_ram6_rd_addr(history_buffer_ram6_rd_addr), + .history_buffer_ram6_rd_mask(history_buffer_ram6_rd_mask), + .history_buffer_ram6_rd_en(history_buffer_ram6_rd_en), + .history_buffer_ram6_wr_addr(history_buffer_ram6_wr_addr), + .history_buffer_ram6_wr_data(history_buffer_ram6_wr_data), + .history_buffer_ram6_wr_mask(history_buffer_ram6_wr_mask), + .history_buffer_ram6_wr_en(history_buffer_ram6_wr_en), + + .history_buffer_ram7_rd_data(history_buffer_ram7_rd_data), + .history_buffer_ram7_rd_addr(history_buffer_ram7_rd_addr), + .history_buffer_ram7_rd_mask(history_buffer_ram7_rd_mask), + .history_buffer_ram7_rd_en(history_buffer_ram7_rd_en), + .history_buffer_ram7_wr_addr(history_buffer_ram7_wr_addr), + .history_buffer_ram7_wr_data(history_buffer_ram7_wr_data), + .history_buffer_ram7_wr_mask(history_buffer_ram7_wr_mask), + .history_buffer_ram7_wr_en(history_buffer_ram7_wr_en), + + .dpd_ram_rd_data(dpd_ram_rd_data), + .dpd_ram_rd_addr(dpd_ram_rd_addr), + .dpd_ram_rd_mask(dpd_ram_rd_mask), + .dpd_ram_rd_en(dpd_ram_rd_en), + .dpd_ram_wr_addr(dpd_ram_wr_addr), + .dpd_ram_wr_data(dpd_ram_wr_data), + .dpd_ram_wr_mask(dpd_ram_wr_mask), + .dpd_ram_wr_en(dpd_ram_wr_en), + + .fse_tmp_ram_rd_data(fse_tmp_ram_rd_data), + .fse_tmp_ram_rd_addr(fse_tmp_ram_rd_addr), + .fse_tmp_ram_rd_mask(fse_tmp_ram_rd_mask), + .fse_tmp_ram_rd_en(fse_tmp_ram_rd_en), + .fse_tmp_ram_wr_addr(fse_tmp_ram_wr_addr), + .fse_tmp_ram_wr_data(fse_tmp_ram_wr_data), + .fse_tmp_ram_wr_mask(fse_tmp_ram_wr_mask), + .fse_tmp_ram_wr_en(fse_tmp_ram_wr_en), + + .fse_tmp2_ram_rd_data(fse_tmp2_ram_rd_data), + .fse_tmp2_ram_rd_addr(fse_tmp2_ram_rd_addr), + .fse_tmp2_ram_rd_mask(fse_tmp2_ram_rd_mask), + .fse_tmp2_ram_rd_en(fse_tmp2_ram_rd_en), + .fse_tmp2_ram_wr_addr(fse_tmp2_ram_wr_addr), + .fse_tmp2_ram_wr_data(fse_tmp2_ram_wr_data), + .fse_tmp2_ram_wr_mask(fse_tmp2_ram_wr_mask), + .fse_tmp2_ram_wr_en(fse_tmp2_ram_wr_en), + + .ll_def_fse_ram_rd_data(ll_def_fse_ram_rd_data), + .ll_def_fse_ram_rd_addr(ll_def_fse_ram_rd_addr), + .ll_def_fse_ram_rd_mask(ll_def_fse_ram_rd_mask), + .ll_def_fse_ram_rd_en(ll_def_fse_ram_rd_en), + .ll_def_fse_ram_wr_addr(ll_def_fse_ram_wr_addr), + .ll_def_fse_ram_wr_data(ll_def_fse_ram_wr_data), + .ll_def_fse_ram_wr_mask(ll_def_fse_ram_wr_mask), + .ll_def_fse_ram_wr_en(ll_def_fse_ram_wr_en), + + .ll_fse_ram_rd_data(ll_fse_ram_rd_data), + .ll_fse_ram_rd_addr(ll_fse_ram_rd_addr), + .ll_fse_ram_rd_mask(ll_fse_ram_rd_mask), + .ll_fse_ram_rd_en(ll_fse_ram_rd_en), + .ll_fse_ram_wr_addr(ll_fse_ram_wr_addr), + .ll_fse_ram_wr_data(ll_fse_ram_wr_data), + .ll_fse_ram_wr_mask(ll_fse_ram_wr_mask), + .ll_fse_ram_wr_en(ll_fse_ram_wr_en), + + .ml_def_fse_ram_rd_data(ml_def_fse_ram_rd_data), + .ml_def_fse_ram_rd_addr(ml_def_fse_ram_rd_addr), + .ml_def_fse_ram_rd_mask(ml_def_fse_ram_rd_mask), + .ml_def_fse_ram_rd_en(ml_def_fse_ram_rd_en), + .ml_def_fse_ram_wr_addr(ml_def_fse_ram_wr_addr), + .ml_def_fse_ram_wr_data(ml_def_fse_ram_wr_data), + .ml_def_fse_ram_wr_mask(ml_def_fse_ram_wr_mask), + .ml_def_fse_ram_wr_en(ml_def_fse_ram_wr_en), + + .ml_fse_ram_rd_data(ml_fse_ram_rd_data), + .ml_fse_ram_rd_addr(ml_fse_ram_rd_addr), + .ml_fse_ram_rd_mask(ml_fse_ram_rd_mask), + .ml_fse_ram_rd_en(ml_fse_ram_rd_en), + .ml_fse_ram_wr_addr(ml_fse_ram_wr_addr), + .ml_fse_ram_wr_data(ml_fse_ram_wr_data), + .ml_fse_ram_wr_mask(ml_fse_ram_wr_mask), + .ml_fse_ram_wr_en(ml_fse_ram_wr_en), + + .of_def_fse_ram_rd_data(of_def_fse_ram_rd_data), + .of_def_fse_ram_rd_addr(of_def_fse_ram_rd_addr), + .of_def_fse_ram_rd_mask(of_def_fse_ram_rd_mask), + .of_def_fse_ram_rd_en(of_def_fse_ram_rd_en), + .of_def_fse_ram_wr_addr(of_def_fse_ram_wr_addr), + .of_def_fse_ram_wr_data(of_def_fse_ram_wr_data), + .of_def_fse_ram_wr_mask(of_def_fse_ram_wr_mask), + .of_def_fse_ram_wr_en(of_def_fse_ram_wr_en), + + .of_fse_ram_rd_data(of_fse_ram_rd_data), + .of_fse_ram_rd_addr(of_fse_ram_rd_addr), + .of_fse_ram_rd_mask(of_fse_ram_rd_mask), + .of_fse_ram_rd_en(of_fse_ram_rd_en), + .of_fse_ram_wr_addr(of_fse_ram_wr_addr), + .of_fse_ram_wr_data(of_fse_ram_wr_data), + .of_fse_ram_wr_mask(of_fse_ram_wr_mask), + .of_fse_ram_wr_en(of_fse_ram_wr_en), + + .huffman_literals_prescan_ram_rd_data(huffman_literals_prescan_ram_rd_data), + .huffman_literals_prescan_ram_rd_addr(huffman_literals_prescan_ram_rd_addr), + .huffman_literals_prescan_ram_rd_mask(huffman_literals_prescan_ram_rd_mask), + .huffman_literals_prescan_ram_rd_en(huffman_literals_prescan_ram_rd_en), + .huffman_literals_prescan_ram_wr_addr(huffman_literals_prescan_ram_wr_addr), + .huffman_literals_prescan_ram_wr_data(huffman_literals_prescan_ram_wr_data), + .huffman_literals_prescan_ram_wr_mask(huffman_literals_prescan_ram_wr_mask), + .huffman_literals_prescan_ram_wr_en(huffman_literals_prescan_ram_wr_en), + + .huffman_literals_weights_mem_ram_rd_data(huffman_literals_weights_mem_ram_rd_data), + .huffman_literals_weights_mem_ram_rd_addr(huffman_literals_weights_mem_ram_rd_addr), + .huffman_literals_weights_mem_ram_rd_mask(huffman_literals_weights_mem_ram_rd_mask), + .huffman_literals_weights_mem_ram_rd_en(huffman_literals_weights_mem_ram_rd_en), + .huffman_literals_weights_mem_ram_wr_addr(huffman_literals_weights_mem_ram_wr_addr), + .huffman_literals_weights_mem_ram_wr_data(huffman_literals_weights_mem_ram_wr_data), + .huffman_literals_weights_mem_ram_wr_mask(huffman_literals_weights_mem_ram_wr_mask), + .huffman_literals_weights_mem_ram_wr_en(huffman_literals_weights_mem_ram_wr_en), + + .literals_buffer_ram0_rd_data(literals_buffer_ram0_rd_data), + .literals_buffer_ram0_rd_addr(literals_buffer_ram0_rd_addr), + .literals_buffer_ram0_rd_mask(literals_buffer_ram0_rd_mask), + .literals_buffer_ram0_rd_en(literals_buffer_ram0_rd_en), + .literals_buffer_ram0_wr_addr(literals_buffer_ram0_wr_addr), + .literals_buffer_ram0_wr_data(literals_buffer_ram0_wr_data), + .literals_buffer_ram0_wr_mask(literals_buffer_ram0_wr_mask), + .literals_buffer_ram0_wr_en(literals_buffer_ram0_wr_en), + + .literals_buffer_ram1_rd_data(literals_buffer_ram1_rd_data), + .literals_buffer_ram1_rd_addr(literals_buffer_ram1_rd_addr), + .literals_buffer_ram1_rd_mask(literals_buffer_ram1_rd_mask), + .literals_buffer_ram1_rd_en(literals_buffer_ram1_rd_en), + .literals_buffer_ram1_wr_addr(literals_buffer_ram1_wr_addr), + .literals_buffer_ram1_wr_data(literals_buffer_ram1_wr_data), + .literals_buffer_ram1_wr_mask(literals_buffer_ram1_wr_mask), + .literals_buffer_ram1_wr_en(literals_buffer_ram1_wr_en), + + .literals_buffer_ram2_rd_data(literals_buffer_ram2_rd_data), + .literals_buffer_ram2_rd_addr(literals_buffer_ram2_rd_addr), + .literals_buffer_ram2_rd_mask(literals_buffer_ram2_rd_mask), + .literals_buffer_ram2_rd_en(literals_buffer_ram2_rd_en), + .literals_buffer_ram2_wr_addr(literals_buffer_ram2_wr_addr), + .literals_buffer_ram2_wr_data(literals_buffer_ram2_wr_data), + .literals_buffer_ram2_wr_mask(literals_buffer_ram2_wr_mask), + .literals_buffer_ram2_wr_en(literals_buffer_ram2_wr_en), + + .literals_buffer_ram3_rd_data(literals_buffer_ram3_rd_data), + .literals_buffer_ram3_rd_addr(literals_buffer_ram3_rd_addr), + .literals_buffer_ram3_rd_mask(literals_buffer_ram3_rd_mask), + .literals_buffer_ram3_rd_en(literals_buffer_ram3_rd_en), + .literals_buffer_ram3_wr_addr(literals_buffer_ram3_wr_addr), + .literals_buffer_ram3_wr_data(literals_buffer_ram3_wr_data), + .literals_buffer_ram3_wr_mask(literals_buffer_ram3_wr_mask), + .literals_buffer_ram3_wr_en(literals_buffer_ram3_wr_en), + + .literals_buffer_ram4_rd_data(literals_buffer_ram4_rd_data), + .literals_buffer_ram4_rd_addr(literals_buffer_ram4_rd_addr), + .literals_buffer_ram4_rd_mask(literals_buffer_ram4_rd_mask), + .literals_buffer_ram4_rd_en(literals_buffer_ram4_rd_en), + .literals_buffer_ram4_wr_addr(literals_buffer_ram4_wr_addr), + .literals_buffer_ram4_wr_data(literals_buffer_ram4_wr_data), + .literals_buffer_ram4_wr_mask(literals_buffer_ram4_wr_mask), + .literals_buffer_ram4_wr_en(literals_buffer_ram4_wr_en), + + .literals_buffer_ram5_rd_data(literals_buffer_ram5_rd_data), + .literals_buffer_ram5_rd_addr(literals_buffer_ram5_rd_addr), + .literals_buffer_ram5_rd_mask(literals_buffer_ram5_rd_mask), + .literals_buffer_ram5_rd_en(literals_buffer_ram5_rd_en), + .literals_buffer_ram5_wr_addr(literals_buffer_ram5_wr_addr), + .literals_buffer_ram5_wr_data(literals_buffer_ram5_wr_data), + .literals_buffer_ram5_wr_mask(literals_buffer_ram5_wr_mask), + .literals_buffer_ram5_wr_en(literals_buffer_ram5_wr_en), + + .literals_buffer_ram6_rd_data(literals_buffer_ram6_rd_data), + .literals_buffer_ram6_rd_addr(literals_buffer_ram6_rd_addr), + .literals_buffer_ram6_rd_mask(literals_buffer_ram6_rd_mask), + .literals_buffer_ram6_rd_en(literals_buffer_ram6_rd_en), + .literals_buffer_ram6_wr_addr(literals_buffer_ram6_wr_addr), + .literals_buffer_ram6_wr_data(literals_buffer_ram6_wr_data), + .literals_buffer_ram6_wr_mask(literals_buffer_ram6_wr_mask), + .literals_buffer_ram6_wr_en(literals_buffer_ram6_wr_en), + + .literals_buffer_ram7_rd_data(literals_buffer_ram7_rd_data), + .literals_buffer_ram7_rd_addr(literals_buffer_ram7_rd_addr), + .literals_buffer_ram7_rd_mask(literals_buffer_ram7_rd_mask), + .literals_buffer_ram7_rd_en(literals_buffer_ram7_rd_en), + .literals_buffer_ram7_wr_addr(literals_buffer_ram7_wr_addr), + .literals_buffer_ram7_wr_data(literals_buffer_ram7_wr_data), + .literals_buffer_ram7_wr_mask(literals_buffer_ram7_wr_mask), + .literals_buffer_ram7_wr_en(literals_buffer_ram7_wr_en), + + // CSR Interface + .zstd_dec__csr_axi_aw_r(zstd_dec__csr_axi_aw), + .zstd_dec__csr_axi_aw_r_vld(zstd_dec__csr_axi_aw_vld), + .zstd_dec__csr_axi_aw_r_rdy(zstd_dec__csr_axi_aw_rdy), + .zstd_dec__csr_axi_w_r(zstd_dec__csr_axi_w), + .zstd_dec__csr_axi_w_r_vld(zstd_dec__csr_axi_w_vld), + .zstd_dec__csr_axi_w_r_rdy(zstd_dec__csr_axi_w_rdy), + .zstd_dec__csr_axi_b_s(zstd_dec__csr_axi_b), + .zstd_dec__csr_axi_b_s_vld(zstd_dec__csr_axi_b_vld), + .zstd_dec__csr_axi_b_s_rdy(zstd_dec__csr_axi_b_rdy), + .zstd_dec__csr_axi_ar_r(zstd_dec__csr_axi_ar), + .zstd_dec__csr_axi_ar_r_vld(zstd_dec__csr_axi_ar_vld), + .zstd_dec__csr_axi_ar_r_rdy(zstd_dec__csr_axi_ar_rdy), + .zstd_dec__csr_axi_r_s(zstd_dec__csr_axi_r), + .zstd_dec__csr_axi_r_s_vld(zstd_dec__csr_axi_r_vld), + .zstd_dec__csr_axi_r_s_rdy(zstd_dec__csr_axi_r_rdy), + + // FrameHeaderDecoder + .zstd_dec__fh_axi_ar_s(zstd_dec__fh_axi_ar), + .zstd_dec__fh_axi_ar_s_vld(zstd_dec__fh_axi_ar_vld), + .zstd_dec__fh_axi_ar_s_rdy(zstd_dec__fh_axi_ar_rdy), + .zstd_dec__fh_axi_r_r(zstd_dec__fh_axi_r), + .zstd_dec__fh_axi_r_r_vld(zstd_dec__fh_axi_r_vld), + .zstd_dec__fh_axi_r_r_rdy(zstd_dec__fh_axi_r_rdy), + + // BlockHeaderDecoder + .zstd_dec__bh_axi_ar_s(zstd_dec__bh_axi_ar), + .zstd_dec__bh_axi_ar_s_vld(zstd_dec__bh_axi_ar_vld), + .zstd_dec__bh_axi_ar_s_rdy(zstd_dec__bh_axi_ar_rdy), + .zstd_dec__bh_axi_r_r(zstd_dec__bh_axi_r), + .zstd_dec__bh_axi_r_r_vld(zstd_dec__bh_axi_r_vld), + .zstd_dec__bh_axi_r_r_rdy(zstd_dec__bh_axi_r_rdy), + + // RawBlockDecoder + .zstd_dec__raw_axi_ar_s(zstd_dec__raw_axi_ar), + .zstd_dec__raw_axi_ar_s_vld(zstd_dec__raw_axi_ar_vld), + .zstd_dec__raw_axi_ar_s_rdy(zstd_dec__raw_axi_ar_rdy), + .zstd_dec__raw_axi_r_r(zstd_dec__raw_axi_r), + .zstd_dec__raw_axi_r_r_vld(zstd_dec__raw_axi_r_vld), + .zstd_dec__raw_axi_r_r_rdy(zstd_dec__raw_axi_r_rdy), + + // Output Writer + .zstd_dec__output_axi_aw_s(zstd_dec__output_axi_aw), + .zstd_dec__output_axi_aw_s_vld(zstd_dec__output_axi_aw_vld), + .zstd_dec__output_axi_aw_s_rdy(zstd_dec__output_axi_aw_rdy), + .zstd_dec__output_axi_w_s(zstd_dec__output_axi_w), + .zstd_dec__output_axi_w_s_vld(zstd_dec__output_axi_w_vld), + .zstd_dec__output_axi_w_s_rdy(zstd_dec__output_axi_w_rdy), + .zstd_dec__output_axi_b_r(zstd_dec__output_axi_b), + .zstd_dec__output_axi_b_r_vld(zstd_dec__output_axi_b_vld), + .zstd_dec__output_axi_b_r_rdy(zstd_dec__output_axi_b_rdy), + + // Other ports + .zstd_dec__notify_s_vld(notify_vld), + .zstd_dec__notify_s_rdy(notify_rdy) ); assign frame_header_decoder_axi_r_rresp[2] = '0; @@ -499,6 +2285,9 @@ module zstd_dec_wrapper #( /* * AXI Interconnect */ + +// parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT), + axi_crossbar_wrapper #( .DATA_WIDTH(AXI_DATA_W), .ADDR_WIDTH(AXI_ADDR_W), @@ -531,7 +2320,7 @@ module zstd_dec_wrapper #( .s00_axi_wstrb('0), .s00_axi_wlast('0), .s00_axi_wuser('0), - .s00_axi_wvalid(), + .s00_axi_wvalid('0), .s00_axi_wready(), .s00_axi_bid(), .s00_axi_bresp(), @@ -575,7 +2364,7 @@ module zstd_dec_wrapper #( .s01_axi_wstrb('0), .s01_axi_wlast('0), .s01_axi_wuser('0), - .s01_axi_wvalid(), + .s01_axi_wvalid('0), .s01_axi_wready(), .s01_axi_bid(), .s01_axi_bresp(), @@ -619,7 +2408,7 @@ module zstd_dec_wrapper #( .s02_axi_wstrb('0), .s02_axi_wlast('0), .s02_axi_wuser('0), - .s02_axi_wvalid(), + .s02_axi_wvalid('0), .s02_axi_wready(), .s02_axi_bid(), .s02_axi_bresp(), @@ -666,7 +2455,7 @@ module zstd_dec_wrapper #( .s03_axi_wvalid(output_axi_w_wvalid), .s03_axi_wready(output_axi_w_wready), .s03_axi_bid(output_axi_b_bid), - .s03_axi_bresp(output_axi_b_bresp), + .s03_axi_bresp(output_axi_b_bresp[1:0]), .s03_axi_buser(), .s03_axi_bvalid(output_axi_b_bvalid), .s03_axi_bready(output_axi_b_bready), @@ -690,6 +2479,490 @@ module zstd_dec_wrapper #( .s03_axi_rvalid(), .s03_axi_rready('0), + // axi_ram_s__0 + .s04_axi_awid('0), + .s04_axi_awaddr('0), + .s04_axi_awlen('0), + .s04_axi_awsize('0), + .s04_axi_awburst('0), + .s04_axi_awlock('0), + .s04_axi_awcache('0), + .s04_axi_awprot('0), + .s04_axi_awqos('0), + .s04_axi_awuser('0), + .s04_axi_awvalid('0), + .s04_axi_awready(), + .s04_axi_wdata('0), + .s04_axi_wstrb('0), + .s04_axi_wlast('0), + .s04_axi_wuser('0), + .s04_axi_wvalid('0), + .s04_axi_wready(), + .s04_axi_bid(), + .s04_axi_bresp(), + .s04_axi_buser(), + .s04_axi_bvalid(), + .s04_axi_bready('0), + .s04_axi_arid(axi_ram_s__0_axi_ar_arid), + .s04_axi_araddr(axi_ram_s__0_axi_ar_araddr), + .s04_axi_arlen(axi_ram_s__0_axi_ar_arlen), + .s04_axi_arsize(axi_ram_s__0_axi_ar_arsize), + .s04_axi_arburst(axi_ram_s__0_axi_ar_arburst), + .s04_axi_arlock('0), + .s04_axi_arcache(axi_ram_s__0_axi_ar_arcache), + .s04_axi_arprot(axi_ram_s__0_axi_ar_arprot), + .s04_axi_arqos(axi_ram_s__0_axi_ar_arqos), + .s04_axi_aruser('0), + .s04_axi_arvalid(axi_ram_s__0_axi_ar_arvalid), + .s04_axi_arready(axi_ram_s__0_axi_ar_arready), + .s04_axi_rid(axi_ram_s__0_axi_r_rid), + .s04_axi_rdata(axi_ram_s__0_axi_r_rdata), + .s04_axi_rresp(axi_ram_s__0_axi_r_rresp[1:0]), + .s04_axi_rlast(axi_ram_s__0_axi_r_rlast), + .s04_axi_ruser(), + .s04_axi_rvalid(axi_ram_s__0_axi_r_rvalid), + .s04_axi_rready(axi_ram_s__0_axi_r_rready), + + // axi_ram_s__1 + .s05_axi_awid('0), + .s05_axi_awaddr('0), + .s05_axi_awlen('0), + .s05_axi_awsize('0), + .s05_axi_awburst('0), + .s05_axi_awlock('0), + .s05_axi_awcache('0), + .s05_axi_awprot('0), + .s05_axi_awqos('0), + .s05_axi_awuser('0), + .s05_axi_awvalid('0), + .s05_axi_awready(), + .s05_axi_wdata('0), + .s05_axi_wstrb('0), + .s05_axi_wlast('0), + .s05_axi_wuser('0), + .s05_axi_wvalid('0), + .s05_axi_wready(), + .s05_axi_bid(), + .s05_axi_bresp(), + .s05_axi_buser(), + .s05_axi_bvalid(), + .s05_axi_bready('0), + .s05_axi_arid(axi_ram_s__1_axi_ar_arid), + .s05_axi_araddr(axi_ram_s__1_axi_ar_araddr), + .s05_axi_arlen(axi_ram_s__1_axi_ar_arlen), + .s05_axi_arsize(axi_ram_s__1_axi_ar_arsize), + .s05_axi_arburst(axi_ram_s__1_axi_ar_arburst), + .s05_axi_arlock('0), + .s05_axi_arcache(axi_ram_s__1_axi_ar_arcache), + .s05_axi_arprot(axi_ram_s__1_axi_ar_arprot), + .s05_axi_arqos(axi_ram_s__1_axi_ar_arqos), + .s05_axi_aruser('0), + .s05_axi_arvalid(axi_ram_s__1_axi_ar_arvalid), + .s05_axi_arready(axi_ram_s__1_axi_ar_arready), + .s05_axi_rid(axi_ram_s__1_axi_r_rid), + .s05_axi_rdata(axi_ram_s__1_axi_r_rdata), + .s05_axi_rresp(axi_ram_s__1_axi_r_rresp[1:0]), + .s05_axi_rlast(axi_ram_s__1_axi_r_rlast), + .s05_axi_ruser(), + .s05_axi_rvalid(axi_ram_s__1_axi_r_rvalid), + .s05_axi_rready(axi_ram_s__1_axi_r_rready), + + // axi_ram_s__2 + .s06_axi_awid('0), + .s06_axi_awaddr('0), + .s06_axi_awlen('0), + .s06_axi_awsize('0), + .s06_axi_awburst('0), + .s06_axi_awlock('0), + .s06_axi_awcache('0), + .s06_axi_awprot('0), + .s06_axi_awqos('0), + .s06_axi_awuser('0), + .s06_axi_awvalid('0), + .s06_axi_awready(), + .s06_axi_wdata('0), + .s06_axi_wstrb('0), + .s06_axi_wlast('0), + .s06_axi_wuser('0), + .s06_axi_wvalid('0), + .s06_axi_wready(), + .s06_axi_bid(), + .s06_axi_bresp(), + .s06_axi_buser(), + .s06_axi_bvalid(), + .s06_axi_bready('0), + .s06_axi_arid(axi_ram_s__2_axi_ar_arid), + .s06_axi_araddr(axi_ram_s__2_axi_ar_araddr), + .s06_axi_arlen(axi_ram_s__2_axi_ar_arlen), + .s06_axi_arsize(axi_ram_s__2_axi_ar_arsize), + .s06_axi_arburst(axi_ram_s__2_axi_ar_arburst), + .s06_axi_arlock('0), + .s06_axi_arcache(axi_ram_s__2_axi_ar_arcache), + .s06_axi_arprot(axi_ram_s__2_axi_ar_arprot), + .s06_axi_arqos(axi_ram_s__2_axi_ar_arqos), + .s06_axi_aruser('0), + .s06_axi_arvalid(axi_ram_s__2_axi_ar_arvalid), + .s06_axi_arready(axi_ram_s__2_axi_ar_arready), + .s06_axi_rid(axi_ram_s__2_axi_r_rid), + .s06_axi_rdata(axi_ram_s__2_axi_r_rdata), + .s06_axi_rresp(axi_ram_s__2_axi_r_rresp[1:0]), + .s06_axi_rlast(axi_ram_s__2_axi_r_rlast), + .s06_axi_ruser(), + .s06_axi_rvalid(axi_ram_s__2_axi_r_rvalid), + .s06_axi_rready(axi_ram_s__2_axi_r_rready), + + // axi_ram_s__3 + .s07_axi_awid('0), + .s07_axi_awaddr('0), + .s07_axi_awlen('0), + .s07_axi_awsize('0), + .s07_axi_awburst('0), + .s07_axi_awlock('0), + .s07_axi_awcache('0), + .s07_axi_awprot('0), + .s07_axi_awqos('0), + .s07_axi_awuser('0), + .s07_axi_awvalid('0), + .s07_axi_awready(), + .s07_axi_wdata('0), + .s07_axi_wstrb('0), + .s07_axi_wlast('0), + .s07_axi_wuser('0), + .s07_axi_wvalid('0), + .s07_axi_wready(), + .s07_axi_bid(), + .s07_axi_bresp(), + .s07_axi_buser(), + .s07_axi_bvalid(), + .s07_axi_bready('0), + .s07_axi_arid(axi_ram_s__3_axi_ar_arid), + .s07_axi_araddr(axi_ram_s__3_axi_ar_araddr), + .s07_axi_arlen(axi_ram_s__3_axi_ar_arlen), + .s07_axi_arsize(axi_ram_s__3_axi_ar_arsize), + .s07_axi_arburst(axi_ram_s__3_axi_ar_arburst), + .s07_axi_arlock('0), + .s07_axi_arcache(axi_ram_s__3_axi_ar_arcache), + .s07_axi_arprot(axi_ram_s__3_axi_ar_arprot), + .s07_axi_arqos(axi_ram_s__3_axi_ar_arqos), + .s07_axi_aruser('0), + .s07_axi_arvalid(axi_ram_s__3_axi_ar_arvalid), + .s07_axi_arready(axi_ram_s__3_axi_ar_arready), + .s07_axi_rid(axi_ram_s__3_axi_r_rid), + .s07_axi_rdata(axi_ram_s__3_axi_r_rdata), + .s07_axi_rresp(axi_ram_s__3_axi_r_rresp[1:0]), + .s07_axi_rlast(axi_ram_s__3_axi_r_rlast), + .s07_axi_ruser(), + .s07_axi_rvalid(axi_ram_s__3_axi_r_rvalid), + .s07_axi_rready(axi_ram_s__3_axi_r_rready), + + // axi_ram_s__4 + .s08_axi_awid('0), + .s08_axi_awaddr('0), + .s08_axi_awlen('0), + .s08_axi_awsize('0), + .s08_axi_awburst('0), + .s08_axi_awlock('0), + .s08_axi_awcache('0), + .s08_axi_awprot('0), + .s08_axi_awqos('0), + .s08_axi_awuser('0), + .s08_axi_awvalid('0), + .s08_axi_awready(), + .s08_axi_wdata('0), + .s08_axi_wstrb('0), + .s08_axi_wlast('0), + .s08_axi_wuser('0), + .s08_axi_wvalid('0), + .s08_axi_wready(), + .s08_axi_bid(), + .s08_axi_bresp(), + .s08_axi_buser(), + .s08_axi_bvalid(), + .s08_axi_bready('0), + .s08_axi_arid(axi_ram_s__4_axi_ar_arid), + .s08_axi_araddr(axi_ram_s__4_axi_ar_araddr), + .s08_axi_arlen(axi_ram_s__4_axi_ar_arlen), + .s08_axi_arsize(axi_ram_s__4_axi_ar_arsize), + .s08_axi_arburst(axi_ram_s__4_axi_ar_arburst), + .s08_axi_arlock('0), + .s08_axi_arcache(axi_ram_s__4_axi_ar_arcache), + .s08_axi_arprot(axi_ram_s__4_axi_ar_arprot), + .s08_axi_arqos(axi_ram_s__4_axi_ar_arqos), + .s08_axi_aruser('0), + .s08_axi_arvalid(axi_ram_s__4_axi_ar_arvalid), + .s08_axi_arready(axi_ram_s__4_axi_ar_arready), + .s08_axi_rid(axi_ram_s__4_axi_r_rid), + .s08_axi_rdata(axi_ram_s__4_axi_r_rdata), + .s08_axi_rresp(axi_ram_s__4_axi_r_rresp[1:0]), + .s08_axi_rlast(axi_ram_s__4_axi_r_rlast), + .s08_axi_ruser(), + .s08_axi_rvalid(axi_ram_s__4_axi_r_rvalid), + .s08_axi_rready(axi_ram_s__4_axi_r_rready), + + // axi_ram_s__5 + .s09_axi_awid('0), + .s09_axi_awaddr('0), + .s09_axi_awlen('0), + .s09_axi_awsize('0), + .s09_axi_awburst('0), + .s09_axi_awlock('0), + .s09_axi_awcache('0), + .s09_axi_awprot('0), + .s09_axi_awqos('0), + .s09_axi_awuser('0), + .s09_axi_awvalid('0), + .s09_axi_awready(), + .s09_axi_wdata('0), + .s09_axi_wstrb('0), + .s09_axi_wlast('0), + .s09_axi_wuser('0), + .s09_axi_wvalid('0), + .s09_axi_wready(), + .s09_axi_bid(), + .s09_axi_bresp(), + .s09_axi_buser(), + .s09_axi_bvalid(), + .s09_axi_bready('0), + .s09_axi_arid(axi_ram_s__5_axi_ar_arid), + .s09_axi_araddr(axi_ram_s__5_axi_ar_araddr), + .s09_axi_arlen(axi_ram_s__5_axi_ar_arlen), + .s09_axi_arsize(axi_ram_s__5_axi_ar_arsize), + .s09_axi_arburst(axi_ram_s__5_axi_ar_arburst), + .s09_axi_arlock('0), + .s09_axi_arcache(axi_ram_s__5_axi_ar_arcache), + .s09_axi_arprot(axi_ram_s__5_axi_ar_arprot), + .s09_axi_arqos(axi_ram_s__5_axi_ar_arqos), + .s09_axi_aruser('0), + .s09_axi_arvalid(axi_ram_s__5_axi_ar_arvalid), + .s09_axi_arready(axi_ram_s__5_axi_ar_arready), + .s09_axi_rid(axi_ram_s__5_axi_r_rid), + .s09_axi_rdata(axi_ram_s__5_axi_r_rdata), + .s09_axi_rresp(axi_ram_s__5_axi_r_rresp[1:0]), + .s09_axi_rlast(axi_ram_s__5_axi_r_rlast), + .s09_axi_ruser(), + .s09_axi_rvalid(axi_ram_s__5_axi_r_rvalid), + .s09_axi_rready(axi_ram_s__5_axi_r_rready), + + // axi_ram_s__6 + .s10_axi_awid('0), + .s10_axi_awaddr('0), + .s10_axi_awlen('0), + .s10_axi_awsize('0), + .s10_axi_awburst('0), + .s10_axi_awlock('0), + .s10_axi_awcache('0), + .s10_axi_awprot('0), + .s10_axi_awqos('0), + .s10_axi_awuser('0), + .s10_axi_awvalid('0), + .s10_axi_awready(), + .s10_axi_wdata('0), + .s10_axi_wstrb('0), + .s10_axi_wlast('0), + .s10_axi_wuser('0), + .s10_axi_wvalid('0), + .s10_axi_wready(), + .s10_axi_bid(), + .s10_axi_bresp(), + .s10_axi_buser(), + .s10_axi_bvalid(), + .s10_axi_bready('0), + .s10_axi_arid(axi_ram_s__6_axi_ar_arid), + .s10_axi_araddr(axi_ram_s__6_axi_ar_araddr), + .s10_axi_arlen(axi_ram_s__6_axi_ar_arlen), + .s10_axi_arsize(axi_ram_s__6_axi_ar_arsize), + .s10_axi_arburst(axi_ram_s__6_axi_ar_arburst), + .s10_axi_arlock('0), + .s10_axi_arcache(axi_ram_s__6_axi_ar_arcache), + .s10_axi_arprot(axi_ram_s__6_axi_ar_arprot), + .s10_axi_arqos(axi_ram_s__6_axi_ar_arqos), + .s10_axi_aruser('0), + .s10_axi_arvalid(axi_ram_s__6_axi_ar_arvalid), + .s10_axi_arready(axi_ram_s__6_axi_ar_arready), + .s10_axi_rid(axi_ram_s__6_axi_r_rid), + .s10_axi_rdata(axi_ram_s__6_axi_r_rdata), + .s10_axi_rresp(axi_ram_s__6_axi_r_rresp[1:0]), + .s10_axi_rlast(axi_ram_s__6_axi_r_rlast), + .s10_axi_ruser(), + .s10_axi_rvalid(axi_ram_s__6_axi_r_rvalid), + .s10_axi_rready(axi_ram_s__6_axi_r_rready), + + // axi_ram_s__7 + .s11_axi_awid('0), + .s11_axi_awaddr('0), + .s11_axi_awlen('0), + .s11_axi_awsize('0), + .s11_axi_awburst('0), + .s11_axi_awlock('0), + .s11_axi_awcache('0), + .s11_axi_awprot('0), + .s11_axi_awqos('0), + .s11_axi_awuser('0), + .s11_axi_awvalid('0), + .s11_axi_awready(), + .s11_axi_wdata('0), + .s11_axi_wstrb('0), + .s11_axi_wlast('0), + .s11_axi_wuser('0), + .s11_axi_wvalid('0), + .s11_axi_wready(), + .s11_axi_bid(), + .s11_axi_bresp(), + .s11_axi_buser(), + .s11_axi_bvalid(), + .s11_axi_bready('0), + .s11_axi_arid(axi_ram_s__7_axi_ar_arid), + .s11_axi_araddr(axi_ram_s__7_axi_ar_araddr), + .s11_axi_arlen(axi_ram_s__7_axi_ar_arlen), + .s11_axi_arsize(axi_ram_s__7_axi_ar_arsize), + .s11_axi_arburst(axi_ram_s__7_axi_ar_arburst), + .s11_axi_arlock('0), + .s11_axi_arcache(axi_ram_s__7_axi_ar_arcache), + .s11_axi_arprot(axi_ram_s__7_axi_ar_arprot), + .s11_axi_arqos(axi_ram_s__7_axi_ar_arqos), + .s11_axi_aruser('0), + .s11_axi_arvalid(axi_ram_s__7_axi_ar_arvalid), + .s11_axi_arready(axi_ram_s__7_axi_ar_arready), + .s11_axi_rid(axi_ram_s__7_axi_r_rid), + .s11_axi_rdata(axi_ram_s__7_axi_r_rdata), + .s11_axi_rresp(axi_ram_s__7_axi_r_rresp[1:0]), + .s11_axi_rlast(axi_ram_s__7_axi_r_rlast), + .s11_axi_ruser(), + .s11_axi_rvalid(axi_ram_s__7_axi_r_rvalid), + .s11_axi_rready(axi_ram_s__7_axi_r_rready), + + // axi_ram_s__8 + .s12_axi_awid('0), + .s12_axi_awaddr('0), + .s12_axi_awlen('0), + .s12_axi_awsize('0), + .s12_axi_awburst('0), + .s12_axi_awlock('0), + .s12_axi_awcache('0), + .s12_axi_awprot('0), + .s12_axi_awqos('0), + .s12_axi_awuser('0), + .s12_axi_awvalid('0), + .s12_axi_awready(), + .s12_axi_wdata('0), + .s12_axi_wstrb('0), + .s12_axi_wlast('0), + .s12_axi_wuser('0), + .s12_axi_wvalid('0), + .s12_axi_wready(), + .s12_axi_bid(), + .s12_axi_bresp(), + .s12_axi_buser(), + .s12_axi_bvalid(), + .s12_axi_bready('0), + .s12_axi_arid(axi_ram_s__8_axi_ar_arid), + .s12_axi_araddr(axi_ram_s__8_axi_ar_araddr), + .s12_axi_arlen(axi_ram_s__8_axi_ar_arlen), + .s12_axi_arsize(axi_ram_s__8_axi_ar_arsize), + .s12_axi_arburst(axi_ram_s__8_axi_ar_arburst), + .s12_axi_arlock('0), + .s12_axi_arcache(axi_ram_s__8_axi_ar_arcache), + .s12_axi_arprot(axi_ram_s__8_axi_ar_arprot), + .s12_axi_arqos(axi_ram_s__8_axi_ar_arqos), + .s12_axi_aruser('0), + .s12_axi_arvalid(axi_ram_s__8_axi_ar_arvalid), + .s12_axi_arready(axi_ram_s__8_axi_ar_arready), + .s12_axi_rid(axi_ram_s__8_axi_r_rid), + .s12_axi_rdata(axi_ram_s__8_axi_r_rdata), + .s12_axi_rresp(axi_ram_s__8_axi_r_rresp[1:0]), + .s12_axi_rlast(axi_ram_s__8_axi_r_rlast), + .s12_axi_ruser(), + .s12_axi_rvalid(axi_ram_s__8_axi_r_rvalid), + .s12_axi_rready(axi_ram_s__8_axi_r_rready), + + // axi_ram_s__9 + .s13_axi_awid('0), + .s13_axi_awaddr('0), + .s13_axi_awlen('0), + .s13_axi_awsize('0), + .s13_axi_awburst('0), + .s13_axi_awlock('0), + .s13_axi_awcache('0), + .s13_axi_awprot('0), + .s13_axi_awqos('0), + .s13_axi_awuser('0), + .s13_axi_awvalid('0), + .s13_axi_awready(), + .s13_axi_wdata('0), + .s13_axi_wstrb('0), + .s13_axi_wlast('0), + .s13_axi_wuser('0), + .s13_axi_wvalid('0), + .s13_axi_wready(), + .s13_axi_bid(), + .s13_axi_bresp(), + .s13_axi_buser(), + .s13_axi_bvalid(), + .s13_axi_bready('0), + .s13_axi_arid(axi_ram_s__9_axi_ar_arid), + .s13_axi_araddr(axi_ram_s__9_axi_ar_araddr), + .s13_axi_arlen(axi_ram_s__9_axi_ar_arlen), + .s13_axi_arsize(axi_ram_s__9_axi_ar_arsize), + .s13_axi_arburst(axi_ram_s__9_axi_ar_arburst), + .s13_axi_arlock('0), + .s13_axi_arcache(axi_ram_s__9_axi_ar_arcache), + .s13_axi_arprot(axi_ram_s__9_axi_ar_arprot), + .s13_axi_arqos(axi_ram_s__9_axi_ar_arqos), + .s13_axi_aruser('0), + .s13_axi_arvalid(axi_ram_s__9_axi_ar_arvalid), + .s13_axi_arready(axi_ram_s__9_axi_ar_arready), + .s13_axi_rid(axi_ram_s__9_axi_r_rid), + .s13_axi_rdata(axi_ram_s__9_axi_r_rdata), + .s13_axi_rresp(axi_ram_s__9_axi_r_rresp[1:0]), + .s13_axi_rlast(axi_ram_s__9_axi_r_rlast), + .s13_axi_ruser(), + .s13_axi_rvalid(axi_ram_s__9_axi_r_rvalid), + .s13_axi_rready(axi_ram_s__9_axi_r_rready), + + // axi_ram_s__10 + .s14_axi_awid('0), + .s14_axi_awaddr('0), + .s14_axi_awlen('0), + .s14_axi_awsize('0), + .s14_axi_awburst('0), + .s14_axi_awlock('0), + .s14_axi_awcache('0), + .s14_axi_awprot('0), + .s14_axi_awqos('0), + .s14_axi_awuser('0), + .s14_axi_awvalid('0), + .s14_axi_awready(), + .s14_axi_wdata('0), + .s14_axi_wstrb('0), + .s14_axi_wlast('0), + .s14_axi_wuser('0), + .s14_axi_wvalid('0), + .s14_axi_wready(), + .s14_axi_bid(), + .s14_axi_bresp(), + .s14_axi_buser(), + .s14_axi_bvalid(), + .s14_axi_bready('0), + .s14_axi_arid(axi_ram_s__10_axi_ar_arid), + .s14_axi_araddr(axi_ram_s__10_axi_ar_araddr), + .s14_axi_arlen(axi_ram_s__10_axi_ar_arlen), + .s14_axi_arsize(axi_ram_s__10_axi_ar_arsize), + .s14_axi_arburst(axi_ram_s__10_axi_ar_arburst), + .s14_axi_arlock('0), + .s14_axi_arcache(axi_ram_s__10_axi_ar_arcache), + .s14_axi_arprot(axi_ram_s__10_axi_ar_arprot), + .s14_axi_arqos(axi_ram_s__10_axi_ar_arqos), + .s14_axi_aruser('0), + .s14_axi_arvalid(axi_ram_s__10_axi_ar_arvalid), + .s14_axi_arready(axi_ram_s__10_axi_ar_arready), + .s14_axi_rid(axi_ram_s__10_axi_r_rid), + .s14_axi_rdata(axi_ram_s__10_axi_r_rdata), + .s14_axi_rresp(axi_ram_s__10_axi_r_rresp[1:0]), + .s14_axi_rlast(axi_ram_s__10_axi_r_rlast), + .s14_axi_ruser(), + .s14_axi_rvalid(axi_ram_s__10_axi_r_rvalid), + .s14_axi_rready(axi_ram_s__10_axi_r_rready), + /* * AXI Manager interface */ diff --git a/xls/modules/zstd/zstd_dec_cocotb_test.py b/xls/modules/zstd/zstd_dec_cocotb_test.py new file mode 100644 index 0000000000..c9c96d9544 --- /dev/null +++ b/xls/modules/zstd/zstd_dec_cocotb_test.py @@ -0,0 +1,2001 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import sys +import math +import enum +import pathlib +import tempfile + +import cocotb +from cocotb import triggers +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, ClockCycles, Event +from cocotb.binary import BinaryValue +from cocotb.utils import get_sim_time +from cocotb_bus.scoreboard import Scoreboard + +from cocotbext.axi import axi_channels +from cocotbext.axi.axi_master import AxiMaster +from cocotbext.axi.axi_channels import ( + AxiAWBus, + AxiWBus, + AxiWMonitor, + AxiBBus, + AxiWriteBus, + AxiARBus, + AxiRBus, + AxiReadBus, + AxiBus, + AxiBTransaction, + AxiBSource, + AxiBSink, + AxiBMonitor, + AxiRTransaction, + AxiRSource, + AxiRSink, + AxiRMonitor, +) +from cocotbext.axi.axi_ram import AxiRam +from cocotbext.axi.sparse_memory import SparseMemory + +import xls.modules.zstd.cocotb.channel as xlschannel +from xls.modules.zstd.cocotb import data_generator +from xls.modules.zstd.cocotb.memory import AxiRamFromFile +from xls.modules.zstd.cocotb.utils import run_test +from xls.modules.zstd.cocotb import xlsstruct + +AXI_DATA_W = 64 +AXI_DATA_W_BYTES = AXI_DATA_W // 8 +MAX_ENCODED_FRAME_SIZE_B = 2**32 +NOTIFY_CHANNEL = "notify" +RESET_CHANNEL = "reset" + +# Override default widths of AXI response signals +signal_widths = {"bresp": 3} +axi_channels.AxiBBus._signal_widths = signal_widths +axi_channels.AxiBTransaction._signal_widths = signal_widths +axi_channels.AxiBSource._signal_widths = signal_widths +axi_channels.AxiBSink._signal_widths = signal_widths +axi_channels.AxiBMonitor._signal_widths = signal_widths +signal_widths = {"rresp": 3, "rlast": 1} +axi_channels.AxiRBus._signal_widths = signal_widths +axi_channels.AxiRTransaction._signal_widths = signal_widths +axi_channels.AxiRSource._signal_widths = signal_widths +axi_channels.AxiRSink._signal_widths = signal_widths +axi_channels.AxiRMonitor._signal_widths = signal_widths + + +@xlsstruct.xls_dataclass +class NotifyStruct(xlsstruct.XLSStruct): + pass + + +SYMBOL_W = 8 +NUM_OF_BITS_W = 8 +BASE_W = 16 + + +@xlsstruct.xls_dataclass +class FseTableRecord(xlsstruct.XLSStruct): + base: BASE_W + num_of_bits: NUM_OF_BITS_W + symbol: SYMBOL_W + + +PARALLEL_ACCESS_WIDTH = 8 +MAX_WEIGHT = 11 +WEIGHT_LOG = math.ceil(math.log2(MAX_WEIGHT + 1)) +VALID_W = 1 + + +@xlsstruct.xls_dataclass +class CodeBuilderOutput(xlsstruct.XLSStruct): + symbol_valid_7: VALID_W + symbol_valid_6: VALID_W + symbol_valid_5: VALID_W + symbol_valid_4: VALID_W + symbol_valid_3: VALID_W + symbol_valid_2: VALID_W + symbol_valid_1: VALID_W + symbol_valid_0: VALID_W + code_length_7: WEIGHT_LOG + code_length_6: WEIGHT_LOG + code_length_5: WEIGHT_LOG + code_length_4: WEIGHT_LOG + code_length_3: WEIGHT_LOG + code_length_2: WEIGHT_LOG + code_length_1: WEIGHT_LOG + code_length_0: WEIGHT_LOG + code_7: MAX_WEIGHT + code_6: MAX_WEIGHT + code_5: MAX_WEIGHT + code_4: MAX_WEIGHT + code_3: MAX_WEIGHT + code_2: MAX_WEIGHT + code_1: MAX_WEIGHT + code_0: MAX_WEIGHT + + +class CSR(enum.Enum): + """ + Maps the offsets to the ZSTD Decoder registers. + """ + + STATUS = 0 + START = 1 + INPUTBUFFER = 2 + OUTPUTBUFFER = 3 + + +class Status(enum.Enum): + """ + Codes for the Status register. + """ + + IDLE = 0x0 + RUNNING = 0x1 + + +def check_ram_contents(mem, expected, name=""): + for i, value in enumerate(expected): + assert mem[i].value == value + + +def print_fse_ram_contents(mem, name="", size=None): + for i in range(size): + data = FseTableRecord.from_int(mem[i].value) + print(f"{name} [{i}]: {data}") + + +def print_ram_contents(mem, name="", size=None): + for i in range(size): + print(f"{name} [{i}]\t: {hex(mem[i].value)}") + + +def fields_as_array(data, prefix, count): + return [getattr(data, f"{prefix}_{i}") for i in range(count)] + + +def set_termination_event(monitor, event, transactions): + def terminate_cb(_): + if monitor.stats.received_transactions == transactions: + event.set() + + monitor.add_callback(terminate_cb) + + +@cocotb.coroutine +async def set_handshake_event(clk, channel, event): + while True: + await RisingEdge(clk) + if channel.rdy.value and channel.vld.value: + event.set() + + +@cocotb.coroutine +async def get_handshake_event(dut, event, func): + while True: + await event.wait() + func() + event.clear() + + +def connect_axi_read_bus(dut, name=""): + axi_ar = "axi_ar" + axi_r = "axi_r" + + if name: + name += "_" + + bus_axi_ar = axi_channels.AxiARBus.from_prefix(dut, name + axi_ar) + bus_axi_r = axi_channels.AxiRBus.from_prefix(dut, name + axi_r) + + return axi_channels.AxiReadBus(bus_axi_ar, bus_axi_r) + + +def connect_axi_write_bus(dut, name=""): + axi_aw = "axi_aw" + axi_w = "axi_w" + axi_b = "axi_b" + + if name: + name += "_" + + bus_axi_aw = axi_channels.AxiAWBus.from_prefix(dut, name + axi_aw) + bus_axi_w = axi_channels.AxiWBus.from_prefix(dut, name + axi_w) + bus_axi_b = axi_channels.AxiBBus.from_prefix(dut, name + axi_b) + + return axi_channels.AxiWriteBus(bus_axi_aw, bus_axi_w, bus_axi_b) + + +def connect_axi_bus(dut, name=""): + bus_axi_read = connect_axi_read_bus(dut, name) + bus_axi_write = connect_axi_write_bus(dut, name) + + return axi_channels.AxiBus(bus_axi_write, bus_axi_read) + + +async def csr_write(cpu, csr, data): + if isinstance(data, int): + data = data.to_bytes(AXI_DATA_W_BYTES, byteorder="little") + assert len(data) <= AXI_DATA_W_BYTES + await cpu.write(csr.value * AXI_DATA_W_BYTES, data) + + +async def csr_read(cpu, csr): + return await cpu.read(csr.value * AXI_DATA_W_BYTES, AXI_DATA_W_BYTES) + + +async def test_csr(dut): + + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + await reset_dut(dut, 50) + + csr_bus = connect_axi_bus(dut, "csr") + + cpu = AxiMaster(csr_bus, dut.clk, dut.rst) + + await triggers.ClockCycles(dut.clk, 10) + i = 0 + for reg in CSR: + expected_src = bytearray.fromhex("0DF0AD8BEFBEADDE") + assert len(expected_src) >= AXI_DATA_W_BYTES + expected = expected_src[-AXI_DATA_W_BYTES:] + expected[0] += i + await csr_write(cpu, reg, expected) + read = await csr_read(cpu, reg) + assert ( + read.data == expected + ), "Expected data doesn't match contents of the {}".format(reg) + i += 1 + await triggers.ClockCycles(dut.clk, 10) + + +async def test_reset(dut): + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + await reset_dut(dut, 50) + + csr_bus = connect_axi_bus(dut, "csr") + cpu = AxiMaster(csr_bus, dut.clk, dut.rst) + + await triggers.ClockCycles(dut.clk, 10) + await start_decoder(cpu) + timeout = 10 + status = await csr_read(cpu, CSR.STATUS) + while (int.from_bytes(status.data, byteorder="little") == Status.IDLE.value) & ( + timeout != 0 + ): + status = await csr_read(cpu, CSR.STATUS) + timeout -= 1 + assert timeout != 0 + + await reset_dut(dut, 50) + await wait_for_idle(cpu, 10) + + await triggers.ClockCycles(dut.clk, 10) + + +async def configure_decoder(dut, cpu, ibuf_addr, obuf_addr): + status = await csr_read(cpu, CSR.STATUS) + if int.from_bytes(status.data, byteorder="little") != Status.IDLE.value: + await reset_dut(dut, 50) + await csr_write(cpu, CSR.INPUTBUFFER, ibuf_addr) + await csr_write(cpu, CSR.OUTPUTBUFFER, obuf_addr) + + +async def start_decoder(cpu): + await csr_write(cpu, CSR.START, 0x1) + + +async def wait_for_idle(cpu, timeout=100): + status = await csr_read(cpu, CSR.STATUS) + while (int.from_bytes(status.data, byteorder="little") != Status.IDLE.value) & ( + timeout != 0 + ): + status = await csr_read(cpu, CSR.STATUS) + timeout -= 1 + assert timeout != 0 + + +async def reset_dut(dut, rst_len=10): + dut.rst.setimmediatevalue(0) + await triggers.ClockCycles(dut.clk, rst_len) + dut.rst.setimmediatevalue(1) + await triggers.ClockCycles(dut.clk, rst_len) + dut.rst.setimmediatevalue(0) + + +def get_clock_time(clock: Clock): + return get_sim_time(units="step") / clock.period + + +def connect_xls_channel(dut, channel_name, xls_struct): + channel = xlschannel.XLSChannel(dut, channel_name, dut.clk, start_now=True) + monitor = xlschannel.XLSChannelMonitor(dut, channel_name, dut.clk, xls_struct) + + return (channel, monitor) + + +def prepare_test_environment(dut): + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + memory_bus = connect_axi_bus(dut, "memory") + csr_bus = connect_axi_bus(dut, "csr") + axi_buses = {"memory": memory_bus, "csr": csr_bus} + + cpu = AxiMaster(csr_bus, dut.clk, dut.rst) + + return (axi_buses, cpu, clock) + + +async def test_fse_lookup_decoder(dut, clock, expected_fse_lookups): + lookup_dec_resp_channel = xlschannel.XLSChannel( + dut.ZstdDecoder.xls_modules_zstd_sequence_dec__ZstdDecoderInst__ZstdDecoder_0__CompressBlockDecoder_0__SequenceDecoder_0__SequenceDecoderCtrl_0__FseLookupCtrl_0_next_inst148, + "zstd_dec__flc_resp", + dut.clk, + ) + fse_lookup_resp_handshake = triggers.Event() + + block_cnt = 0 + + def func(): + nonlocal block_cnt + assert block_cnt <= len(expected_fse_lookups) + print_fse_ram_contents( + dut.ll_fse_ram.mem, "LL", size=len(expected_fse_lookups[block_cnt]["ll"]) + ) + print_fse_ram_contents( + dut.ml_fse_ram.mem, "ML", size=len(expected_fse_lookups[block_cnt]["ml"]) + ) + print_fse_ram_contents( + dut.of_fse_ram.mem, "OF", size=len(expected_fse_lookups[block_cnt]["of"]) + ) + check_ram_contents( + dut.ll_fse_ram.mem, [x.value for x in expected_fse_lookups[block_cnt]["ll"]] + ) + check_ram_contents( + dut.ml_fse_ram.mem, [x.value for x in expected_fse_lookups[block_cnt]["ml"]] + ) + check_ram_contents( + dut.of_fse_ram.mem, [x.value for x in expected_fse_lookups[block_cnt]["of"]] + ) + block_cnt += 1 + + cocotb.start_soon( + set_handshake_event(dut.clk, lookup_dec_resp_channel, fse_lookup_resp_handshake) + ) + cocotb.start_soon(get_handshake_event(dut, fse_lookup_resp_handshake, func)) + + +async def test_fse_lookup_decoder_for_huffman(dut, clock, expected_fse_lookups): + lookup_dec_resp_channel = xlschannel.XLSChannel( + dut.ZstdDecoder.xls_modules_zstd_comp_lookup_dec__ZstdDecoderInst__ZstdDecoder_0__CompressBlockDecoder_0__LiteralsDecoder_0__HuffmanLiteralsDecoder_0__HuffmanWeightsDecoder_0__HuffmanFseWeightsDecoder_0__CompLookupDecoder_0__64_8_16_1_15_8_32_1_7_9_8_1_8_16_1_next_inst5, + "zstd_dec__fse_table_finish__1", + dut.clk, + ) + fse_lookup_resp_handshake = triggers.Event() + + block_cnt = 0 + + def func(): + nonlocal block_cnt + assert block_cnt <= len(expected_fse_lookups) + print_fse_ram_contents( + dut.huffman_literals_weights_fse_ram_ram.mem, + f"HUFMMAN ({block_cnt})", + size=len(expected_fse_lookups[block_cnt]), + ) + check_ram_contents( + dut.huffman_literals_weights_fse_ram_ram.mem, + [x.value for x in expected_fse_lookups[block_cnt]], + ) + block_cnt += 1 + + cocotb.start_soon( + set_handshake_event(dut.clk, lookup_dec_resp_channel, fse_lookup_resp_handshake) + ) + cocotb.start_soon(get_handshake_event(dut, fse_lookup_resp_handshake, func)) + + +def reverse_expected_huffman_codes(exp_codes): + def reverse_bits(value, max_bits): + bv = BinaryValue(value=value, n_bits=max_bits, bigEndian=False) + return int(BinaryValue(value=bv.binstr[::-1], n_bits=max_bits, bigEndian=False)) + + max_bits = max(d["length"] for d in exp_codes) + + codes = [] + for record in exp_codes: + codes += [ + { + "code": reverse_bits(record["code"], max_bits), + "length": record["length"], + "symbol": record["symbol"], + } + ] + return codes + + +async def test_huffman_codes(dut, clock, expected_codes): + WEIGHT_CODE_BUILDER_INST = ( + dut.ZstdDecoder.xls_modules_zstd_huffman_code_builder__ZstdDecoderInst__ZstdDecoder_0__CompressBlockDecoder_0__LiteralsDecoder_0__HuffmanLiteralsDecoder_0__WeightCodeBuilder_0_next_inst19 + ) + CODES_CHANNEL_NAME = "zstd_dec__code_builder_codes" + + codes_channel = xlschannel.XLSChannel( + WEIGHT_CODE_BUILDER_INST, CODES_CHANNEL_NAME, dut.clk + ) + huffman_code_handshake = triggers.Event() + + codes = [] + block_cnt = 0 + packet_cnt = 0 + symbol_cnt = 0 + + def func(): + nonlocal codes + nonlocal symbol_cnt + nonlocal packet_cnt + nonlocal block_cnt + + assert block_cnt <= 32 + codes_data = getattr(WEIGHT_CODE_BUILDER_INST, CODES_CHANNEL_NAME) + data = CodeBuilderOutput.from_int(codes_data.value) + + symbol_valid_array = fields_as_array(data, "symbol_valid", 8) + code_length_array = fields_as_array(data, "code_length", 8) + code_array = fields_as_array(data, "code", 8) + + for symbol_valid, code_length, code in zip( + symbol_valid_array, code_length_array, code_array + ): + if symbol_valid == 1: + codes += [{"symbol": symbol_cnt, "code": code, "length": code_length}] + symbol_cnt += 1 + packet_cnt += 1 + + if packet_cnt == 32: + assert codes == reverse_expected_huffman_codes(expected_codes[block_cnt]) + packet_cnt = 0 + symbol_cnt = 0 + block_cnt += 1 + codes = [] + + cocotb.start_soon( + set_handshake_event(dut.clk, codes_channel, huffman_code_handshake) + ) + cocotb.start_soon(get_handshake_event(dut, huffman_code_handshake, func)) + + +async def test_huffman_weights(dut, clock, expected_huffman_weights): + lookup_dec_resp_channel = xlschannel.XLSChannel( + dut.ZstdDecoder.xls_modules_zstd_huffman_ctrl__ZstdDecoderInst__ZstdDecoder_0__CompressBlockDecoder_0__LiteralsDecoder_0__HuffmanLiteralsDecoder_0__HuffmanControlAndSequence_0__32_64_next_inst20, + "zstd_dec__weights_dec_resp", + dut.clk, + ) + huffman_weights_resp_handshake = triggers.Event() + + block_cnt = 0 + + def func(): + nonlocal block_cnt + assert block_cnt <= len(expected_huffman_weights) + print_ram_contents( + dut.huffman_literals_weights_mem_ram_ram.mem, + f"WEIGHTS ({block_cnt})", + size=64, + ) + check_ram_contents( + dut.huffman_literals_weights_mem_ram_ram.mem, + expected_huffman_weights[block_cnt], + ) + block_cnt += 1 + + cocotb.start_soon( + set_handshake_event( + dut.clk, lookup_dec_resp_channel, huffman_weights_resp_handshake + ) + ) + cocotb.start_soon(get_handshake_event(dut, huffman_weights_resp_handshake, func)) + + +async def test_decoder( + dut, seed, block_type, literal_type, axi_buses, cpu, clock, pregenerated +): + """Test decoder with zstd-compressed data + + if a file name is provided in `pregenerated`, use it as input + otherwise generate a random file using (seed, block_type, literal_type) + + The output of the decoder is compared with the output of decodercorpus + using the same input file. + """ + memory_bus = axi_buses["memory"] + + (unused_notify_channel, notify_monitor) = connect_xls_channel( + dut, NOTIFY_CHANNEL, NotifyStruct + ) + assert_notify = triggers.Event() + set_termination_event(notify_monitor, assert_notify, 1) + + mem_size = MAX_ENCODED_FRAME_SIZE_B + ibuf_addr = 0x0 + obuf_addr = mem_size // 2 + + # TODO if pregenerated is used, + # block_type, literal_type and seed aren't used. Handle this better. + if pregenerated: + encoded = open(pregenerated, "rb") + else: + # FIXME: use delete_on_close=False after moving to python 3.12 + encoded = tempfile.NamedTemporaryFile(delete=False) + # Generate ZSTD frame to temporary file + data_generator.GenerateFrame(seed, block_type, encoded.name, literal_type) + + print( + "\nusing" + + (" pregenerated" if pregenerated else f" randomly generated (seed={seed})") + + f" input file for decoder: {encoded.name}\n" + ) + + await reset_dut(dut, 50) + + expected_decoded_frame = data_generator.DecompressFrame(encoded.read()) + encoded.close() + reference_memory = SparseMemory(mem_size) + reference_memory.write(obuf_addr, expected_decoded_frame) + + # Initialise testbench memory with generated ZSTD frame + memory = AxiRamFromFile( + bus=memory_bus, clock=dut.clk, reset=dut.rst, path=encoded.name, size=mem_size + ) + + await configure_decoder(dut, cpu, ibuf_addr, obuf_addr) + output_monitor = AxiWMonitor(memory_bus.write.w, dut.clk, dut.rst) + await start_decoder(cpu) + decode_start = get_clock_time(clock) + await output_monitor.wait() + decode_first_packet = get_clock_time(clock) + await assert_notify.wait() + decode_end = get_clock_time(clock) + await wait_for_idle(cpu) + # Read decoded frame in chunks of AXI_DATA_W length + # Compare against frame decompressed with the reference library + expected_packet_count = ( + len(expected_decoded_frame) + (AXI_DATA_W_BYTES - 1) + ) // AXI_DATA_W_BYTES + for read_op in range(0, expected_packet_count): + addr = obuf_addr + (read_op * AXI_DATA_W_BYTES) + mem_contents = memory.read(addr, AXI_DATA_W_BYTES) + exp_mem_contents = reference_memory.read(addr, AXI_DATA_W_BYTES) + assert mem_contents == exp_mem_contents, ( + "{} bytes of memory contents at address {} " + "don't match the expected contents:\n" + "{}\nvs\n{}" + ).format( + AXI_DATA_W_BYTES, + hex(addr), + hex(int.from_bytes(mem_contents, byteorder="little")), + hex(int.from_bytes(exp_mem_contents, byteorder="little")), + ) + await ClockCycles(dut.clk, 20) + + +async def testing_routine( + dut, + test_cases=1, + block_type=data_generator.BlockType.RANDOM, + literal_type=data_generator.LiteralType.RANDOM, + pregenerated=None, + expected_fse_lookups=None, + expected_fse_huffman_lookups=None, + expected_huffman_weights=None, + expected_huffman_codes=None, +): + (axi_buses, cpu, clock) = prepare_test_environment(dut) + frame_id = 0 + for test_case in range(test_cases): + if expected_fse_lookups is not None: + await test_fse_lookup_decoder(dut, clock, expected_fse_lookups) + if expected_fse_huffman_lookups is not None: + await test_fse_lookup_decoder_for_huffman( + dut, clock, expected_fse_huffman_lookups + ) + if expected_huffman_codes is not None: + await test_huffman_codes(dut, clock, expected_huffman_codes) + if expected_huffman_weights is not None: + await test_huffman_weights(dut, clock, expected_huffman_weights) + await test_decoder( + dut, 2, block_type, literal_type, axi_buses, cpu, clock, pregenerated + ) + print("Decoding {} ZSTD frames done".format(block_type.name)) + + +@cocotb.test(timeout_time=50, timeout_unit="ms") +async def zstd_csr_test(dut): + await test_csr(dut) + + +@cocotb.test(timeout_time=50, timeout_unit="ms") +async def zstd_reset_test(dut): + await test_reset(dut) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def zstd_raw_frames_test(dut): + test_cases = 5 + block_type = data_generator.BlockType.RAW + await testing_routine(dut, test_cases, block_type) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def zstd_rle_frames_test(dut): + test_cases = 5 + block_type = data_generator.BlockType.RLE + await testing_routine(dut, test_cases, block_type) + + +# Tests with pregenerated inputs +# +# block type and literal type in arguments and file names reflect what was used +# for generating them. The file names also contain the value of seed but the +# bazel environment is not hermetic in terms of reproducible results with the +# same seed value +# The tests are disabled by default as none of them passes currently. +# Use them to verify progress in specific parts of the decoder. + +# TODO the workdir / data relation is weird. How to pass this better? +PREGENERATED_FILES_DIR = "../xls/modules/zstd/data/" + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def pregenerated_compressed_raw_1(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_compressed_raw_1.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RAW + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def pregenerated_compressed_raw_2(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_compressed_raw_2.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RAW + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def pregenerated_compressed_rle_1(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_compressed_rle_1.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RLE + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=1000, timeout_unit="ms") +async def pregenerated_compressed_rle_2(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_compressed_rle_2.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RLE + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=1000, timeout_unit="ms") +async def pregenerated_compressed_random_1(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_compressed_random_1.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_weights = [ + [ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01000100, + 0x06000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000010, + 0x00100030, + 0x00700000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000001, + 0x00010003, + 0x00080000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x10001000, + 0x50000000, + ], + [ + 0x02000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000010, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00003000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00010000, + ], + ] + + expected_huffman_codes = [ + [ + {"code": 0x00, "length": 8, "symbol": 0x31}, + {"code": 0x01, "length": 8, "symbol": 0x35}, + {"code": 0x20, "length": 3, "symbol": 0x39}, + {"code": 0x02, "length": 8, "symbol": 0x6E}, + {"code": 0x03, "length": 8, "symbol": 0x72}, + {"code": 0x08, "length": 6, "symbol": 0x76}, + {"code": 0x40, "length": 2, "symbol": 0x7A}, + {"code": 0x04, "length": 8, "symbol": 0xAF}, + {"code": 0x05, "length": 8, "symbol": 0xB3}, + {"code": 0x0C, "length": 6, "symbol": 0xB7}, + {"code": 0x80, "length": 1, "symbol": 0xBB}, + {"code": 0x06, "length": 8, "symbol": 0xF0}, + {"code": 0x07, "length": 8, "symbol": 0xF4}, + {"code": 0x10, "length": 4, "symbol": 0xF8}, + ], + [ + {"code": 0x02, "length": 2, "symbol": 0x01}, + {"code": 0x00, "length": 3, "symbol": 0x66}, + {"code": 0x04, "length": 1, "symbol": 0x9C}, + {"code": 0x01, "length": 3, "symbol": 0xCB}, + ], + ] + + expected_fse_huffman_lookups = [ + [ + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0016), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0018), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001C), + FseTableRecord(symbol=0x03, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001E), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0001), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0002), + FseTableRecord(symbol=0x08, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0003), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0005), + FseTableRecord(symbol=0x01, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0006), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0007), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0008), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0009), + FseTableRecord(symbol=0x07, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000A), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000B), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000C), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000D), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000E), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000F), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0010), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0011), + FseTableRecord(symbol=0x06, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0012), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0013), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0014), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0015), + ], + [ + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001E), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0001), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0002), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0003), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0005), + FseTableRecord(symbol=0x03, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0006), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0007), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0008), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0009), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000A), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000B), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000C), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000D), + FseTableRecord(symbol=0x02, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000E), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000F), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0010), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0011), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0012), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0013), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0014), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0015), + FseTableRecord(symbol=0x01, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0016), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0017), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0018), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0019), + ], + [ + FseTableRecord(symbol=0x00, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x01, num_of_bits=0x04, base=0x0000), + FseTableRecord(symbol=0x02, num_of_bits=0x05, base=0x0020), + FseTableRecord(symbol=0x03, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x05, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x06, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x08, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x0A, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x0D, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x10, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x13, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x16, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x19, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x1C, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x1F, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x21, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x23, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x25, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x27, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x29, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x2B, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x2D, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x01, num_of_bits=0x04, base=0x0010), + FseTableRecord(symbol=0x02, num_of_bits=0x04, base=0x0000), + FseTableRecord(symbol=0x03, num_of_bits=0x05, base=0x0020), + FseTableRecord(symbol=0x04, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x06, num_of_bits=0x05, base=0x0020), + FseTableRecord(symbol=0x07, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x09, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x0C, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x0F, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x12, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x15, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x18, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x1B, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x1E, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x20, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x22, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x24, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x26, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x28, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x2A, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x2C, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x01, num_of_bits=0x04, base=0x0020), + FseTableRecord(symbol=0x01, num_of_bits=0x04, base=0x0030), + FseTableRecord(symbol=0x02, num_of_bits=0x04, base=0x0010), + FseTableRecord(symbol=0x04, num_of_bits=0x05, base=0x0020), + FseTableRecord(symbol=0x05, num_of_bits=0x05, base=0x0020), + FseTableRecord(symbol=0x07, num_of_bits=0x05, base=0x0020), + FseTableRecord(symbol=0x08, num_of_bits=0x05, base=0x0020), + FseTableRecord(symbol=0x0B, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x0E, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x11, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x14, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x17, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x1A, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x1D, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x34, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x33, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x32, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x31, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x30, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x2F, num_of_bits=0x06, base=0x0000), + FseTableRecord(symbol=0x2E, num_of_bits=0x06, base=0x0000), + ], + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_codes=expected_huffman_codes, + expected_huffman_weights=expected_huffman_weights, + expected_fse_huffman_lookups=expected_fse_huffman_lookups, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def pregenerated_compressed_random_2(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_compressed_random_2.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +# Tests with predefined FSE tables and Huffman-encoded literals + + +@cocotb.test(timeout_time=350, timeout_unit="ms") +async def fse_huffman_literals_predefined_sequences_seed_107958(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "fse_huffman_literals_predefined_sequences_seed_107958.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_weights = [ + [ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x10000000, + 0x00004000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00010000, + 0x00000005, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000020, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x03000000, + ] + ] + + expected_fse_huffman_lookups = [ + [ + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0018), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001E), + FseTableRecord(symbol=0x01, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0001), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0002), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0003), + FseTableRecord(symbol=0x05, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0005), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0006), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0007), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0008), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0009), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000A), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000B), + FseTableRecord(symbol=0x04, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000C), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000D), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000E), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000F), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0010), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0011), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0012), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0013), + FseTableRecord(symbol=0x02, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0014), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0015), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0016), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0017), + ] + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_weights=expected_huffman_weights, + expected_fse_huffman_lookups=expected_fse_huffman_lookups, + ) + + +@cocotb.test(timeout_time=350, timeout_unit="ms") +async def fse_huffman_literals_predefined_sequences_seed_204626(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "fse_huffman_literals_predefined_sequences_seed_204626.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=350, timeout_unit="ms") +async def fse_huffman_literals_predefined_sequences_seed_210872(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "fse_huffman_literals_predefined_sequences_seed_210872.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=350, timeout_unit="ms") +async def fse_huffman_literals_predefined_sequences_seed_299289(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "fse_huffman_literals_predefined_sequences_seed_299289.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=350, timeout_unit="ms") +async def fse_huffman_literals_predefined_sequences_seed_319146(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "fse_huffman_literals_predefined_sequences_seed_319146.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_codes = [ + [ + {"code": 0x300, "length": 2, "symbol": 0x07}, + {"code": 0x60, "length": 5, "symbol": 0x0E}, + {"code": 0x0A, "length": 9, "symbol": 0x15}, + {"code": 0x00, "length": 10, "symbol": 0x1C}, + {"code": 0x180, "length": 3, "symbol": 0x25}, + {"code": 0x30, "length": 6, "symbol": 0x2C}, + {"code": 0x0C, "length": 9, "symbol": 0x33}, + {"code": 0x01, "length": 10, "symbol": 0x3A}, + {"code": 0xC0, "length": 4, "symbol": 0x43}, + {"code": 0x18, "length": 7, "symbol": 0x4A}, + {"code": 0x02, "length": 10, "symbol": 0x51}, + {"code": 0x100, "length": 4, "symbol": 0x61}, + {"code": 0x20, "length": 7, "symbol": 0x68}, + {"code": 0x03, "length": 10, "symbol": 0x6F}, + {"code": 0x80, "length": 5, "symbol": 0x7F}, + {"code": 0x10, "length": 8, "symbol": 0x86}, + {"code": 0x04, "length": 10, "symbol": 0x8D}, + {"code": 0x200, "length": 3, "symbol": 0x96}, + {"code": 0x40, "length": 6, "symbol": 0x9D}, + {"code": 0x0E, "length": 9, "symbol": 0xA4}, + {"code": 0x05, "length": 10, "symbol": 0xAB}, + {"code": 0x280, "length": 3, "symbol": 0xB4}, + {"code": 0x50, "length": 6, "symbol": 0xBB}, + {"code": 0x06, "length": 10, "symbol": 0xC2}, + {"code": 0x07, "length": 10, "symbol": 0xC9}, + {"code": 0x140, "length": 4, "symbol": 0xD2}, + {"code": 0x28, "length": 7, "symbol": 0xD9}, + {"code": 0x08, "length": 10, "symbol": 0xE0}, + {"code": 0xA0, "length": 5, "symbol": 0xF0}, + {"code": 0x14, "length": 8, "symbol": 0xF7}, + {"code": 0x09, "length": 10, "symbol": 0xFE}, + ] + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_codes=expected_huffman_codes, + ) + + +@cocotb.test(timeout_time=1000, timeout_unit="ms") +async def fse_huffman_literals_predefined_sequences_seed_331938(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "fse_huffman_literals_predefined_sequences_seed_331938.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_codes = [ + [ + {"code": 0x00, "length": 9, "symbol": 0x13}, + {"code": 0x20, "length": 5, "symbol": 0x1B}, + {"code": 0x01, "length": 9, "symbol": 0x32}, + {"code": 0x10, "length": 6, "symbol": 0x3A}, + {"code": 0x100, "length": 2, "symbol": 0x42}, + {"code": 0x02, "length": 9, "symbol": 0x51}, + {"code": 0x18, "length": 6, "symbol": 0x59}, + {"code": 0x180, "length": 2, "symbol": 0x61}, + {"code": 0x08, "length": 7, "symbol": 0x78}, + {"code": 0x80, "length": 3, "symbol": 0x80}, + {"code": 0x0C, "length": 7, "symbol": 0x97}, + {"code": 0xC0, "length": 3, "symbol": 0x9F}, + {"code": 0x04, "length": 8, "symbol": 0xB6}, + {"code": 0x40, "length": 4, "symbol": 0xBE}, + {"code": 0x06, "length": 8, "symbol": 0xD5}, + {"code": 0x60, "length": 4, "symbol": 0xDD}, + {"code": 0x03, "length": 9, "symbol": 0xF4}, + {"code": 0x30, "length": 5, "symbol": 0xFC}, + ] + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_codes=expected_huffman_codes, + ) + + +@cocotb.test(timeout_time=350, timeout_unit="ms") +async def fse_huffman_literals_predefined_sequences_seed_333824(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "fse_huffman_literals_predefined_sequences_seed_333824.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +# Test cases crated manually to allow working with small sizes of inputs. + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def pregenerated_compressed_minimal(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_compressed_minimal.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def pregenerated_uncompressed(dut): + input_name = PREGENERATED_FILES_DIR + "pregenerated_uncompressed.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +# Test cases with predefined FSE tables and RAW/RLE literals + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_literals_predefined_sequences_seed_406229(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_literals_predefined_sequences_seed_406229.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_literals_predefined_sequences_seed_411034(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_literals_predefined_sequences_seed_411034.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_literals_predefined_sequences_seed_413015(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_literals_predefined_sequences_seed_413015.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_literals_predefined_sequences_seed_436165(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_literals_predefined_sequences_seed_436165.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_literals_predefined_sequences_seed_464057(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_literals_predefined_sequences_seed_464057.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_literals_predefined_sequences_seed_466803(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_literals_predefined_sequences_seed_466803.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def raw_literals_predefined_sequences_seed_422473(dut): + input_name = ( + PREGENERATED_FILES_DIR + "raw_literals_predefined_sequences_seed_422473.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def raw_literals_predefined_sequences_seed_436965(dut): + input_name = ( + PREGENERATED_FILES_DIR + "raw_literals_predefined_sequences_seed_436965.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def raw_literals_predefined_sequences_seed_462302(dut): + input_name = ( + PREGENERATED_FILES_DIR + "raw_literals_predefined_sequences_seed_462302.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_raw_literals_predefined_sequences_seed_408158(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_raw_literals_predefined_sequences_seed_408158.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_raw_literals_predefined_sequences_seed_499212(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_raw_literals_predefined_sequences_seed_499212.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +# Tests with inputs that correspond to the values in arrays defined in +# data/*.x files + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def comp_frame(dut): + input_name = PREGENERATED_FILES_DIR + "comp_frame.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=500, timeout_unit="ms") +async def comp_frame_fse_comp(dut): + input_name = PREGENERATED_FILES_DIR + "comp_frame_fse_comp.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_fse_lookups = [ + { + "ll": [ + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0012), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0014), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0012), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0014), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0016), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0018), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001E), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0020), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0022), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0024), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0026), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0028), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0016), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0018), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x001A), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x001C), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x001E), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0020), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0022), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0024), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0026), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0028), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x002A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x002A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x002C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x002E), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0030), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0032), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0034), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0036), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0038), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x003A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x003C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x003E), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x002C), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x002E), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0030), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0032), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0034), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0036), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x0038), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x003A), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x003C), + FseTableRecord(symbol=0x06, num_of_bits=0x01, base=0x003E), + ], + "of": [ + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x0018), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x001C), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x0020), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x0024), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x0028), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x002C), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x0030), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x0034), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0014), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0018), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x001C), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0020), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0024), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0028), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x002C), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0014), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0018), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x001C), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0020), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0024), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0028), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x002C), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x0038), + FseTableRecord(symbol=0x01, num_of_bits=0x02, base=0x003C), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0030), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0034), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x0038), + FseTableRecord(symbol=0x02, num_of_bits=0x02, base=0x003C), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0030), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0034), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x0038), + FseTableRecord(symbol=0x05, num_of_bits=0x02, base=0x003C), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0012), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0014), + FseTableRecord(symbol=0x01, num_of_bits=0x01, base=0x0016), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x02, num_of_bits=0x01, base=0x0012), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x05, num_of_bits=0x01, base=0x0012), + ], + "ml": [ + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x0018), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x001C), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x0020), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x0024), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x0028), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x002C), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x0030), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x0034), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0014), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0018), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x001C), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0020), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0024), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0028), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x002C), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0014), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0018), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x001C), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0020), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0024), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0028), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x002C), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x0038), + FseTableRecord(symbol=0x00, num_of_bits=0x02, base=0x003C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0030), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0034), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x0038), + FseTableRecord(symbol=0x15, num_of_bits=0x02, base=0x003C), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0030), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0034), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x0038), + FseTableRecord(symbol=0x1C, num_of_bits=0x02, base=0x003C), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x0000), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x0002), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0012), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0014), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0016), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x15, num_of_bits=0x01, base=0x0012), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x0006), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x0008), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x000A), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x000C), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x000E), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x0010), + FseTableRecord(symbol=0x1C, num_of_bits=0x01, base=0x0012), + ], + } + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_fse_lookups=expected_fse_lookups, + ) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def comp_frame_fse_repeated(dut): + input_name = PREGENERATED_FILES_DIR + "comp_frame_fse_repeated.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def comp_frame_huffman(dut): + input_name = PREGENERATED_FILES_DIR + "comp_frame_huffman.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def comp_frame_huffman_fse(dut): + input_name = PREGENERATED_FILES_DIR + "comp_frame_huffman_fse.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=1000, timeout_unit="ms") +async def raw_literals_compressed_sequences_seed_903062(dut): + input_name = ( + PREGENERATED_FILES_DIR + "raw_literals_compressed_sequences_seed_903062.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def raw_literals_rle_sequences_seed_700216(dut): + input_name = PREGENERATED_FILES_DIR + "raw_literals_rle_sequences_seed_700216.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=1000, timeout_unit="ms") +async def rle_literals_compressed_sequences_seed_701326(dut): + input_name = ( + PREGENERATED_FILES_DIR + "rle_literals_compressed_sequences_seed_701326.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=200, timeout_unit="ms") +async def rle_literals_rle_sequences_seed_2(dut): + input_name = PREGENERATED_FILES_DIR + "rle_literals_rle_sequences_seed_2.zst" + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + await testing_routine(dut, test_cases, block_type, literal_type, input_name) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def treeless_huffman_literals_compressed_sequences_seed_400077(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "treeless_huffman_literals_compressed_sequences_seed_400077.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_weights = [ + [ + 0x10000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00300000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000004, + 0x00000000, + 0x00010000, + ] + ] + + expected_huffman_codes = [ + [ + {"code": 0x00, "length": 4, "symbol": 0x00}, + {"code": 0x02, "length": 3, "symbol": 0x3D}, + {"code": 0x04, "length": 2, "symbol": 0x7A}, + {"code": 0x08, "length": 1, "symbol": 0xB7}, + {"code": 0x01, "length": 4, "symbol": 0xC3}, + ] + ] + + expected_fse_huffman_lookups = [ + [ + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0018), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001E), + FseTableRecord(symbol=0x01, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0001), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0002), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0003), + FseTableRecord(symbol=0x04, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0005), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0006), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0007), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0008), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0009), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000A), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000B), + FseTableRecord(symbol=0x03, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000C), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000D), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000E), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000F), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0010), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0011), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0012), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0013), + FseTableRecord(symbol=0x02, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0014), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0015), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0016), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0017), + ] + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_codes=expected_huffman_codes, + expected_huffman_weights=expected_huffman_weights, + expected_fse_huffman_lookups=expected_fse_huffman_lookups, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025( + dut, +): + input_name = ( + PREGENERATED_FILES_DIR + + "treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400025.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_weights = [ + [ + 0x11111111, + 0x11111111, + ] + ] + + expected_huffman_codes = [ + [ + {"code": 0x00, "length": 4, "symbol": 0x00}, + {"code": 0x01, "length": 4, "symbol": 0x01}, + {"code": 0x02, "length": 4, "symbol": 0x02}, + {"code": 0x03, "length": 4, "symbol": 0x03}, + {"code": 0x04, "length": 4, "symbol": 0x04}, + {"code": 0x05, "length": 4, "symbol": 0x05}, + {"code": 0x06, "length": 4, "symbol": 0x06}, + {"code": 0x07, "length": 4, "symbol": 0x07}, + {"code": 0x08, "length": 4, "symbol": 0x08}, + {"code": 0x09, "length": 4, "symbol": 0x09}, + {"code": 0x0A, "length": 4, "symbol": 0x0A}, + {"code": 0x0B, "length": 4, "symbol": 0x0B}, + {"code": 0x0C, "length": 4, "symbol": 0x0C}, + {"code": 0x0D, "length": 4, "symbol": 0x0D}, + {"code": 0x0E, "length": 4, "symbol": 0x0E}, + {"code": 0x0F, "length": 4, "symbol": 0x0F}, + ] + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_codes=expected_huffman_codes, + expected_huffman_weights=expected_huffman_weights, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061( + dut, +): + input_name = ( + PREGENERATED_FILES_DIR + + "treeless_huffman_literals_predefined_rle_compressed_sequences_seed_400061.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_weights = [ + [ + 0x11111111, + 0x11111111, + ] + ] + + expected_huffman_codes = [ + [ + {"code": 0x00, "length": 4, "symbol": 0x00}, + {"code": 0x01, "length": 4, "symbol": 0x01}, + {"code": 0x02, "length": 4, "symbol": 0x02}, + {"code": 0x03, "length": 4, "symbol": 0x03}, + {"code": 0x04, "length": 4, "symbol": 0x04}, + {"code": 0x05, "length": 4, "symbol": 0x05}, + {"code": 0x06, "length": 4, "symbol": 0x06}, + {"code": 0x07, "length": 4, "symbol": 0x07}, + {"code": 0x08, "length": 4, "symbol": 0x08}, + {"code": 0x09, "length": 4, "symbol": 0x09}, + {"code": 0x0A, "length": 4, "symbol": 0x0A}, + {"code": 0x0B, "length": 4, "symbol": 0x0B}, + {"code": 0x0C, "length": 4, "symbol": 0x0C}, + {"code": 0x0D, "length": 4, "symbol": 0x0D}, + {"code": 0x0E, "length": 4, "symbol": 0x0E}, + {"code": 0x0F, "length": 4, "symbol": 0x0F}, + ] + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_codes=expected_huffman_codes, + expected_huffman_weights=expected_huffman_weights, + ) + + +@cocotb.test(timeout_time=2000, timeout_unit="ms") +async def treeless_huffman_literals_rle_sequences_seed_403927(dut): + input_name = ( + PREGENERATED_FILES_DIR + + "treeless_huffman_literals_rle_sequences_seed_403927.zst" + ) + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RANDOM + + expected_huffman_weights = [ + [ + 0x00003001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x02001000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000020, + 0x01000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80010010, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000700, + 0x10000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00600100, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000005, + 0x00100000, + ] + ] + + expected_huffman_codes = [ + [ + {"code": 0x0C, "length": 6, "symbol": 0x04}, + {"code": 0x00, "length": 8, "symbol": 0x07}, + {"code": 0x08, "length": 7, "symbol": 0x29}, + {"code": 0x01, "length": 8, "symbol": 0x2C}, + {"code": 0x0A, "length": 7, "symbol": 0x4E}, + {"code": 0x02, "length": 8, "symbol": 0x51}, + {"code": 0x80, "length": 1, "symbol": 0x70}, + {"code": 0x03, "length": 8, "symbol": 0x73}, + {"code": 0x04, "length": 8, "symbol": 0x76}, + {"code": 0x40, "length": 2, "symbol": 0x95}, + {"code": 0x05, "length": 8, "symbol": 0x98}, + {"code": 0x20, "length": 3, "symbol": 0xBA}, + {"code": 0x06, "length": 8, "symbol": 0xBD}, + {"code": 0x10, "length": 4, "symbol": 0xDF}, + {"code": 0x07, "length": 8, "symbol": 0xE2}, + ] + ] + + expected_fse_huffman_lookups = [ + [ + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0012), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0014), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0016), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x0018), + FseTableRecord(symbol=0x05, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001A), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001C), + FseTableRecord(symbol=0x00, num_of_bits=0x01, base=0x001E), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0000), + FseTableRecord(symbol=0x08, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0001), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0002), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0003), + FseTableRecord(symbol=0x03, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0004), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0005), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0006), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0007), + FseTableRecord(symbol=0x07, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0008), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0009), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000A), + FseTableRecord(symbol=0x02, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000B), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000C), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000D), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000E), + FseTableRecord(symbol=0x06, num_of_bits=0x05, base=0x0000), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x000F), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0010), + FseTableRecord(symbol=0x00, num_of_bits=0x00, base=0x0011), + FseTableRecord(symbol=0x01, num_of_bits=0x05, base=0x0000), + ] + ] + + await testing_routine( + dut, + test_cases, + block_type, + literal_type, + input_name, + expected_huffman_codes=expected_huffman_codes, + expected_huffman_weights=expected_huffman_weights, + expected_fse_huffman_lookups=expected_fse_huffman_lookups, + ) + + +# Tests with inputs generated randomly on test execution + + +@cocotb.test(timeout_time=5000, timeout_unit="ms") +async def zstd_compressed_frames_test(dut): + test_cases = 1 + block_type = data_generator.BlockType.COMPRESSED + literal_type = data_generator.LiteralType.RAW + await testing_routine(dut, test_cases, block_type, literal_type) + +if __name__ == "__main__": + sys.path.append(str(pathlib.Path(__file__).parent)) + with tempfile.NamedTemporaryFile(mode="w") as modified_zstd_verilog: + toplevel = "zstd_dec_wrapper" + test_module = [pathlib.Path(__file__).stem] + verilog_sources = [ + modified_zstd_verilog.name, + "xls/modules/zstd/rtl/xls_fifo_wrapper.sv", + "xls/modules/zstd/rtl/zstd_dec_wrapper.sv", + "xls/modules/zstd/axi_crossbar_wrapper.v", + "external/com_github_alexforencich_verilog_axi/rtl/axi_crossbar.v", + "external/com_github_alexforencich_verilog_axi/rtl/axi_crossbar_rd.v", + "external/com_github_alexforencich_verilog_axi/rtl/axi_crossbar_wr.v", + "external/com_github_alexforencich_verilog_axi/rtl/axi_crossbar_addr.v", + "external/com_github_alexforencich_verilog_axi/rtl/axi_register_rd.v", + "external/com_github_alexforencich_verilog_axi/rtl/axi_register_wr.v", + "external/com_github_alexforencich_verilog_axi/rtl/arbiter.v", + "external/com_github_alexforencich_verilog_axi/rtl/priority_encoder.v", + "xls/modules/zstd/rtl/ram_1r1w.v", + ] + + with open("xls/modules/zstd/zstd_dec.v") as zstd_verilog: + modified_content = zstd_verilog.read().replace( + "__xls_modules_zstd", "xls_modules_zstd" + ) + modified_zstd_verilog.write(modified_content) + + modified_zstd_verilog.flush() # + run_test(toplevel, test_module, verilog_sources) diff --git a/xls/modules/zstd/zstd_dec_ll_fse_default.mem b/xls/modules/zstd/zstd_dec_ll_fse_default.mem new file mode 100644 index 0000000000..fd3bfafa24 --- /dev/null +++ b/xls/modules/zstd/zstd_dec_ll_fse_default.mem @@ -0,0 +1,256 @@ +00000400 +00100400 +00200501 +00000503 +00000504 +00000506 +00000507 +00000509 +0000050a +0000050c +0000060e +00000510 +00000512 +00000513 +00000515 +00000516 +00000518 +00200519 +0000051a +0000061b +0000061d +0000061f +00200400 +00000401 +00000502 +00200504 +00000505 +00200507 +00000508 +0020050a +0000050b +0000060d +00200510 +00000511 +00200513 +00000514 +00200516 +00000517 +00000419 +00100419 +0020051a +0000061c +0000061e +00300400 +00100401 +00200502 +00200503 +00200505 +00200506 +00200508 +00200509 +0020050b +0020050c +0000060f +00200511 +00200512 +00200514 +00200515 +00200517 +00200518 +00000623 +00000622 +00000621 +00000620 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/xls/modules/zstd/zstd_dec_ml_fse_default.mem b/xls/modules/zstd/zstd_dec_ml_fse_default.mem new file mode 100644 index 0000000000..04b32295c8 --- /dev/null +++ b/xls/modules/zstd/zstd_dec_ml_fse_default.mem @@ -0,0 +1,256 @@ +00000600 +00000401 +00200502 +00000503 +00000505 +00000506 +00000508 +0000060a +0000060d +00000610 +00000613 +00000616 +00000619 +0000061c +0000061f +00000621 +00000623 +00000625 +00000627 +00000629 +0000062b +0000062d +00100401 +00000402 +00200503 +00000504 +00200506 +00000507 +00000609 +0000060c +0000060f +00000612 +00000615 +00000618 +0000061b +0000061e +00000620 +00000622 +00000624 +00000626 +00000628 +0000062a +0000062c +00200401 +00300401 +00100402 +00200504 +00200505 +00200507 +00200508 +0000060b +0000060e +00000611 +00000614 +00000617 +0000061a +0000061d +00000634 +00000633 +00000632 +00000631 +00000630 +0000062f +0000062e +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 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+00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/xls/modules/zstd/zstd_dec_of_fse_default.mem b/xls/modules/zstd/zstd_dec_of_fse_default.mem new file mode 100644 index 0000000000..9d81689c66 --- /dev/null +++ b/xls/modules/zstd/zstd_dec_of_fse_default.mem @@ -0,0 +1,256 @@ +00000500 +00000406 +00000509 +0000050f +00000515 +00000503 +00000407 +0000050c +00000512 +00000517 +00000505 +00000408 +0000050e +00000514 +00000502 +00100407 +0000050b +00000511 +00000516 +00000504 +00100408 +0000050d +00000513 +00000501 +00100406 +0000050a +00000510 +0000051c +0000051b +0000051a +00000519 +00000518 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/xls/modules/zstd/zstd_dec_test.x b/xls/modules/zstd/zstd_dec_test.x index 2db5105f38..854bfa06e2 100644 --- a/xls/modules/zstd/zstd_dec_test.x +++ b/xls/modules/zstd/zstd_dec_test.x @@ -28,10 +28,11 @@ import xls.modules.zstd.parallel_rams; import xls.modules.zstd.literals_buffer; import xls.modules.zstd.fse_table_creator; import xls.modules.zstd.ram_mux; -// import xls.modules.zstd.zstd_frame_testcases as comp_frame; -// import xls.modules.zstd.data.comp_frame_huffman as comp_frame; -// import xls.modules.zstd.data.comp_frame_fse_comp as comp_frame; -// import xls.modules.zstd.data.comp_frame_fse_repeated as comp_frame; + +import xls.modules.zstd.data.comp_frame_huffman; +import xls.modules.zstd.data.comp_frame_huffman_fse; +import xls.modules.zstd.data.comp_frame_fse_comp; +import xls.modules.zstd.data.comp_frame_fse_repeated; import xls.modules.zstd.data.comp_frame; const TEST_WINDOW_LOG_MAX = u32:30; @@ -153,8 +154,9 @@ fn csr_addr(c: zstd_dec::Csr) -> uN[TEST_AXI_ADDR_W] { (c as uN[TEST_AXI_ADDR_W]) << 3 } -#[test_proc] -proc ZstdDecoderTest { +type TestFrames = common::DataArray[1]; + +proc ZstdDecoderTester { type CsrAxiAr = axi::AxiAr; type CsrAxiR = axi::AxiR; type CsrAxiAw = axi::AxiAw; @@ -258,7 +260,8 @@ proc ZstdDecoderTest { type LitBufRamWrReq = ram::WriteReq; type LitBufRamWrResp = ram::WriteResp; - terminator: chan out; + start_r: chan<()> in; + finished_s: chan<()> out; csr_axi_aw_s: chan out; csr_axi_w_s: chan out; @@ -318,7 +321,7 @@ proc ZstdDecoderTest { init {} - config(terminator: chan out) { + config(start_r: chan<()> in, finished_s: chan<()> out) { let (csr_axi_aw_s, csr_axi_aw_r) = chan("csr_axi_aw"); let (csr_axi_w_s, csr_axi_w_r) = chan("csr_axi_w"); @@ -702,7 +705,7 @@ proc ZstdDecoderTest { >(raw_axi_ar_r, raw_axi_r_s, raw_ram_rd_req_s, raw_ram_rd_resp_r); ( - terminator, + start_r, finished_s, csr_axi_aw_s, csr_axi_w_s, csr_axi_b_r, csr_axi_ar_s, csr_axi_r_r, fh_axi_ar_r, fh_axi_r_s, fh_ram_wr_req_s, fh_ram_wr_resp_r, bh_axi_ar_r, bh_axi_r_s, bh_ram_wr_req_s, bh_ram_wr_resp_r, @@ -721,10 +724,12 @@ proc ZstdDecoderTest { } next (state: ()) { + let tok = join(); + let (tok, _) = recv(tok, start_r); + trace_fmt!("Test start"); - let frames_count = array_size(comp_frame::FRAMES); + let frames_count = array_size(FRAMES); - let tok = join(); // FILL THE LL DEFAULT RAM trace_fmt!("Filling LL default FSE table"); @@ -779,7 +784,7 @@ proc ZstdDecoderTest { let tok = unroll_for! (test_i, tok): (u32, token) in u32:0..frames_count { trace_fmt!("Loading testcase {:x}", test_i + u32:1); - let frame = comp_frame::FRAMES[test_i]; + let frame = FRAMES[test_i]; let tok = for (i, tok): (u32, token) in u32:0..frame.array_length { let req = RamWrReq { addr: i as uN[TEST_RAM_ADDR_W], @@ -839,7 +844,7 @@ proc ZstdDecoderTest { }); let (tok, _) = recv(tok, csr_axi_b_r); - let decomp_frame = comp_frame::DECOMPRESSED_FRAMES[test_i]; + let decomp_frame = DECOMPRESSED_FRAMES[test_i]; // Test ZstdDecoder memory output interface // Mock the output memory buffer as a DSLX array // It is required to handle AXI write transactions and to write the incoming data to @@ -858,7 +863,7 @@ proc ZstdDecoderTest { // The maximal number if beats in AXI burst transaction let MAX_AXI_TRANSFERS = u32:256; // Actual size of decompressed payload for current test - let DECOMPRESSED_BYTES = comp_frame::DECOMPRESSED_FRAMES[test_i].length; + let DECOMPRESSED_BYTES = DECOMPRESSED_FRAMES[test_i].length; trace_fmt!("ZstdDecTest: Start receiving output"); let (tok, final_output_memory, final_output_memory_id, final_transfered_bytes) = for (axi_transaction, (tok, output_memory, output_memory_id, transfered_bytes)): @@ -913,6 +918,142 @@ proc ZstdDecoderTest { tok }(tok); + send(tok, finished_s, ()); + } +} + +#[test_proc] +proc RawLiteralsPredefinedSequencesTest { + terminator: chan out; + start_s: chan<()> out; + finished_r: chan<()> in; + + init {} + + config (terminator: chan out,) { + const FRAMES = comp_frame::FRAMES; + const DECOMPRESSED_FRAMES = comp_frame::DECOMPRESSED_FRAMES; + + let (start_s, start_r) = chan<()>("start"); + let (finished_s, finished_r) = chan<()>("finished"); + + spawn ZstdDecoderTester(start_r, finished_s); + (terminator, start_s, finished_r) + } + + next(state: ()) { + let tok = send(join(), start_s, ()); + let (tok, _) = recv(tok, finished_r); + send(tok, terminator, true); + } +} + +#[test_proc] +proc RleLiteralsRepeatedSequencesTest { + terminator: chan out; + start_s: chan<()> out; + finished_r: chan<()> in; + + init {} + + config (terminator: chan out,) { + + const FRAMES = comp_frame_fse_repeated::FRAMES; + const DECOMPRESSED_FRAMES = comp_frame_fse_repeated::DECOMPRESSED_FRAMES; + + let (start_s, start_r) = chan<()>("start"); + let (finished_s, finished_r) = chan<()>("finished"); + + spawn ZstdDecoderTester(start_r, finished_s); + (terminator, start_s, finished_r) + } + + next(state: ()) { + let tok = send(join(), start_s, ()); + let (tok, _) = recv(tok, finished_r); + send(tok, terminator, true); + } +} + +// TODO: Tests with the `_skip` suffix are disabled in CI +// due to high memory usage. Re-enable them when the DSLX +// interpreter becomes more memory-efficient. + +#[test_proc] +proc RawHuffmanLiteralsPredefinedSequencesTest_skip { + terminator: chan out; + start_s: chan<()> out; + finished_r: chan<()> in; + + init {} + + config (terminator: chan out,) { + const FRAMES = comp_frame_huffman::FRAMES; + const DECOMPRESSED_FRAMES = comp_frame_huffman::DECOMPRESSED_FRAMES; + + let (start_s, start_r) = chan<()>("start"); + let (finished_s, finished_r) = chan<()>("finished"); + + spawn ZstdDecoderTester(start_r, finished_s); + (terminator, start_s, finished_r) + } + + next(state: ()) { + let tok = send(join(), start_s, ()); + let (tok, _) = recv(tok, finished_r); + send(tok, terminator, true); + } +} + +#[test_proc] +proc FseHuffmanLiteralsPredefinedSequencesTest_skip { + terminator: chan out; + start_s: chan<()> out; + finished_r: chan<()> in; + + init {} + + config (terminator: chan out,) { + const FRAMES = comp_frame_huffman_fse::FRAMES; + const DECOMPRESSED_FRAMES = comp_frame_huffman_fse::DECOMPRESSED_FRAMES; + + let (start_s, start_r) = chan<()>("start"); + let (finished_s, finished_r) = chan<()>("finished"); + + spawn ZstdDecoderTester(start_r, finished_s); + (terminator, start_s, finished_r) + } + + next(state: ()) { + let tok = send(join(), start_s, ()); + let (tok, _) = recv(tok, finished_r); + send(tok, terminator, true); + } +} + +#[test_proc] +proc RawHuffmanLiteralsCompressedSequencesTest_skip { + terminator: chan out; + start_s: chan<()> out; + finished_r: chan<()> in; + + init {} + + config (terminator: chan out,) { + + const FRAMES = comp_frame_fse_comp::FRAMES; + const DECOMPRESSED_FRAMES = comp_frame_fse_comp::DECOMPRESSED_FRAMES; + + let (start_s, start_r) = chan<()>("start"); + let (finished_s, finished_r) = chan<()>("finished"); + + spawn ZstdDecoderTester(start_r, finished_s); + (terminator, start_s, finished_r) + } + + next(state: ()) { + let tok = send(join(), start_s, ()); + let (tok, _) = recv(tok, finished_r); send(tok, terminator, true); } } diff --git a/xls/modules/zstd/zstd_frame_dslx.py b/xls/modules/zstd/zstd_frame_dslx.py new file mode 100644 index 0000000000..c5ad2e177b --- /dev/null +++ b/xls/modules/zstd/zstd_frame_dslx.py @@ -0,0 +1,155 @@ +# Copyright 2024 The XLS Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""ZSTD test frame generator for DSLX tests. + +This module interacts with the data_generator module and underlying +Decodecorpus in order to generate inputs and expected outputs for the ZSTD +Decoder tests in DSLX. + +It generates the ZSTD frame and then decodes it with the reference ZSTD +library. Both the encoded frame and decoded data are written to a DSLX file by +converting raw bytes of the frame and decoded data into DSLX structures. + +Resulting file can be included in the ZSTD Decoder DSLX test and used as the +inputs and expected output for the testbench. +""" + +import argparse +import math +import random +import tempfile +import pathlib + +from xls.modules.zstd.cocotb import data_generator + + +def GenerateTestData(seed, btype): + with tempfile.NamedTemporaryFile() as tmp: + data_generator.GenerateFrame(seed, btype, tmp.name) + tmp.seek(0) + return tmp.read() + + +def Bytes2DSLX(frames, bytes_per_word, array_name): + """Converts a list of byte frames to a DSLX constant array declaration. + + Args: + frames (List[bytes]): List of byte sequences representing frames. + bytes_per_word (int): Number of bytes per word in the output format. + array_name (str): Name of the resulting DSLX constant array. + + Returns: + str: A string containing the DSLX constant array declaration. + """ + frames_hex = [] + maxlen = max(len(frame) for frame in frames) + maxlen_size = math.ceil(maxlen / bytes_per_word) + bits_per_word = bytes_per_word * 8 + for i, frame in enumerate(frames): + frame_hex = [] + for i in range(0, len(frame), bytes_per_word): + # reverse byte order to make them little endian + word = bytes(reversed(frame[i : i + bytes_per_word])).hex() + frame_hex.append(f"uN[{bits_per_word}]:0x{word}") + + array_length = len(frame_hex) + if len(frame) < maxlen: + frame_hex += [f"uN[{bits_per_word}]:0x0", "..."] + + frame_array = ( + f"DataArray<{bits_per_word}, {maxlen_size}>{{\n" + f" length: u32:{len(frame)},\n" + f" array_length: u32:{array_length},\n" + f" data: uN[{bits_per_word}][{maxlen_size}]:[{', '.join(frame_hex)}]\n" + f"}}" + ) + frames_hex.append(frame_array) + + frames_str = ",\n".join(frames_hex) + frames_array = ( + f"pub const {array_name}:DataArray<\n" + f" u32:{bits_per_word},\n" + f" u32:{maxlen_size}\n" + f">[{len(frames_hex)}] = [{frames_str}];\n" + ) + return frames_array + + +def GenerateDataStruct(): + return ( + "pub struct DataArray{\n" + " data: uN[BITS_PER_WORD][LENGTH],\n" + " length: u32,\n" + " array_length: u32\n" + "}\n" + ) + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument( + "-n", help="Number of testcases to generate", type=int, default=1 + ) + parser.add_argument( + "--seed", help="Seed for the testcases generator", type=int, default=0 + ) + parser.add_argument( + "--btype", + help=( + "Block types allowed in the generated testcases. If multiple block types " + "are supplied, generated testcases will cycle through them" + ), + type=data_generator.BlockType.from_string, + choices=list(data_generator.BlockType), + default=data_generator.BlockType.RANDOM, + nargs="+", + ) + parser.add_argument( + "-o", + "--output", + help="Filename of the DSLX output file", + type=pathlib.Path, + default=pathlib.Path("frames_test_data.x"), + ) + parser.add_argument( + "--bytes-per-word", + help="Width of a word in memory, in bytes", + type=int, + default=8, + ) + args = parser.parse_args() + + random.seed(args.seed) + byte_frames = [ + GenerateTestData(random.randrange(2**32), args.btype[i % len(args.btype)]) + for i in range(args.n) + ] + with open(args.output, "w") as dslx_output: + dslx_output.write(GenerateDataStruct()) + + dslx_frames = Bytes2DSLX(byte_frames, args.bytes_per_word, "FRAMES") + dslx_output.write(dslx_frames) + + byte_frames_decompressed = list( + map(data_generator.DecompressFrame, byte_frames) + ) + dslx_frames_decompressed = Bytes2DSLX( + byte_frames_decompressed, args.bytes_per_word, "DECOMPRESSED_FRAMES" + ) + dslx_output.write(dslx_frames_decompressed) + + +if __name__ == "__main__": + main()