From c8ddc1cb20602701ea4a3447ec85b24f10c3a605 Mon Sep 17 00:00:00 2001 From: Dan Callaghan Date: Thu, 30 Sep 2021 16:27:26 +1000 Subject: [PATCH] hps: switch SPI flash to DDR mode Signed-off-by: Dan Callaghan --- soc/hps_soc.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/soc/hps_soc.py b/soc/hps_soc.py index 3cdd915e7..418a094fd 100755 --- a/soc/hps_soc.py +++ b/soc/hps_soc.py @@ -161,7 +161,9 @@ def setup_litespi_flash(self): self.submodules.spiflash_phy = LiteSPIPHY( self.platform.request("spiflash4x"), GD25LQ128D(Codes.READ_1_1_4), - default_divisor=0) + default_divisor=0, + rate='1:2', + extra_latency=1) self.submodules.spiflash_mmap = LiteSPI(phy=self.spiflash_phy, mmap_endianness = self.cpu.endianness) self.csr.add("spiflash_mmap")