In some situations interrupt dispatching occurs one instruction early

[tbsp]

The attached test ROM fails to exit the following loop in GB Online, and continues to show an X, because the vblank interrupt fires before the ldh a,[rLY] instruction is processed, and the handler takes enough time that when it returns LY is $91. The loop can be fixed by changing the jr nz to jr nc, but the emulator should be fixed to process the ldh before dispatching the interrupt. This bug was identified as the reason for Adjustris not working in the emulator.

.waitForLY
ldh a,[rLY]
cp $90
jr nz,.waitForLY

On real hardware and many other emulators the test ROM will show a checkmark as it properly exits the wait loop. Some investigation was done by gekkio on 2018-04-03 using his test bench. Some of the findings are as follows:

on real hardware it reads $8F fourteen times
then it reads $90
and then interrupt dispatching starts
so the $FF44 read that returns $90 is the last instruction before the interrupt dispatching happens

ok looks like 16412 NOPs are needed to see LY=90

ld a, $81
ldh (<LCDC), a
; 16412 NOPs
ldh a, (<LY)
; A is now $90

so that's relative to the initial LCDC write
if you put 16411 NOPs instead, A is still $8F

LY=LYC interrupt also happens after LY=$90 appears

ld a, $81
ldh (<LCDC), a
; 16412 NOPs
; 3 NOPs so same duration as ldh a, (<LY)
; <-- interrupt dispatching starts

vblankTest.zip

[avivace]

Thank you for the detailed report and the test rom provided, will be very useful