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Missing pin connection of bus creates wrong verilog #34

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ganeshgore opened this issue Feb 1, 2025 · 0 comments
Open

Missing pin connection of bus creates wrong verilog #34

ganeshgore opened this issue Feb 1, 2025 · 0 comments

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@ganeshgore
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if one of the bits of x-bit ports is not connected to the wire the generated Verilog is incorrect.
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@ganeshgore