.gitlab-ci.yml

# Copyright 2023 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

variables:
  GIT_STRATEGY: clone
  GIT_SUBMODULE_STRATEGY: recursive
  # Enable colors in CI terminal
  TERM: ansi
  FORCE_COLOR: 1
  # Configure environment
  CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_LINKER: /usr/pack/gcc-9.2.0-af/linux-x64/bin/gcc
  LLVM_SYS_120_PREFIX: /usr/pack/llvm-12.0.1-af
  CMAKE: cmake-3.18.1
  UV_CACHE_DIR: $CI_BUILDS_DIR/../cache/uv

default:
  # Allow interrupting long-running jobs when a new pipeline on the same branch is triggered
  interruptible: true
  timeout: 60m
  before_script:
    # The CI is configured such that the uv cache directory (`UV_CACHE_DIR`),
    # is located on the same file system outside of the build directory.
    # `uv` should try to hardlink files instead of copying them to save space
    - export UV_LINK_MODE=hardlink
    - source iis-setup.sh

##############
# Build docs #
##############

docs:
  script:
    - make docs

#####################
# Python unit tests #
#####################

pytest:
  script:
    - pytest

#################################
# Build Snitch cluster software #
#################################

snitch-cluster-sw:
  script:
    - make sw -j
  artifacts:
    paths:
      - sw/**/build/*.elf
    expire_in: 1 day

#######################
# Standalone IP tests #
#######################

# Build and run all individual IP testbenches.
# Currently missing IP tests:
# - snitch_vm
# - snitch_ipu
# - snitch_dma
# - snitch
snitch-ip-tests:
  parallel:
    matrix:
      - IP:
          - mem_interface
          - snitch_cluster
          - tcdm_interface
          - snitch_ssr
          - reqrsp_interface
  script:
    - cd hw/$IP
    - ./util/compile.sh
    - ./util/run_vsim.sh

####################
# Simulation tests #
####################

# Verilator
snitch-cluster-vlt:
  needs: [snitch-cluster-sw]
  script:
    - make verilator
    - cd test
    - ../util/experiments/run.py run.yaml --simulator verilator -j --run-dir runs/vlt

# VCS
snitch-cluster-vcs:
  needs: [snitch-cluster-sw]
  script:
    - make vcs
    - cd test
    - ../util/experiments/run.py run.yaml --simulator vcs -j --run-dir runs/vcs

# Questa
snitch-cluster-vsim:
  needs: [snitch-cluster-sw]
  script:
    - make vsim -j
    - cd test
    - ../util/experiments/run.py run.yaml --simulator vsim -j --run-dir runs/vsim
    - ../util/experiments/run.py riscv_tests_isa.yaml --simulator vsim -j --run-dir runs/vsim
    # Test convenience Make target
    - cd ..
    - make vsim-run SN_BINARY=$PWD/sw/kernels/blas/axpy/build/axpy.elf \
        SN_VERIFY_PY=$PWD/sw/kernels/blas/axpy/scripts/verify.py
    # Test trace annotation
    - make SIM_DIR=$PWD/test/runs/vsim/simple annotate -j
    # Run additional, more extensive tests
    - cd test/blas/gemm && ./test.sh && cd -
    - cd test/dnn/transpose && ./test.sh && cd -
    - cd test/dnn/flashattention_2 && ./test.sh && cd -
  artifacts:
    when: on_failure
    expire_in: 1 day
    paths:
      - test/runs/vsim/**/sim.txt


# Test OmegaNet TCDM interconnect
snitch-cluster-omega-vsim:
  script:
    - make CFG_OVERRIDE=cfg/omega.json sw -j
    - make vsim -j
    - cd test
    - ../util/experiments/run.py run.yaml --simulator vsim -j --run-dir runs/vsim

# Test Multi-channel DMA
snitch-cluster-mchan-vsim:
  script:
    - make CFG_OVERRIDE=cfg/dma_mchan.json sw -j
    - make vsim -j
    - cd test
    - ../util/experiments/run.py dma_mchan.yaml --simulator vsim -j --run-dir runs/vsim

# Test Mempool configuration
snitch-cluster-mempool-vsim:
  script:
    - make CFG_OVERRIDE=cfg/mempool.json SN_MCPU=snitch-mempool sw -j
    - make vsim -j
    - cd test
    - ../util/experiments/run.py mempool.yaml --simulator vsim -j --run-dir runs/vsim
    - make -C .. SIM_DIR=$PWD/runs/vsim/simple SN_MCPU=snitch-mempool annotate -j

# Additional tests for different FREP configurations
snitch-cluster-frep-vsim:
  script:
    # Large FREP configuration
    - make CFG_OVERRIDE=cfg/frep_xl.json sw -j
    - make vsim -j
    - cd test
    - ../util/experiments/run.py frep_xl.yaml --simulator vsim -j --run-dir runs/vsim
    - cd -
    # Small FREP configuration
    - make CFG_OVERRIDE=cfg/frep_xs.json sw -j
    - make vsim -j
    - cd test
    - ../util/experiments/run.py frep_xs.yaml --simulator vsim -j --run-dir runs/vsim

# COPIFT and scalar chaining experiments
snitch-cluster-copift-sc-vsim:
  script:
    - make CFG_OVERRIDE=experiments/copift/cfg.json vsim -j
    - cd experiments/copift
    - ./experiments.py experiments.yaml --actions sw run perf -j
    - cd ../chaining
    - ./experiments.py experiments.yaml --actions sw run perf -j

###################################
# Open-source implementation flow #
###################################

yosys-synthesis:
  timeout: 2h
  script:
    - make CFG_OVERRIDE=cfg/yosys-ci.json yosys
    # Following steps are not included in open-source CI since netlist
    # compilation with Verilator takes an excessive amount of time and memory.
    - make PS_FREE_SIM=1 vsim
    - make sw -j
    - make vsim-run SN_BINARY=$PWD/sw/tests/build/simple.elf

################################
# Non-free implementation flow #
################################

nonfree:
  script:
    - make nonfree
    - make elab