From 307938fff4f7653932e496d9ed572741ef347624 Mon Sep 17 00:00:00 2001 From: fyquah Date: Wed, 6 Dec 2023 21:27:58 +0000 Subject: [PATCH] Cherry pick ben's docs changes --- README.md | 6 ++++-- zprize/msm_pippenger/README.md | 5 ++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 721a4fe0..c2204b21 100644 --- a/README.md +++ b/README.md @@ -47,8 +47,10 @@ opam exec -- dune build opam exec -- dune runtest ``` -Now please continue to the relevant section listed [above](#zprize-submissions) -to build the top level designs from source. +Now please continue to the relevant to build the top level designs from source. + +- [MSM](zprize/msm_pippenger/README.md) +- [NTT](zprize/ntt/) # Contributing diff --git a/zprize/msm_pippenger/README.md b/zprize/msm_pippenger/README.md index d6fb3a39..6b8d72ff 100644 --- a/zprize/msm_pippenger/README.md +++ b/zprize/msm_pippenger/README.md @@ -143,7 +143,7 @@ still being able to successfully route in Vivado. Instructions are given below for building from source. A prerequisite is that OCaml has been setup (outlined in the main [README.md](../../README.md)). -It is important you use the AMI version 1.10.5 and Vivado version 2020.2 to +It is important you use the [FPGA Developer AMI (Amazon Linux 2)](https://aws.amazon.com/marketplace/pp/prodview-iehshpgi7hcjg) version 1.10.5 and Vivado version 2020.2 to acheive the same results. The rtl_checksum expected of the Verilog when generated from the Hardcaml source is 1929f78e1e4bafd9cf88d507a3afa055. @@ -188,8 +188,7 @@ more points. ## Building an FPGA image for AWS You need to clone the [aws-fpga repo](https://github.com/aws/aws-fpga/), as well -as run on an AWS box with the [FPGA Developer -AMI](https://aws.amazon.com/marketplace/pp/prodview-gimv3gqbpe57k) installed. +as run on an AWS box with the [FPGA Developer AMI (Amazon Linux 2)](https://aws.amazon.com/marketplace/pp/prodview-iehshpgi7hcjg) installed. ``` source ~/aws-fpga/vitis_setup.sh