From 5fb109f3d30fa235b43a34b17b03c0f9a5c3d4a2 Mon Sep 17 00:00:00 2001 From: Anders Olofsson Date: Fri, 21 Nov 2014 21:55:46 +0100 Subject: [PATCH] 8086, ARMv7, CRISv10, CRISv32 and MIPS32r2 --- .gitignore | 3 + 8086.tex | 325 ++++++++++++++++++++++++++++++++++ Makefile | 13 ++ README | 76 ++++++++ armv7.tex | 480 +++++++++++++++++++++++++++++++++++++++++++++++++++ crisv10.tex | 334 +++++++++++++++++++++++++++++++++++ crisv32.tex | 315 +++++++++++++++++++++++++++++++++ mips32r2.tex | 327 +++++++++++++++++++++++++++++++++++ sheet.cls | 96 +++++++++++ 9 files changed, 1969 insertions(+) create mode 100644 .gitignore create mode 100644 8086.tex create mode 100644 Makefile create mode 100644 README create mode 100644 armv7.tex create mode 100644 crisv10.tex create mode 100644 crisv32.tex create mode 100644 mips32r2.tex create mode 100644 sheet.cls diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..3eec47d --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +*.aux +*.log +*.pdf diff --git a/8086.tex b/8086.tex new file mode 100644 index 0000000..f76423e --- /dev/null +++ b/8086.tex @@ -0,0 +1,325 @@ +% +% Copyright (C) 2014 Anders Olofsson +% +% Copying and distribution of this file, with or without modification, +% are permitted in any medium without royalty provided the copyright +% notice and this notice are preserved. This file is offered as-is, +% without any warranty. +% +\documentclass{sheet} +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{ae,aecompl} +\usepackage[english]{babel} +\usepackage[a4paper, landscape, margin=.1in]{geometry} +\usepackage{amssymb} + +\def\sheetheaderfont{\bfseries} +\def\sheettablefont{\footnotesize\sffamily} +\def\sheetheadercolor{black!10} +\def\sheetrowcolor{black!5} + +\def\tabcolsep{2pt} +\def\arraystretch{1.3} +\defsheet{asmtable}{4}{|m{3.7em} m{4.1em}|X|m{3.1em}|} +\defsheet{asmtable2}{4}{|m{6.8em} m{1em}|X|m{3.1em}|} +\defsheet{table-X}{1}{|X|} +\defsheet{table-lX}{2}{|l X|} +\defsheet{table-lXX}{3}{|l X X|} +\defsheet{table-llXl}{4}{|l l X l|} + +\pagefooter{8086 version 1.0 page \thepage} + +\begin{document} +\begin{multicols}{3} +\raggedcolumns + +\begin{center} +{\Large\bfseries 8086 Quick Reference} +\end{center} +% +\begin{table-lX}{Keys} +i & Immediate operand \\ +a & Accumulator (AL or AX) \\ +r & General register (AX,BX,CX,DX,SI,DI,BP,SP or 8bit parts) \\ +seg & Segment register (CS,DS,SS,ES) \\ +sh & Shift operand (1 or CL) \\ +d & Destination operand (register or memory) \\ +s & Source operand (register, memory or immediate) \\ +cc & Condidion code \\ +value$^{\pm}_{ }$ & Value is sign extended \\ +$\smul$ $\sdiv$ $\asr$ & Operation is signed \\ +****** & Flags COZSPA are affected (*), undefined (u), cleared (0) \\ +\end{table-lX} +% +\begin{asmtable}{Arithmetic Instructions} +ADC & d, s & d = d $+$ (s $+$ C) & ****** \\ +ADD & d, s & d = d $+$ s & ****** \\ +CBW & & AX = AL$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +CMP & d, s & d $-$ s & ****** \\ +CWD & & DX:AX = AX$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +DEC & d & d = d $-$ 1 & {--}***** \\ +DIV & d$^{ }_{8}$ & AL = AX $\udiv$ d; AH = AX $\umod$ d & uuuuuu \\ +DIV & d$^{ }_{16}$ & AX = DX:AX $\udiv$ d; DX = DX:AX $\umod$ d & uuuuuu \\ +IDIV & d$^{ }_{8}$ & AL = AX $\sdiv$ d; AH = AX $\smod$ d & uuuuuu \\ +IDIV & d$^{ }_{16}$ & AX = DX:AX $\sdiv$ d; DX = DX:AX $\smod$ d & uuuuuu \\ +IMUL & d$^{ }_{8}$ & AX = AL $\smul$ d & **uuuu \\ +IMUL & d$^{ }_{16}$ & DX:AX = AX $\smul$ d & **uuuu \\ +INC & d & d = d $+$ 1 & {--}***** \\ +LEA & r$^{ }_{16}$, [m] & r = m & {--}{--}{--}{--}{--}{--} \\ +MUL & d$^{ }_{8}$ & AX = AL $\umul$ d & **uuuu \\ +MUL & d$^{ }_{16}$ & DX:AX = AX $\umul$ d & **uuuu \\ +NEG & d & d = 0 $-$ d & ****** \\ +SBB & d, s & d = d $-$ (s $+$ C) & ****** \\ +SUB & d, s & d = d $-$ s & ****** \\ +\end{asmtable} +% +\begin{asmtable}{I/O Instructions} +HLT & & Wait for reset, NMI or INT & {--}{--}{--}{--}{--}{--} \\ +IN & a, i$^{ }_{8}$ & a = IO[i] & {--}{--}{--}{--}{--}{--} \\ +IN & a, DX & a = IO[DX] & {--}{--}{--}{--}{--}{--} \\ +\textit{NOP} & & & {--}{--}{--}{--}{--}{--} \\ +OUT & i$^{ }_{8}$, a & IO[i] = a & {--}{--}{--}{--}{--}{--} \\ +OUT & DX, a & IO[DX] = a & {--}{--}{--}{--}{--}{--} \\ +\end{asmtable} +% +\begin{asmtable}{Jump and Branch Instructions} +CALL & rel$^{ }_{16}$ & PUSH IP; IP $+$= rel & {--}{--}{--}{--}{--}{--} \\ +CALL & ptr$^{ }_{32}$ & PUSH CS,IP; CS:IP = ptr & {--}{--}{--}{--}{--}{--} \\ +CALL & d$^{ }_{16}$ & PUSH IP; IP = d & {--}{--}{--}{--}{--}{--} \\ +CALL & [m$^{ }_{32}$] & PUSH CS,IP; CS:IP = [m] & {--}{--}{--}{--}{--}{--} \\ +INT & i$^{ }_{8}$ & PUSH F,CS,IP; CS:IP=[0:4*i]; I=0 & {--}{--}{--}{--}{--}{--} \\ +INTO & & if(O) INT 4 & {--}{--}{--}{--}{--}{--} \\ +IRET & & POP IP,CS,F & ****** \\ +Jcc & rel$^{ }_{8}$ & if(cc) IP $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +JCXZ & rel$^{ }_{8}$ & if(CX $=$ 0) IP $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +JMP & rel & IP $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +JMP & ptr$^{ }_{32}$ & CS:IP = ptr & {--}{--}{--}{--}{--}{--} \\ +JMP & d$^{ }_{16}$ & IP = d & {--}{--}{--}{--}{--}{--} \\ +JMP & [m$^{ }_{32}$] & CS:IP = [m] & {--}{--}{--}{--}{--}{--} \\ +LOOP & rel$^{ }_{8}$ & if($--$CX $\ne$ 0) IP $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +LOOPE & rel$^{ }_{8}$ & if(Z \&\& $--$CX $\ne$ 0) IP $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +LOOPNE & rel$^{ }_{8}$ & if(!Z \&\& $--$CX $\ne$ 0) IP $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--}{--}{--} \\ +RET & & POP IP & {--}{--}{--}{--}{--}{--} \\ +RET & i$^{ }_{16}$ & POP IP; SP $+$= i & {--}{--}{--}{--}{--}{--} \\ +RETF & & POP IP,CS & {--}{--}{--}{--}{--}{--} \\ +RETF & i$^{ }_{16}$ & POP IP,CS; SP $+$= i & {--}{--}{--}{--}{--}{--} \\ +\end{asmtable} +% +\begin{asmtable}{Flag Instructions} +CLC & & C = 0 & 0{--}{--}{--}{--}{--} \\ +CLD & & D = 0 & {--}{--}{--}{--}{--}{--} \\ +CLI & & I = 0 & {--}{--}{--}{--}{--}{--} \\ +CMC & & C = !C & *{--}{--}{--}{--}{--} \\ +LAHF & & AH = S:Z:0:A:0:P:1:C & {--}{--}{--}{--}{--}{--} \\ +POPF & & POP -:-:-:-:O:D:I:T:S:Z:-:A:-:P:-:C & ****** \\ +PUSHF & & PUSH 1:1:1:1:O:D:I:T:S:Z:0:A:0:P:1:C & {--}{--}{--}{--}{--}{--} \\ +SAHF & & S:Z:-:A:-:P:-:C = AH & *{--}**** \\ +SALF & & AL = (C ? 0xff : 0x00) & {--}{--}{--}{--}{--}{--} \\ +STC & & C = 1 & 1{--}{--}{--}{--}{--} \\ +STD & & D = 1 & {--}{--}{--}{--}{--}{--} \\ +STI & & I = 1 & {--}{--}{--}{--}{--}{--} \\ +\end{asmtable} +% +\begin{asmtable2}{String Instructions} +CMPS\{BW\} & & [SI] $-$ [ES:DI]; Advance SI and DI & ****** \\ +LODS\{BW\} & & a = [SI]; Advance SI & {--}{--}{--}{--}{--}{--} \\ +MOVS\{BW\} & & [ES:DI] = [SI]; Advance SI and DI & {--}{--}{--}{--}{--}{--} \\ +SCAS\{BW\} & & a - [SI]; Advance SI & ****** \\ +STOS\{BW\} & & [ES:DI] = a; Advance DI & {--}{--}{--}{--}{--}{--} \\ +\end{asmtable2} +% +\begin{asmtable}{Bitwise Instructions} +AND & d, s & d = d \& s & 00***u \\ +NOT & d & d = $\sim$d & {--}{--}{--}{--}{--}{--} \\ +OR & d, s & d = d | s & 00***u \\ +RCL & d, sh & C:d = C:d $\rol$ sh & **{--}{--}{--}{--} \\ +RCR & d, sh & C:d = C:d $\ror$ sh & **{--}{--}{--}{--} \\ +ROL & d, sh & d = d $\rol$ sh & **{--}{--}{--}{--} \\ +ROR & d, sh & d = d $\ror$ sh & **{--}{--}{--}{--} \\ +SAR & d, sh & d = d $\asr$ sh & *****u \\ +SHL & d, sh & d = d $\lsl$ sh & *****u \\ +SHR & d, sh & d = d $\lsr$ sh & *****u \\ +TEST & d, s & d \& s & 00***u \\ +XOR & d, s & d = d $\oplus$ s & 00***u \\ +\end{asmtable} +% +\begin{asmtable}{Data Transfer Instructions} +LDS & r$^{ }_{16}$, [m$^{ }_{32}$] & DS:r = [m] & {--}{--}{--}{--}{--}{--} \\ +LES & r$^{ }_{16}$, [m$^{ }_{32}$] & ES:r = [m] & {--}{--}{--}{--}{--}{--} \\ +MOV & d, s & d = s & {--}{--}{--}{--}{--}{--} \\ +MOV & d$^{ }_{16}$, seg & d = seg & {--}{--}{--}{--}{--}{--} \\ +MOV & seg, d$^{ }_{16}$ & seg = d & {--}{--}{--}{--}{--}{--} \\ +POP & d$^{ }_{16}$ & SP $+$= 2; d = [SS:SP$-$2] & {--}{--}{--}{--}{--}{--} \\ +POP & seg & SP $+$= 2; seg = [SS:SP$-$2] & {--}{--}{--}{--}{--}{--} \\ +PUSH & d$^{ }_{16}$ & SP $-$= 2; [SS:SP$-$2] = d & {--}{--}{--}{--}{--}{--} \\ +PUSH & seg & SP $-$= 2; [SS:SP$-$2] = seg & {--}{--}{--}{--}{--}{--} \\ +XCHG & r, d & r:d = d:r & {--}{--}{--}{--}{--}{--} \\ +XLAT & & AL = [BX $+$ AL] & {--}{--}{--}{--}{--}{--} \\ +\end{asmtable} +% +\begin{asmtable}{BCD Instructions} +AAA & & if(AL$^{ }_{3:0}$>9 || A) AL=(AL$+$6)\&0x0f; AH$++$; \newline A=C=1; else AL=AL\&0x0f; A=C=0 & *uuuu* \\ +AAD & i$^{ }_{8}$ & AL = AL $+$ AH $\umul$ i; AH = 0 & uu***u \\ +AAM & i$^{ }_{8}$ & AL = AL $\udiv$ i; AH = AL $\umod$ i & uu***u \\ +AAS & & if(AL$^{ }_{3:0}$>9 || A) AL=(AL$-$6)\&0x0f; AH$--$; \newline A=C=1; else AL=AL\&0x0f; A=C=0 & *uuuu* \\ +DAA & & if(AL$^{ }_{3:0}$>9 || A) C:AL$+$=6; A=1; else A=0 \newline if(AL$^{ }_{7:4}$>9 || C) AL$+$=0x60; C=1; else C=0 & *u**** \\ +DAS & & if(AL$^{ }_{3:0}$>9 || A) C:AL$-$=6; A=1; else A=0 \newline if(AL$^{ }_{7:4}$>9 || C) AL$-$=0x60; C=1; else C=0 & *u**** \\ +\end{asmtable} +% +\begin{asmtable}{Prefix Instructions} +seg: & & Use seg instead of DS or SS & {--}{--}{--}{--}{--}{--} \\ +LOCK & & Assert LOCK\# & {--}{--}{--}{--}{--}{--} \\ +REP & strcmd & do \{ strcmd; CX{-}{-} \} while(CX $\ne$ 0) & {--}{--}{--}{--}{--}{--} \\ +REPE & strcmd & do \{ strcmd; CX{-}{-} \} while(Z \&\& CX $\ne$ 0) & ****** \\ +REPNE & strcmd & do \{ strcmd; CX{-}{-} \} while(!Z \&\& CX $\ne$ 0) & ****** \\ +\end{asmtable} +% +\begin{table-lX}{Execution Times} +ADC/ADD/AND/OR/SUB/SBB/XOR r,r | r,m | m,r & 3 | 9+ea | 16+ea \\ +ADC/ADD/AND/OR/SUB/SBB/XOR r,i | m,i & 4 | 17+ea \\ +CMP r,r | CMP r,i | CMP r,m | CMP m,i & 3 | 4 | 9+ea | 10+ea \\ +TEST r,r | TEST r,i | TEST r,m | TEST m,i & 3 | 5 | 9+ea | 11+ea \\ +DEC/INC r | DEC/INC m & 3 | 15+ea \\ +NEG/NOT r | NEG/NOT m & 3 | 16+ea \\ +shift/rotate r,1 | shift/rotate m,1 & 2 | 15+ea \\ +shift/rotate r,CL | shift/rotate m,CL & 8+4n | 20+4n+ea \\ +CBW | CWD | LEA | LDS/LES & 2 | 5 | 2+ea | 16+ea \\ +MOV r,i | MOV m,i & 4 | 10+ea \\ +MOV r/seg,r/seg | MOV r/seg,m | MOV m,r/seg & 2 | 8+ea | 9+ea \\ +MOV a,[i$^{ }_{16}$] | MOV [i$^{ }_{16}$],a | XLAT & 10 | 10 | 11 \\ +XCHG r$^{ }_{16}$,AX | XCHG r,r | XCHG r,m & 3 | 4 | 17+ea \\ +PUSH r | PUSHF | PUSH seg | PUSH m & 10 | 10 | 11 | 16+ea \\ +POP r | POPF | POP seg | POP m & 8 | 8 | 8 | 17+ea \\ +CL\{CDI\}/ST\{CDI\}/CMC | SALC | LAHF/SAHF & 2 | 3 | 4 \\ +DAA/DAS | AAA/AAS | AAD | AAM & 4 | 8 | 60 | 83 \\ +IN/OUT DX | IN/OUT i | HLT | WAIT & 8 | 10 | 2 | 4 \\ +JMP rel | JMP ptr$^{ }_{32}$ | CALL rel | CALL ptr$^{ }_{32}$ & 15 | 15 | 19 | 28 \\ +JMP r | JMP m$^{ }_{16}$ | JMP m$^{ }_{32}$ & 11 | 18+ea | 24+ea \\ +CALL r | CALL m$^{ }_{16}$ | CALL m$^{ }_{32}$ & 16 | 21+ea | 37+ea \\ +Jcc | JCXZ & 4/16 | 6/18 \\ +LOOP | LOOPE/LOOPNE & 5/18 | 5/19 \\ +RET | RET i | RETF | RETF i | IRET & 16 | 20 | 26 | 25 | 32 \\ +INT i | INT 3 | INTO | Ext INT & 51 | 52 | 4/53 | 61 \\ +STOS\{BW\} | REP STOS\{BW\} & 11 | 9+10n \\ +LODS\{BW\} | REP LODS\{BW\} & 12 | 9+13n \\ +MOVS\{BW\} | REP MOVS\{BW\} & 18 | 9+17n \\ +SCAS\{BW\} | REPE/REPNE SCAS\{BW\} & 15 | 9+15n \\ +CMPS\{BW\} | REPE/REPNE CMPS\{BW\} & 22 | 9+22n \\ +MUL r$^{ }_{8}$ | MUL r$^{ }_{16}$ & 70-77 | 118-135 \\ +IMUL r$^{ }_{8}$ | IMUL r$^{ }_{16}$ & 80-89 | 128-154 \\ +DIV r$^{ }_{8}$ | DIV r$^{ }_{16}$ & 80-90 | 144-162 \\ +IDIV r$^{ }_{8}$ | IDIV r$^{ }_{16}$ & 101-112 | 165-184 \\ +DIV/IDIV/MUL/IMUL with mem instead of reg & +6+ea \\ +Segment override or LOCK prefix & +2 \\ +Word operand at odd address & +4 \\ +{}[BX], [SI], [DI] & ea = 5 \\ +{}[i$^{ }_{16}$] & ea = 6 \\ +{}[BX$+$SI] or [BP$+$DI] & ea = 7 \\ +{}[BX$+$DI] or [BP$+$SI] & ea = 8 \\ +{}[BX$+$i$^{\pm}_{ }$], [BP$+$i$^{\pm}_{ }$] [SI$+$i$^{\pm}_{ }$], [DI$+$i$^{\pm}_{ }$] & ea = 9 \\ +{}[BX$+$SI$+$i$^{\pm}_{ }$] or [BP$+$DI$+$i$^{\pm}_{ }$] & ea = 11 \\ +{}[BX$+$DI$+$i$^{\pm}_{ }$] or [BP$+$SI$+$i$^{\pm}_{ }$] & ea = 12 \\ +\end{table-lX} +% +\begin{table-lX}{Registers} +AX & Accumulator Register (AL, AH) \\ +BX & Base Register (BL, BH) \\ +CX & Counter Register (CL, CH) \\ +DX & Data Register (DL, DH) \\ +SI & Source Index \\ +DI & Destination Index \\ +BP & Base Pointer \\ +SP & Stack Pointer \\ +IP & Instruction Pointer \\ +F & Flags (O,D,I,T,S,Z,A,P,C) \\ +CS & Code Segment \\ +DS & Data Segment \\ +SS & Stack Segment \\ +ES & Extra Segment \\ +\end{table-lX} +% +\begin{table-llXl}{Flags} +C & 0x0001 & Carry Flag & CY, NC \\ +P & 0x0004 & Parity Flag & PE, PO \\ +A & 0x0010 & Auxiliary Flag & AC, NA \\ +Z & 0x0040 & Zero Flag & ZR, NZ \\ +S & 0x0080 & Sign Flag & NG, PL \\ +T & 0x0100 & Trap Flag & \\ +I & 0x0200 & Interrupt Flag & EI, DI \\ +D & 0x0400 & Direction Flag & DN, UP \\ +O & 0x0800 & Overflow Flag & OV, NV \\ +\end{table-llXl} +% +\begin{table-lX}{DEBUG Commands} +A [\emph{address}] & Assemble instructions \\ +C \emph{range} \emph{address} & Compare memory \\ +D [\emph{address} | \emph{range}] & Dump memory \\ +E \emph{address} [\emph{list}] & Enter data \\ +F \emph{range} \emph{list} & Fill data \\ +G [=\emph{address}] [\emph{address} [\emph{address}...]] & Execute (with optional breakpoints) \\ +H \emph{value} \emph{value} & Add and subtract values \\ +I \emph{portaddress} & Read byte from I/O port \\ +L [\emph{address} [\emph{drive} \emph{sector} \emph{count}]] & Load file or sectors (sets BX:CX to size) \\ +M \emph{range} \emph{address} & Move memory \\ +N \emph{filename} [\emph{parameters}] & Set filename and command arguments \\ +O \emph{portaddress} \emph{value} & Write byte to I/O port \\ +Q & Quit DEBUG \\ +R [\emph{registername}] & Display and modify registers(s) \\ +S \emph{range} \emph{list} & Search memory \\ +T [=\emph{address}] [\emph{count}] & Trace \\ +U [\emph{address} | \emph{range}] & Unassemble instructions \\ +W [\emph{address} [\emph{drive} \emph{sector} \emph{count}]] & Load file or sectors (size is BX:CX) \\ +\end{table-lX} +% +\begin{table-lXX}{Condition Codes} +O & Overflow & !O \\ +NO & No overflow & O \\ +B, NAE, C & Below, Carry set & C \\ +NB, AE, NC & Above or equal, Carry clear & !C \\ +E, Z & Equal, Zero & Z \\ +NE, NZ & Not equal, Not zero & !Z \\ +BE, NA & Below or equal & C | Z \\ +NBE, A & Above & !C \& !Z \\ +S & Sign & S \\ +NS & Not sign & !S \\ +P, PE & Parity, Even parity & P \\ +NP, PO & Not parity, Odd parity & !P \\ +L, NGE & Less than & S $\ne$ O \\ +NL, GE & Greater than or equal to & S $=$ O \\ +LE, NG & Less than or equal to & S $\ne$ O | Z \\ +NLE, G & Greater than & S $=$ O \& !Z \\ +\end{table-lXX} +% +\begin{table-lX}{Interrupt Vectors} +0x00 & Divide error (DIV/IDIV/AAM instructions) \\ +0x01 & Single step (Trap flag) \\ +0x02 & NMI signal \\ +0x03 & Breakpoint (INT 3 instruction) \\ +0x04 & Overflow (INTO instruction) \\ +0x08 & IRQ 0 (Timer 0) \\ +0x09 & IRQ 1 (Keyboard) \\ +0x0a & IRQ 2 \\ +0x0b & IRQ 3 \\ +0x0c & IRQ 4 (First serial port) \\ +0x0d & IRQ 5 \\ +0x0e & IRQ 6 (Floppy controller) \\ +0x0f & IRQ 7 (First parallel port) \\ +\end{table-lX} +% +\begin{table-X}{Notes} +Any write to a segment disables interrupts and traps for one instruction. \\ +Source and destination operands can't both be memory at the same time. \\ +Default segment is SS when BP is used as index, otherwise DS. \\ +String instructions increase/decrease SI and DI by data size when D is 0/1. \\ +Shift/rotate right by 1 sets O flag to xor of two lowest bits. \\ +Shift/rotate left by 1 sets O flag to xor of C and highest bit. \\ +Instruction prefetch queue is 6 bytes. \\ +POP and MOV to CS is possible on 8086 but invalid opcodes on later CPUs. \\ +Shift/rotate uses all bits of CL on 8086 but only lower 5 bits on later CPUs. \\ +PUSH SP pushes decremented SP on 8086. Later CPUs push original SP. \\ +DEBUG range parameter is either "\emph{start} \emph{end}" or "\emph{start} L \emph{end}". \\ +\end{table-X} +% +\end{multicols} +\end{document} diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..5707b92 --- /dev/null +++ b/Makefile @@ -0,0 +1,13 @@ +TARGETS = 8086.pdf mips32r2.pdf armv7.pdf crisv10.pdf crisv32.pdf + +all: $(TARGETS) + +$(TARGETS): sheet.cls + +# Build twice to make sure the footers get correct positions +%.pdf: %.tex + pdflatex -halt-on-error $< + pdflatex -halt-on-error $< + +clean: + rm -f *.pdf *.log *.aux diff --git a/README b/README new file mode 100644 index 0000000..7f2b138 --- /dev/null +++ b/README @@ -0,0 +1,76 @@ +Instruction Set Quick Reference Sheets +Copyright (C) 2014 Anders Olofsson + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. This file is offered as-is, +without any warranty. + + +Purpose +======= +I made these reference sheets because I found myself needing them and +apart from a MIPS32 quick reference [8] I was unable to find any +instruction set references that would fit a single page and still have +all the details I wanted. +The purpose of these sheets are to get as much information as possible +in a few pages making it possible for someone who already knows the +architecture to have an overview of the instruction set. +I've also tried to use common syntaxes for the instruction descriptions +rather than following some architecture specific conventions to make +the sheets look consistent. + + +Included Sheets +=============== + +8086 +---- +Instruction set of Intel 8086 including execution times for all +instructions. Also includes a quick help for using DOS DEBUG. +Note that this is a pure 8086 sheet, i.e. no instructions or features +added by later x86 processors are included. +Floating point instructions for 8087 are not included. + +Note: I was unable to find the execution time for SETALC instruction + anywhere so the value listed is derived from testing on an actual + AMD 8086 CPU. + + +ARM v7 +------ +Instruction sets of ARM, Thumb and Thumb2 including version information +for ARM versions 6, 6T, 6k and 7. +Floating point and coprocessor instructions are not included + + +CRIS v10 +-------- +Instruction set of CRIS v10 including all memory addressing modes, +execution times and examples for performing multiplication and +division. + + +CRIS v32 +-------- +Instruction set of CRIS v32 including execution times and example for +performing division. + + +MIPS32 R2 +--------- +Instruction sets of MIPS32 release 2 and MIPS16e. +Floating point and coprocessor 2 instructions are not included. + + +Sources +======= +[1] Various internet sources, notably HelpPC for 8086 execution times. +[2] "Intel 64 and IA-32 architectures software developer's manual" +[3] "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition" +[4] "AXIS ETRAX 100LX Programmer's Manual" +[5] "ETRAX FS Designer's Reference" +[6] Additional information about CRIS architectures (with permission) + from internal resources within AXIS Communications. +[7] "MIPS32 Architecture For Programmers" (MD00086 and MD00076) +[8] "MIPS32 Instruction Set Quick Reference" (MD00565) diff --git a/armv7.tex b/armv7.tex new file mode 100644 index 0000000..17ace6b --- /dev/null +++ b/armv7.tex @@ -0,0 +1,480 @@ +% +% Copyright (C) 2014 Anders Olofsson +% +% Copying and distribution of this file, with or without modification, +% are permitted in any medium without royalty provided the copyright +% notice and this notice are preserved. This file is offered as-is, +% without any warranty. +% +\documentclass{sheet} +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{ae,aecompl} +\usepackage[english]{babel} +\usepackage[a4paper, landscape, margin=.1in]{geometry} +\usepackage{amssymb} +\usepackage{verbatim} + +\def\sheetheaderfont{\bfseries} +\def\sheettablefont{\footnotesize\sffamily} +\def\sheetheadercolor{black!10} +\def\sheetrowcolor{black!5} + +\newcolumntype{N}{>{\raggedleft\arraybackslash}m{1.8em}} +\def\tabcolsep{2pt} +\def\arraystretch{1.3} +\defsheet{asmtable}{4}{|m{4.6em} m{6.7em}|X|N|} +\defsheet{table-lX}{2}{|l X|} +\defsheet{table-lXN}{3}{|l|X|N|} +\defsheet{table-llX}{3}{|l l X|} + +\pagefooter{ARMv7 version 1.0 page \thepage} + +\begin{document} +\begin{multicols}{3} +\raggedcolumns + +\begin{center} +{\Large\bfseries ARMv7 Quick Reference} +\end{center} +% +\begin{asmtable}{Arithmetic Instructions} +ADC\{S\} & rx, ry, op2 & rx = ry $+$ op2 $+$ C & \\ +ADD\{S\} & rx, ry, op2 & rx = ry $+$ op2 & \\ +ADDW & rx, ry, \#i$^{ }_{12}$ & rx = ry $+$ i$^{\emptyset}_{ }$ & T \\ +ADR & rx, $\pm$rel$^{ }_{12}$ & rx = PC $\pm$ rel & \\ +CMN & rx, op2 & rx $+$ op2 & \\ +CMP & rx, op2 & rx $-$ op2 & \\ +QADD & rx, ry, rz & rx = SATS(ry $+$ rz, 32) & \\ +QDADD & rx, ry, rz & rx = SATS(ry $+$ SATS(2$\times$rz, 32), 32) & \\ +QDSUB & rx, ry, rz & rx = SATS(ry $-$ SATS(2$\times$rz, 32), 32) & \\ +QSUB & rx, ry, rz & rx = SATS(ry $-$ rz, 32) & \\ +RSB\{S\} & rx, ry, op2 & rx = op2 $-$ ry & \\ +RSC\{S\} & rx, ry, op2 & rx = op2 $-$ (ry $+$ C) & A \\ +SBC\{S\} & rx, ry, op2 & rx = ry $-$ (op2 $+$ C) & \\ +SDIV & rx, ry, rz & rx = ry $\sdiv$ rz & 7 \\ +SSAT & rx, \#j$^{ }_{5}$, ry\{slr\} & rx = SATS(ry $\lsl\asr$ sh, j)$^{\pm}_{ }$ & 6 \\ +SSAT16 & rx, \#j$^{ }_{4}$, ry & rx = SATS(ry$^{\pm}_{H1}$, j)$^{\pm}_{ }$:SATS(ry$^{\pm}_{H0}$, j)$^{\pm}_{ }$ & 6 \\ +SUB\{S\} & rx, ry, op2 & rx = ry $-$ op2 & \\ +SUBW & rx, ry, \#i$^{ }_{12}$ & rx = ry $-$ i$^{\emptyset}_{ }$ & T \\ +UDIV & rx, ry, rz & rx = ry $\udiv$ rz & 7 \\ +USAD8 & rx, ry, rz & rx = $\sum_{n=0}^{3}$(ABS(ry$^{\emptyset}_{Bn}$)$-$rz$^{\emptyset}_{Bn}$) & 6 \\ +USADA8 & rx, ry, rz, rw & rx = rw $+$ $\sum_{n=0}^{3}$(ABS(ry$^{\emptyset}_{Bn}$)$-$rz$^{\emptyset}_{Bn}$) & 6 \\ +USAT & rx, \#j$^{ }_{5}$, ry\{slr\} & rx = SATU(ry $\lsl\asr$ sh, j)$^{\pm}_{ }$ & 6 \\ +USAT16 & rx, \#i$^{ }_{4}$, ry & rx = SATU(ry$^{\pm}_{H1}$, i)$^{\pm}_{ }$:SATU(ry$^{\pm}_{H0}$, i)$^{\pm}_{ }$ & 6 \\ +\end{asmtable} +% +\begin{table-lXN}{Operand 2} +\#i$^{ }_{32}$ & i$^{ }_{8}$ $\ror$ i$^{ }_{4}$:0 & A \\ +\#i$^{ }_{32}$ & 0$^{ }_{24}$:i$^{ }_{8}$, 0$^{ }_{8}$:i$^{ }_{8}$0$^{ }_{8}$:i$^{ }_{8}$, i$^{ }_{8}$:0$^{ }_{8}$i$^{ }_{8}$:0$^{ }_{8}$ or i$^{ }_{8}$:i$^{ }_{8}$i$^{ }_{8}$:i$^{ }_{8}$ & T \\ +\#i$^{ }_{32}$ & 1:i$^{ }_{7}$ $\lsl$ \{1..24\} & T \\ +rz & rz & \\ +rz, LSL \#n & rz $\lsl$ \{1..31\} & \\ +rz, LSR \#n & rz $\lsr$ \{1..32\} & \\ +rz, ASR \#n & rz $\asr$ \{1..32\} & \\ +rz, ROR \#n & rz $\ror$ \{1..31\} & \\ +rz, RRX & C:rz$^{ }_{31:1}$; C = rz$^{ }_{0}$ & \\ +rz, LSL rw & rz $\lsl$ rw & A \\ +rz, LSR rw & rz $\lsr$ rw & A \\ +rz, ASR rw & rz $\asr$ rw & A \\ +rz, ROR rw & rz $\ror$ rw & A \\ +\end{table-lXN} +% +\begin{asmtable}{Bitwise and Move Instructions} +AND\{S\} & rx, ry, op2 & rx = ry \& op2 & \\ +\textit{ASR\{S\}} & rx, ry, \#j$^{ }_{5}$ & rx = ry $\asr$ j & \\ +\textit{ASR\{S\}} & rx, ry, Rs & rx = ry $\asr$ Rs & \\ +BFC & rx, \#p, \#n & rx$^{ }_{p+n-1:p}$ = 0$^{ }_{n}$ & 6t \\ +BFI & rx, ry, \#p, \#n & rx$^{ }_{p+n-1:p}$ = ry$^{ }_{n-1:0}$ & 6t \\ +BIC\{S\} & rx, ry, op2 & rx = ry \& $\sim$op2 & \\ +CLZ & rx, ry & rx = CountLeadingZeros(ry) & \\ +EOR\{S\} & rx, ry, op2 & rx = ry $\oplus$ op2 & \\ +\textit{LSL\{S\}} & rx, ry, \#i$^{ }_{5}$ & rx = ry $\lsl$ i & \\ +\textit{LSL\{S\}} & rx, ry, Rs & rx = ry $\lsl$ Rs & \\ +\textit{LSR\{S\}} & rx, ry, \#j$^{ }_{5}$ & rx = ry $\lsr$ j & \\ +\textit{LSR\{S\}} & rx, ry, Rs & rx = ry $\lsr$ Rs & \\ +MOV\{S\} & rx, op2 & rx = op2 & \\ +MOVT & rx, \#i$^{ }_{16}$ & rx$^{ }_{31:16}$ = i & 6t \\ +MOVW & rx, \#i$^{ }_{16}$ & rx = i$^{\emptyset}_{ }$ & \\ +MVN\{S\} & rx, op2 & rx = $\sim$op2 & \\ +ORN\{S\} & rx, ry, op2 & rx = ry | $\sim$op2 & T \\ +ORR\{S\} & rx, ry, op2 & rx = ry | op2 & \\ +RBIT & rx, ry & rx = ReverseBits(ry) & 6t \\ +REV & rx, ry & rx = ry$^{ }_{B0}$:ry$^{ }_{B1}$:ry$^{ }_{B2}$:ry$^{ }_{B3}$ & 6 \\ +REV16 & rx, ry & rx = ry$^{ }_{B2}$:ry$^{ }_{B3}$:ry$^{ }_{B0}$:ry$^{ }_{B1}$ & 6 \\ +REVSH & rx, ry & rx = ry$^{\pm}_{B0}$:ry$^{ }_{B1}$ & 6 \\ +\textit{ROR\{S\}} & rx, ry, \#i$^{ }_{5}$ & rx = ry $\ror$ i & \\ +\textit{ROR\{S\}} & rx, ry, Rs & rx = ry $\ror$ Rs & \\ +\textit{RRX\{S\}} & rx, ry & rx = C:ry$^{ }_{31:1}$; C = ry$^{ }_{0}$ & \\ +SBFX & rx, ry, \#p, \#n & rx = ry$^{\pm}_{p+n-1:p}$ & 6t \\ +TEQ & rx, op2 & rx | op2 & \\ +TST & rx, op2 & rx \& op2 & \\ +UBFX & rx, ry, \#p, \#n & rx = ry$^{\emptyset}_{p+n-1:p}$ & 6t \\ +\end{asmtable} +% +\begin{asmtable}{Branch and Jump Instructions} +B & rel$^{ }_{26}$ & PC = PC $+$ rel$^{\pm}_{25:2}$:0$^{ }_{1:0}$ & A \\ +B & rel$^{ }_{25}$ & PC = PC $+$ rel$^{\pm}_{24:1}$:0 & T \\ +Bcc & rel$^{ }_{21}$ & if(cc) PC = PC $+$ rel$^{\pm}_{20:1}$:0 & I \\ +BKPT & \#i$^{ }_{16}$ & BreakPoint(i) & I \\ +BL & rel$^{ }_{26}$ & LR=PC$^{ }_{31:1}$:0; PC$+$=rel$^{\pm}_{25:2}$:0$^{ }_{1:0}$ & A \\ +BL & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1; PC$+$=rel$^{\pm}_{24:1}$:0 & T \\ +BLX & rel$^{ }_{26}$ & LR=PC$^{ }_{31:1}$:0; Set=1; PC$+$=rel$^{\pm}_{25:1}$:0 & A \\ +BLX & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1; Set=0; PC$+$=rel$^{\pm}_{24:2}$:0$^{ }_{1:0}$ & T \\ +BLX & rx & LR=PC$^{ }_{31:1}$:0; Set=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & A \\ +BX & rx & Set = rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & A \\ +%BXJ & rx & Set=2; PC = rx$^{ }_{31:1}$:0 & \\ +TBB & rx, ry & PC = PC $+$ [rx $+$ ry]$^{\emptyset}_{B0}$ & T \\ +TBH & rx, ry, LSL \#1 & PC = PC $+$ [rx $+$ ry $\lsl$ 1]$^{\emptyset}_{H0}$ & T \\ +\end{asmtable} +% +\begin{asmtable}{Load and Store Instructions} +LDMDA & rx\{!\}, rlist & rlist = [rx$-$4$\times$cnt$+$4]; if(!) rx$-$=4$\times$cnt & A \\ +LDMDB & rx\{!\}, rlist & rlist = [rx $-$ 4$\times$cnt]; if(!) rx$-$=4$\times$cnt & \\ +LDM\textit{IA} & rx\{!\}, rlist & rlist = [rx]; if(!) rx $+$= 4$\times$cnt & \\ +LDMIB & rx\{!\}, rlist & rlist = [rx $+$ 4]; if(!) rx $+$= 4$\times$cnt & A \\ +LDR\{T\} & rx, [addr] & rx = [addr] & \\ +LDRB\{T\} & rx, [addr] & rx = [addr]$^{\emptyset}_{8}$ & \\ +LDRD & rx, ry, [addr] & ry:rx = [addr] & \\ +LDRH\{T\} & rx, [addr] & rx = [addr]$^{\emptyset}_{16}$ & \\ +LDRSB\{T\} & rx, [addr] & rx = [addr]$^{\pm}_{8}$ & \\ +LDRSH\{T\} & rx, [addr] & rx = [addr]$^{\pm}_{16}$ & \\ +\textit{POP} & rlist & rlist = [SP]; SP $+$= 4$\times$cnt & \\ +\textit{PUSH} & rlist & SP $-$= 4$\times$cnt; [SP] = rlist & \\ +STMDA & rx\{!\}, rlist & [rx$-$4$\times$cnt$+$4] = rlist; if(!) rx$-$=4$\times$cnt & A \\ +STMDB & rx\{!\}, rlist & [rx $-$ 4$\times$cnt] = rlist; if(!) rx$-$=4$\times$cnt & \\ +STM\textit{IA} & rx\{!\}, rlist & [rx] = rlist; if(!) rx $+$= 4$\times$cnt & \\ +STMIB & rx\{!\}, rlist & [rx$+$4] = rlist; if(!) rx $+$= 4$\times$cnt & A \\ +STR\{T\} & rx, [addr] & [addr] = rx & \\ +STRB\{T\} & rx, [addr] & [addr]$^{ }_{8}$ = rx$^{ }_{B0}$ & \\ +STRD & rx, ry, [addr] & [addr] = ry:rx & \\ +STRH\{T\} & rx, [addr] & [addr]$^{ }_{16}$ = rx$^{ }_{H0}$ & \\ +%SWP & rx, ry, [rz] & rx = [rz]; [rz] = ry & A,D \\ +%SWPB & rx, ry, [rz] & rx = [rz]$^{\emptyset}_{8}$; [rz] = ry$^{ }_{B0}$ & A,D \\ +\end{asmtable} +% +\begin{table-llX}{ARM LDR/STR Addressing Modes} +non-T & [rz\{, \#$\pm$i$^{ }_{8}$\}]\{!\} & addr = rz $\pm$ i; if(!) rz = addr \\ +xxR\{,B\} & [rz\{, \#$\pm$i$^{ }_{12}$\}]\{!\} & addr = rz $\pm$ i; if(!) rz = addr \\ +any & [rz]\{, \#$\pm$i$^{ }_{8}$\} & addr = rz; rz $\pm$= i \\ +xxR\{,B\}\{T\} & [rz], \#$\pm$i$^{ }_{12}$ & addr = rz; rz $\pm$= i \\ +non-T & [rz, $\pm$rw]\{!\} & addr = rz $\pm$ rw; if(!) rz = addr \\ +xxR\{,B\} & [rz, $\pm$rw\{AS\}]\{!\} & addr = rz $\pm$ AS(rw); if(!) rz = addr \\ +any & [rz], $\pm$rw & addr = rz; rz $\pm$= rw \\ +xxR\{,B\}\{T\} & [rz], $\pm$rw\{AS\} & addr = rz; rz $\pm$= AS(rw) \\ +LD non-T & $\pm$rel$^{ }_{8}$ & addr = PC $\pm$ rel \\ +LDR\{,B\} & $\pm$rel$^{ }_{12}$ & addr = PC $\pm$ rel \\ +\end{table-llX} +% +\begin{table-llX}{Thumb2 LDR/STR Addressing Modes} +any & [rz\{, \#i$^{ }_{8}$\}] & addr = rz $+$ i \\ +xxR\{,B,H,SB,SH\} & [rz, \#i$^{ }_{12}$] & addr = rz $+$ i \\ +xxR\{,B,H,SB,SH\} & [rz, \#$\pm$i$^{ }_{8}$]\{!\} & addr = rz $\pm$ i; if(!) rz = addr \\ +xxR\{,B,H,SB,SH\} & [rz], \#$\pm$i$^{ }_{8}$ & addr = rz; rz $\pm$= i \\ +xxR\{,B,H,SB,SH\} & [rz,rw\{,LSL \#i$^{ }_{2}$\}] & addr = rz $+$ rw $\lsl$ i \\ +LDR\{,B,H,SB,SH\} & $\pm$rel$^{ }_{12}$ & addr = PC $\pm$ rel \\ +xxRD & [rz\{, \#$\pm$i$^{ }_{10}$\}]\{!\} & addr=rz$\pm$i$^{ }_{9:2}$:0$^{ }_{1:0}$; if(!) rz=addr \\ +xxRD & [rz], \#$\pm$i$^{ }_{10}$ & addr = rz; rz $\pm$= i$^{\pm}_{9:2}$:0$^{ }_{1:0}$ \\ +LDRD & $\pm$rel$^{ }_{10}$ & addr = PC $\pm$ rel$^{ }_{9:2}$:0$^{ }_{1:0}$ \\ +\end{table-llX} +% +\begin{asmtable}{Multiplication Instructions} +MLA & rx, ry, rz, rw & rx = rw $+$ ry $\umul$ rz & \\ +MLA\{S\} & rx, ry, rz, rw & rx = rw $+$ ry $\umul$ rz & A \\ +MLS & rx, ry, rz, rw & rx = rw $-$ ry $\umul$ rz & 6t \\ +MUL & rx, ry, rz & rx = ry $\umul$ rz & \\ +MUL\{S\} & rx, ry, rz & rx = ry $\umul$ rz & A \\ +SMLAxy & rx, ry, rz, rw & rx = rw $+$ ry$^{\pm}_{Hx}$ $\smul$ rz$^{\pm}_{Hy}$ & \\ +SMLaD & rx, ry, rz, rw & rx = rw $+$ ry$^{\pm}_{H0}$$\smul$rz$^{\pm}_{H0}$ $\pm$ ry$^{\pm}_{H1}$$\smul$rz$^{\pm}_{H1}$ & 6 \\ +SMLaDX & rx, ry, rz, rw & rx = rw $+$ ry$^{\pm}_{H0}$$\smul$rz$^{\pm}_{H1}$ $\pm$ ry$^{\pm}_{H1}$$\smul$rz$^{\pm}_{H0}$ & \\ +SMLaLD & rx, ry, rz, rw & ry:rx $+$= rz$^{\pm}_{H0}$$\smul$rw$^{\pm}_{H0}$ $\pm$ rz$^{\pm}_{H1}$$\smul$rw$^{\pm}_{H1}$ & 6 \\ +SMLaLDX & rx, ry, rz, rw & ry:rx $+$= rz$^{\pm}_{H0}$$\smul$rw$^{\pm}_{H1}$ $\pm$ rz$^{\pm}_{H1}$$\smul$rw$^{\pm}_{H0}$ & \\ +SMLAL & rx, ry, rz, rw & ry:rx $+$= rz $\smul$ rw & \\ +SMLAL\{S\} & rx, ry, rz, rw & ry:rx $+$= rz $\smul$ rw & A \\ +SMLALxy & rx, ry, rz, rw & ry:rx $+$= rz$^{\pm}_{Hx}$ $\smul$ rw$^{\pm}_{Hy}$ & \\ +SMLAWy & rx, ry, rz, rw & rx = rw $+$ ry $\smul$ rz$^{\pm}_{Hy}$ & \\ +SMMLa & rx, ry, rz, rw & rx = rw $\pm$ (ry $\smul$ rz)$^{ }_{63:32}$ & 6 \\ +SMMLaR & rx, ry, rz, rw & rx = rw $\pm$ (ry$\smul$rz $+$ 0x80000000)$^{ }_{63:32}$ & \\ +SMMUL & rx, ry, rz & rx = (ry $\smul$ rz)$^{ }_{63:32}$ & 6 \\ +SMMULR & rx, ry, rz & rx = (ry $\smul$ rz $+$ 0x80000000)$^{ }_{63:32}$ & \\ +SMUaD & rx, ry, rz & rx = ry$^{\pm}_{H0}$ $\smul$ rz$^{\pm}_{H0}$ $\pm$ ry$^{\pm}_{H1}$ $\smul$ rz$^{\pm}_{H1}$ & 6 \\ +SMUaDX & rx, ry, rz & rx = ry$^{\pm}_{H0}$ $\smul$ rz$^{\pm}_{H1}$ $\pm$ ry$^{\pm}_{H1}$ $\smul$ rz$^{\pm}_{H0}$ & \\ +SMULxy & rx, ry, rz & rx = ry$^{\pm}_{Hx}$ $\smul$ rz$^{\pm}_{Hy}$ & \\ +SMULL & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & \\ +SMULL\{S\} & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & A \\ +SMULWy & rx, ry, rz & rx = (ry $\smul$ rz$^{\pm}_{Hy}$)$^{ }_{47:16}$ & \\ +UMAAL & rx, ry, rz, rw & ry:rx = ry $+$ rx $+$ rz $\umul$ rw & \\ +UMLAL & rx, ry, rz, rw & ry:rx $+$= rz $\umul$ rw & \\ +UMULL & rx, ry, rz, rw & ry:rx = rz $\umul$ rw & \\ +\end{asmtable} +% +\begin{asmtable}{Parallel Instructions} +pADD16 & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = p(ry$^{ }_{Hn}$ $+$ rz$^{ }_{Hn}$) & 6 \\ +pADD8 & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = p(ry$^{ }_{Bn}$ $+$ rz$^{ }_{Bn}$) & 6 \\ +pASX & rx, ry, rz & rx = p(ry$^{ }_{H1}$ $+$ rz$^{ }_{H0}$):p(ry$^{ }_{H0}$ $-$ rz$^{ }_{H1}$) & 6 \\ +pSAX & rx, ry, rz & rx = p(ry$^{ }_{H1}$ $-$ rz$^{ }_{H0}$):p(ry$^{ }_{H0}$ $+$ rz$^{ }_{H1}$) & 6 \\ +pSUB16 & rx, ry, rz & for(n=0..1) rx$^{ }_{Hn}$ = p(ry$^{ }_{Hn}$ $-$ rz$^{ }_{Hn}$) & 6 \\ +pSUB8 & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = p(ry$^{ }_{Bn}$ $-$ rz$^{ }_{Bn}$) & 6 \\ +SEL & rx, ry, rz & for(n=0..3) rx$^{ }_{Bn}$ = (GEn ? ry : rz)$^{ }_{Bn}$ & 6 \\ +\end{asmtable} +% +\begin{table-lX}{Parallel Instruction Prefixes} +Q & Signed operation, Results are saturated \\ +S & Signed operation, Results are truncated \\ +SH & Signed operation, Results are right shifted by one \\ +U & Unsigned operation, Results are truncated \\ +UH & Unsigned operation, Results are right shifted by one \\ +UQ & Unsigned operation, Results are saturated \\ +\end{table-lX} +% +\begin{asmtable}{Packing and Unpacking Instructions} +PKHBT & rx, ry, rz\{sl\} & rx = (rz $\lsl$ sh)$^{ }_{H1}$:ry$^{ }_{H0}$ & 6 \\ +PKHTB & rx, ry, rz\{sr\} & rx = ry$^{ }_{H1}$:(rz $\asr$ sh)$^{ }_{H0}$ & 6 \\ +SXTAB & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\pm}_{B0}$ & 6 \\ +SXTAB16 & rx, ry, rz\{rb\} & for(n=0..1) rx$^{ }_{Hn}$=ry$^{ }_{Hn}$$+$(rz$\ror$sh)$^{\pm}_{B2n}$ & 6 \\ +SXTAH & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\pm}_{H0}$ & 6 \\ +SXTB & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\pm}_{B0}$ & 6 \\ +SXTB16 & rx, ry\{rb\} & for(n=0..1) rx$^{ }_{Hn}$ = (ry $\ror$ sh)$^{\pm}_{B2n}$ & 6 \\ +SXTH & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\pm}_{H0}$ & 6 \\ +UXTAB & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\emptyset}_{B0}$ & 6 \\ +UXTAB16 & rx, ry, rz\{rb\} & for(n=0..1) rx$^{ }_{Hn}$=ry$^{ }_{Hn}$$+$(rz$\ror$sh)$^{\emptyset}_{B2n}$ & 6 \\ +UXTAH & rx, ry, rz\{rb\} & rx = ry $+$ (rz $\ror$ sh)$^{\emptyset}_{H0}$ & 6 \\ +UXTB & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\emptyset}_{B0}$ & 6 \\ +UXTB16 & rx, ry\{rb\} & for(n=0..1) rx$^{ }_{Hn}$ = (ry $\ror$ sh)$^{\emptyset}_{B2n}$ & 6 \\ +UXTH & rx, ry\{rb\} & rx = (ry $\ror$ sh)$^{\emptyset}_{H0}$ & 6 \\ +\end{asmtable} +% +\begin{asmtable}{Exclusive Load and Store Instructions} +CLREX & & ClearExclusiveLocal() & I,6k \\ +LDREX & rx, [ry] & rx = [ry]; SetExclusiveMonitor & 6k \\ +LDREX & rx, [ry, \#i$^{ }_{10}$] & rx = [ry$+$i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$]; SetExclusiveMonitor & T,6k \\ +LDREXB & rx, [ry] & rx = [ry]$^{\emptyset}_{8}$; SetExclusiveMonitor & 6k \\ +LDREXD & rx, ry, [rz] & ry:rx = [rz]; SetExclusiveMonitor & 6k \\ +LDREXH & rx, [ry] & rx = [ry]$^{\emptyset}_{16}$; SetExclusiveMonitor & 6k \\ +STREX & rx,ry,[rz] & if(Pass) [rz] = ry; rx = Pass ? 1 : 0 & 6k \\ +STREX & rx,ry,[rz,\#i$^{ }_{10}$] & if(Pass) [rz$+$i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$]=ry; rx=Pass?1:0 & T,6k \\ +STREXB & rx,ry,[rz] & if(Pass) [rz]$^{ }_{8}$ = ry$^{ }_{B0}$; rx = Pass?1:0 & 6k \\ +STREXD & rx,ry,rz,[rw] & if(Pass) [rw] = rz:ry; rx = Pass?1:0 & 6k \\ +STREXH & rx,ry,[rz] & if(Pass) [rz]$^{ }_{16}$ = ry$^{ }_{H0}$; rx = Pass?1:0 & 6k \\ +\end{asmtable} +% +\begin{asmtable}{System Instructions} +CPSI\{D,E\} & \{aif\}\{, \#mode\} & \{a\}\{i\}\{f\} = (E ? 1: 0); MODE = mode & 6 \\ +CPS & \#mode & MODE = mode & 6 \\ +ERET & & PC = LR; CPSR = SPSR & 7 \\ +HVC & \#i$^{ }_{16}$ & CallHypervisor(i) & 7 \\ +MRS & rx, xPSR & rx = \{CPSR,SPSR\} & \\ +MRS & rx, Rbanked & rx = Rbanked & 7 \\ +MSR & xPSR, rx & \{CPSR,SPSR\} = rx & \\ +MSR & Rbanked, rx & Rbanked = rx & 7 \\ +MSR & xPSR\_\{cxsf\}, i & \{CPSR,SPSR\}$^{ }_{f,s,x,c}$ = i$^{ }_{f,s,x,c}$ & A \\ +MSR & xPSR\_\{cxsf\}, rx & \{CPSR,SPSR\}$^{ }_{f,s,x,c}$ = rx$^{ }_{f,s,x,c}$ & \\ +RFEdi & rx\{!\} & LDMdi rx\{!\}, \{PC, CPSR\} & \\ +SMC & \#i$^{ }_{4}$ & CallSecureMonitor() & 6k \\ +SRSdi & SP\{!\}, \#mode & STMdi SP\_mode\{!\}, \{LR, SPSR\} & 6 \\ +\end{asmtable} +% +\begin{asmtable}{Special Instructions} +DBG & \#i$^{ }_{4}$ & DebugHint(i) & 7 \\ +DMB & option & DataMemoryBarrier(option) & I,7 \\ +DSB & option & DataSynchronizationBarrier(option) & I,7 \\ +ISB & SY & InstructionSynchronizationBarrier(SY) & I,7 \\ +NOP & & & 6k \\ +PLD\{W\} & [addr] & PreloadData(addr) & \\ +%PLD\{W\} & [rx, \#i$^{ }_{12}$] & PreloadData(rx $+$ i) & \\ +%PLD\{W\} & [rx, \#$-$i$^{ }_{8}$] & PreloadData(rx $-$ i) & \\ +%PLD\{W\} & [rx, \#$-$i$^{ }_{12}$] & PreloadData(rx $-$ i) & A \\ +%PLD & $\pm$rel$^{ }_{12}$ & PreloadData(PC $\pm$ rel) & \\ +%PLD\{W\} & [rx, ry\{, LSL \#i$^{ }_{2}$\}] & PreloadData(rx $+$ ry $\lsl$ i) & \\ +%PLD\{W\} & [rx, $\pm$ry\{AS\}] & PreloadData(rx $\pm$ AS(ry)) & A \\ +PLI & [addr] & PreloadInstr(addr) & 7 \\ +%PLI & [rx, \#i$^{ }_{12}$] & PreloadInstr(rx $+$ i) & 7 \\ +%PLI & [rx, \#$-$i$^{ }_{8}$] & PreloadInstr(rx $-$ i) & 7 \\ +%PLI & [rx, \#$-$i$^{ }_{12}$] & PreloadInstr(rx $-$ i) & A,7 \\ +%PLI & $\pm$rel$^{ }_{12}$ & PreloadInstr(PC $\pm$ rel) & 7\\ +%PLI & [rx, ry\{, LSL \#i$^{ }_{2}$\}] & PreloadInstr(rx $+$ ry $\lsl$ i) & 7 \\ +%PLI & [rx, $\pm$ry\{AS\}] & PreloadInstr(rx $\pm$ AS(ry)) & A,7 \\ +SETEND & \{BE/LE\} & EndianState = \{BE/LE\} & I,6 \\ +SEV & & SendEvent() & 6k \\ +SVC & \#i$^{ }_{24}$ & CallSupervisor() & A \\ +UDF & \#i$^{ }_{16}$ & UndefinedException() & \\ +WFE & & WaitForEvent() & 6k \\ +WFI & & WaitForInterrupt() & 6k \\ +YIELD & & HintYield() & 6k \\ +\end{asmtable} +% +\begin{table-lX}{Keys} +\{S\} & Optional suffix, if present update flags \\ +\{t\} & Conditional for additional instructions (T or E) \\ +\{T\} & LDR/STR instruction uses user privileges. \\ +a & A or S to add or subtract operand. \\ +x, y & Selects bottom (B) or top (T) half of register(s) \\ +cc & Condition code (can suffix most ARM instructions) \\ +di & DA, DB, IA or IB for decrease/increase before/after. \\ +i, j & Immediate operand, range 0..max / 1..max+1 \\ +rx, ry, rz, rw & General register \\ +Rbanked & Banked register \\ +rlist & Comma separated list of registers within \{ \}. \\ +op2 & Immediate or shifted register \\ +xPSR & APSR, CPSR or SPSR \\ +SAT\{S,U\}(x,b) & Saturated signed/unsigned b bit value \\ +B\{0,1,2,3\} & Selected byte (bits 7:0, 15:8, 23:16 or 31:24) \\ +H\{0,1\} & Selected half word (bits 15:0 or 31:16) \\ +\{rb\} & Optional rotate (ROR 8, ROR 16 or ROR 24) \\ +\{slr\} & Optional shift (LSL \#\{1..31\} or ASR \#\{1..32\}) \\ +\{sl\} & Optional left shift (LSL \#\{1..31\}) \\ +\{sr\} & Optional right shift (ASR \#\{1..32\}) \\ +\{AS\} & ARM shift or rotate (LSL/ROR \#\{1..31\}, LSR/ASR \#\{1..32\} or RRX) \\ +value$^{\pm}_{ }$, value$^{\emptyset}_{ }$ & Value is sign/zero extended\\ +$\smul$ $\sdiv$ $\asr$ & Operation is signed \\ +\end{table-lX} +% +\begin{table-lX}{Notes} +6 & Introduced in ARMv6 \\ +6k & Introduced in ARMv6k \\ +6t & Introduced in ARMv6T2 \\ +7 & Introduced in ARMv7 \\ +A & Only available in ARM mode \\ +%D & Deprecated instruction \\ +H & Thumb1 instruction can use high registers \\ +I & Can't be conditional \\ +S & Thumb16 instruction updates status flags unless in IT block \\ +T & Only available in Thumb mode \\ +\end{table-lX} +% +\begin{table-llX}{General Registers} +R0-R3 & & Arguments and return values (useable by Thumb16) \\ +R4-R7 & & General purpose (must be preserved, useable by Thumb16) \\ +R8-R11 & & General purpose registers (must be preserved) \\ +R12 & IP & Intra-procedure-call scratch register \\ +R13 & SP & Stack pointer \\ +R14 & LR & Return address \\ +R15 & PC & Program counter \\ +\end{table-llX} +% +\begin{table-llX}{Condition Codes} +EQ & Equal & Z \\ +NE & Not equal & !Z \\ +CS/HS & Carry set, Unsigned higher or same & C \\ +CC/LO & Carry clear, Unsigned lower & !C \\ +MI & Minus, Negative & N \\ +PL & Plus, Positive or zero & !N \\ +VS & Overflow & V \\ +VC & No overflow & !V \\ +HI & Unsigned higher & C \& !Z \\ +LS & Unsigned lower or same & !C | Z \\ +GE & Signed greater than or equal & N $=$ V \\ +LT & Signed less than & N $\ne$ V \\ +GT & Signed greater than & !Z \& N $=$ V \\ +LE & Signed less than or equal & Z | N $\ne$ V \\ +AL & Always (default) & 1 \\ +\end{table-llX} +% +\begin{table-lX}{DMB and DSB Options} +SY & Full system, Read and write \\ +(SY)ST & Full system, Write only \\ +ISH & Inner shareable, Read and write \\ +ISHST & Inner shareable, Write only \\ +NSH & Non-shareable, Read and write \\ +NSHST & Non-shareable, Write only \\ +OSH & Outer shareable, Read and write \\ +OSHST & Outer sharable, Write only \\ +\end{table-lX} +% +\begin{asmtable}{Thumb16 Bitwise and Move Instructions} +AND & rx, ry & rx = rx \& ry & S \\ +ASR & rx, ry, \#j$^{ }_{5}$ & rx = ry $\asr$ j & S \\ +ASR & rx, ry & rx = rx $\asr$ ry & S \\ +BIC & rx, ry & rx = rx \& $\sim$ry & S \\ +EOR & rx, ry & rx = rx $\oplus$ ry & S \\ +LSL & rx, ry, \#i$^{ }_{5}$ & rx = ry $\lsl$ i & S \\ +LSL & rx, ry & rx = rx $\lsl$ ry & S \\ +LSR & rx, ry, \#j$^{ }_{5}$ & rx = ry $\lsr$ j & S \\ +LSR & rx, ry & rx = rx $\lsr$ ry & S \\ +MOV & rx, \#i$^{ }_{8}$ & rx = i$^{\emptyset}_{ }$ & S \\ +MOV & rx, ry & rx = ry & H \\ +MOVS & rx, ry & rx = ry & \\ +MVN & rx, ry & rx = $\sim$ry & S \\ +ORR & rx, ry & rx = rx | ry & S \\ +REV & rx, ry & rx = ry$^{ }_{7:0}$:ry$^{ }_{15:8}$:ry$^{ }_{23:16}$:ry$^{ }_{31:24}$ & 6 \\ +REV16 & rx, ry & rx = ry$^{ }_{23:16}$:ry$^{ }_{31:24}$:ry$^{ }_{7:0}$:ry$^{ }_{15:8}$ & 6 \\ +REVSH & rx, ry & rx = ry$^{\pm}_{7:0}$:ry$^{ }_{15:8}$ & 6 \\ +ROR & rx, ry & rx = rx $\ror$ ry & S \\ +SXTB & rx, ry & rx = ry$^{\pm}_{7:0}$ & \\ +SXTH & rx, ry & rx = ry$^{\pm}_{15:0}$ & \\ +TST & rx, ry & rx \& ry & \\ +UXTB & rx, ry & rx = ry$^{\emptyset}_{7:0}$ & \\ +UXTH & rx, ry & rx = ry$^{\emptyset}_{15:0}$ & \\ +\end{asmtable} +% +\begin{asmtable}{Thumb16 Branch and Special Instructions} +B & rel$^{ }_{12}$ & PC = PC $+$ rel$^{\pm}_{11:1}$:0 & \\ +Bcc & rel$^{ }_{9}$ & if(cc) PC = PC $+$ rel$^{\pm}_{8:1}$:0 & I \\ +BKPT & \#i$^{ }_{8}$ & BreakPoint(i) & I \\ +BL & rel$^{ }_{23}$ & LR=PC$^{ }_{31:1}$:1; PC$+$=rel$^{\pm}_{22:1}$:0 & \\ +BLX & rel$^{ }_{23}$ & LR=PC$^{ }_{31:1}$:1; Set=0; PC$+$=rel$^{\pm}_{22:2}$:0$^{ }_{1:0}$ & \\ +BLX & rx & LR=PC$^{ }_{31:1}$:1; Set=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & \\ +BX & rx & Set=rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & \\ +CBNZ & rx, rel$^{ }_{7}$ & if(rx $\ne$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0 & I,6t \\ +CBZ & rx, rel$^{ }_{7}$ & if(rx $=$ 0) PC $+$= rel$^{\emptyset}_{6:1}$:0 & I,6t \\ +CPSI\{D,E\} & \{aif\} & \{a\}\{i\}\{f\} = (E ? 1 : 0) & 6 \\ +IT\{t\{t\{t\}\}\} & cc & if(cc) NextInstruction & I,6t \\ +NOP & & & 6k \\ +SETEND & \{BE/LE\} & EndianState = \{BE/LE\} & I,6 \\ +SEV & & SendEvent() & 7 \\ +SVC & \#i$^{ }_{8}$ & CallSupervisor() & \\ +UDF & \#i$^{ }_{8}$ & UndefinedException() & \\ +WFE & & WaitForEvent() & 7 \\ +WFI & & WaitForInterrupt() & 7 \\ +YIELD & & HintYield() & 7 \\ +\end{asmtable} +% +\begin{asmtable}{Thumb16 Arithmetic Instructions} +ADC & rx, ry & rx = rx $+$ ry $+$ C & S \\ +ADD & rx, ry, \#i$^{ }_{3}$ & rx = ry $+$ i$^{\emptyset}_{ }$ & S \\ +ADD & rx, \#i$^{ }_{8}$ & rx = rx $+$ i$^{\emptyset}_{ }$ & S \\ +ADD & rx, ry, rz & rx = ry $+$ rz & S \\ +ADD & rx, ry & rx = rx $+$ ry & H \\ +ADD & rx, SP, \#i$^{ }_{8}$ & rx = SP $+$ i$^{\emptyset}_{ }$ & \\ +ADD & SP, \#i$^{ }_{9}$ & SP = SP $+$ i$^{\emptyset}_{8:2}$:0$^{ }_{1:0}$ & \\ +ADR & rx, rel$^{ }_{10}$ & rx = PC $+$ rel$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$ & \\ +CMN & rx, ry & rx $+$ ry & \\ +CMP & rx, \#i$^{ }_{8}$ & rx $-$ i$^{\emptyset}_{ }$ & \\ +CMP & rx, ry & rx $-$ ry & H \\ +MUL & rx, ry & rx = rx $\umul$ ry & S \\ +RSB & rx, ry, \#0 & rx = 0 $-$ ry & S \\ +SBC & rx, ry & rx = rx $-$ (ry $+$ C) & S \\ +SUB & rx, ry, \#i$^{ }_{3}$ & rx = ry $-$ i$^{\emptyset}_{ }$ & S \\ +SUB & rx, \#i$^{ }_{8}$ & rx = rx $-$ i$^{\emptyset}_{ }$ & S \\ +SUB & rx, ry, rz & rx = ry $-$ rz & S \\ +SUB & SP, \#i$^{ }_{9}$ & SP = SP $-$ i$^{\emptyset}_{8:2}$:0$^{ }_{1:0}$ & \\ +\end{asmtable} +% +\begin{asmtable}{Thumb16 Load and Store Instructions} +LDM\textit{IA} & rx\{!\}, rlist & rlist = [rx]; if(!) rx $+$= 4$\times$cnt & \\ +LDMIA & SP!, rlist & rlist = [SP]; SP $+$= 4$\times$cnt & \\ +LDR & rx, [ry\{, \#i$^{ }_{7}$\}] & rx = [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] & \\ +LDR & rx, [SP\{, \#i$^{ }_{10}$\}] & rx = [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & \\ +LDR & rx, rel$^{ }_{10}$ & rx = [PC $+$ rel$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & \\ +LDR & rx, [ry, rz] & rx = [ry $+$ rz] & \\ +LDRB & rx, [ry\{, \#i$^{ }_{5}$\}] & rx = [ry $+$ i$^{\emptyset}_{ }$]$^{\emptyset}_{8}$ & \\ +LDRB & rx, [ry, rz] & rx = [ry $+$ rz]$^{\emptyset}_{8}$ & \\ +LDRH & rx, [ry\{, \#i$^{ }_{6}$\}] & rx = [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{\emptyset}_{16}$ & \\ +LDRH & rx, [ry, rz] & rx = [ry $+$ rz]$^{\emptyset}_{16}$ & \\ +LDRSB & rx, [ry, rz] & rx = [ry $+$ rz]$^{\pm}_{8}$ & \\ +LDRSH & rx, [ry, rz] & rx = [ry $+$ rz]$^{\pm}_{16}$ & \\ +\textit{POP} & rlist & rlist = [SP]; SP $+$= 4$\times$cnt & \\ +\textit{PUSH} & rlist & SP $-$= 4$\times$cnt; [SP] = rlist & \\ +STM\textit{IA} & rx!, rlist & [rx] = rlist; rx $+$= 4$\times$cnt & \\ +STMDB & SP!, rlist & SP $-$= 4$\times$cnt; [SP] = rlist & \\ +STR & rx, [ry\{, \#i$^{ }_{7}$\}] & [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] = rx & \\ +STR & rx, [SP\{, \#i$^{ }_{10}$\}] & [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] = rx & \\ +STR & rx, [ry, rz] & [ry $+$ rz] = rx & \\ +STRB & rx, [ry\{, \#i$^{ }_{5}$\}] & [ry $+$ i$^{\emptyset}_{ }$]$^{ }_{8}$ = rx$^{ }_{7:0}$ & \\ +STRB & rx, [ry, rz] & [ry $+$ rz]$^{ }_{8}$ = rx$^{ }_{7:0}$ & \\ +STRH & rx, [ry\{, \#i$^{ }_{6}$\}] & [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{ }_{16}$ = rx$^{ }_{15:0}$ & \\ +STRH & rx, [ry, rz] & [ry $+$ rz]$^{ }_{16}$ = rx$^{ }_{15:0}$ & \\ +\end{asmtable} +% +\end{multicols} +\end{document} diff --git a/crisv10.tex b/crisv10.tex new file mode 100644 index 0000000..082f422 --- /dev/null +++ b/crisv10.tex @@ -0,0 +1,334 @@ +% +% Copyright (C) 2014 Anders Olofsson +% +% Copying and distribution of this file, with or without modification, +% are permitted in any medium without royalty provided the copyright +% notice and this notice are preserved. This file is offered as-is, +% without any warranty. +% +\documentclass{sheet} +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{ae,aecompl} +\usepackage[english]{babel} +\usepackage[a4paper, landscape, margin=.1in]{geometry} +\usepackage{amssymb} +\usepackage{verbatim} + +\def\sheetheaderfont{\bfseries} +\def\sheettablefont{\footnotesize\sffamily} +\def\sheetheadercolor{black!10} +\def\sheetrowcolor{black!5} + +\newcolumntype{N}{>{\raggedleft\arraybackslash}m{2.0em}} +\def\tabcolsep{2pt} +\def\arraystretch{1.3} +\defsheet{asmtable}{5}{|m{5.2em} m{3.7em}|X|m{2.0em} N|} +\defsheet{table-X}{1}{|X|} +\defsheet{table-lX}{2}{|l X|} +\defsheet{table-lXN}{3}{|l X N|} +\defsheet{table-llXN}{4}{|l l X N|} +\defsheet{table-lXlN}{4}{|l X l N|} +\defsheet{table-Xlllll}{6}{|X l l l l l|} + +\pagefooter{CRISv10 version 1.0 page \thepage} + +\begin{document} +\begin{multicols}{3} +\raggedcolumns + +\begin{center} +{\Large\bfseries CRISv10 Quick Reference} +\end{center} +% +\begin{table-lX}{Keys} +rd, rs, rn & General register (R0..R15) \\ +pr & Special register (P0..P15) \\ +i & Immediate operand \\ +s & Source. Any addressing mode \\ +si & Source. Any addressing mode except register \\ +se & Source. Indexed, offset, double indirect or absolute addressing \\ +d & Destination. Any addressing mode \\ +di & Destination. Any addressing mode except register \\ +cc & Condition code \\ +m & Size modifier (b, w or d for byte, word or dword) \\ +z & Size modifier (b or w for byte or word) \\ +value$^{\pm}_{ }$ & Value is sign extended\\ +value$^{\emptyset}_{ }$ & Value is zero extended\\ +value$^{\{SU\}}_{ }$ & Signed or zero extend according to instruction name \\ +$\smul$ $\asr$ & Operation is signed \\ +{}**** & Flags NZVC are unchanged (--), affected (*) or cleared (0) \\ +\end{table-lX} +% +\begin{asmtable}{Bitwise Instructions} +AND.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ \& s$^{ }_{m}$ & **00 & \\ +AND.m & se, rn, rd & rd$^{ }_{m}$ = rn$^{ }_{m}$ \& se$^{ }_{m}$ & **00 & \\ +ANDQ & i$^{ }_{6}$, rd & rd = rd \& i$^{\pm}_{ }$ & **00 & \\ +ASR.m & rs, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\asr$ rs$^{ }_{5:0}$ & **00 & \\ +ASRQ & i$^{ }_{5}$, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\asr$ i & **00 & \\ +BTST & rs, rd & N = rd$^{ }_{rs_{4:0}}$; Z = (rd$^{ }_{rs_{4:0}:0}$ $=$ 0) & **00 & \\ +BTSTQ & i$^{ }_{5}$, rd & N = rd$^{ }_{i}$; Z = (rs$^{ }_{i:0}$ = 0) & **00 & \\ +LSL.m & rs, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsl$ rs$^{ }_{5:0}$ & **00 & P \\ +LSLQ & i$^{ }_{5}$, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsl$ i & **00 & P \\ +LSR.m & rs, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsr$ rs$^{ }_{5:0}$ & **00 & P \\ +LSRQ & i$^{ }_{5}$, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsr$ i & **00 & P \\ +LZ & rs, rd & rd = CountLeadingZeros(rs) & 0*00 & \\ +\textit{NOT} & rd & rd = $\sim$rd & **00 & P \\ +OR.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ | s$^{ }_{m}$ & **00 & \\ +OR.m & se, rn, rd & rd$^{ }_{m}$ = rn$^{ }_{m}$ | se$^{ }_{m}$ & **00 & \\ +ORQ & i$^{ }_{6}$, rd & rd = rd | i$^{\pm}_{ }$ & **00 & \\ +XOR & rs, rd & rd = rd $\oplus$ rs & **00 & \\ +\end{asmtable} +% +\begin{asmtable}{SWAP\{NWBR\} Instruction} +SWAPN & rd & rd = $\sim$rd & **00 & P,V \\ +SWAPW & rd & rd = rd$^{ }_{15:0}$:rd$^{ }_{31:16}$ & **00 & P,V \\ +SWAPB & rd & rd = rd$^{ }_{23:16}$:rd$^{ }_{31:24}$:rd$^{ }_{7:0}$:rd$^{ }_{15:8}$ & **00 & P,V \\ +SWAPR & rd & for(n=0..3) rd$^{ }_{Bn}$=ReverseBits(rd$^{ }_{Bn}$) & **00 & P,V \\ +\end{asmtable} +% +\begin{asmtable}{Arithmetic Instructions} +ABS & rs, rd & rd = (rs$^{ }_{31}$ $=$ 1 ? 0$-$rs : rs) & **00 & X \\ +ADD.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $+$ s$^{ }_{m}$ & **** & X \\ +ADD.m & se, rn, rd & rd$^{ }_{m}$ = rn$^{ }_{m}$ $+$ se$^{ }_{m}$ & **** & X \\ +ADDC & si, rd & rd = rd $+$ si $+$ C & **** & V \\ +ADDI & rs.m, rd & rd = rd $+$ rs $\umul$ sizeof(m) & {--}{--}{--}{--} & P,X \\ +ADDQ & i$^{ }_{6}$, rd & rd = rd $+$ i$^{\emptyset}_{ }$ & **** & X \\ +ADD\{SU\}.z & s, rd & rd = rd $+$ s$^{\{SU\}}_{z}$ & **** & X \\ +ADD\{SU\}.z & se, rn, rd & rd = rn $+$ se$^{\{SU\}}_{z}$ & **** & X \\ +BOUND.m & s, rd & rd = MIN(rd, s$^{\emptyset}_{m}$) & **00 & P,X \\ +BOUND.m & se, rn, rd & rd = MIN(rn, se$^{\emptyset}_{m}$) & **00 & P,X \\ +CMP.m & s, rd & rd$^{ }_{m}$ $-$ s$^{ }_{m}$ & **** & X \\ +CMPQ & i$^{ }_{6}$, rd & rd $-$ i$^{\pm}_{ }$ & **** & X \\ +CMP\{SU\}.z & s, rd & rd $-$ s$^{\{SU\}}_{z}$ & **** & X \\ +DSTEP & rs, rd & rd $\lsl$= 1; if(rd $\ge$ rs) rd = rd $-$ rs & **00 & P,X \\ +MSTEP & rs, rd & rd $\lsl$= 1; if(N) rd = rd $+$ rs & **00 & P,X \\ +MULS.m & rs, rd & MOF:rd = rd$^{\pm}_{m}$ $\smul$ rs$^{\pm}_{m}$ & ***0 & P,V \\ +MULU.m & rs, rd & MOF:rd = rd$^{\emptyset}_{m}$ $\umul$ rs$^{\emptyset}_{m}$ & ***0 & P,V \\ +NEG.m & rs, rd & rd$^{ }_{m}$ = 0 $-$ rs$^{ }_{m}$ & **** & P,X \\ +SUB.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $-$ s$^{ }_{m}$ & **** & X \\ +SUB.m & se, rn, rd & rd$^{ }_{m}$ = rn$^{ }_{m}$ $-$ se$^{ }_{m}$ & **** & X \\ +SUBQ & i$^{ }_{6}$, rd & rd = rd $-$ i$^{\emptyset}_{ }$ & **** & X \\ +SUB\{SU\}.z & s, rd & rd = rd $-$ s$^{\{SU\}}_{z}$ & **** & X \\ +SUB\{SU\}.z & se, rn, rd & rd = rn $-$ se$^{\{SU\}}_{z}$ & **** & X \\ +TEST.m & s & s$^{ }_{m}$ $-$ 0 & **00 & X \\ +\end{asmtable} +% +\begin{asmtable}{Data Transfer Instructions} +\textit{CLEAR.m} & d & d$^{ }_{m}$ = 0 & {--}{--}{--}{--} & D,I \\ +MOVE.m & s, rd & rd$^{ }_{m}$ = s$^{ }_{m}$ & **00 & \\ +MOVE.m & rs, di & di$^{ }_{m}$ = rs$^{ }_{m}$ & {--}{--}{--}{--} & \\ +MOVE & s, pr & pr = s$^{ }_{sizeof(pr)}$ & {--}{--}{--}{--} & I \\ +MOVE & pr, d & d$^{ }_{sizeof(pr)}$ = pr & {--}{--}{--}{--} & D,I \\ +MOVEM & si, rd & rd = si[0] \ldots R0 = si[4*d] & {--}{--}{--}{--} & \\ +MOVEM & rs, di & di[0] = rs \ldots di[4*s] = R0 & {--}{--}{--}{--} & \\ +MOVEQ & i$^{ }_{6}$, rd & rd = i$^{\pm}_{ }$ & **00 & \\ +MOV\{SU\}.z & s, rd & rd = s$^{\{SU\}}_{z}$ & **00 & \\ +\textit{POP} & rd & rd = [SP$+$] & **00 & \\ +\textit{POP} & pr & pr = [SP$+$] & {--}{--}{--}{--} & I \\ +\textit{PUSH} & rs & [SP = SP $-$ 4] = rs & {--}{--}{--}{--} & \\ +\textit{PUSH} & pr & [SP = SP $-$ sizeof(pr)] = pr & {--}{--}{--}{--} & I \\ +RBF & si & CpuState = si; if(U) mode = user & {--}{--}{--}{--} & V \\ +SBFS & di & di = CpuState & {--}{--}{--}{--} & I,V \\ +Scc & rd & rd = (cc ? 1 : 0) & {--}{--}{--}{--} & I,P \\ +\end{asmtable} +% +\begin{asmtable}{Jump and Branch Instructions} +Bcc & rel$^{ }_{8}$ & if(cc) PC $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--} & D,I,L \\ +Bcc & rel$^{ }_{16}$ & if(cc) PC $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--} & D,I,L \\ +BREAK & i$^{ }_{4}$ & BRP=PC; PC=IBR$+$8$\umul$i; mode=super & {--}{--}{--}{--} & L \\ +J\{BIS\}RC & s & \{BIS\}RP = PC + 4; PC = s & {--}{--}{--}{--} & I,L,V \\ +JIR & s & IRP = PC; PC = s & {--}{--}{--}{--} & I,L \\ +JMPU & si & PC = si; if(U) mode = user & {--}{--}{--}{--} & I,L,V \\ +JSR & s & SRP = PC; PC = s & {--}{--}{--}{--} & I,L \\ +JUMP & s & PC = s & {--}{--}{--}{--} & I,L \\ +NOP & & & {--}{--}{--}{--} & \\ +\textit{RET} & & PC = SRP & {--}{--}{--}{--} & D,I,L \\ +\textit{RETB} & & PC = BRP; if(U) mode = user & {--}{--}{--}{--} & D,I,L \\ +\textit{RETI} & & PC = IRP; if(U) mode = user & {--}{--}{--}{--} & D,I,L \\ +\end{asmtable} +% +\begin{asmtable}{Flag Instructions} +\textit{AX} & & X = 1 & {--}{--}{--}{--} & I \\ +CLEARF & & ,F,P = 0 & **** & I \\ +\textit{DI} & & I = 0 & {--}{--}{--}{--} & I \\ +\textit{EI} & & I = 1 & {--}{--}{--}{--} & I \\ +SETF & & = 1 & **** & I \\ +\end{asmtable} +% +\begin{table-lXN}{Addressing Modes} +rn & Register & \\ +{}[rn] & Indirect & +1 \\ +{}[rn+] & Autoincrement & +1 \\ +{}i$^{ }_{8}$, i$^{ }_{16}$, i$^{ }_{32}$ & Immediate (alias for [PC+]) & L,+1 \\ +{}[rn + i$^{\pm}_{8}$] & Immediate byte offset & L,+2 \\ +{}[rn + rm.m] & Indexed (rm is multiplied by sizeof(m)) & L,+2 \\ +{}[rp = rn + i$^{\pm}_{8}$] & Immediate byte offset with assign & L,+2 \\ +{}[rp = rn + rm.m] & Indexed with assign & L,+2 \\ +{}[rn + i$^{\pm}_{m}$] & Immediate offset (alias for [rn + [PC+].m]) & L,+3 \\ +{}[rn + [rm].m] & Indirect offset & L,+3 \\ +{}[rn + [rm+].m] & Autoincrement offset & L,+3 \\ +{}[rp = rn + i$^{\pm}_{m}$] & Immediate offset with assign & L,+3 \\ +{}[rp = rn + [rm].m] & Indirect offset with assign & L,+3 \\ +{}[rp = rn + [rm+].m] & Autoincrement offset with assign & L,+3 \\ +{}[[rn]] & Double indirect & L,+3 \\ +{}[[rn+]] & Double indirect with autoincrement & L,+3 \\ +{}[i$^{ }_{32}$] & Absolute (alias for [[PC+]]) & L,+3 \\ +\end{table-lXN} +% +\begin{table-llXN}{Registers} +R0-R8 & & General registers (must be preserved) & \\ +R9 & & General register & \\ +R10-R13 & & Function arguments and return value(s) & \\ +R14 & SP & Stack pointer & \\ +R15 & PC & Program counter & \\ +P0 & & Constant zero register (8 bits) & \\ +P1 & VR & Version register (8 bits) & \\ +P4 & & Constant zero register (16 bits) & \\ +P5 & CCR & Condition code register (16 bits) & \\ +P7 & MOF & Multiply overflow register & V \\ +P8 & & Constant zero register & \\ +P9 & IBR & Interrupt base register & M \\ +P10 & IRP & Interrupt return pointer & \\ +P11 & SRP & Subroutine return pointer & \\ +P12 & BAR & Breakpoint address register & M,V \\ +P13 & DCCR & Dword condition code register & V \\ +P14 & BRP & Breakpoint return pointer & V \\ +P15 & USP & User mode stack pointer & V \\ +\end{table-llXN} +% +\begin{table-lXN}{Flags} +C & Carry flag & \\ +V & Overflow flag & \\ +Z & Zero flag & \\ +N & Negative flag & \\ +X & Extended arithmetic flag & \\ +I & Interrupt enable flag & M \\ +B & Breakpoint enable flag & M,V \\ +M & NMI flag & M,V \\ +U & User mode flag & V \\ +P & Write failed flag & V \\ +F & Interrupt acknowledge flag & V \\ +\end{table-lXN} +% +\begin{table-lX}{Notes} +D & One delay slot before jump/branch is taken \\ +I & Interrupts are disabled until the next instruction has executed \\ +L & Cannot be used in delay slot \\ +M & Can only be written in supervisor mode \\ +P & Destination operand cannot be PC \\ +V & Only available on some chip versions \\ +X & C flag is added/subtracted if X flag is set \\ ++(1..3) & Execution time is increased by 1..3 cycles \\ +\end{table-lX} +% +\begin{table-lXlN}{Condition Codes} +CC/HS & Carry clear / Higher or same & !C & \\ +CS/LO & Carry set / Lower & C & \\ +NE & Not equal & !Z & \\ +EQ & Equal & Z & \\ +VC & Overflow clear & !V & \\ +VS & Overflow set & V & \\ +PL & Plus & !N & \\ +MI & Minus & N & \\ +LS & Lower or same & C | Z & \\ +HI & Higher & !C \& !Z & \\ +GE & Signed greater or equal & N $=$ V & \\ +LT & Signed less than & N $\ne$ V & \\ +GT & Signed greater than & N $=$ V \& !Z & \\ +LE & Signed less or equal & N $\ne$ V | Z & \\ +A & Always true & 1 & \\ +WF & Write failed & P & V \\ +\end{table-lXlN} +% +\begin{table-lX}{Execution Times} +1 & General instructions \\ +2 & Bcc with 16bit offset \\ +2 & BREAK, MULS and MULU \\ +2 & SWAPNWBH (only version 8 and 10 when using all 4 modifiers) \\ +2 & Interrupt acknowledge sequence \\ +5 & SBFS \\ +6..8 & RBF \\ ++(1..3) & Memory access (see addressing modes) \\ ++1 & Each memory access crossing a dword boundary \\ ++1 & PC as destination without delay slot (includes TEST.m PC) \\ ++1 & Each register moved by MOVEM \\ ++1 & Each dword memory access if bus width is 16 bits \\ +\end{table-lX} +% +\begin{table-Xlllll}{Version Specific Features} +DMA integrated in CPU & 4 & & & & \\ +EXT condition code & 4 & & & & \\ +Jump with context (JBRC/JIRC/JSRC) & & 8 & 10 & 13 & 17 \\ +SWAP instruction & & 8 & 10 & 13 & 17 \\ +Multiplication (MULS/MULU) & & & 10 & & 17 \\ +Read/write CPU state (RBF/SBFS) & & & 10 & 13 & 17 \\ +Integrity check (P flag, WF condition) & & & 10 & 13 & 17 \\ +User mode (U flag) & & & 10 & & \\ +JMPU instruction, MOF/BAR/USP registers & & & 10 & 13 & 17 \\ +ADDC instruction & & & & 13 & 17 \\ +\end{table-Xlllll} +% +\newsavebox\ExampleUDiv +\begin{lrbox}{\ExampleUDiv}\begin{lstlisting} +MOVU.W [num], R0 ; Move the numerator to +MOVU.W [denom], R1 ; the low word of R0 and +LSLQ 16, R1 ; the denominator to the +SUBQ 1, R1 ; upper word of R1. +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 ; After 16 iterations the +DSTEP R1, R0 ; quotient is in the low +DSTEP R1, R0 ; word of R0 and the +DSTEP R1, R0 ; remainder is in the +DSTEP R1, R0 ; upper word of R0. +\end{lstlisting}\end{lrbox} +\begin{table-X}{Example: 16-bit by 16-bit Unsigned Division} +\usebox\ExampleUDiv\\ +\end{table-X} +% +\newsavebox\ExampleUMul +\begin{lrbox}{\ExampleUMul}\begin{lstlisting} +MOVU.W [value1], R1 ; Move the operands to +MOVU.W [value2], R0 ; the low word of R1 and +LSLQ 16, R0 ; the upper word of R0. +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 +MSTEP R1, R0 ; After 16 iterations, the +MSTEP R1, R0 ; 32 bit result is in R0. +\end{lstlisting}\end{lrbox} +\begin{table-X}{Example: 16-bit by 16-bit Unsigned Multiplication} +\usebox\ExampleUMul\\ +\end{table-X} +% +\begin{table-lX}{Preprocessor Macros} +\_\_cris\_\_ & Always set to 1 \\ +\_\_CRIS\_\_ & Always set to 1 \\ +\_\_GNU\_CRIS\_\_ & Always set to 1 \\ +\_\_arch\_\textit{X} & Target CPU specified by -march=\textit{X} \\ +\_\_tune\_\textit{X} & Tuning selected by -mtune=\textit{X} \\ +\end{table-lX} +% +\end{multicols} +\end{document} diff --git a/crisv32.tex b/crisv32.tex new file mode 100644 index 0000000..e19bf0b --- /dev/null +++ b/crisv32.tex @@ -0,0 +1,315 @@ +% +% Copyright (C) 2014 Anders Olofsson +% +% Copying and distribution of this file, with or without modification, +% are permitted in any medium without royalty provided the copyright +% notice and this notice are preserved. This file is offered as-is, +% without any warranty. +% +\documentclass{sheet} +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{ae,aecompl} +\usepackage[english]{babel} +\usepackage[a4paper, landscape, margin=.1in]{geometry} +\usepackage{amssymb} +\usepackage{verbatim} + +\def\sheetheaderfont{\bfseries} +\def\sheettablefont{\footnotesize\sffamily} +\def\sheetheadercolor{black!10} +\def\sheetrowcolor{black!5} + +\newcolumntype{N}{>{\raggedleft\arraybackslash}m{1.4em}} +\def\tabcolsep{2pt} +\def\arraystretch{1.3} +\defsheet{asmtable}{5}{|m{5.2em} m{5.7em}|X|m{2.0em} N|} +\defsheet{table-X}{1}{|X|} +\defsheet{table-lX}{2}{|l X|} +\defsheet{table-lXl}{3}{|l X l|} +\defsheet{table-lXN}{3}{|l X N|} +\defsheet{table-llX}{3}{|l l X|} +\defsheet{table-llXN}{4}{|l l X N|} + +\pagefooter{CRISv32 version 1.0 page \thepage} + +\begin{document} +\begin{multicols}{3} +\raggedcolumns + +\begin{center} +{\Large\bfseries CRISv32 Quick Reference} +\end{center} +% +\begin{table-lX}{Keys} +rd, rs, rn & General register (R0..R15) \\ +pr & Special register (P0..P15) \\ +sr & Support function register \\ +i$^{ }_{5}$, i$^{ }_{6}$ & Immediate operand \\ +{}[rn] & Indirect addressing mode \\ +{}[rn+] & Autoincrement addressing mode (cannot use ACR) \\ +i$^{ }_{8}$, i$^{ }_{16}$, i$^{ }_{32}$ & Immediate addressing mode (alias for [PC+]) \\ +s & Source operand (rn, [rn], [rn+], i$^{ }_{8}$, i$^{ }_{16}$ or i$^{ }_{32}$) \\ +si & Source operand ([rn], [rn+], i$^{ }_{8}$, i$^{ }_{16}$ or i$^{ }_{32}$) \\ +sm & Source operand ([rn] or [rn+]) \\ +d & Destination operand (rn, [rn] or [rn+]) \\ +di & Destination operand ([rn] or [rn+]) \\ +cc & Condition code \\ +m & Size modifier (b, w or d for byte, word or dword) \\ +z & Size modifier (b or w for byte or word) \\ +value$^{\pm}_{ }$ & Value is sign extended\\ +value$^{\emptyset}_{ }$ & Value is zero extended\\ +value$^{\{SU\}}_{ }$ & Signed or zero extend according to instruction name \\ +$\smul$ $\asr$ & Operation is signed \\ +{}**** & Flags NZVC are unchanged (--), affected (*) or cleared (0) \\ +\end{table-lX} +% +\begin{asmtable}{Bitwise Instructions} +AND.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ \& s$^{ }_{m}$ & **{--}{--} & \\ +ANDQ & i$^{ }_{6}$, rd & rd = rd \& i$^{\pm}_{ }$ & **{--}{--} & \\ +ASR.m & rs, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\asr$ rs$^{ }_{5:0}$ & **{--}{--} & \\ +ASRQ & i$^{ }_{5}$, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\asr$ i & **{--}{--} & \\ +BTST & rs, rd & N = rd$^{ }_{rs_{4:0}}$; Z = (rd$^{ }_{rs_{4:0}:0}$ $=$ 0) & **{--}{--} & \\ +BTSTQ & i$^{ }_{5}$, rd & N = rd$^{ }_{i}$; Z = (rs$^{ }_{i:0}$ = 0) & **{--}{--} & \\ +LSL.m & rs, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsl$ rs$^{ }_{5:0}$ & **{--}{--} & \\ +LSLQ & i$^{ }_{5}$, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsl$ i & **{--}{--} & \\ +LSR.m & rs, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsr$ rs$^{ }_{5:0}$ & **{--}{--} & \\ +LSRQ & i$^{ }_{5}$, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $\lsr$ i & **{--}{--} & \\ +LZ & rs, rd & rd = CountLeadingZeros(rs) & 0*{--}{--} & \\ +\textit{NOT} & rd & rd = $\sim$rd & **{--}{--} & \\ +OR.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ | s$^{ }_{m}$ & **{--}{--} & \\ +ORQ & i$^{ }_{6}$, rd & rd = rd | i$^{\pm}_{ }$ & **{--}{--} & \\ +XOR & rs, rd & rd = rd $\oplus$ rs & **{--}{--} & \\ +\end{asmtable} +% +\begin{asmtable}{SWAP\{NWBR\} Instruction} +SWAPN & rd & rd = $\sim$rd & **{--}{--} & \\ +SWAPW & rd & rd = rd$^{ }_{15:0}$:rd$^{ }_{31:16}$ & **{--}{--} & \\ +SWAPB & rd & rd = rd$^{ }_{23:16}$:rd$^{ }_{31:24}$:rd$^{ }_{7:0}$:rd$^{ }_{15:8}$ & **{--}{--} & \\ +SWAPR & rd & for(n=0..3) rd$^{ }_{Bn}$=ReverseBits(rd$^{ }_{Bn}$) & **{--}{--} & \\ +\end{asmtable} +% +\begin{asmtable}{Arithmetic Instructions} +ABS & rs, rd & rd = (rs$^{ }_{31}$ $=$ 1 ? 0$-$rs : rs) & **{--}{--} & \\ +ADD.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $+$ s$^{ }_{m}$ & **** & X \\ +ADDC & s, rd & rd = rd $+$ si $+$ C & **** & \\ +ADDQ & i$^{ }_{6}$, rd & rd = rd $+$ i$^{\emptyset}_{ }$ & **** & X \\ +ADD\{SU\}.z & s, rd & rd = rd $+$ s$^{\{SU\}}_{z}$ & **** & X \\ +CMP.m & s, rd & rd$^{ }_{m}$ $-$ s$^{ }_{m}$ & **** & X \\ +CMPQ & i$^{ }_{6}$, rd & rd $-$ i$^{\pm}_{ }$ & **** & X \\ +CMP\{SU\}.z & s, rd & rd $-$ s$^{\{SU\}}_{z}$ & **** & X \\ +DSTEP & rs, rd & rd $\lsl$= 1; if(rd $\ge$ rs) rd = rd $-$ rs & **{--}{--} & \\ +MCP & pr, rd & R:rd = rd + pr + R & ***{--} & \\ +MULS.m & rs, rd & MOF:rd = rd$^{\pm}_{m}$ $\smul$ rs$^{\pm}_{m}$ & ***{--} & \\ +MULU.m & rs, rd & MOF:rd = rd$^{\emptyset}_{m}$ $\umul$ rs$^{\emptyset}_{m}$ & ***{--} & \\ +NEG.m & rs, rd & rd$^{ }_{m}$ = 0 $-$ rs$^{ }_{m}$ & **** & X \\ +SUB.m & s, rd & rd$^{ }_{m}$ = rd$^{ }_{m}$ $-$ s$^{ }_{m}$ & **** & X \\ +SUBQ & i$^{ }_{6}$, rd & rd = rd $-$ i$^{\emptyset}_{ }$ & **** & X \\ +SUB\{SU\}.z & s, rd & rd = rd $-$ s$^{\{SU\}}_{z}$ & **** & X \\ +TEST.m & sm & sm$^{ }_{m}$ $-$ 0 & **00 & \\ +\end{asmtable} +% +\begin{asmtable}{Data Transfer Instructions} +\textit{CLEAR.m} & d & d$^{ }_{m}$ = 0 & {--}{--}{--}{--} & \\ +MOVE.m & s, rd & rd$^{ }_{m}$ = s$^{ }_{m}$ & **{--}{--} & \\ +MOVE.m & rs, di & di$^{ }_{m}$ = rs$^{ }_{m}$ & {--}{--}{--}{--} & \\ +MOVE & s, pr & pr = s$^{ }_{sizeof(pr)}$ & {--}{--}{--}{--} & M \\ +MOVE & pr, d & d$^{ }_{sizeof(pr)}$ = pr & {--}{--}{--}{--} & \\ +MOVE & rs, sr & SRS.sr = rs & {--}{--}{--}{--} & M \\ +MOVE & sr, rd & rd = SRS.sr & {--}{--}{--}{--} & \\ +MOVEM & rs, di & di[0] = R0 \ldots di[4*s] = rs & {--}{--}{--}{--} & \\ +MOVEM & sm, rd & R0 = sm[0] \ldots rd = sm[4*d] & {--}{--}{--}{--} & \\ +MOVEQ & i$^{ }_{6}$, rd & rd = i$^{\pm}_{ }$ & {--}{--}{--}{--} & \\ +MOV\{SU\}.z & s, rd & rd = s$^{\{SU\}}_{z}$ & **{--}{--} & \\ +Scc & rd & rd = (cc ? 1 : 0) & {--}{--}{--}{--} & \\ +\end{asmtable} +% +\begin{asmtable}{Address Calculation Instructions} +ADDI & rs.m, rd & rd = rd $+$ rs $\umul$ sizeof(m) & {--}{--}{--}{--} & X \\ +ADDI & rs.m, rd, ACR & ACR = rd $+$ rs $\umul$ sizeof(m) & {--}{--}{--}{--} & X \\ +ADDO.m & si, rd, ACR & ACR = rd + si$^{\pm}_{m}$ & {--}{--}{--}{--} & X \\ +ADDOQ & i$^{ }_{8}$, rd, ACR & ACR = rd + i$^{\pm}_{ }$ & {--}{--}{--}{--} & X \\ +BOUND.m & rs, rd & rd = MIN(rd, rs$^{\emptyset}_{m}$) & **{--}{--} & \\ +BOUND.m & i$^{ }_{m}$, rd & rd = MIN(rd, i$^{\emptyset}_{ }$) & **{--}{--} & \\ +LAPC & i$^{ }_{32}$, rd & rd = PC + i & {--}{--}{--}{--} & \\ +LAPCQ & i$^{ }_{5}$, rd & rd = PC + i$^{\emptyset}_{4:1}$:0 & {--}{--}{--}{--} & \\ +\end{asmtable} +% +\begin{asmtable}{Jump and Branch Instructions} +\textit{BA} & i$^{ }_{32}$ & PC $+$= i & {--}{--}{--}{--} & D,L \\ +BAS\{C\} & i$^{ }_{32}$, pr & pr = PC + (C ? 12 : 8); PC $+$= i & {--}{--}{--}{--} & D,L \\ +Bcc & rel$^{ }_{9}$ & if(cc) PC $+$= rel$^{\pm}_{8:1}$:0 & {--}{--}{--}{--} & D,L \\ +Bcc & rel$^{ }_{16}$ & if(cc) PC $+$= rel$^{\pm}_{ }$ & {--}{--}{--}{--} & D,L \\ +BREAK & i$^{ }_{4}$ & BRP=PC; PC=[EBP+0x10+4$\umul$i] & {--}{--}{--}{--} & \\ +\textit{BSR\{C\}} & i$^{ }_{32}$ & SRP = PC + (C ? 12 : 8); PC$+$=i & {--}{--}{--}{--} & D,L \\ +JAS\{C\} & rs, pr & pr = PC + (C ? 8 : 4); PC = rs & {--}{--}{--}{--} & D,L \\ +JAS\{C\} & i$^{ }_{32}$, pr & pr = PC + (C ? 12 : 8); PC = i & {--}{--}{--}{--} & D,L \\ +\textit{JSR\{C\}} & rs & SRP = PC + (C ? 8 : 4); PC = rs & {--}{--}{--}{--} & D,L \\ +\textit{JSR\{C\}} & i$^{ }_{32}$ & SRP = PC + (C ? 12 : 8); PC = i & {--}{--}{--}{--} & D,L \\ +\textit{JUMP} & rs & PC = rs & {--}{--}{--}{--} & D,L \\ +\textit{JUMP} & i$^{ }_{32}$ & PC = i & {--}{--}{--}{--} & D,L \\ +JUMP & pr & PC = pr & {--}{--}{--}{--} & D,L \\ +\textit{RET} & & PC = SRP & {--}{--}{--}{--} & D,L \\ +\textit{RETE} & & PC = ERP & {--}{--}{--}{--} & D,L \\ +\textit{RETN} & & PC = NRP & {--}{--}{--}{--} & D,L \\ +\end{asmtable} +% +\begin{asmtable}{Flag Instructions} +\textit{AX} & & X = 1 & {--}{--}{--}{--} & \\ +CLEARF & & = 0 & **** & M \\ +\textit{DI} & & I = 0 & {--}{--}{--}{--} & M \\ +\textit{EI} & & I = 1 & {--}{--}{--}{--} & M \\ +RFE & & CCS$^{ }_{29:0}$ $\lsr$= 10; P = !R & **** & M \\ +RFG & & CCS, NRP and SRS restored & **** & M \\ +RFN & & CCS$^{ }_{29:0}$ $\lsr$= 10; M = 1; P = !R & **** & M \\ +SETF & & = 1 & **** & M \\ +SFE & & CCS$^{ }_{29:0}$ $\lsl$= 10 & 0000 & M \\ +\end{asmtable} +% +\begin{asmtable}{Special Instructions} +FIDXD & [rs] & Flush data cache with index & {--}{--}{--}{--} & L,M \\ +FIDXI & [rs] & Flush instruction cache with index & {--}{--}{--}{--} & L,M \\ +FTAGD & [rs] & Flush data cache with address & {--}{--}{--}{--} & L,M \\ +FTAGI & [rs] & Flush instruction cache with address & {--}{--}{--}{--} & L,M \\ +HALT & & Stop and wait for exceptions & {--}{--}{--}{--} & L,M \\ +\textit{NOP} & & & {--}{--}{--}{--} & \\ +\end{asmtable} +% +\begin{table-lX}{Notes} +D & One delay slot before jump/branch is taken \\ +L & Cannot be used in delay slot \\ +M & Behavior or access is restricted in user mode \\ +X & C flag is added/subtracted if X flag is set \\ +\end{table-lX} +% +\begin{table-llXN}{Registers} +R0-R8 & & General registers (must be preserved) & \\ +R9 & & General register & \\ +R10-R13 & & Function arguments and return value(s) & \\ +R14 & SP & Stack pointer & \\ +R15 & ACR & Address calculation register & \\ + & PC & Program counter & \\ +P0 & BZ & Zero byte constant register (8 bits) & \\ +P1 & VR & Version register (8 bits) & \\ +P2 & PID & Process ID & M \\ +P3 & SRS & Support register select (8 bits) & M \\ +P4 & WZ & Zero word constant register (16 bits) & \\ +P5 & EXS & Exception status & \\ +P6 & EDA & Exception data address & \\ +P7 & MOF & Multiply overflow register & V \\ +P8 & DZ & Zero dword constant register & \\ +P9 & EBP & Exception base register & M \\ +P10 & ERP & Exception return pointer & \\ +P11 & SRP & Subroutine return pointer & \\ +P12 & NRP & NMI return pointer & \\ +P13 & CCS & Condition code stack & \\ +P14 & USP & User mode stack pointer & \\ +P15 & SPC & Single step PC & M \\ +\end{table-llXN} +% +\begin{table-lXl}{Condition Codes} +CC/HS & Carry clear / Higher or same & !C \\ +CS/LO & Carry set / Lower & C \\ +NE & Not equal & !Z \\ +EQ & Equal & Z \\ +VC & Overflow clear & !V \\ +VS & Overflow set & V \\ +PL & Plus & !N \\ +MI & Minus & N \\ +LS & Lower or same & C | Z \\ +HI & Higher & !C \& !Z \\ +GE & Signed greater or equal & N $=$ V \\ +LT & Signed less than & N $\ne$ V \\ +GT & Signed greater than & N $=$ V \& !Z \\ +LE & Signed less or equal & N $\ne$ V | Z \\ +A & Always true & 1 \\ +SB & Sequence broken & P \\ +\end{table-lXl} +% +\begin{table-lXN}{Flags} +C & Carry & \\ +V & Overflow & \\ +Z & Zero & \\ +N & Negative & \\ +X & Extend & \\ +I & Interrupt enable & M \\ +U & User mode & M \\ +P & Sequence broken & \\ +R & Restore P on RFE. Carry for MCP instruction & \\ +S & Single step & M \\ +S1..C1 & First stack level & \\ +S2..C2 & Second stack level & \\ +M & NMI enable & M \\ +Q & Pending single step & M \\ +\end{table-lXN} +% +\begin{table-lX}{Execution Times} +1 & General instructions \\ ++1 & Multiplication operand modified in preceding instruction \\ ++1 & Memory access using register modified in preceding instruction \\ ++1 & Jump destination register modified in preceding instruction \\ ++2 & Source registers for MOVEM modified in two preceding instructions \\ ++3 & Destination regs for MOVEM modified in three following instructions \\ ++2 & Branch instruction prediction miss \\ ++2 & Read from memory within two cycles of write \\ ++2 & Write to memory within two cycles of write to a clean cache line \\ ++1 & Each memory access across (32 byte) cache line boundary \\ ++1 & First instruction after JUMP crosses a (32 byte) cache line boundary \\ +\end{table-lX} +% +\begin{table-llX}{Support Register Banks} +0 & B\_GC & General configuration and guru mode registers \\ +1 & B\_IM & Instruction MMU registers \\ +2 & B\_DM & Data MMU registers \\ +3 & B\_BP & Breakpoint registers \\ +255 & B\_Z & All support registers are always zero \\ +\end{table-llX} +% +\begin{table-lX}{Exception Vectors} +0x00 & NMI \\ +0x03 & Single step \\ +0x04..0x07 & Instruction TLB refill/invalid/access/write \\ +0x08..0x0b & Data TLB refill/invalid/access/write \\ +0x0c & Hardware breakpoint \\ +0x10..0x1f & Break 0..15 \\ +0x20..0xff & Interrupts \\ +\end{table-lX} +% +\newsavebox\ExampleUDiv +\begin{lrbox}{\ExampleUDiv}\begin{lstlisting} +MOVU.W [num], R0 ; Move the numerator to +MOVU.W [denom], R1 ; the low word of R0 and +LSLQ 16, R1 ; the denominator to the +SUBQ 1, R1 ; upper word of R1. +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 +DSTEP R1, R0 ; After 16 iterations the +DSTEP R1, R0 ; quotient is in the low +DSTEP R1, R0 ; word of R0 and the +DSTEP R1, R0 ; remainder is in the +DSTEP R1, R0 ; upper word of R0. +\end{lstlisting}\end{lrbox} +\begin{table-X}{Example: 16-bit by 16-bit Unsigned Division} +\usebox\ExampleUDiv\\ +\end{table-X} +% +\begin{table-lX}{Preprocessor Macros} +\_\_cris\_\_ & Always set to 1 \\ +\_\_CRIS\_\_ & Always set to 1 \\ +\_\_GNU\_CRIS\_\_ & Always set to 1 \\ +\_\_arch\_v32 & Always set to 1 \\ +\_\_CRIS\_arch\_version & Always set to 32 \\ +\_\_tune\_\textit{X} & Tuning selected by -mtune=\textit{X} \\ +\end{table-lX} +% +\end{multicols} +\end{document} diff --git a/mips32r2.tex b/mips32r2.tex new file mode 100644 index 0000000..2bd740f --- /dev/null +++ b/mips32r2.tex @@ -0,0 +1,327 @@ +% +% Copyright (C) 2014 Anders Olofsson +% +% Copying and distribution of this file, with or without modification, +% are permitted in any medium without royalty provided the copyright +% notice and this notice are preserved. This file is offered as-is, +% without any warranty. +% +\documentclass{sheet} +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{ae,aecompl} +\usepackage[english]{babel} +\usepackage[a4paper, landscape, margin=.1in]{geometry} +\usepackage{amssymb} + +\def\sheetheaderfont{\bfseries} +\def\sheettablefont{\footnotesize\sffamily} +\def\sheetheadercolor{black!10} +\def\sheetrowcolor{black!5} + +\def\tabcolsep{2pt} +\def\arraystretch{1.3} +\defsheet{asmtable}{4}{|m{4.2em} m{5.0em}|X|m{0.7em}|} +\defsheet{table-lX}{2}{|l X|} +\defsheet{table-llX}{3}{|l l X|} + +\pagefooter{MIPS32r2 version 1.0 page \thepage} + +\begin{document} +\begin{multicols}{3} +\raggedcolumns + +\begin{center} +{\Large\bfseries MIPS32r2 Quick Reference} +\end{center} +% +\begin{table-lX}{Keys} +rx, ry, rz & General registers \\ +i, p, s, rel, ptr, off & Immediate operand \\ +ISA & ISA mode (0=MIPS32, 1=MIPS16e) \\ +value$^{\pm}_{ }$ & Value is sign extended \\ +value$^{\emptyset}_{ }$ & Value is zero extended \\ +$\smul$ $\sdiv$ $\smod$ $\asr$ $\slt$ $\sge$ & Operation is signed \\ +\end{table-lX} +% +\begin{asmtable}{Arithmetic Instructions} +ADD & rx, ry, rz & rx = ry $+$ rz & O \\ +ADDI & rx, ry, i$^{ }_{16}$ & rx = ry $+$ i$^{\pm}_{ }$ & O \\ +ADDIU & rx, ry, i$^{ }_{16}$ & rx = ry $+$ i$^{\pm}_{ }$ & \\ +ADDU & rx, ry, rz & rx = ry $+$ rz & \\ +DIV & rx, ry & HI = rx $\sdiv$ ry; LO = rx $\smod$ ry & \\ +DIVU & rx, ry & HI = rx $\udiv$ ry; LO = rx $\umod$ ry & \\ +MADD & rx, ry & HI:LO = HI:LO $+$ rx $\smul$ ry & \\ +MADDU & rx, ry & HI:LO = HI:LO $+$ rx $\umul$ ry & \\ +MSUB & rx, ry & HI:LO = HI:LO $-$ rx $\smul$ ry & \\ +MSUBU & rx, ry & HI:LO = HI:LO $-$ rx $\umul$ ry & \\ +MUL & rx, ry, rz & rx = ry $\smul$ rz & \\ +MULT & rx, ry & HI:LO = rx $\smul$ ry & \\ +MULTU & rx, ry & HI:LO = rx $\umul$ ry & \\ +\textit{NEGU} & rx, ry & rx = 0 $-$ ry & \\ +SUB & rx, ry, rz & rx = ry $-$ rz & O \\ +SUBU & rx, ry, rz & rx = ry $-$ rz & \\ +\end{asmtable} +% +\begin{asmtable}{Load and Store Instructions} +LB & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\pm}_{8}$ & \\ +LBU & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\emptyset}_{8}$ & \\ +LH & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\pm}_{16}$ & \\ +LHU & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{\emptyset}_{16}$ & \\ +LL & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]; LL = 1 & \\ +LW & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$] & \\ +LWL & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; rx$^{ }_{31:24-s\umul 8}$ = [ry $+$ off$^{\pm}_{ }$]$^{ }_{8+s\umul 8}$ & \\ +LWR & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; rx$^{ }_{31-s\umul 8:0}$ = [ry $+$ off$^{\pm}_{ }$]$^{ }_{32-s\umul 8}$ & \\ +SB & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$]$^{ }_{8}$ = rx$^{ }_{7:0}$ & \\ +SC & rx, off$^{ }_{16}$(ry) & if(atomic) [ry $+$ off$^{\pm}_{ }$]=rx; rx=1; else rx=0 & \\ +SH & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$]$^{ }_{16}$ = rx$^{ }_{15:0}$ & \\ +SW & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$] = rx & \\ +SWL & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; [ry $+$ off$^{\pm}_{ }$]$^{ }_{8+s\umul 8}$ = rx$^{ }_{31:24-s\umul 8}$ & \\ +SWR & rx, off$^{ }_{16}$(ry) & s=(ry$+$off$^{\pm}_{ }$)$^{ }_{1:0}$; [ry $+$ off$^{\pm}_{ }$]$^{ }_{32-s\umul 8}$ = rx$^{ }_{31-s\umul 8:0}$ & \\ +\textit{ULW} & rx, off$^{ }_{16}$(ry) & rx = [ry $+$ off$^{\pm}_{ }$]$^{unaligned}_{ }$ & \\ +\textit{USW} & rx, off$^{ }_{16}$(ry) & [ry $+$ off$^{\pm}_{ }$]$^{unaligned}_{ }$ = rx & \\ +\end{asmtable} +% +\begin{asmtable}{Bitwise Instructions} +AND & rx, ry, rz & rx = ry \& rz & \\ +ANDI & rx, ry, i$^{ }_{16}$ & rx = ry \& i$^{\emptyset}_{ }$ & \\ +CLO & rx, ry & rx = CountLeadingOnes(ry) & \\ +CLZ & rx, ry & rx = CountLeadingZeros(ry) & \\ +EXT & rx, ry, p, s & rx = ry$^{\emptyset}_{p+s-1:p}$ & 2 \\ +INS & rx, ry, p, s & rx$^{ }_{p+s-1:p}$ = ry$^{ }_{s-1:0}$ & 2 \\ +NOR & rx, ry, rz & rx = $\sim$(ry | rz) & \\ +\textit{NOT} & rx, ry & rx = $\sim$ry & \\ +OR & rx, ry, rz & rx = ry | rz & \\ +ORI & rx, ry, i$^{ }_{16}$ & rx = ry | i$^{\emptyset}_{ }$ & \\ +ROTR & rx, ry, i$^{ }_{5}$ & rx = ry $\ror$ i & \\ +ROTRV & rx, ry, rz & rx = ry $\ror$ rz$^{ }_{4:0}$ & \\ +SLL & rx, ry, i$^{ }_{5}$ & rx = ry $\lsl$ i & \\ +SLLV & rx, ry, rz & rx = ry $\lsl$ rz$^{ }_{4:0}$ & \\ +SRA & rx, ry, i$^{ }_{5}$ & rx = ry $\asr$ i & \\ +SRAV & rx, ry, rz & rx = ry $\asr$ rz$^{ }_{4:0}$ & \\ +SRL & rx, ry, i$^{ }_{5}$ & rx = ry $\lsr$ i & \\ +SRLV & rx, ry, rz & rx = ry $\lsr$ rz$^{ }_{4:0}$ & \\ +WSBH & rx, ry & rx = ry$^{ }_{23:16}$:ry$^{ }_{31:24}$:ry$^{ }_{7:0}$:ry$^{ }_{15:8}$ & 2 \\ +XOR & rx, ry, rz & rx = ry $\oplus$ rz & \\ +XORI & rx, ry, i$^{ }_{16}$ & rx = ry $\oplus$ i$^{\emptyset}_{ }$ & \\ +\end{asmtable} +% +\begin{asmtable}{Jump and Branch Instructions} +\textit{B} & rel$^{ }_{18}$ & PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +\textit{BAL} & rel$^{ }_{18}$ & RA = PC$+$8; PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BEQ & rx, ry, rel$^{ }_{18}$ & if (rx $=$ ry) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +\textit{BEQZ} & rx, rel$^{ }_{18}$ & if (rx $=$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BGEZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BGEZAL & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 0) RA = PC$+$8; PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BGTZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 0 \&\& rx $\ne$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BLEZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 1 || rx $=$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BLTZ & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 1) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BLTZAL & rx, rel$^{ }_{18}$ & if (rx$^{ }_{31}$ $=$ 1) RA = PC$+$8; PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +BNE & rx, ry, rel$^{ }_{18}$ & if (rx $\ne$ ry) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +\textit{BNEZ} & rx, rel$^{ }_{18}$ & if (rx $\ne$ 0) PC $+$= rel$^{\pm}_{16:2}$:0$^{ }_{1:0}$ & D \\ +J & ptr$^{ }_{28}$ & PC = PC$^{ }_{31:29}$:ptr$^{ }_{28:2}$:0$^{ }_{1:0}$ & D \\ +JAL & ptr$^{ }_{28}$ & RA=PC$+$8; PC=PC$^{ }_{31:29}$:ptr$^{ }_{28:2}$:0$^{ }_{1:0}$ & D \\ +JALX & ptr$^{ }_{28}$ & ISA=1; RA=PC$+$8; PC=PC$^{ }_{31:29}$:ptr$^{ }_{28:2}$:0$^{ }_{1:0}$ & D \\ +JALR & rx, ry & rx=PC$+$8; ISA=ry$^{ }_{0}$; PC=ry$^{ }_{31:1}$:0 & D \\ +\textit{JALR} & rx & RA=PC$+$8; ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & D \\ +JALR.HB & rx, ry & rx=PC$+$8; ISA=ry$^{ }_{0}$; PC=ry$^{ }_{31:1}$:0; ClrHazards & D \\ +\textit{JALR.HB} & rx & RA=PC$+$8; ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0; ClrHazards & D \\ +JR & rx & ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0 & D \\ +JR.HB & rx & ISA=rx$^{ }_{0}$; PC=rx$^{ }_{31:1}$:0; ClrHazards & D \\ +\end{asmtable} +% +\begin{asmtable}{Data Transfer Instructions} +\textit{LA} & rx, rel & rx = rel & \\ +\textit{LI} & rx, i$^{ }_{32}$ & rx = i & \\ +LUI & rx, i$^{ }_{16}$ & rx = i $\lsl$ 16 & \\ +MFHI & rx & rx = HI & \\ +MFLO & rx & rx = LO & \\ +\textit{MOVE} & rx, ry & rx = ry & \\ +MOVN & rx, ry, rz & if (rz $\ne$ 0) rx = ry & \\ +MOVZ & rx, ry, rz & if (rz $=$ 0) rx = ry & \\ +MTHI & rx & HI = rx & \\ +MTLO & rx & LO = rx & \\ +RDHWR & rx, ry & rx = HardwareRegister(ry) & 2 \\ +SEB & rx, ry & rx = ry$^{\pm}_{7:0}$ & 2 \\ +SEH & rx, ry & rx = ry$^{\pm}_{15:0}$ & 2 \\ +SLT & rx, ry, rz & rx = (ry $\slt$ rz ? 1 : 0) & \\ +SLTI & rx, ry, i$^{ }_{16}$ & rx = (ry $\slt$ i$^{\pm}_{ }$ ? 1 : 0) & \\ +SLTIU & rx, ry, i$^{ }_{16}$ & rx = (ry $\ult$ i$^{\pm}_{ }$ ? 1 : 0) & \\ +SLTU & rx, ry, rz & rx = (ry $\ult$ rz ? 1 : 0) & \\ +\end{asmtable} +% +\begin{asmtable}{Control Instructions} +CACHE & i$^{ }_{5}$, off$^{ }_{16}$(rx) & CacheOperation(i, rx$+$off$^{\pm}_{ }$) & \\ +EHB & & ExecutionHazardBarrier & \\ +\textit{NOP} & & & \\ +PAUSE & & While(LL $\ne$ 0) Wait & \\ +PREF & i$^{ }_{5}$, off$^{ }_{16}$(ry) & PrefetchMemory(ry $+$ off$^{\pm}_{ }$) & \\ +SSNOP & & SuperScalarNoOperation & \\ +SYNC & stype$^{ }_{5}$ & SyncOperation(stype) & \\ +SYNCI & off$^{ }_{16}$(rx) & SyncCacheLines(rx $+$ off$^{\pm}_{ }$) & 2 \\ +\end{asmtable} +% +\begin{asmtable}{Trap Instructions} +BREAK & i$^{ }_{20}$ & Exception(Breakpoint) & \\ +SYSCALL & code$^{ }_{20}$ & Exception(SystemCall) & \\ +TEQ & rx, ry & if (rx $=$ ry) Exception(Trap) & \\ +TEQI & rx, i$^{ }_{16}$ & if (rx $=$ i$^{\pm}_{ }$) Exception(Trap) & \\ +TGE & rx, ry & if (rx $\sge$ ry) Exception(Trap) & \\ +TGEI & rx, i$^{ }_{16}$ & if (rx $\sge$ i$^{\pm}_{ }$) Exception(Trap) & \\ +TGEIU & rx, i$^{ }_{16}$ & if (rx $\uge$ i$^{\pm}_{ }$) Exception(Trap) & \\ +TGEU & rx, ry & if (rx $\uge$ ry) Exception(Trap) & \\ +TLT & rx, ry & if (rx $\slt$ ry) Exception(Trap) & \\ +TLTI & rx, i$^{ }_{16}$ & if (rx $\slt$ i$^{\pm}_{ }$) Exception(Trap) & \\ +TLTIU & rx, i$^{ }_{16}$ & if (rx $\ult$ i$^{\pm}_{ }$) Exception(Trap) & \\ +TLTU & rx, ry & if (rx $\ult$ ry) Exception(Trap) & \\ +TNE & rx, ry & if (rx $\ne$ ry) Exception(Trap) & \\ +TNEI & rx, i$^{ }_{16}$ & if (rx $\ne$ i$^{\pm}_{ }$) Exception(Trap) & \\ +\end{asmtable} +% +\begin{asmtable}{Privileged Instructions} +\textit{DI} & & STATUS$^{ }_{IE}$ = 0 & 2 \\ +DI & rx & rx = STATUS; STATUS$^{ }_{IE}$ = 0 & 2 \\ +DERET & & DebugExceptionReturn & \\ +\textit{EI} & & STATUS$^{ }_{IE}$ = 1 & 2 \\ +EI & rx & rx = STATUS; STATUS$^{ }_{IE}$ = 1 & 2 \\ +ERET & & ExceptionReturn & \\ +MFC0 & rx, ry, i$^{ }_{3}$ & rx = Coprocessor0Register[ry, i] & \\ +MTC0 & rx, ry, i$^{ }_{3}$ & Coprocessor0Register[ry, i] = rx & \\ +RDPGPR & rx, ry & rx = PreviousShadowSet(ry) & 2 \\ +SDBBP & code$^{ }_{20}$ & SoftwareDebugBreakpoint & \\ +TLBP & & TlbIndex = FindTlbEntry(EntryHi) & \\ +TLBR & & Entry:PageMask = TlbEntry[TlbIndex] & \\ +TLBWI & & TlbEntry[TlbIndex] = Entry:PageMask & \\ +TLBWR & & TlbEntry[TlbRandom] = Entry:PageMask & \\ +WAIT & & Wait for interrupt or external request & \\ +WRPGPR & rx, ry & PreviousShadowSet(rx) = ry & 2 \\ +\end{asmtable} +% +\begin{table-llX}{Cache Operations} +0x00..0x03 & Index & (Writeback and) invalidate instr/data/3rd/2nd cache \\ +0x04..0x07 & Index & Load tag instr/data/3rd/2nd cache \\ +0x08..0x0b & Index & Store tag instr/data/3rd/2nd cache \\ +0x10..0x13 & Address & Invalidate instr/data/3rd/2nd cache \\ +0x14 & Address & Fill instruction cache \\ +0x15..0x17 & Address & Writeback and invalidate data/3rd/2nd cache \\ +0x19..0x1b & Address & Writeback data/3rd/2nd cache \\ +0x1c..0x1d & Address & Fetch and lock instruction/data cache \\ +\end{table-llX} +% +\begin{table-lX}{RDHWR Register Numbers} +0 & Number of current CPU \\ +1 & Address step size to be used with SYNCI instruction \\ +2 & High-resolution cycle counter \\ +3 & Resolution of the cycle counter \\ +29 & User local register \\ +\end{table-lX} +% +\begin{table-lX}{Notes} +2 & Only available on MIPS32 Release 2 \\ +D & Delay slot of one instruction before jump is executed \\ +O & Exception without modifying the destination register on signed overflow. \\ +R & If extended, can also include A*..A3 and any of S2..S8 in reglist. \\ +S & The shift count may be 1..8. Extendedable to 0..31. \\ +X & Immediate can be extended by up to 11 bits (max 16 bits total). \newline The extended immediate is unsigned for CMPI and LI, otherwise signed. \\ +\end{table-lX} +% +\begin{table-llX}{General Registers} +0 & ZERO & Always zero \\ +1 & AT & \\ +2..3 & V0..V1 & Function return value (usable by MIPS16e) \\ +4..7 & A0..A3 & Function parameters (usable by MIPS16e) \\ +8..15 & T0..T7 & Temporary \\ +16..23 & S0..S7 & Must be preserved (S0..S1 usable by MIPS16e) \\ +24..25 & T8..T9 & Temporary \\ +26..27 & K0..K1 & Kernel use \\ +28 & GP & Global pointer \\ +29 & SP & Stack pointer \\ +30 & FP/S8 & Stack frame pointer, must be preserved \\ +31 & RA & Function return address \\ + & PC & Program Counter \\ +\end{table-llX} +% +\begin{asmtable}{MIPS16e Load and Store Instructions} +LB & rx, i$^{ }_{5}$(ry) & rx = [ry $+$ i$^{\emptyset}$]$^{\pm}_{8}$ & X \\ +LBU & rx, i$^{ }_{5}$(ry) & rx = [ry $+$ i$^{\emptyset}$]$^{\emptyset}_{8}$ & X \\ +LH & rx, i$^{ }_{6}$(ry) & rx = [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{\pm}_{16}$ & X \\ +LHU & rx, i$^{ }_{6}$(ry) & rx = [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{\emptyset}_{16}$ & X \\ +LW & rx, i$^{ }_{7}$(ry) & rx = [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] & X \\ +LW & rx, i$^{ }_{10}$(PC) & rx = [PC$^{ }_{31:2}$:0$^{ }_{1:0}$ $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & X \\ +LW & rx, i$^{ }_{10}$(SP) & rx = [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] & X \\ +SB & rx, i$^{ }_{5}$(ry) & [ry $+$ i$^{\emptyset}_{ }$]$^{ }_{8}$ = rx$^{ }_{8}$ & X \\ +SH & rx, i$^{ }_{6}$(ry) & [ry $+$ i$^{\emptyset}_{5:1}$:0]$^{ }_{16}$ = rx$^{ }_{16}$ & X \\ +SW & rx, i$^{ }_{7}$(ry) & [ry $+$ i$^{\emptyset}_{6:2}$:0$^{ }_{1:0}$] = rx & X \\ +SW & rx, i$^{ }_{10}$(SP) & [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] = rx & X \\ +SW & RA, i$^{ }_{10}$(SP) & [SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$] = RA & X \\ +\end{asmtable} +% +\begin{asmtable}{MIPS16e Data Transfer Instructions} +\textit{LA} & rx, rel & rx = rel & \\ +LI & rx, i$^{ }_{8}$ & rx = i$^{\emptyset}_{ }$ & X \\ +MFHI & rx & rx = HI & \\ +MFLO & rx & rx = LO & \\ +MOVE & rx, r32 & rx = r32 & \\ +MOVE & r32, ry & r32 = rx & \\ +RESTORE & reglist, i$^{ }_{7}$ & SP $+$= i$^{ }_{6:2}$:0$^{ }_{1:0}$; reglist = [SP] & R \\ +SAVE & reglist, i$^{ }_{7}$ & [SP] = reglist; SP $-$= i$^{ }_{6:2}$:0$^{ }_{1:0}$ & R \\ +SEB & rx & rx = rx$^{\pm}_{7:0}$ & \\ +SEH & rx & rx = rx$^{\pm}_{15:0}$ & \\ +SLT & rx, ry & T8 = (rx $\slt$ ry ? 1 : 0) & \\ +SLTI & rx, i$^{ }_{8}$ & T8 = (rx $\slt$ i$^{\emptyset}_{ }$ ? 1 : 0) & X \\ +SLTIU & rx, i$^{ }_{8}$ & T8 = (rx $\ult$ i$^{\emptyset}_{ }$ ? 1 : 0) & X \\ +SLTU & rx, ry & T8 = (rx $\ult$ ry ? 1 : 0) & \\ +ZEB & rx & rx = rx$^{\emptyset}_{7:0}$ & \\ +ZEH & rx & rx = rx$^{\emptyset}_{15:0}$ & \\ +\end{asmtable} +% +\begin{asmtable}{MIPS16e Jump and Branch Instructions} +B & rel$^{ }_{12}$ & PC $+$= rel$^{\pm}_{11:1}$:0 & X \\ +BEQZ & rx, rel$^{ }_{9}$ & if(rx $=$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & X \\ +BNEZ & rx, rel$^{ }_{9}$ & if(rx $\ne$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & X \\ +BREAK & i$^{ }_{6}$ & Breakpoint trap & X \\ +BTEQZ & rel$^{ }_{9}$ & if(T8 $=$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & X \\ +BTNEZ & rel$^{ }_{9}$ & if(T8 $\ne$ 0) PC $+$= rel$^{\pm}_{8:1}$:0 & \\ +JAL & ptr$^{ }_{28}$ & RA=PC$+$5; PC=PC$^{ }_{31:28}$:ptr$^{ }_{27:2}$:0$^{ }_{1:0}$ & D \\ +JALR & RA, rx & ISA=rx$^{ }_{0}$; RA=PC$+$5; PC=rx$^{ }_{31:1}$:0 & D \\ +JALRC & RA, rx & ISA=rx$^{ }_{0}$; RA=PC$+$3; PC=rx$^{ }_{31:1}$:0 & \\ +JALX & ptr$^{ }_{28}$ & ISA=0; RA=PC$+$5; PC=PC$^{ }_{31:28}$:ptr$^{ }_{27:2}$:0$^{ }_{1:0}$ & D \\ +JR & rx & ISA=rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & D \\ +JR & RA & ISA=RA$^{ }_{0}$; PC = RA$^{ }_{31:1}$:0 & D \\ +JRC & rx & ISA=rx$^{ }_{0}$; PC = rx$^{ }_{31:1}$:0 & \\ +JRC & RA & ISA=RA$^{ }_{0}$; PC = RA$^{ }_{31:1}$:0 & \\ +\textit{NOP} & & & \\ +\end{asmtable} +% +\begin{asmtable}{MIPS16e Arithmetic Instructions} +ADDIU & rx, i$^{ }_{8}$ & rx = rx $+$ i$^{\pm}_{ }$ & X \\ +ADDIU & rx, ry, i$^{ }_{4}$ & rx = ry $+$ i$^{\pm}_{ }$ & X \\ +ADDIU & rx, PC, i$^{ }_{10}$ & rx = PC $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$ & \\ +ADDIU & SP, i$^{ }_{11}$ & SP = SP $+$ i$^{\pm}_{10:3}$:0$^{ }_{2:0}$ & X \\ +ADDIU & rx, SP, i$^{ }_{10}$ & rx = SP $+$ i$^{\emptyset}_{9:2}$:0$^{ }_{1:0}$ & \\ +ADDU & rx, ry, rz & rx = ry $+$ rz & \\ +DIV & rx, ry & LO = rx $\sdiv$ ry; HI = rx $\smod$ ry & \\ +DIVU & rx, ry & LO = rx $\div$ ry; HI = rx $\umod$ ry & \\ +MULT & rx, ry & HI:LO = rx $\smul$ ry & \\ +MULTU & rx, ry & HI:LO = rx $\umul$ ry & \\ +NEG & rx, ry & rx = 0 $-$ ry & \\ +SUBU & rx, ry, rz & rx = ry $-$ rz & \\ +\end{asmtable} +% +\begin{asmtable}{MIPS16e Bitwise Instructions} +AND & rx, ry & rx = rx \& ry & \\ +CMP & rx, ry & T8 = rx $\oplus$ ry & \\ +CMPI & rx, i$^{ }_{8}$ & T8 = rx $\oplus$ i$^{\emptyset}_{ }$ & X \\ +NOT & rx, ry & rx = $\sim$ry & \\ +OR & rx, ry & rx = rx | ry & \\ +SLL & rx, ry, i$^{ }_{3}$ & rx = ry $\lsl$ i & S \\ +SLLV & rx, ry & rx = rx $\lsl$ ry$^{ }_{4:0}$ & \\ +SRA & rx, ry, i$^{ }_{3}$ & rx = ry $\asr$ i & S \\ +SRAV & rx, ry & rx = rx $\asr$ ry$^{ }_{4:0}$ & \\ +SRL & rx, ry, i$^{ }_{3}$ & rx = ry $\lsr$ i & S \\ +SRLV & rx, ry & rx = rx $\lsr$ ry$^{ }_{4:0}$ & \\ +XOR & rx, ry & rx = rx $\oplus$ ry & \\ +\end{asmtable} +% +\end{multicols} +\end{document} diff --git a/sheet.cls b/sheet.cls new file mode 100644 index 0000000..ef6fc9b --- /dev/null +++ b/sheet.cls @@ -0,0 +1,96 @@ +% +% Copyright (C) 2014 Anders Olofsson +% +% Copying and distribution of this file, with or without modification, +% are permitted in any medium without royalty provided the copyright +% notice and this notice are preserved. This file is offered as-is, +% without any warranty. +% +\ProvidesClass{sheet} +\PassOptionsToPackage{table}{xcolor} +\LoadClass{article} +\RequirePackage{pgf} +\RequirePackage{tikz} +\RequirePackage{multicol} +\RequirePackage{tabularx} +\RequirePackage{colortbl} +\RequirePackage{everypage} +\RequirePackage{listings} +\RequirePackage{amsmath} + +\tikzstyle{every picture} = [inner sep=0pt, outer sep=0pt, font={\sheettablefont}] + +\def\TX@find@end#1{% + \def\@tempa{#1}% + \ifx\@tempa\TX@% + \toks@\expandafter{\the\toks@\AddBeforeEndtabularx}% + \expandafter\TX@endtabularx + \else\toks@\expandafter + {\the\toks@\end{#1}}\expandafter\TX@get@body\fi} + +\def\AddBeforeEndtabularx{\hline} + +\newenvironment{@SheetTableBase}[3]{ +\rowcolors{2}{\sheetrowcolor}{white} +\tikzpicture \draw node \bgroup +\tabularx{\columnwidth}{#2} + \hline + \rowcolor{\sheetheadercolor} + \multicolumn{#1}{|l|}{\sheetheaderfont#3} \\ + \hline +}{ + %\hline +\endtabularx\egroup; +\endtikzpicture +\vspace{3mm} +} + +\def\defsheet#1#2#3{% +\newenvironment{#1}[1]{\@SheetTableBase{#2}{#3}{##1}}{\end@SheetTableBase}% +} + +\parindent=0pt + +\def\pagefooter{ +\begin{tikzpicture}[remember picture,overlay] +\draw [line width=1mm, fill=red] +(current page.south east) node [xshift=-.1in, yshift=.1in, anchor=south east, font={\rmfamily\normalsize}] {\pagefootertext}; +\end{tikzpicture} +} + +\def\pagefooter#1{ +\AddEverypageHook{ +\begin{tikzpicture}[remember picture,overlay] +\draw (current page.south east) node [xshift=-.1in, yshift=.1in, anchor=south east, font={\rmfamily\normalsize}] {#1}; +\end{tikzpicture} +}} + +\lstset{language=C,basicstyle=\small\ttfamily,breaklines=true} + +% Disable italics in math mode +\DeclareMathVersion{nmath} +\DeclareSymbolFont{nletters}{OT1}{cmss}{m}{n} +\SetSymbolFont{letters}{nmath}{OT1}{cmss}{m}{n} +\DeclareSymbolFont{noperators}{OT1}{cmss}{m}{n} +\SetSymbolFont{operators}{nmath}{OT1}{cmss}{m}{n} +\SetMathAlphabet\mathit{nmath}{OT1}{cmss}{m}{n} +\SetMathAlphabet\mathrm{nmath}{OT1}{cmss}{m}{n} +\mathversion{nmath} + +% Math symbols +\def\smul{\bar{\times}} +\def\umul{\times} +\def\sdiv{\bar{\div}} +\def\udiv{\div} +\def\smod{\bar{\%}} +\def\umod{\%} +\def\asr{\bar{\gg}} +\def\lsr{\gg} +\def\lsl{\ll} +\def\rol{\lll} +\def\ror{\ggg} +% Note: < and > doesn't render properly in math mode with current fonts +\def\slt{\bar{\text{<}}} +\def\ult{\text{<}} +\def\sge{\bar{\ge}} +\def\uge{\ge}