From 58e3a44fe0f7b84d5ff213ba0160e1d8b0cb3e55 Mon Sep 17 00:00:00 2001
From: Anders Olofsson <flynd@licq.org>
Date: Sun, 18 Oct 2015 22:17:28 +0200
Subject: [PATCH] cris: Multiple minor formatting and grammar fixes

---
 crisv10.tex | 20 ++++++++++----------
 crisv32.tex |  6 +++---
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/crisv10.tex b/crisv10.tex
index f6623be..7d902b8 100644
--- a/crisv10.tex
+++ b/crisv10.tex
@@ -31,7 +31,7 @@
 \defsheet{table-lXlN}{4}{|l X l N|}
 \defsheet{table-Xlllll}{6}{|X l l l l l|}
 
-\pagefooter{CRISv10 version 1 page \thepage}
+\pagefooter{CRISv10 version 2 page \thepage}
 
 \begin{document}
 \begin{multicols}{3}
@@ -51,11 +51,11 @@
 d		& Destination. Any addressing mode \\
 di		& Destination. Any addressing mode except register \\
 cc		& Condition code \\
-m		& Size modifier (b, w or d for byte, word or dword) \\
+m		& Size modifier (b, w, or d for byte, word, or dword) \\
 z		& Size modifier (b or w for byte or word) \\
 value$^{\pm}_{ }$	& Value is sign extended\\
 value$^{\emptyset}_{ }$	& Value is zero extended\\
-value$^{\{SU\}}_{ }$	& Signed or zero extend according to instruction name \\
+value$^{\{SU\}}_{ }$	& Sign or zero extended according to instruction name \\
 $\smul$ $\asr$	& Operation is signed \\
 {}****		& Flags NZVC are unchanged (--), affected (*) or cleared (0) \\
 \end{table-lX}
@@ -120,8 +120,8 @@
 MOVE.m		& rs, di		& di$^{ }_{m}$ = rs$^{ }_{m}$			& {--}{--}{--}{--}	& \\
 MOVE		& s, pr			& pr = s$^{ }_{sizeof(pr)}$			& {--}{--}{--}{--}	& I \\
 MOVE		& pr, d			& d$^{ }_{sizeof(pr)}$ = pr			& {--}{--}{--}{--}	& D,I \\
-MOVEM		& si, rd		& rd = si[0] \ldots R0 = si[4*d]		& {--}{--}{--}{--}	& \\
-MOVEM		& rs, di		& di[0] = rs \ldots di[4*s] = R0		& {--}{--}{--}{--}	& \\
+MOVEM		& si, rd		& rd = si[0] \ldots R0 = si[4$\umul$d]		& {--}{--}{--}{--}	& \\
+MOVEM		& rs, di		& di[0] = rs \ldots di[4$\umul$s] = R0		& {--}{--}{--}{--}	& \\
 MOVEQ		& i$^{ }_{6}$, rd	& rd = i$^{\pm}_{ }$				& **00	& \\
 MOV\{SU\}.z	& s, rd			& rd = s$^{\{SU\}}_{z}$				& **00	& \\
 \textit{POP}	& rd			& rd = [SP$+$]					& **00	& \\
@@ -219,7 +219,7 @@
 P	& Destination operand cannot be PC \\
 V	& Only available on some chip versions \\
 X	& C flag is added/subtracted if X flag is set \\
-+(1..3)	& Execution time is increased by 1..3 cycles \\
++1,+2,+3	& Execution time is increased by 1, 2, or 3 cycles \\
 \end{table-lX}
 %
 \begin{table-lXlN}{Condition Codes}
@@ -259,13 +259,13 @@
 \begin{table-Xlllll}{Version Specific Features}
 DMA integrated in CPU				& 4	&	&	&	& \\
 EXT condition code				& 4	&	&	&	& \\
-Jump with context (JBRC/JIRC/JSRC)		&	& 8	& 10	& 13	& 17 \\
+Jump with context (JBRC/JIRC/JSRC instructions)	&	& 8	& 10	& 13	& 17 \\
 SWAP instruction				&	& 8	& 10	& 13	& 17 \\
-Multiplication (MULS/MULU)			&	&	& 10	&	& 17 \\
-Read/write CPU state (RBF/SBFS)			&	&	& 10	& 13	& 17 \\
+Multiplication (MULS/MULU instructions)		&	&	& 10	&	& 17 \\
+Read/write CPU state (RBF/SBFS instructions)	&	&	& 10	& 13	& 17 \\
 Integrity check (P flag, WF condition)		&	&	& 10	& 13	& 17 \\
 User mode (U flag)				&	&	& 10	&	& \\
-JMPU instruction, MOF/BAR/USP registers		&	&	& 10	& 13	& 17 \\
+JMPU instruction, (MOF/BAR/USP registers)	&	&	& 10	& 13	& 17 \\
 ADDC instruction				&	&	&	& 13	& 17 \\
 \end{table-Xlllll}
 %
diff --git a/crisv32.tex b/crisv32.tex
index 98dbf2b..41ed3c8 100644
--- a/crisv32.tex
+++ b/crisv32.tex
@@ -31,7 +31,7 @@
 \defsheet{table-llX}{3}{|l l X|}
 \defsheet{table-llXN}{4}{|l l X N|}
 
-\pagefooter{CRISv32 version 1 page \thepage}
+\pagefooter{CRISv32 version 2 page \thepage}
 
 \begin{document}
 \begin{multicols}{3}
@@ -117,8 +117,8 @@
 MOVE		& pr, d			& d$^{ }_{sizeof(pr)}$ = pr			& {--}{--}{--}{--}	& \\
 MOVE		& rs, sr		& SRS.sr = rs					& {--}{--}{--}{--}	& M \\
 MOVE		& sr, rd		& rd = SRS.sr					& {--}{--}{--}{--}	& \\
-MOVEM		& rs, di		& di[0] = R0 \ldots di[4*s] = rs		& {--}{--}{--}{--}	& \\
-MOVEM		& sm, rd		& R0 = sm[0] \ldots rd = sm[4*d]		& {--}{--}{--}{--}	& \\
+MOVEM		& rs, di		& di[0] = R0 \ldots di[4$\umul$s] = rs		& {--}{--}{--}{--}	& \\
+MOVEM		& sm, rd		& R0 = sm[0] \ldots rd = sm[4$\umul$d]		& {--}{--}{--}{--}	& \\
 MOVEQ		& i$^{ }_{6}$, rd	& rd = i$^{\pm}_{ }$				& {--}{--}{--}{--}	& \\
 MOV\{SU\}.z	& s, rd			& rd = s$^{\{SU\}}_{z}$				& **{--}{--}	& \\
 Scc		& rd			& rd = (cc ? 1 : 0)				& {--}{--}{--}{--}	& \\