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parent 84ff0e0
author Thea Aarrestad <[email protected]> 1620032180 +0200 committer Sioni Summers <[email protected]> 1636569147 +0100 First version of CNN notebook Adding QKeras model and start of hls4ml part for cnn tutorial removing outputs Changing to hlsm4l master and updating notebook Switching on bias in QConv2DBN first autoq draft updating n trials for autoq adding vivado reports for baseline Adding vivado_hls.app moving .app to reference dir Adding AutoQ bonus exercise Adding hls projects moving to hls4ml master fixing AutoQ part changing description of CNN implementation Fixing bug with non-editable cells and missing layer when loading models
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‎environment.yml

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name: hls4ml-tutorial-0.5.0
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name: hls4ml-tutorial
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channels:
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- conda-forge
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dependencies:
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- pip:
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- jupyter
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- tensorflow==2.3.1
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- hls4ml[profiling]==0.5.0
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- tensorflow_datasets
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- git+https://github.com/fastmachinelearning/hls4ml.git#egg=hls4ml[profiling]
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- git+https://github.com/google/qkeras.git#egg=qkeras
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- scikit-learn
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- git+https://github.com/thesps/conifer.git

‎images/conv2d_animation.gif

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‎images/test.png

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‎part6_cnns.ipynb

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‎pruned_cnn/myproject_prj/solution1/syn/report/myproject_csynth.rpt

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‎pruned_cnn/vivado_synth.rpt

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Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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--------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
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| Date : Mon Jun 28 13:59:34 2021
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| Host : geonosis.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
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| Command : report_utilization -file vivado_synth.rpt
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| Design : myproject
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| Device : xcu250figd2104-2L
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| Design State : Synthesized
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--------------------------------------------------------------------------------------
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Utilization Design Information
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Table of Contents
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-----------------
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1. CLB Logic
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1.1 Summary of Registers by Type
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2. BLOCKRAM
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3. ARITHMETIC
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4. I/O
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5. CLOCK
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6. ADVANCED
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7. CONFIGURATION
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8. Primitives
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9. Black Boxes
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10. Instantiated Netlists
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11. SLR Connectivity
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12. SLR Connectivity Matrix
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13. SLR CLB Logic and Dedicated Block Utilization
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14. SLR IO Utilization
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1. CLB Logic
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------------
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+----------------------------+--------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------------+--------+-------+-----------+-------+
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| CLB LUTs* | 123948 | 0 | 1728000 | 7.17 |
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| LUT as Logic | 120268 | 0 | 1728000 | 6.96 |
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| LUT as Memory | 3680 | 0 | 791040 | 0.47 |
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| LUT as Distributed RAM | 0 | 0 | | |
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| LUT as Shift Register | 3680 | 0 | | |
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| CLB Registers | 43435 | 0 | 3456000 | 1.26 |
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| Register as Flip Flop | 43435 | 0 | 3456000 | 1.26 |
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| Register as Latch | 0 | 0 | 3456000 | 0.00 |
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| CARRY8 | 13270 | 0 | 216000 | 6.14 |
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| F7 Muxes | 256 | 0 | 864000 | 0.03 |
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| F8 Muxes | 0 | 0 | 432000 | 0.00 |
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| F9 Muxes | 0 | 0 | 216000 | 0.00 |
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+----------------------------+--------+-------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 0 | Yes | - | Set |
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| 0 | Yes | - | Reset |
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| 1069 | Yes | Set | - |
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| 42366 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. BLOCKRAM
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-----------
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+-------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------------+------+-------+-----------+-------+
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| Block RAM Tile | 42 | 0 | 2688 | 1.56 |
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| RAMB36/FIFO* | 0 | 0 | 2688 | 0.00 |
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| RAMB18 | 84 | 0 | 5376 | 1.56 |
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| RAMB18E2 only | 84 | | | |
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| URAM | 0 | 0 | 1280 | 0.00 |
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+-------------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
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3. ARITHMETIC
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-------------
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+----------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------+------+-------+-----------+-------+
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| DSPs | 5386 | 0 | 12288 | 43.83 |
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| DSP48E2 only | 5386 | | | |
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+----------------+------+-------+-----------+-------+
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4. I/O
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------
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+------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| Bonded IOB | 274 | 0 | 676 | 40.53 |
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+------------+------+-------+-----------+-------+
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5. CLOCK
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--------
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+----------------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+----------------------+------+-------+-----------+-------+
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| GLOBAL CLOCK BUFFERs | 1 | 0 | 1344 | 0.07 |
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| BUFGCE | 1 | 0 | 384 | 0.26 |
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| BUFGCE_DIV | 0 | 0 | 64 | 0.00 |
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| BUFG_GT | 0 | 0 | 768 | 0.00 |
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| BUFGCTRL* | 0 | 0 | 128 | 0.00 |
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| PLL | 0 | 0 | 32 | 0.00 |
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| MMCM | 0 | 0 | 16 | 0.00 |
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+----------------------+------+-------+-----------+-------+
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* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
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6. ADVANCED
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-----------
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+-----------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------------+------+-------+-----------+-------+
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| CMACE4 | 0 | 0 | 12 | 0.00 |
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| GTYE4_CHANNEL | 0 | 0 | 24 | 0.00 |
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| GTYE4_COMMON | 0 | 0 | 6 | 0.00 |
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| ILKNE4 | 0 | 0 | 8 | 0.00 |
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| OBUFDS_GTE4 | 0 | 0 | 12 | 0.00 |
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| OBUFDS_GTE4_ADV | 0 | 0 | 12 | 0.00 |
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| PCIE40E4 | 0 | 0 | 4 | 0.00 |
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| SYSMONE4 | 0 | 0 | 4 | 0.00 |
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+-----------------+------+-------+-----------+-------+
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7. CONFIGURATION
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----------------
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+-------------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2 | 0 | 0 | 16 | 0.00 |
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| DNA_PORTE2 | 0 | 0 | 4 | 0.00 |
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| EFUSE_USR | 0 | 0 | 4 | 0.00 |
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| FRAME_ECCE4 | 0 | 0 | 4 | 0.00 |
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| ICAPE3 | 0 | 0 | 8 | 0.00 |
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| MASTER_JTAG | 0 | 0 | 4 | 0.00 |
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| STARTUPE3 | 0 | 0 | 4 | 0.00 |
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+-------------+------+-------+-----------+-------+
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8. Primitives
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-------------
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+----------+-------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+-------+---------------------+
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| LUT2 | 52029 | CLB |
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| FDRE | 42366 | Register |
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| LUT3 | 41635 | CLB |
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| LUT4 | 40010 | CLB |
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| CARRY8 | 13270 | CLB |
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| LUT6 | 12631 | CLB |
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| LUT5 | 10697 | CLB |
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| DSP48E2 | 5386 | Arithmetic |
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| LUT1 | 4899 | CLB |
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| SRL16E | 2816 | CLB |
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| FDSE | 1069 | Register |
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| SRLC32E | 864 | CLB |
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| MUXF7 | 256 | CLB |
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| OBUF | 210 | I/O |
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| RAMB18E2 | 84 | Block Ram |
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| INBUF | 64 | I/O |
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| IBUFCTRL | 64 | Others |
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| BUFGCE | 1 | Clock |
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+----------+-------+---------------------+
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9. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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10. Instantiated Netlists
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-------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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11. SLR Connectivity
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--------------------
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+----------------------------------+------+-------+-----------+-------+
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| | Used | Fixed | Available | Util% |
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+----------------------------------+------+-------+-----------+-------+
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| SLR3 <-> SLR2 | 0 | | 23040 | 0.00 |
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| SLR2 -> SLR3 | 0 | | | 0.00 |
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| Using TX_REG only | 0 | 0 | | |
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| Using RX_REG only | 0 | 0 | | |
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| Using Both TX_REG and RX_REG | 0 | 0 | | |
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| SLR3 -> SLR2 | 0 | | | 0.00 |
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| Using TX_REG only | 0 | 0 | | |
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| Using RX_REG only | 0 | 0 | | |
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| Using Both TX_REG and RX_REG | 0 | 0 | | |
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| SLR2 <-> SLR1 | 0 | | 23040 | 0.00 |
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| SLR1 -> SLR2 | 0 | | | 0.00 |
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| Using TX_REG only | 0 | 0 | | |
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| Using RX_REG only | 0 | 0 | | |
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| Using Both TX_REG and RX_REG | 0 | 0 | | |
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| SLR2 -> SLR1 | 0 | | | 0.00 |
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| Using TX_REG only | 0 | 0 | | |
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| Using RX_REG only | 0 | 0 | | |
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| Using Both TX_REG and RX_REG | 0 | 0 | | |
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| SLR1 <-> SLR0 | 0 | | 23040 | 0.00 |
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| SLR0 -> SLR1 | 0 | | | 0.00 |
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| Using TX_REG only | 0 | 0 | | |
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| Using RX_REG only | 0 | 0 | | |
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| Using Both TX_REG and RX_REG | 0 | 0 | | |
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| SLR1 -> SLR0 | 0 | | | 0.00 |
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| Using TX_REG only | 0 | 0 | | |
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| Using RX_REG only | 0 | 0 | | |
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| Using Both TX_REG and RX_REG | 0 | 0 | | |
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+----------------------------------+------+-------+-----------+-------+
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| Total SLLs Used | 0 | | | |
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+----------------------------------+------+-------+-----------+-------+
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12. SLR Connectivity Matrix
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---------------------------
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+-----------+------+------+------+------+
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| FROM \ TO | SLR3 | SLR2 | SLR1 | SLR0 |
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+-----------+------+------+------+------+
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| SLR3 | 0 | 0 | 0 | 0 |
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| SLR2 | 0 | 0 | 0 | 0 |
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| SLR1 | 0 | 0 | 0 | 0 |
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| SLR0 | 0 | 0 | 0 | 0 |
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+-----------+------+------+------+------+
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13. SLR CLB Logic and Dedicated Block Utilization
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-------------------------------------------------
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+----------------------------+------+------+------+------+--------+--------+--------+--------+
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| Site Type | SLR0 | SLR1 | SLR2 | SLR3 | SLR0 % | SLR1 % | SLR2 % | SLR3 % |
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+----------------------------+------+------+------+------+--------+--------+--------+--------+
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| CLB | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| CLBL | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| CLBM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| CLB LUTs | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| LUT as Logic | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| LUT as Memory | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| LUT as Distributed RAM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| LUT as Shift Register | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| CLB Registers | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| CARRY8 | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| F7 Muxes | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| F8 Muxes | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| F9 Muxes | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| Block RAM Tile | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| RAMB36/FIFO | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| RAMB18 | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| URAM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| DSPs | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| PLL | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| MMCM | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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| Unique Control Sets | 0 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 | 0.00 |
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+----------------------------+------+------+------+------+--------+--------+--------+--------+
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* Note: Available Control Sets based on CLB Registers / 8
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14. SLR IO Utilization
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----------------------
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+-----------+-----------+---------+------------+----------+------------+----------+-----+
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| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
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+-----------+-----------+---------+------------+----------+------------+----------+-----+
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| SLR3 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
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| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
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| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
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| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
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+-----------+-----------+---------+------------+----------+------------+----------+-----+
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| Total | 0 | | 0 | | 0 | | 0 |
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+-----------+-----------+---------+------------+----------+------------+----------+-----+
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