@@ -77,7 +77,10 @@ enum FlashBootstrap {
77
77
/* Number of watchpoints available */ \
78
78
uint32_t num_wps ; \
79
79
struct watchpoint * * hw_wps ;\
80
- enum FlashBootstrap flashBootstrap ; //0 - don't care, 1 - TMS low, 2 - TMS high
80
+ /* 0 - don't care, 1 - TMS low, 2 - TMS high */ \
81
+ enum FlashBootstrap flashBootstrap ; \
82
+ /* Base directory for semihosting I/O */ \
83
+ char * semihost_basedir ;
81
84
82
85
struct esp108_common {
83
86
// struct jtag_tap *tap;
@@ -181,30 +184,30 @@ struct xtensa_algorithm {
181
184
#define XT_REG_A3 (esp108_regs[XT_REG_IDX_AR3].reg_num)
182
185
#define XT_REG_A4 (esp108_regs[XT_REG_IDX_AR4].reg_num)
183
186
184
- #define _XT_INS_FORMAT_RSR (OPCODE ,SR ,T ) (OPCODE \
185
- | ((SR & 0xFF) << 8) \
186
- | ((T & 0x0F) << 4))
187
+ #define _XT_INS_FORMAT_RSR (OPCODE ,SR ,T ) (( OPCODE) \
188
+ | (((SR) & 0xFF) << 8) \
189
+ | (((T) & 0x0F) << 4))
187
190
188
- #define _XT_INS_FORMAT_RRR (OPCODE ,ST ,R ) (OPCODE \
189
- | ((ST & 0xFF) << 4) \
190
- | ((R & 0x0F) << 12))
191
+ #define _XT_INS_FORMAT_RRR (OPCODE ,ST ,R ) (( OPCODE) \
192
+ | (((ST) & 0xFF) << 4) \
193
+ | (((R) & 0x0F) << 12))
191
194
192
- #define _XT_INS_FORMAT_RRRN (OPCODE ,S , T ,IMM4 ) (OPCODE \
193
- | ((T & 0x0F) << 4) \
194
- | ((S & 0x0F) << 8) \
195
- | ((IMM4 & 0x0F) << 12))
195
+ #define _XT_INS_FORMAT_RRRN (OPCODE ,S , T ,IMM4 ) (( OPCODE) \
196
+ | (((T) & 0x0F) << 4) \
197
+ | (((S) & 0x0F) << 8) \
198
+ | ((( IMM4) & 0x0F) << 12))
196
199
197
- #define _XT_INS_FORMAT_RRI8 (OPCODE ,R ,S ,T ,IMM8 ) (OPCODE \
198
- | ((IMM8 & 0xFF) << 16) \
199
- | ((R & 0x0F) << 12 ) \
200
- | ((S & 0x0F) << 8 ) \
201
- | ((T & 0x0F) << 4 ))
200
+ #define _XT_INS_FORMAT_RRI8 (OPCODE ,R ,S ,T ,IMM8 ) (( OPCODE) \
201
+ | ((( IMM8) & 0xFF) << 16) \
202
+ | (((R) & 0x0F) << 12 ) \
203
+ | (((S) & 0x0F) << 8 ) \
204
+ | (((T) & 0x0F) << 4 ))
202
205
203
- #define _XT_INS_FORMAT_RRI4 (OPCODE ,IMM4 ,R ,S ,T ) (OPCODE \
204
- | ((IMM4 & 0x0F) << 20) \
205
- | ((R & 0x0F) << 12) \
206
- | ((S & 0x0F) << 8) \
207
- | ((T & 0x0F) << 4))
206
+ #define _XT_INS_FORMAT_RRI4 (OPCODE ,IMM4 ,R ,S ,T ) (( OPCODE) \
207
+ | ((( IMM4) & 0x0F) << 20) \
208
+ | (((R) & 0x0F) << 12) \
209
+ | (((S) & 0x0F) << 8) \
210
+ | (((T) & 0x0F) << 4))
208
211
209
212
210
213
/* Xtensa processor instruction opcodes
@@ -254,7 +257,7 @@ struct xtensa_algorithm {
254
257
#define XT_INS_WFR (FR ,T ) _XT_INS_FORMAT_RRR(0xFA0000,((FR<<4)|0x5),T)
255
258
256
259
/* 32-bit break */
257
- #define XT_INS_BREAK (IMM1 ,IMM2 ) _XT_INS_FORMAT_RRR(0x004000, IMM1, IMM2)
260
+ #define XT_INS_BREAK (IMM1 ,IMM2 ) _XT_INS_FORMAT_RRR(0x000000,(( IMM1&0x0F)<<4)|( IMM2&0x0F),0x4 )
258
261
/* 16-bit break */
259
262
#define XT_INS_BREAKN (IMM4 ) _XT_INS_FORMAT_RRRN(0x00000D,IMM4,0x2,0xF)
260
263
0 commit comments