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target/esp32c6-h2: fix reset sequence
1 parent f1d5859 commit 031dc4d

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3 files changed

+10
-8
lines changed

3 files changed

+10
-8
lines changed

tcl/target/esp32c6.cfg

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -65,17 +65,18 @@ proc esp32c6_soc_reset { } {
6565

6666
# clear dmactive to clear sbbusy otherwise debug module gets stuck
6767
riscv dmi_write 0x10 0
68-
riscv dmi_write 0x10 1
69-
halt
68+
riscv dmi_write 0x10 0x40000001
69+
# Here debugger reads dmstatus as 0xc03a2
7070

7171
# Wait for the reset to happen
7272
sleep 10
7373
poll
74+
# Here debugger reads dmstatus as 0x3a2
7475

7576
# Disable the watchdogs again
7677
esp32c6_wdt_disable
7778

78-
# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
79+
# Here debugger reads anyhalted and allhalted bits as set (0x3a2)
7980
# We will clean allhalted state by resuming the core.
8081
riscv dmi_write 0x10 0x40000001
8182

tcl/target/esp32h2.cfg

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -65,17 +65,18 @@ proc esp32h2_soc_reset { } {
6565

6666
# clear dmactive to clear sbbusy otherwise debug module gets stuck
6767
riscv dmi_write 0x10 0
68-
riscv dmi_write 0x10 1
69-
halt
68+
riscv dmi_write 0x10 0x40000001
69+
# Here debugger reads dmstatus as 0xc03a2
7070

7171
# Wait for the reset to happen
7272
sleep 10
7373
poll
74+
# Here debugger reads dmstatus as 0x3a2
7475

7576
# Disable the watchdogs again
7677
esp32h2_wdt_disable
7778

78-
# Here debugger reads allresumeack and allhalted bits as set (0x330a2)
79+
# Here debugger reads anyhalted and allhalted bits as set (0x3a2)
7980
# We will clean allhalted state by resuming the core.
8081
riscv dmi_write 0x10 0x40000001
8182

testing/esp/test_apptrace.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,8 +90,8 @@ def test_apptrace_reset(self):
9090
trace_file.close()
9191
trace_src = 'file://%s' % trace_file_name
9292
reader = reader_create(trace_src, 1.0)
93-
# 0 ms poll period, stop when 800 bytes are received or due to 10 s timeout
94-
self.oocd.apptrace_start("%s 0 800 10" % trace_src)
93+
# 10 ms poll period, stop when 800 bytes are received or due to 10 s timeout
94+
self.oocd.apptrace_start("%s 10 800 10" % trace_src)
9595
self.resume_exec()
9696
sleep(1) # let it works some time
9797
self.stop_exec()

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