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jessebrahamjessebraham
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New package releases (#173)
* Use latest published `svd2rust` * Bump version numbers for relevant packages
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‎esp32/Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
[package]
22
name = "esp32"
3-
version = "0.27.0"
3+
version = "0.28.0"
44
edition = "2021"
55
rust-version = "1.67"
66
description = "Peripheral access crate for the ESP32"

‎esp32/src/lib.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.31.1 (c133a7b 2023-11-29))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
1+
#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.31.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
22
#![allow(non_camel_case_types)]
33
#![allow(non_snake_case)]
44
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]

‎esp32/src/rmt/int_clr.rs

+8-8
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
#[doc = "Register `INT_CLR` writer"]
22
pub type W = crate::W<INT_CLR_SPEC>;
3-
#[doc = "Field `CH_TX_END[0-7]` writer - Set this bit to clear the rmt_ch%s_rx_end_int_raw.."]
3+
#[doc = "Field `CH_TX_END(0-7)` writer - Set this bit to clear the rmt_ch%s_rx_end_int_raw.."]
44
pub type CH_TX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
5-
#[doc = "Field `CH_RX_END[0-7]` writer - Set this bit to clear the rmt_ch%s_tx_end_int_raw."]
5+
#[doc = "Field `CH_RX_END(0-7)` writer - Set this bit to clear the rmt_ch%s_tx_end_int_raw."]
66
pub type CH_RX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
7-
#[doc = "Field `CH_ERR[0-7]` writer - Set this bit to clear the rmt_ch%s_err_int_raw."]
7+
#[doc = "Field `CH_ERR(0-7)` writer - Set this bit to clear the rmt_ch%s_err_int_raw."]
88
pub type CH_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
9-
#[doc = "Field `CH_TX_THR_EVENT[0-7]` writer - Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt."]
9+
#[doc = "Field `CH_TX_THR_EVENT(0-7)` writer - Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt."]
1010
pub type CH_TX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
1111
#[cfg(feature = "impl-register-debug")]
1212
impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
@@ -15,7 +15,7 @@ impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
1515
}
1616
}
1717
impl W {
18-
#[doc = "Set this bit to clear the rmt_ch[0-7]_rx_end_int_raw.."]
18+
#[doc = "Set this bit to clear the rmt_ch(0-7)_rx_end_int_raw.."]
1919
#[doc = ""]
2020
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field"]
2121
#[inline(always)]
@@ -73,7 +73,7 @@ impl W {
7373
pub fn ch7_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
7474
CH_TX_END_W::new(self, 21)
7575
}
76-
#[doc = "Set this bit to clear the rmt_ch[0-7]_tx_end_int_raw."]
76+
#[doc = "Set this bit to clear the rmt_ch(0-7)_tx_end_int_raw."]
7777
#[doc = ""]
7878
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field"]
7979
#[inline(always)]
@@ -131,7 +131,7 @@ impl W {
131131
pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
132132
CH_RX_END_W::new(self, 22)
133133
}
134-
#[doc = "Set this bit to clear the rmt_ch[0-7]_err_int_raw."]
134+
#[doc = "Set this bit to clear the rmt_ch(0-7)_err_int_raw."]
135135
#[doc = ""]
136136
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field"]
137137
#[inline(always)]
@@ -189,7 +189,7 @@ impl W {
189189
pub fn ch7_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
190190
CH_ERR_W::new(self, 23)
191191
}
192-
#[doc = "Set this bit to clear the rmt_ch[0-7]_tx_thr_event_int_raw interrupt."]
192+
#[doc = "Set this bit to clear the rmt_ch(0-7)_tx_thr_event_int_raw interrupt."]
193193
#[doc = ""]
194194
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field"]
195195
#[inline(always)]

‎esp32/src/rmt/int_ena.rs

+20-20
Original file line numberDiff line numberDiff line change
@@ -2,24 +2,24 @@
22
pub type R = crate::R<INT_ENA_SPEC>;
33
#[doc = "Register `INT_ENA` writer"]
44
pub type W = crate::W<INT_ENA_SPEC>;
5-
#[doc = "Field `CH_TX_END[0-7]` reader - Set this bit to enable rmt_ch%s_tx_end_int_st."]
5+
#[doc = "Field `CH_TX_END(0-7)` reader - Set this bit to enable rmt_ch%s_tx_end_int_st."]
66
pub type CH_TX_END_R = crate::BitReader;
7-
#[doc = "Field `CH_TX_END[0-7]` writer - Set this bit to enable rmt_ch%s_tx_end_int_st."]
7+
#[doc = "Field `CH_TX_END(0-7)` writer - Set this bit to enable rmt_ch%s_tx_end_int_st."]
88
pub type CH_TX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9-
#[doc = "Field `CH_RX_END[0-7]` reader - Set this bit to enable rmt_ch%s_rx_end_int_st."]
9+
#[doc = "Field `CH_RX_END(0-7)` reader - Set this bit to enable rmt_ch%s_rx_end_int_st."]
1010
pub type CH_RX_END_R = crate::BitReader;
11-
#[doc = "Field `CH_RX_END[0-7]` writer - Set this bit to enable rmt_ch%s_rx_end_int_st."]
11+
#[doc = "Field `CH_RX_END(0-7)` writer - Set this bit to enable rmt_ch%s_rx_end_int_st."]
1212
pub type CH_RX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13-
#[doc = "Field `CH_ERR[0-7]` reader - Set this bit to enable rmt_ch%s_err_int_st."]
13+
#[doc = "Field `CH_ERR(0-7)` reader - Set this bit to enable rmt_ch%s_err_int_st."]
1414
pub type CH_ERR_R = crate::BitReader;
15-
#[doc = "Field `CH_ERR[0-7]` writer - Set this bit to enable rmt_ch%s_err_int_st."]
15+
#[doc = "Field `CH_ERR(0-7)` writer - Set this bit to enable rmt_ch%s_err_int_st."]
1616
pub type CH_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17-
#[doc = "Field `CH_TX_THR_EVENT[0-7]` reader - Set this bit to enable rmt_ch%s_tx_thr_event_int_st."]
17+
#[doc = "Field `CH_TX_THR_EVENT(0-7)` reader - Set this bit to enable rmt_ch%s_tx_thr_event_int_st."]
1818
pub type CH_TX_THR_EVENT_R = crate::BitReader;
19-
#[doc = "Field `CH_TX_THR_EVENT[0-7]` writer - Set this bit to enable rmt_ch%s_tx_thr_event_int_st."]
19+
#[doc = "Field `CH_TX_THR_EVENT(0-7)` writer - Set this bit to enable rmt_ch%s_tx_thr_event_int_st."]
2020
pub type CH_TX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
2121
impl R {
22-
#[doc = "Set this bit to enable rmt_ch[0-7]_tx_end_int_st."]
22+
#[doc = "Set this bit to enable rmt_ch(0-7)_tx_end_int_st."]
2323
#[doc = ""]
2424
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field"]
2525
#[inline(always)]
@@ -29,7 +29,7 @@ impl R {
2929
CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0)
3030
}
3131
#[doc = "Iterator for array of:"]
32-
#[doc = "Set this bit to enable rmt_ch[0-7]_tx_end_int_st."]
32+
#[doc = "Set this bit to enable rmt_ch(0-7)_tx_end_int_st."]
3333
#[inline(always)]
3434
pub fn ch_tx_end_iter(&self) -> impl Iterator<Item = CH_TX_END_R> + '_ {
3535
(0..8).map(|n| CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0))
@@ -74,7 +74,7 @@ impl R {
7474
pub fn ch7_tx_end(&self) -> CH_TX_END_R {
7575
CH_TX_END_R::new(((self.bits >> 21) & 1) != 0)
7676
}
77-
#[doc = "Set this bit to enable rmt_ch[0-7]_rx_end_int_st."]
77+
#[doc = "Set this bit to enable rmt_ch(0-7)_rx_end_int_st."]
7878
#[doc = ""]
7979
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field"]
8080
#[inline(always)]
@@ -84,7 +84,7 @@ impl R {
8484
CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0)
8585
}
8686
#[doc = "Iterator for array of:"]
87-
#[doc = "Set this bit to enable rmt_ch[0-7]_rx_end_int_st."]
87+
#[doc = "Set this bit to enable rmt_ch(0-7)_rx_end_int_st."]
8888
#[inline(always)]
8989
pub fn ch_rx_end_iter(&self) -> impl Iterator<Item = CH_RX_END_R> + '_ {
9090
(0..8).map(|n| CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0))
@@ -129,7 +129,7 @@ impl R {
129129
pub fn ch7_rx_end(&self) -> CH_RX_END_R {
130130
CH_RX_END_R::new(((self.bits >> 22) & 1) != 0)
131131
}
132-
#[doc = "Set this bit to enable rmt_ch[0-7]_err_int_st."]
132+
#[doc = "Set this bit to enable rmt_ch(0-7)_err_int_st."]
133133
#[doc = ""]
134134
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field"]
135135
#[inline(always)]
@@ -139,7 +139,7 @@ impl R {
139139
CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0)
140140
}
141141
#[doc = "Iterator for array of:"]
142-
#[doc = "Set this bit to enable rmt_ch[0-7]_err_int_st."]
142+
#[doc = "Set this bit to enable rmt_ch(0-7)_err_int_st."]
143143
#[inline(always)]
144144
pub fn ch_err_iter(&self) -> impl Iterator<Item = CH_ERR_R> + '_ {
145145
(0..8).map(|n| CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0))
@@ -184,7 +184,7 @@ impl R {
184184
pub fn ch7_err(&self) -> CH_ERR_R {
185185
CH_ERR_R::new(((self.bits >> 23) & 1) != 0)
186186
}
187-
#[doc = "Set this bit to enable rmt_ch[0-7]_tx_thr_event_int_st."]
187+
#[doc = "Set this bit to enable rmt_ch(0-7)_tx_thr_event_int_st."]
188188
#[doc = ""]
189189
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field"]
190190
#[inline(always)]
@@ -194,7 +194,7 @@ impl R {
194194
CH_TX_THR_EVENT_R::new(((self.bits >> (n + 24)) & 1) != 0)
195195
}
196196
#[doc = "Iterator for array of:"]
197-
#[doc = "Set this bit to enable rmt_ch[0-7]_tx_thr_event_int_st."]
197+
#[doc = "Set this bit to enable rmt_ch(0-7)_tx_thr_event_int_st."]
198198
#[inline(always)]
199199
pub fn ch_tx_thr_event_iter(&self) -> impl Iterator<Item = CH_TX_THR_EVENT_R> + '_ {
200200
(0..8).map(|n| CH_TX_THR_EVENT_R::new(((self.bits >> (n + 24)) & 1) != 0))
@@ -310,7 +310,7 @@ impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
310310
}
311311
}
312312
impl W {
313-
#[doc = "Set this bit to enable rmt_ch[0-7]_tx_end_int_st."]
313+
#[doc = "Set this bit to enable rmt_ch(0-7)_tx_end_int_st."]
314314
#[doc = ""]
315315
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field"]
316316
#[inline(always)]
@@ -368,7 +368,7 @@ impl W {
368368
pub fn ch7_tx_end(&mut self) -> CH_TX_END_W<INT_ENA_SPEC> {
369369
CH_TX_END_W::new(self, 21)
370370
}
371-
#[doc = "Set this bit to enable rmt_ch[0-7]_rx_end_int_st."]
371+
#[doc = "Set this bit to enable rmt_ch(0-7)_rx_end_int_st."]
372372
#[doc = ""]
373373
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field"]
374374
#[inline(always)]
@@ -426,7 +426,7 @@ impl W {
426426
pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_ENA_SPEC> {
427427
CH_RX_END_W::new(self, 22)
428428
}
429-
#[doc = "Set this bit to enable rmt_ch[0-7]_err_int_st."]
429+
#[doc = "Set this bit to enable rmt_ch(0-7)_err_int_st."]
430430
#[doc = ""]
431431
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field"]
432432
#[inline(always)]
@@ -484,7 +484,7 @@ impl W {
484484
pub fn ch7_err(&mut self) -> CH_ERR_W<INT_ENA_SPEC> {
485485
CH_ERR_W::new(self, 23)
486486
}
487-
#[doc = "Set this bit to enable rmt_ch[0-7]_tx_thr_event_int_st."]
487+
#[doc = "Set this bit to enable rmt_ch(0-7)_tx_thr_event_int_st."]
488488
#[doc = ""]
489489
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field"]
490490
#[inline(always)]

‎esp32/src/rmt/int_raw.rs

+12-12
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
11
#[doc = "Register `INT_RAW` reader"]
22
pub type R = crate::R<INT_RAW_SPEC>;
3-
#[doc = "Field `CH_TX_END[0-7]` reader - The interrupt raw bit for channel %s turns to high level when the transmit process is done."]
3+
#[doc = "Field `CH_TX_END(0-7)` reader - The interrupt raw bit for channel %s turns to high level when the transmit process is done."]
44
pub type CH_TX_END_R = crate::BitReader;
5-
#[doc = "Field `CH_RX_END[0-7]` reader - The interrupt raw bit for channel %s turns to high level when the receive process is done."]
5+
#[doc = "Field `CH_RX_END(0-7)` reader - The interrupt raw bit for channel %s turns to high level when the receive process is done."]
66
pub type CH_RX_END_R = crate::BitReader;
7-
#[doc = "Field `CH_ERR[0-7]` reader - The interrupt raw bit for channel %s turns to high level when channle %s detects some errors."]
7+
#[doc = "Field `CH_ERR(0-7)` reader - The interrupt raw bit for channel %s turns to high level when channle %s detects some errors."]
88
pub type CH_ERR_R = crate::BitReader;
9-
#[doc = "Field `CH_TX_THR_EVENT[0-7]` reader - The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas."]
9+
#[doc = "Field `CH_TX_THR_EVENT(0-7)` reader - The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas."]
1010
pub type CH_TX_THR_EVENT_R = crate::BitReader;
1111
impl R {
12-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when the transmit process is done."]
12+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when the transmit process is done."]
1313
#[doc = ""]
1414
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field"]
1515
#[inline(always)]
@@ -19,7 +19,7 @@ impl R {
1919
CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0)
2020
}
2121
#[doc = "Iterator for array of:"]
22-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when the transmit process is done."]
22+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when the transmit process is done."]
2323
#[inline(always)]
2424
pub fn ch_tx_end_iter(&self) -> impl Iterator<Item = CH_TX_END_R> + '_ {
2525
(0..8).map(|n| CH_TX_END_R::new(((self.bits >> (n * 3)) & 1) != 0))
@@ -64,7 +64,7 @@ impl R {
6464
pub fn ch7_tx_end(&self) -> CH_TX_END_R {
6565
CH_TX_END_R::new(((self.bits >> 21) & 1) != 0)
6666
}
67-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when the receive process is done."]
67+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when the receive process is done."]
6868
#[doc = ""]
6969
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field"]
7070
#[inline(always)]
@@ -74,7 +74,7 @@ impl R {
7474
CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0)
7575
}
7676
#[doc = "Iterator for array of:"]
77-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when the receive process is done."]
77+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when the receive process is done."]
7878
#[inline(always)]
7979
pub fn ch_rx_end_iter(&self) -> impl Iterator<Item = CH_RX_END_R> + '_ {
8080
(0..8).map(|n| CH_RX_END_R::new(((self.bits >> (n * 3 + 1)) & 1) != 0))
@@ -119,7 +119,7 @@ impl R {
119119
pub fn ch7_rx_end(&self) -> CH_RX_END_R {
120120
CH_RX_END_R::new(((self.bits >> 22) & 1) != 0)
121121
}
122-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when channle [0-7] detects some errors."]
122+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when channle (0-7) detects some errors."]
123123
#[doc = ""]
124124
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field"]
125125
#[inline(always)]
@@ -129,7 +129,7 @@ impl R {
129129
CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0)
130130
}
131131
#[doc = "Iterator for array of:"]
132-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when channle [0-7] detects some errors."]
132+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when channle (0-7) detects some errors."]
133133
#[inline(always)]
134134
pub fn ch_err_iter(&self) -> impl Iterator<Item = CH_ERR_R> + '_ {
135135
(0..8).map(|n| CH_ERR_R::new(((self.bits >> (n * 3 + 2)) & 1) != 0))
@@ -174,7 +174,7 @@ impl R {
174174
pub fn ch7_err(&self) -> CH_ERR_R {
175175
CH_ERR_R::new(((self.bits >> 23) & 1) != 0)
176176
}
177-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when transmitter in channle[0-7] have send datas more than reg_rmt_tx_lim_ch[0-7] after detecting this interrupt software can updata the old datas with new datas."]
177+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when transmitter in channle(0-7) have send datas more than reg_rmt_tx_lim_ch(0-7) after detecting this interrupt software can updata the old datas with new datas."]
178178
#[doc = ""]
179179
#[doc = "NOTE: `n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field"]
180180
#[inline(always)]
@@ -184,7 +184,7 @@ impl R {
184184
CH_TX_THR_EVENT_R::new(((self.bits >> (n + 24)) & 1) != 0)
185185
}
186186
#[doc = "Iterator for array of:"]
187-
#[doc = "The interrupt raw bit for channel [0-7] turns to high level when transmitter in channle[0-7] have send datas more than reg_rmt_tx_lim_ch[0-7] after detecting this interrupt software can updata the old datas with new datas."]
187+
#[doc = "The interrupt raw bit for channel (0-7) turns to high level when transmitter in channle(0-7) have send datas more than reg_rmt_tx_lim_ch(0-7) after detecting this interrupt software can updata the old datas with new datas."]
188188
#[inline(always)]
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pub fn ch_tx_thr_event_iter(&self) -> impl Iterator<Item = CH_TX_THR_EVENT_R> + '_ {
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(0..8).map(|n| CH_TX_THR_EVENT_R::new(((self.bits >> (n + 24)) & 1) != 0))

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