From bc355d6328397c966c38a20496270fe9393fe547 Mon Sep 17 00:00:00 2001 From: Zgarbul Andrey Date: Sat, 30 Mar 2024 17:16:10 +0300 Subject: [PATCH] fix mcpwm clusters (#219) --- common_patches/mcpwm_collect.yaml | 40 +++- esp32c6/src/mcpwm0/ch/carrier_cfg.rs | 123 +++++----- esp32c6/src/mcpwm0/ch/dt_cfg.rs | 245 +++++++++----------- esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs | 18 +- esp32c6/src/mcpwm0/ch/dt_red_cfg.rs | 18 +- esp32c6/src/mcpwm0/ch/fh_cfg0.rs | 312 ++++++++++++-------------- esp32c6/src/mcpwm0/ch/fh_cfg1.rs | 81 +++---- esp32c6/src/mcpwm0/ch/fh_status.rs | 20 +- esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs | 84 +++---- esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs | 18 +- esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs | 18 +- esp32h2/src/mcpwm0/ch/carrier_cfg.rs | 123 +++++----- esp32h2/src/mcpwm0/ch/dt_cfg.rs | 245 +++++++++----------- esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs | 18 +- esp32h2/src/mcpwm0/ch/dt_red_cfg.rs | 18 +- esp32h2/src/mcpwm0/ch/fh_cfg0.rs | 312 ++++++++++++-------------- esp32h2/src/mcpwm0/ch/fh_cfg1.rs | 81 +++---- esp32h2/src/mcpwm0/ch/fh_status.rs | 20 +- esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs | 84 +++---- esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs | 18 +- esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs | 18 +- esp32p4/src/mcpwm0/ch/carrier_cfg.rs | 123 +++++----- esp32p4/src/mcpwm0/ch/dt_cfg.rs | 242 +++++++++----------- esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs | 18 +- esp32p4/src/mcpwm0/ch/dt_red_cfg.rs | 18 +- esp32p4/src/mcpwm0/ch/fh_cfg0.rs | 288 ++++++++++++------------ esp32p4/src/mcpwm0/ch/fh_cfg1.rs | 81 +++---- esp32p4/src/mcpwm0/ch/fh_status.rs | 20 +- esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs | 84 +++---- esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs | 18 +- esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs | 18 +- esp32p4/svd/patches/esp32p4.yaml | 20 +- 32 files changed, 1324 insertions(+), 1520 deletions(-) diff --git a/common_patches/mcpwm_collect.yaml b/common_patches/mcpwm_collect.yaml index 4f852be991..a1d72d9388 100644 --- a/common_patches/mcpwm_collect.yaml +++ b/common_patches/mcpwm_collect.yaml @@ -24,13 +24,19 @@ _cluster: description: Actions triggered by events on PWMx%s GEN?_STMP_CFG: - _strip: GEN?_ + _strip: + - GEN?_ + - CMPR?_ description: Transfer status and update method for time stamp registers A and B GEN?_TSTMP_A: - _strip: GEN?_ + _strip: + - GEN?_ + - CMPR?_ description: Shadow register for register A. GEN?_TSTMP_B: - _strip: GEN?_ + _strip: + - GEN?_ + - CMPR?_ description: Shadow register for register B. GEN?_CFG0: _strip: GEN?_ @@ -42,25 +48,39 @@ _cluster: GEN?_B: description: Actions triggered by events on PWMxB DT?_CFG: - _strip: DT?_ + _strip: + - DT?_ + - DB?_ description: Dead time type selection and configuration DT?_FED_CFG: - _strip: DT?_ + _strip: + - DT?_ + - DB?_ description: Shadow register for falling edge delay (FED). DT?_RED_CFG: - _strip: DT?_ + _strip: + - DT?_ + - DB?_ description: Shadow register for rising edge delay (RED). CARRIER?_CFG: - _strip: CARRIER?_ + _strip: + - CARRIER?_ + - CHOPPER?_ description: Carrier enable and configuratoin FH?_CFG0: - _strip: FH?_ + _strip: + - FH?_ + - TZ?_ description: Actions on PWM0A and PWM0B trip events FH?_CFG1: - _strip: FH?_ + _strip: + - FH?_ + - TZ?_ description: Software triggers for fault handler actions FH?_STATUS: - _strip: FH?_ + _strip: + - FH?_ + - TZ?_ description: Status of fault events. _array: diff --git a/esp32c6/src/mcpwm0/ch/carrier_cfg.rs b/esp32c6/src/mcpwm0/ch/carrier_cfg.rs index d81605bf26..52e906ba7a 100644 --- a/esp32c6/src/mcpwm0/ch/carrier_cfg.rs +++ b/esp32c6/src/mcpwm0/ch/carrier_cfg.rs @@ -2,87 +2,72 @@ pub type R = crate::R; #[doc = "Register `CARRIER_CFG` writer"] pub type W = crate::W; -#[doc = "Field `CHOPPER0_EN` reader - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] -pub type CHOPPER0_EN_R = crate::BitReader; -#[doc = "Field `CHOPPER0_EN` writer - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] -pub type CHOPPER0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CHOPPER0_PRESCALE` reader - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] -pub type CHOPPER0_PRESCALE_R = crate::FieldReader; -#[doc = "Field `CHOPPER0_PRESCALE` writer - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] -pub type CHOPPER0_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CHOPPER0_DUTY` reader - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] -pub type CHOPPER0_DUTY_R = crate::FieldReader; -#[doc = "Field `CHOPPER0_DUTY` writer - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] -pub type CHOPPER0_DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `CHOPPER0_OSHTWTH` reader - width of the first pulse in number of periods of the carrier"] -pub type CHOPPER0_OSHTWTH_R = crate::FieldReader; -#[doc = "Field `CHOPPER0_OSHTWTH` writer - width of the first pulse in number of periods of the carrier"] -pub type CHOPPER0_OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CHOPPER0_OUT_INVERT` reader - when set, invert the output of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_OUT_INVERT_R = crate::BitReader; -#[doc = "Field `CHOPPER0_OUT_INVERT` writer - when set, invert the output of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CHOPPER0_IN_INVERT` reader - when set, invert the input of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_IN_INVERT_R = crate::BitReader; -#[doc = "Field `CHOPPER0_IN_INVERT` writer - when set, invert the input of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRESCALE` reader - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] +pub type PRESCALE_R = crate::FieldReader; +#[doc = "Field `PRESCALE` writer - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] +pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DUTY` reader - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] +pub type DUTY_R = crate::FieldReader; +#[doc = "Field `DUTY` writer - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] +pub type DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OSHTWTH` reader - width of the first pulse in number of periods of the carrier"] +pub type OSHTWTH_R = crate::FieldReader; +#[doc = "Field `OSHTWTH` writer - width of the first pulse in number of periods of the carrier"] +pub type OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `OUT_INVERT` reader - when set, invert the output of PWM0A and PWM0B for this submodule"] +pub type OUT_INVERT_R = crate::BitReader; +#[doc = "Field `OUT_INVERT` writer - when set, invert the output of PWM0A and PWM0B for this submodule"] +pub type OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_INVERT` reader - when set, invert the input of PWM0A and PWM0B for this submodule"] +pub type IN_INVERT_R = crate::BitReader; +#[doc = "Field `IN_INVERT` writer - when set, invert the input of PWM0A and PWM0B for this submodule"] +pub type IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] #[inline(always)] - pub fn chopper0_en(&self) -> CHOPPER0_EN_R { - CHOPPER0_EN_R::new((self.bits & 1) != 0) + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) } #[doc = "Bits 1:4 - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] #[inline(always)] - pub fn chopper0_prescale(&self) -> CHOPPER0_PRESCALE_R { - CHOPPER0_PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8) + pub fn prescale(&self) -> PRESCALE_R { + PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8) } #[doc = "Bits 5:7 - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] #[inline(always)] - pub fn chopper0_duty(&self) -> CHOPPER0_DUTY_R { - CHOPPER0_DUTY_R::new(((self.bits >> 5) & 7) as u8) + pub fn duty(&self) -> DUTY_R { + DUTY_R::new(((self.bits >> 5) & 7) as u8) } #[doc = "Bits 8:11 - width of the first pulse in number of periods of the carrier"] #[inline(always)] - pub fn chopper0_oshtwth(&self) -> CHOPPER0_OSHTWTH_R { - CHOPPER0_OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8) + pub fn oshtwth(&self) -> OSHTWTH_R { + OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bit 12 - when set, invert the output of PWM0A and PWM0B for this submodule"] #[inline(always)] - pub fn chopper0_out_invert(&self) -> CHOPPER0_OUT_INVERT_R { - CHOPPER0_OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_invert(&self) -> OUT_INVERT_R { + OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - when set, invert the input of PWM0A and PWM0B for this submodule"] #[inline(always)] - pub fn chopper0_in_invert(&self) -> CHOPPER0_IN_INVERT_R { - CHOPPER0_IN_INVERT_R::new(((self.bits >> 13) & 1) != 0) + pub fn in_invert(&self) -> IN_INVERT_R { + IN_INVERT_R::new(((self.bits >> 13) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("CARRIER_CFG") - .field("chopper0_en", &format_args!("{}", self.chopper0_en().bit())) - .field( - "chopper0_prescale", - &format_args!("{}", self.chopper0_prescale().bits()), - ) - .field( - "chopper0_duty", - &format_args!("{}", self.chopper0_duty().bits()), - ) - .field( - "chopper0_oshtwth", - &format_args!("{}", self.chopper0_oshtwth().bits()), - ) - .field( - "chopper0_out_invert", - &format_args!("{}", self.chopper0_out_invert().bit()), - ) - .field( - "chopper0_in_invert", - &format_args!("{}", self.chopper0_in_invert().bit()), - ) + .field("en", &format_args!("{}", self.en().bit())) + .field("prescale", &format_args!("{}", self.prescale().bits())) + .field("duty", &format_args!("{}", self.duty().bits())) + .field("oshtwth", &format_args!("{}", self.oshtwth().bits())) + .field("out_invert", &format_args!("{}", self.out_invert().bit())) + .field("in_invert", &format_args!("{}", self.in_invert().bit())) .finish() } } @@ -96,38 +81,38 @@ impl W { #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] #[inline(always)] #[must_use] - pub fn chopper0_en(&mut self) -> CHOPPER0_EN_W { - CHOPPER0_EN_W::new(self, 0) + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) } #[doc = "Bits 1:4 - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] #[inline(always)] #[must_use] - pub fn chopper0_prescale(&mut self) -> CHOPPER0_PRESCALE_W { - CHOPPER0_PRESCALE_W::new(self, 1) + pub fn prescale(&mut self) -> PRESCALE_W { + PRESCALE_W::new(self, 1) } #[doc = "Bits 5:7 - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] #[inline(always)] #[must_use] - pub fn chopper0_duty(&mut self) -> CHOPPER0_DUTY_W { - CHOPPER0_DUTY_W::new(self, 5) + pub fn duty(&mut self) -> DUTY_W { + DUTY_W::new(self, 5) } #[doc = "Bits 8:11 - width of the first pulse in number of periods of the carrier"] #[inline(always)] #[must_use] - pub fn chopper0_oshtwth(&mut self) -> CHOPPER0_OSHTWTH_W { - CHOPPER0_OSHTWTH_W::new(self, 8) + pub fn oshtwth(&mut self) -> OSHTWTH_W { + OSHTWTH_W::new(self, 8) } #[doc = "Bit 12 - when set, invert the output of PWM0A and PWM0B for this submodule"] #[inline(always)] #[must_use] - pub fn chopper0_out_invert(&mut self) -> CHOPPER0_OUT_INVERT_W { - CHOPPER0_OUT_INVERT_W::new(self, 12) + pub fn out_invert(&mut self) -> OUT_INVERT_W { + OUT_INVERT_W::new(self, 12) } #[doc = "Bit 13 - when set, invert the input of PWM0A and PWM0B for this submodule"] #[inline(always)] #[must_use] - pub fn chopper0_in_invert(&mut self) -> CHOPPER0_IN_INVERT_W { - CHOPPER0_IN_INVERT_W::new(self, 13) + pub fn in_invert(&mut self) -> IN_INVERT_W { + IN_INVERT_W::new(self, 13) } } #[doc = "Carrier enable and configuratoin\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`carrier_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`carrier_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/dt_cfg.rs b/esp32c6/src/mcpwm0/ch/dt_cfg.rs index aceffcf960..1826d8ec55 100644 --- a/esp32c6/src/mcpwm0/ch/dt_cfg.rs +++ b/esp32c6/src/mcpwm0/ch/dt_cfg.rs @@ -2,114 +2,114 @@ pub type R = crate::R; #[doc = "Register `DT_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB0_FED_UPMETHOD` reader - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_FED_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `DB0_FED_UPMETHOD` writer - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DB0_RED_UPMETHOD` reader - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_RED_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `DB0_RED_UPMETHOD` writer - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DB0_DEB_MODE` reader - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] -pub type DB0_DEB_MODE_R = crate::BitReader; -#[doc = "Field `DB0_DEB_MODE` writer - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] -pub type DB0_DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_A_OUTSWAP` reader - S6 in table"] -pub type DB0_A_OUTSWAP_R = crate::BitReader; -#[doc = "Field `DB0_A_OUTSWAP` writer - S6 in table"] -pub type DB0_A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_B_OUTSWAP` reader - S7 in table"] -pub type DB0_B_OUTSWAP_R = crate::BitReader; -#[doc = "Field `DB0_B_OUTSWAP` writer - S7 in table"] -pub type DB0_B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_RED_INSEL` reader - S4 in table"] -pub type DB0_RED_INSEL_R = crate::BitReader; -#[doc = "Field `DB0_RED_INSEL` writer - S4 in table"] -pub type DB0_RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_FED_INSEL` reader - S5 in table"] -pub type DB0_FED_INSEL_R = crate::BitReader; -#[doc = "Field `DB0_FED_INSEL` writer - S5 in table"] -pub type DB0_FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_RED_OUTINVERT` reader - S2 in table"] -pub type DB0_RED_OUTINVERT_R = crate::BitReader; -#[doc = "Field `DB0_RED_OUTINVERT` writer - S2 in table"] -pub type DB0_RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_FED_OUTINVERT` reader - S3 in table"] -pub type DB0_FED_OUTINVERT_R = crate::BitReader; -#[doc = "Field `DB0_FED_OUTINVERT` writer - S3 in table"] -pub type DB0_FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_A_OUTBYPASS` reader - S1 in table"] -pub type DB0_A_OUTBYPASS_R = crate::BitReader; -#[doc = "Field `DB0_A_OUTBYPASS` writer - S1 in table"] -pub type DB0_A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_B_OUTBYPASS` reader - S0 in table"] -pub type DB0_B_OUTBYPASS_R = crate::BitReader; -#[doc = "Field `DB0_B_OUTBYPASS` writer - S0 in table"] -pub type DB0_B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_CLK_SEL` reader - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] -pub type DB0_CLK_SEL_R = crate::BitReader; -#[doc = "Field `DB0_CLK_SEL` writer - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] -pub type DB0_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_UPMETHOD` reader - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type FED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `FED_UPMETHOD` writer - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RED_UPMETHOD` reader - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type RED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `RED_UPMETHOD` writer - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DEB_MODE` reader - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DEB_MODE_R = crate::BitReader; +#[doc = "Field `DEB_MODE` writer - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_OUTSWAP` reader - S6 in table"] +pub type A_OUTSWAP_R = crate::BitReader; +#[doc = "Field `A_OUTSWAP` writer - S6 in table"] +pub type A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_OUTSWAP` reader - S7 in table"] +pub type B_OUTSWAP_R = crate::BitReader; +#[doc = "Field `B_OUTSWAP` writer - S7 in table"] +pub type B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RED_INSEL` reader - S4 in table"] +pub type RED_INSEL_R = crate::BitReader; +#[doc = "Field `RED_INSEL` writer - S4 in table"] +pub type RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_INSEL` reader - S5 in table"] +pub type FED_INSEL_R = crate::BitReader; +#[doc = "Field `FED_INSEL` writer - S5 in table"] +pub type FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RED_OUTINVERT` reader - S2 in table"] +pub type RED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `RED_OUTINVERT` writer - S2 in table"] +pub type RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_OUTINVERT` reader - S3 in table"] +pub type FED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `FED_OUTINVERT` writer - S3 in table"] +pub type FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_OUTBYPASS` reader - S1 in table"] +pub type A_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `A_OUTBYPASS` writer - S1 in table"] +pub type A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_OUTBYPASS` reader - S0 in table"] +pub type B_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `B_OUTBYPASS` writer - S0 in table"] +pub type B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SEL` reader - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] +pub type CLK_SEL_R = crate::BitReader; +#[doc = "Field `CLK_SEL` writer - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] +pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:3 - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] - pub fn db0_fed_upmethod(&self) -> DB0_FED_UPMETHOD_R { - DB0_FED_UPMETHOD_R::new((self.bits & 0x0f) as u8) + pub fn fed_upmethod(&self) -> FED_UPMETHOD_R { + FED_UPMETHOD_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] - pub fn db0_red_upmethod(&self) -> DB0_RED_UPMETHOD_R { - DB0_RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + pub fn red_upmethod(&self) -> RED_UPMETHOD_R { + RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bit 8 - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] #[inline(always)] - pub fn db0_deb_mode(&self) -> DB0_DEB_MODE_R { - DB0_DEB_MODE_R::new(((self.bits >> 8) & 1) != 0) + pub fn deb_mode(&self) -> DEB_MODE_R { + DEB_MODE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - S6 in table"] #[inline(always)] - pub fn db0_a_outswap(&self) -> DB0_A_OUTSWAP_R { - DB0_A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0) + pub fn a_outswap(&self) -> A_OUTSWAP_R { + A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - S7 in table"] #[inline(always)] - pub fn db0_b_outswap(&self) -> DB0_B_OUTSWAP_R { - DB0_B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0) + pub fn b_outswap(&self) -> B_OUTSWAP_R { + B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - S4 in table"] #[inline(always)] - pub fn db0_red_insel(&self) -> DB0_RED_INSEL_R { - DB0_RED_INSEL_R::new(((self.bits >> 11) & 1) != 0) + pub fn red_insel(&self) -> RED_INSEL_R { + RED_INSEL_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - S5 in table"] #[inline(always)] - pub fn db0_fed_insel(&self) -> DB0_FED_INSEL_R { - DB0_FED_INSEL_R::new(((self.bits >> 12) & 1) != 0) + pub fn fed_insel(&self) -> FED_INSEL_R { + FED_INSEL_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - S2 in table"] #[inline(always)] - pub fn db0_red_outinvert(&self) -> DB0_RED_OUTINVERT_R { - DB0_RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0) + pub fn red_outinvert(&self) -> RED_OUTINVERT_R { + RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - S3 in table"] #[inline(always)] - pub fn db0_fed_outinvert(&self) -> DB0_FED_OUTINVERT_R { - DB0_FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0) + pub fn fed_outinvert(&self) -> FED_OUTINVERT_R { + FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - S1 in table"] #[inline(always)] - pub fn db0_a_outbypass(&self) -> DB0_A_OUTBYPASS_R { - DB0_A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0) + pub fn a_outbypass(&self) -> A_OUTBYPASS_R { + A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - S0 in table"] #[inline(always)] - pub fn db0_b_outbypass(&self) -> DB0_B_OUTBYPASS_R { - DB0_B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0) + pub fn b_outbypass(&self) -> B_OUTBYPASS_R { + B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] #[inline(always)] - pub fn db0_clk_sel(&self) -> DB0_CLK_SEL_R { - DB0_CLK_SEL_R::new(((self.bits >> 17) & 1) != 0) + pub fn clk_sel(&self) -> CLK_SEL_R { + CLK_SEL_R::new(((self.bits >> 17) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -117,50 +117,29 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_CFG") .field( - "db0_fed_upmethod", - &format_args!("{}", self.db0_fed_upmethod().bits()), + "fed_upmethod", + &format_args!("{}", self.fed_upmethod().bits()), ) .field( - "db0_red_upmethod", - &format_args!("{}", self.db0_red_upmethod().bits()), + "red_upmethod", + &format_args!("{}", self.red_upmethod().bits()), ) + .field("deb_mode", &format_args!("{}", self.deb_mode().bit())) + .field("a_outswap", &format_args!("{}", self.a_outswap().bit())) + .field("b_outswap", &format_args!("{}", self.b_outswap().bit())) + .field("red_insel", &format_args!("{}", self.red_insel().bit())) + .field("fed_insel", &format_args!("{}", self.fed_insel().bit())) .field( - "db0_deb_mode", - &format_args!("{}", self.db0_deb_mode().bit()), + "red_outinvert", + &format_args!("{}", self.red_outinvert().bit()), ) .field( - "db0_a_outswap", - &format_args!("{}", self.db0_a_outswap().bit()), + "fed_outinvert", + &format_args!("{}", self.fed_outinvert().bit()), ) - .field( - "db0_b_outswap", - &format_args!("{}", self.db0_b_outswap().bit()), - ) - .field( - "db0_red_insel", - &format_args!("{}", self.db0_red_insel().bit()), - ) - .field( - "db0_fed_insel", - &format_args!("{}", self.db0_fed_insel().bit()), - ) - .field( - "db0_red_outinvert", - &format_args!("{}", self.db0_red_outinvert().bit()), - ) - .field( - "db0_fed_outinvert", - &format_args!("{}", self.db0_fed_outinvert().bit()), - ) - .field( - "db0_a_outbypass", - &format_args!("{}", self.db0_a_outbypass().bit()), - ) - .field( - "db0_b_outbypass", - &format_args!("{}", self.db0_b_outbypass().bit()), - ) - .field("db0_clk_sel", &format_args!("{}", self.db0_clk_sel().bit())) + .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit())) + .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit())) + .field("clk_sel", &format_args!("{}", self.clk_sel().bit())) .finish() } } @@ -174,74 +153,74 @@ impl W { #[doc = "Bits 0:3 - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] #[must_use] - pub fn db0_fed_upmethod(&mut self) -> DB0_FED_UPMETHOD_W { - DB0_FED_UPMETHOD_W::new(self, 0) + pub fn fed_upmethod(&mut self) -> FED_UPMETHOD_W { + FED_UPMETHOD_W::new(self, 0) } #[doc = "Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] #[must_use] - pub fn db0_red_upmethod(&mut self) -> DB0_RED_UPMETHOD_W { - DB0_RED_UPMETHOD_W::new(self, 4) + pub fn red_upmethod(&mut self) -> RED_UPMETHOD_W { + RED_UPMETHOD_W::new(self, 4) } #[doc = "Bit 8 - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] #[inline(always)] #[must_use] - pub fn db0_deb_mode(&mut self) -> DB0_DEB_MODE_W { - DB0_DEB_MODE_W::new(self, 8) + pub fn deb_mode(&mut self) -> DEB_MODE_W { + DEB_MODE_W::new(self, 8) } #[doc = "Bit 9 - S6 in table"] #[inline(always)] #[must_use] - pub fn db0_a_outswap(&mut self) -> DB0_A_OUTSWAP_W { - DB0_A_OUTSWAP_W::new(self, 9) + pub fn a_outswap(&mut self) -> A_OUTSWAP_W { + A_OUTSWAP_W::new(self, 9) } #[doc = "Bit 10 - S7 in table"] #[inline(always)] #[must_use] - pub fn db0_b_outswap(&mut self) -> DB0_B_OUTSWAP_W { - DB0_B_OUTSWAP_W::new(self, 10) + pub fn b_outswap(&mut self) -> B_OUTSWAP_W { + B_OUTSWAP_W::new(self, 10) } #[doc = "Bit 11 - S4 in table"] #[inline(always)] #[must_use] - pub fn db0_red_insel(&mut self) -> DB0_RED_INSEL_W { - DB0_RED_INSEL_W::new(self, 11) + pub fn red_insel(&mut self) -> RED_INSEL_W { + RED_INSEL_W::new(self, 11) } #[doc = "Bit 12 - S5 in table"] #[inline(always)] #[must_use] - pub fn db0_fed_insel(&mut self) -> DB0_FED_INSEL_W { - DB0_FED_INSEL_W::new(self, 12) + pub fn fed_insel(&mut self) -> FED_INSEL_W { + FED_INSEL_W::new(self, 12) } #[doc = "Bit 13 - S2 in table"] #[inline(always)] #[must_use] - pub fn db0_red_outinvert(&mut self) -> DB0_RED_OUTINVERT_W { - DB0_RED_OUTINVERT_W::new(self, 13) + pub fn red_outinvert(&mut self) -> RED_OUTINVERT_W { + RED_OUTINVERT_W::new(self, 13) } #[doc = "Bit 14 - S3 in table"] #[inline(always)] #[must_use] - pub fn db0_fed_outinvert(&mut self) -> DB0_FED_OUTINVERT_W { - DB0_FED_OUTINVERT_W::new(self, 14) + pub fn fed_outinvert(&mut self) -> FED_OUTINVERT_W { + FED_OUTINVERT_W::new(self, 14) } #[doc = "Bit 15 - S1 in table"] #[inline(always)] #[must_use] - pub fn db0_a_outbypass(&mut self) -> DB0_A_OUTBYPASS_W { - DB0_A_OUTBYPASS_W::new(self, 15) + pub fn a_outbypass(&mut self) -> A_OUTBYPASS_W { + A_OUTBYPASS_W::new(self, 15) } #[doc = "Bit 16 - S0 in table"] #[inline(always)] #[must_use] - pub fn db0_b_outbypass(&mut self) -> DB0_B_OUTBYPASS_W { - DB0_B_OUTBYPASS_W::new(self, 16) + pub fn b_outbypass(&mut self) -> B_OUTBYPASS_W { + B_OUTBYPASS_W::new(self, 16) } #[doc = "Bit 17 - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] #[inline(always)] #[must_use] - pub fn db0_clk_sel(&mut self) -> DB0_CLK_SEL_W { - DB0_CLK_SEL_W::new(self, 17) + pub fn clk_sel(&mut self) -> CLK_SEL_W { + CLK_SEL_W::new(self, 17) } } #[doc = "Dead time type selection and configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs index be668ba898..32a5d442af 100644 --- a/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs +++ b/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `DT_FED_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB0_FED` reader - Shadow register for FED"] -pub type DB0_FED_R = crate::FieldReader; -#[doc = "Field `DB0_FED` writer - Shadow register for FED"] -pub type DB0_FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `FED` reader - Shadow register for FED"] +pub type FED_R = crate::FieldReader; +#[doc = "Field `FED` writer - Shadow register for FED"] +pub type FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Shadow register for FED"] #[inline(always)] - pub fn db0_fed(&self) -> DB0_FED_R { - DB0_FED_R::new((self.bits & 0xffff) as u16) + pub fn fed(&self) -> FED_R { + FED_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_FED_CFG") - .field("db0_fed", &format_args!("{}", self.db0_fed().bits())) + .field("fed", &format_args!("{}", self.fed().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Shadow register for FED"] #[inline(always)] #[must_use] - pub fn db0_fed(&mut self) -> DB0_FED_W { - DB0_FED_W::new(self, 0) + pub fn fed(&mut self) -> FED_W { + FED_W::new(self, 0) } } #[doc = "Shadow register for falling edge delay (FED).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_fed_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_fed_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs b/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs index a999d55351..cbd50cd7b4 100644 --- a/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs +++ b/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `DT_RED_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB0_RED` reader - Shadow register for RED"] -pub type DB0_RED_R = crate::FieldReader; -#[doc = "Field `DB0_RED` writer - Shadow register for RED"] -pub type DB0_RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `RED` reader - Shadow register for RED"] +pub type RED_R = crate::FieldReader; +#[doc = "Field `RED` writer - Shadow register for RED"] +pub type RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Shadow register for RED"] #[inline(always)] - pub fn db0_red(&self) -> DB0_RED_R { - DB0_RED_R::new((self.bits & 0xffff) as u16) + pub fn red(&self) -> RED_R { + RED_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_RED_CFG") - .field("db0_red", &format_args!("{}", self.db0_red().bits())) + .field("red", &format_args!("{}", self.red().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Shadow register for RED"] #[inline(always)] #[must_use] - pub fn db0_red(&mut self) -> DB0_RED_W { - DB0_RED_W::new(self, 0) + pub fn red(&mut self) -> RED_W { + RED_W::new(self, 0) } } #[doc = "Shadow register for rising edge delay (RED).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_red_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_red_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/fh_cfg0.rs b/esp32c6/src/mcpwm0/ch/fh_cfg0.rs index ff9a8f3ff5..16bf20dc2c 100644 --- a/esp32c6/src/mcpwm0/ch/fh_cfg0.rs +++ b/esp32c6/src/mcpwm0/ch/fh_cfg0.rs @@ -2,196 +2,172 @@ pub type R = crate::R; #[doc = "Register `FH_CFG0` writer"] pub type W = crate::W; -#[doc = "Field `TZ0_SW_CBC` reader - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_SW_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_SW_CBC` writer - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F2_CBC` reader - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F2_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_F2_CBC` writer - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F1_CBC` reader - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F1_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_F1_CBC` writer - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F0_CBC` reader - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F0_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_F0_CBC` writer - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_SW_OST` reader - Enable register for software force one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_SW_OST_R = crate::BitReader; -#[doc = "Field `TZ0_SW_OST` writer - Enable register for software force one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F2_OST` reader - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F2_OST_R = crate::BitReader; -#[doc = "Field `TZ0_F2_OST` writer - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F1_OST` reader - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F1_OST_R = crate::BitReader; -#[doc = "Field `TZ0_F1_OST` writer - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F0_OST` reader - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F0_OST_R = crate::BitReader; -#[doc = "Field `TZ0_F0_OST` writer - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_A_CBC_D` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_D_R = crate::FieldReader; -#[doc = "Field `TZ0_A_CBC_D` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_A_CBC_U` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_U_R = crate::FieldReader; -#[doc = "Field `TZ0_A_CBC_U` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_A_OST_D` reader - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_D_R = crate::FieldReader; -#[doc = "Field `TZ0_A_OST_D` writer - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_A_OST_U` reader - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_U_R = crate::FieldReader; -#[doc = "Field `TZ0_A_OST_U` writer - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_CBC_D` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_D_R = crate::FieldReader; -#[doc = "Field `TZ0_B_CBC_D` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_CBC_U` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_U_R = crate::FieldReader; -#[doc = "Field `TZ0_B_CBC_U` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_OST_D` reader - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_D_R = crate::FieldReader; -#[doc = "Field `TZ0_B_OST_D` writer - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_OST_U` reader - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_U_R = crate::FieldReader; -#[doc = "Field `TZ0_B_OST_U` writer - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SW_CBC` reader - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type SW_CBC_R = crate::BitReader; +#[doc = "Field `SW_CBC` writer - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_CBC` reader - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F2_CBC_R = crate::BitReader; +#[doc = "Field `F2_CBC` writer - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_CBC` reader - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F1_CBC_R = crate::BitReader; +#[doc = "Field `F1_CBC` writer - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F0_CBC` reader - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F0_CBC_R = crate::BitReader; +#[doc = "Field `F0_CBC` writer - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_OST` reader - Enable register for software force one-shot mode action. 0: disable, 1: enable"] +pub type SW_OST_R = crate::BitReader; +#[doc = "Field `SW_OST` writer - Enable register for software force one-shot mode action. 0: disable, 1: enable"] +pub type SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_OST` reader - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F2_OST_R = crate::BitReader; +#[doc = "Field `F2_OST` writer - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_OST` reader - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F1_OST_R = crate::BitReader; +#[doc = "Field `F1_OST` writer - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F0_OST` reader - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F0_OST_R = crate::BitReader; +#[doc = "Field `F0_OST` writer - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_CBC_D` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_D_R = crate::FieldReader; +#[doc = "Field `A_CBC_D` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_CBC_U` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_U_R = crate::FieldReader; +#[doc = "Field `A_CBC_U` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_OST_D` reader - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_D_R = crate::FieldReader; +#[doc = "Field `A_OST_D` writer - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_OST_U` reader - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_U_R = crate::FieldReader; +#[doc = "Field `A_OST_U` writer - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_CBC_D` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_CBC_D_R = crate::FieldReader; +#[doc = "Field `B_CBC_D` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_CBC_U` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] +pub type B_CBC_U_R = crate::FieldReader; +#[doc = "Field `B_CBC_U` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] +pub type B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_OST_D` reader - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_D_R = crate::FieldReader; +#[doc = "Field `B_OST_D` writer - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_OST_U` reader - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_U_R = crate::FieldReader; +#[doc = "Field `B_OST_U` writer - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_sw_cbc(&self) -> TZ0_SW_CBC_R { - TZ0_SW_CBC_R::new((self.bits & 1) != 0) + pub fn sw_cbc(&self) -> SW_CBC_R { + SW_CBC_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f2_cbc(&self) -> TZ0_F2_CBC_R { - TZ0_F2_CBC_R::new(((self.bits >> 1) & 1) != 0) + pub fn f2_cbc(&self) -> F2_CBC_R { + F2_CBC_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f1_cbc(&self) -> TZ0_F1_CBC_R { - TZ0_F1_CBC_R::new(((self.bits >> 2) & 1) != 0) + pub fn f1_cbc(&self) -> F1_CBC_R { + F1_CBC_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f0_cbc(&self) -> TZ0_F0_CBC_R { - TZ0_F0_CBC_R::new(((self.bits >> 3) & 1) != 0) + pub fn f0_cbc(&self) -> F0_CBC_R { + F0_CBC_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Enable register for software force one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_sw_ost(&self) -> TZ0_SW_OST_R { - TZ0_SW_OST_R::new(((self.bits >> 4) & 1) != 0) + pub fn sw_ost(&self) -> SW_OST_R { + SW_OST_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f2_ost(&self) -> TZ0_F2_OST_R { - TZ0_F2_OST_R::new(((self.bits >> 5) & 1) != 0) + pub fn f2_ost(&self) -> F2_OST_R { + F2_OST_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f1_ost(&self) -> TZ0_F1_OST_R { - TZ0_F1_OST_R::new(((self.bits >> 6) & 1) != 0) + pub fn f1_ost(&self) -> F1_OST_R { + F1_OST_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f0_ost(&self) -> TZ0_F0_OST_R { - TZ0_F0_OST_R::new(((self.bits >> 7) & 1) != 0) + pub fn f0_ost(&self) -> F0_OST_R { + F0_OST_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_cbc_d(&self) -> TZ0_A_CBC_D_R { - TZ0_A_CBC_D_R::new(((self.bits >> 8) & 3) as u8) + pub fn a_cbc_d(&self) -> A_CBC_D_R { + A_CBC_D_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_cbc_u(&self) -> TZ0_A_CBC_U_R { - TZ0_A_CBC_U_R::new(((self.bits >> 10) & 3) as u8) + pub fn a_cbc_u(&self) -> A_CBC_U_R { + A_CBC_U_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_ost_d(&self) -> TZ0_A_OST_D_R { - TZ0_A_OST_D_R::new(((self.bits >> 12) & 3) as u8) + pub fn a_ost_d(&self) -> A_OST_D_R { + A_OST_D_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_ost_u(&self) -> TZ0_A_OST_U_R { - TZ0_A_OST_U_R::new(((self.bits >> 14) & 3) as u8) + pub fn a_ost_u(&self) -> A_OST_U_R { + A_OST_U_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_cbc_d(&self) -> TZ0_B_CBC_D_R { - TZ0_B_CBC_D_R::new(((self.bits >> 16) & 3) as u8) + pub fn b_cbc_d(&self) -> B_CBC_D_R { + B_CBC_D_R::new(((self.bits >> 16) & 3) as u8) } #[doc = "Bits 18:19 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_cbc_u(&self) -> TZ0_B_CBC_U_R { - TZ0_B_CBC_U_R::new(((self.bits >> 18) & 3) as u8) + pub fn b_cbc_u(&self) -> B_CBC_U_R { + B_CBC_U_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:21 - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_ost_d(&self) -> TZ0_B_OST_D_R { - TZ0_B_OST_D_R::new(((self.bits >> 20) & 3) as u8) + pub fn b_ost_d(&self) -> B_OST_D_R { + B_OST_D_R::new(((self.bits >> 20) & 3) as u8) } #[doc = "Bits 22:23 - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_ost_u(&self) -> TZ0_B_OST_U_R { - TZ0_B_OST_U_R::new(((self.bits >> 22) & 3) as u8) + pub fn b_ost_u(&self) -> B_OST_U_R { + B_OST_U_R::new(((self.bits >> 22) & 3) as u8) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_CFG0") - .field("tz0_sw_cbc", &format_args!("{}", self.tz0_sw_cbc().bit())) - .field("tz0_f2_cbc", &format_args!("{}", self.tz0_f2_cbc().bit())) - .field("tz0_f1_cbc", &format_args!("{}", self.tz0_f1_cbc().bit())) - .field("tz0_f0_cbc", &format_args!("{}", self.tz0_f0_cbc().bit())) - .field("tz0_sw_ost", &format_args!("{}", self.tz0_sw_ost().bit())) - .field("tz0_f2_ost", &format_args!("{}", self.tz0_f2_ost().bit())) - .field("tz0_f1_ost", &format_args!("{}", self.tz0_f1_ost().bit())) - .field("tz0_f0_ost", &format_args!("{}", self.tz0_f0_ost().bit())) - .field( - "tz0_a_cbc_d", - &format_args!("{}", self.tz0_a_cbc_d().bits()), - ) - .field( - "tz0_a_cbc_u", - &format_args!("{}", self.tz0_a_cbc_u().bits()), - ) - .field( - "tz0_a_ost_d", - &format_args!("{}", self.tz0_a_ost_d().bits()), - ) - .field( - "tz0_a_ost_u", - &format_args!("{}", self.tz0_a_ost_u().bits()), - ) - .field( - "tz0_b_cbc_d", - &format_args!("{}", self.tz0_b_cbc_d().bits()), - ) - .field( - "tz0_b_cbc_u", - &format_args!("{}", self.tz0_b_cbc_u().bits()), - ) - .field( - "tz0_b_ost_d", - &format_args!("{}", self.tz0_b_ost_d().bits()), - ) - .field( - "tz0_b_ost_u", - &format_args!("{}", self.tz0_b_ost_u().bits()), - ) + .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit())) + .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit())) + .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit())) + .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit())) + .field("sw_ost", &format_args!("{}", self.sw_ost().bit())) + .field("f2_ost", &format_args!("{}", self.f2_ost().bit())) + .field("f1_ost", &format_args!("{}", self.f1_ost().bit())) + .field("f0_ost", &format_args!("{}", self.f0_ost().bit())) + .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits())) + .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits())) + .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits())) + .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits())) + .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits())) + .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits())) + .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits())) + .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits())) .finish() } } @@ -205,98 +181,98 @@ impl W { #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_sw_cbc(&mut self) -> TZ0_SW_CBC_W { - TZ0_SW_CBC_W::new(self, 0) + pub fn sw_cbc(&mut self) -> SW_CBC_W { + SW_CBC_W::new(self, 0) } #[doc = "Bit 1 - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f2_cbc(&mut self) -> TZ0_F2_CBC_W { - TZ0_F2_CBC_W::new(self, 1) + pub fn f2_cbc(&mut self) -> F2_CBC_W { + F2_CBC_W::new(self, 1) } #[doc = "Bit 2 - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f1_cbc(&mut self) -> TZ0_F1_CBC_W { - TZ0_F1_CBC_W::new(self, 2) + pub fn f1_cbc(&mut self) -> F1_CBC_W { + F1_CBC_W::new(self, 2) } #[doc = "Bit 3 - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f0_cbc(&mut self) -> TZ0_F0_CBC_W { - TZ0_F0_CBC_W::new(self, 3) + pub fn f0_cbc(&mut self) -> F0_CBC_W { + F0_CBC_W::new(self, 3) } #[doc = "Bit 4 - Enable register for software force one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_sw_ost(&mut self) -> TZ0_SW_OST_W { - TZ0_SW_OST_W::new(self, 4) + pub fn sw_ost(&mut self) -> SW_OST_W { + SW_OST_W::new(self, 4) } #[doc = "Bit 5 - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f2_ost(&mut self) -> TZ0_F2_OST_W { - TZ0_F2_OST_W::new(self, 5) + pub fn f2_ost(&mut self) -> F2_OST_W { + F2_OST_W::new(self, 5) } #[doc = "Bit 6 - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f1_ost(&mut self) -> TZ0_F1_OST_W { - TZ0_F1_OST_W::new(self, 6) + pub fn f1_ost(&mut self) -> F1_OST_W { + F1_OST_W::new(self, 6) } #[doc = "Bit 7 - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f0_ost(&mut self) -> TZ0_F0_OST_W { - TZ0_F0_OST_W::new(self, 7) + pub fn f0_ost(&mut self) -> F0_OST_W { + F0_OST_W::new(self, 7) } #[doc = "Bits 8:9 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_cbc_d(&mut self) -> TZ0_A_CBC_D_W { - TZ0_A_CBC_D_W::new(self, 8) + pub fn a_cbc_d(&mut self) -> A_CBC_D_W { + A_CBC_D_W::new(self, 8) } #[doc = "Bits 10:11 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_cbc_u(&mut self) -> TZ0_A_CBC_U_W { - TZ0_A_CBC_U_W::new(self, 10) + pub fn a_cbc_u(&mut self) -> A_CBC_U_W { + A_CBC_U_W::new(self, 10) } #[doc = "Bits 12:13 - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_ost_d(&mut self) -> TZ0_A_OST_D_W { - TZ0_A_OST_D_W::new(self, 12) + pub fn a_ost_d(&mut self) -> A_OST_D_W { + A_OST_D_W::new(self, 12) } #[doc = "Bits 14:15 - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_ost_u(&mut self) -> TZ0_A_OST_U_W { - TZ0_A_OST_U_W::new(self, 14) + pub fn a_ost_u(&mut self) -> A_OST_U_W { + A_OST_U_W::new(self, 14) } #[doc = "Bits 16:17 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_cbc_d(&mut self) -> TZ0_B_CBC_D_W { - TZ0_B_CBC_D_W::new(self, 16) + pub fn b_cbc_d(&mut self) -> B_CBC_D_W { + B_CBC_D_W::new(self, 16) } #[doc = "Bits 18:19 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_cbc_u(&mut self) -> TZ0_B_CBC_U_W { - TZ0_B_CBC_U_W::new(self, 18) + pub fn b_cbc_u(&mut self) -> B_CBC_U_W { + B_CBC_U_W::new(self, 18) } #[doc = "Bits 20:21 - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_ost_d(&mut self) -> TZ0_B_OST_D_W { - TZ0_B_OST_D_W::new(self, 20) + pub fn b_ost_d(&mut self) -> B_OST_D_W { + B_OST_D_W::new(self, 20) } #[doc = "Bits 22:23 - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_ost_u(&mut self) -> TZ0_B_OST_U_W { - TZ0_B_OST_U_W::new(self, 22) + pub fn b_ost_u(&mut self) -> B_OST_U_W { + B_OST_U_W::new(self, 22) } } #[doc = "Actions on PWM0A and PWM0B trip events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/fh_cfg1.rs b/esp32c6/src/mcpwm0/ch/fh_cfg1.rs index 408cdfc7a2..01221dba64 100644 --- a/esp32c6/src/mcpwm0/ch/fh_cfg1.rs +++ b/esp32c6/src/mcpwm0/ch/fh_cfg1.rs @@ -2,61 +2,52 @@ pub type R = crate::R; #[doc = "Register `FH_CFG1` writer"] pub type W = crate::W; -#[doc = "Field `TZ0_CLR_OST` reader - a rising edge will clear on going one-shot mode action"] -pub type TZ0_CLR_OST_R = crate::BitReader; -#[doc = "Field `TZ0_CLR_OST` writer - a rising edge will clear on going one-shot mode action"] -pub type TZ0_CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_CBCPULSE` reader - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] -pub type TZ0_CBCPULSE_R = crate::FieldReader; -#[doc = "Field `TZ0_CBCPULSE` writer - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] -pub type TZ0_CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_FORCE_CBC` reader - a toggle trigger a cycle-by-cycle mode action"] -pub type TZ0_FORCE_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_FORCE_CBC` writer - a toggle trigger a cycle-by-cycle mode action"] -pub type TZ0_FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_FORCE_OST` reader - a toggle (software negate its value) triggers a one-shot mode action"] -pub type TZ0_FORCE_OST_R = crate::BitReader; -#[doc = "Field `TZ0_FORCE_OST` writer - a toggle (software negate its value) triggers a one-shot mode action"] -pub type TZ0_FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR_OST` reader - a rising edge will clear on going one-shot mode action"] +pub type CLR_OST_R = crate::BitReader; +#[doc = "Field `CLR_OST` writer - a rising edge will clear on going one-shot mode action"] +pub type CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CBCPULSE` reader - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] +pub type CBCPULSE_R = crate::FieldReader; +#[doc = "Field `CBCPULSE` writer - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] +pub type CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FORCE_CBC` reader - a toggle trigger a cycle-by-cycle mode action"] +pub type FORCE_CBC_R = crate::BitReader; +#[doc = "Field `FORCE_CBC` writer - a toggle trigger a cycle-by-cycle mode action"] +pub type FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_OST` reader - a toggle (software negate its value) triggers a one-shot mode action"] +pub type FORCE_OST_R = crate::BitReader; +#[doc = "Field `FORCE_OST` writer - a toggle (software negate its value) triggers a one-shot mode action"] +pub type FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"] #[inline(always)] - pub fn tz0_clr_ost(&self) -> TZ0_CLR_OST_R { - TZ0_CLR_OST_R::new((self.bits & 1) != 0) + pub fn clr_ost(&self) -> CLR_OST_R { + CLR_OST_R::new((self.bits & 1) != 0) } #[doc = "Bits 1:2 - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] #[inline(always)] - pub fn tz0_cbcpulse(&self) -> TZ0_CBCPULSE_R { - TZ0_CBCPULSE_R::new(((self.bits >> 1) & 3) as u8) + pub fn cbcpulse(&self) -> CBCPULSE_R { + CBCPULSE_R::new(((self.bits >> 1) & 3) as u8) } #[doc = "Bit 3 - a toggle trigger a cycle-by-cycle mode action"] #[inline(always)] - pub fn tz0_force_cbc(&self) -> TZ0_FORCE_CBC_R { - TZ0_FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0) + pub fn force_cbc(&self) -> FORCE_CBC_R { + FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - a toggle (software negate its value) triggers a one-shot mode action"] #[inline(always)] - pub fn tz0_force_ost(&self) -> TZ0_FORCE_OST_R { - TZ0_FORCE_OST_R::new(((self.bits >> 4) & 1) != 0) + pub fn force_ost(&self) -> FORCE_OST_R { + FORCE_OST_R::new(((self.bits >> 4) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_CFG1") - .field("tz0_clr_ost", &format_args!("{}", self.tz0_clr_ost().bit())) - .field( - "tz0_cbcpulse", - &format_args!("{}", self.tz0_cbcpulse().bits()), - ) - .field( - "tz0_force_cbc", - &format_args!("{}", self.tz0_force_cbc().bit()), - ) - .field( - "tz0_force_ost", - &format_args!("{}", self.tz0_force_ost().bit()), - ) + .field("clr_ost", &format_args!("{}", self.clr_ost().bit())) + .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits())) + .field("force_cbc", &format_args!("{}", self.force_cbc().bit())) + .field("force_ost", &format_args!("{}", self.force_ost().bit())) .finish() } } @@ -70,26 +61,26 @@ impl W { #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"] #[inline(always)] #[must_use] - pub fn tz0_clr_ost(&mut self) -> TZ0_CLR_OST_W { - TZ0_CLR_OST_W::new(self, 0) + pub fn clr_ost(&mut self) -> CLR_OST_W { + CLR_OST_W::new(self, 0) } #[doc = "Bits 1:2 - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] #[inline(always)] #[must_use] - pub fn tz0_cbcpulse(&mut self) -> TZ0_CBCPULSE_W { - TZ0_CBCPULSE_W::new(self, 1) + pub fn cbcpulse(&mut self) -> CBCPULSE_W { + CBCPULSE_W::new(self, 1) } #[doc = "Bit 3 - a toggle trigger a cycle-by-cycle mode action"] #[inline(always)] #[must_use] - pub fn tz0_force_cbc(&mut self) -> TZ0_FORCE_CBC_W { - TZ0_FORCE_CBC_W::new(self, 3) + pub fn force_cbc(&mut self) -> FORCE_CBC_W { + FORCE_CBC_W::new(self, 3) } #[doc = "Bit 4 - a toggle (software negate its value) triggers a one-shot mode action"] #[inline(always)] #[must_use] - pub fn tz0_force_ost(&mut self) -> TZ0_FORCE_OST_W { - TZ0_FORCE_OST_W::new(self, 4) + pub fn force_ost(&mut self) -> FORCE_OST_W { + FORCE_OST_W::new(self, 4) } } #[doc = "Software triggers for fault handler actions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/fh_status.rs b/esp32c6/src/mcpwm0/ch/fh_status.rs index d15095bb51..6c5fc8920f 100644 --- a/esp32c6/src/mcpwm0/ch/fh_status.rs +++ b/esp32c6/src/mcpwm0/ch/fh_status.rs @@ -1,27 +1,27 @@ #[doc = "Register `FH_STATUS` reader"] pub type R = crate::R; -#[doc = "Field `TZ0_CBC_ON` reader - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"] -pub type TZ0_CBC_ON_R = crate::BitReader; -#[doc = "Field `TZ0_OST_ON` reader - Set and reset by hardware. If set, an one-shot mode action is on going"] -pub type TZ0_OST_ON_R = crate::BitReader; +#[doc = "Field `CBC_ON` reader - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"] +pub type CBC_ON_R = crate::BitReader; +#[doc = "Field `OST_ON` reader - Set and reset by hardware. If set, an one-shot mode action is on going"] +pub type OST_ON_R = crate::BitReader; impl R { #[doc = "Bit 0 - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"] #[inline(always)] - pub fn tz0_cbc_on(&self) -> TZ0_CBC_ON_R { - TZ0_CBC_ON_R::new((self.bits & 1) != 0) + pub fn cbc_on(&self) -> CBC_ON_R { + CBC_ON_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Set and reset by hardware. If set, an one-shot mode action is on going"] #[inline(always)] - pub fn tz0_ost_on(&self) -> TZ0_OST_ON_R { - TZ0_OST_ON_R::new(((self.bits >> 1) & 1) != 0) + pub fn ost_on(&self) -> OST_ON_R { + OST_ON_R::new(((self.bits >> 1) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_STATUS") - .field("tz0_cbc_on", &format_args!("{}", self.tz0_cbc_on().bit())) - .field("tz0_ost_on", &format_args!("{}", self.tz0_ost_on().bit())) + .field("cbc_on", &format_args!("{}", self.cbc_on().bit())) + .field("ost_on", &format_args!("{}", self.ost_on().bit())) .finish() } } diff --git a/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs index 925b7219db..c8006017b2 100644 --- a/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs +++ b/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs @@ -2,64 +2,52 @@ pub type R = crate::R; #[doc = "Register `GEN_STMP_CFG` writer"] pub type W = crate::W; -#[doc = "Field `CMPR0_A_UPMETHOD` reader - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_A_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `CMPR0_A_UPMETHOD` writer - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CMPR0_B_UPMETHOD` reader - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_B_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `CMPR0_B_UPMETHOD` writer - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CMPR0_A_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] -pub type CMPR0_A_SHDW_FULL_R = crate::BitReader; -#[doc = "Field `CMPR0_A_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] -pub type CMPR0_A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMPR0_B_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] -pub type CMPR0_B_SHDW_FULL_R = crate::BitReader; -#[doc = "Field `CMPR0_B_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] -pub type CMPR0_B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_UPMETHOD` reader - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type A_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `A_UPMETHOD` writer - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `B_UPMETHOD` reader - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type B_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `B_UPMETHOD` writer - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `A_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] +pub type A_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `A_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] +pub type A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] +pub type B_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `B_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] +pub type B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] - pub fn cmpr0_a_upmethod(&self) -> CMPR0_A_UPMETHOD_R { - CMPR0_A_UPMETHOD_R::new((self.bits & 0x0f) as u8) + pub fn a_upmethod(&self) -> A_UPMETHOD_R { + A_UPMETHOD_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] - pub fn cmpr0_b_upmethod(&self) -> CMPR0_B_UPMETHOD_R { - CMPR0_B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + pub fn b_upmethod(&self) -> B_UPMETHOD_R { + B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bit 8 - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] #[inline(always)] - pub fn cmpr0_a_shdw_full(&self) -> CMPR0_A_SHDW_FULL_R { - CMPR0_A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0) + pub fn a_shdw_full(&self) -> A_SHDW_FULL_R { + A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] #[inline(always)] - pub fn cmpr0_b_shdw_full(&self) -> CMPR0_B_SHDW_FULL_R { - CMPR0_B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0) + pub fn b_shdw_full(&self) -> B_SHDW_FULL_R { + B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_STMP_CFG") - .field( - "cmpr0_a_upmethod", - &format_args!("{}", self.cmpr0_a_upmethod().bits()), - ) - .field( - "cmpr0_b_upmethod", - &format_args!("{}", self.cmpr0_b_upmethod().bits()), - ) - .field( - "cmpr0_a_shdw_full", - &format_args!("{}", self.cmpr0_a_shdw_full().bit()), - ) - .field( - "cmpr0_b_shdw_full", - &format_args!("{}", self.cmpr0_b_shdw_full().bit()), - ) + .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits())) + .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits())) + .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit())) + .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit())) .finish() } } @@ -73,26 +61,26 @@ impl W { #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] #[must_use] - pub fn cmpr0_a_upmethod(&mut self) -> CMPR0_A_UPMETHOD_W { - CMPR0_A_UPMETHOD_W::new(self, 0) + pub fn a_upmethod(&mut self) -> A_UPMETHOD_W { + A_UPMETHOD_W::new(self, 0) } #[doc = "Bits 4:7 - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] #[must_use] - pub fn cmpr0_b_upmethod(&mut self) -> CMPR0_B_UPMETHOD_W { - CMPR0_B_UPMETHOD_W::new(self, 4) + pub fn b_upmethod(&mut self) -> B_UPMETHOD_W { + B_UPMETHOD_W::new(self, 4) } #[doc = "Bit 8 - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] #[inline(always)] #[must_use] - pub fn cmpr0_a_shdw_full(&mut self) -> CMPR0_A_SHDW_FULL_W { - CMPR0_A_SHDW_FULL_W::new(self, 8) + pub fn a_shdw_full(&mut self) -> A_SHDW_FULL_W { + A_SHDW_FULL_W::new(self, 8) } #[doc = "Bit 9 - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] #[inline(always)] #[must_use] - pub fn cmpr0_b_shdw_full(&mut self) -> CMPR0_B_SHDW_FULL_W { - CMPR0_B_SHDW_FULL_W::new(self, 9) + pub fn b_shdw_full(&mut self) -> B_SHDW_FULL_W { + B_SHDW_FULL_W::new(self, 9) } } #[doc = "Transfer status and update method for time stamp registers A and B\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_stmp_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_stmp_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs index d481964165..1dd337661a 100644 --- a/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs +++ b/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `GEN_TSTMP_A` writer"] pub type W = crate::W; -#[doc = "Field `CMPR0_A` reader - PWM generator 0 time stamp A's shadow register"] -pub type CMPR0_A_R = crate::FieldReader; -#[doc = "Field `CMPR0_A` writer - PWM generator 0 time stamp A's shadow register"] -pub type CMPR0_A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `A` reader - PWM generator 0 time stamp A's shadow register"] +pub type A_R = crate::FieldReader; +#[doc = "Field `A` writer - PWM generator 0 time stamp A's shadow register"] +pub type A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - PWM generator 0 time stamp A's shadow register"] #[inline(always)] - pub fn cmpr0_a(&self) -> CMPR0_A_R { - CMPR0_A_R::new((self.bits & 0xffff) as u16) + pub fn a(&self) -> A_R { + A_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_TSTMP_A") - .field("cmpr0_a", &format_args!("{}", self.cmpr0_a().bits())) + .field("a", &format_args!("{}", self.a().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - PWM generator 0 time stamp A's shadow register"] #[inline(always)] #[must_use] - pub fn cmpr0_a(&mut self) -> CMPR0_A_W { - CMPR0_A_W::new(self, 0) + pub fn a(&mut self) -> A_W { + A_W::new(self, 0) } } #[doc = "Shadow register for register A.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs index 6f92b43a5a..1d128d47ed 100644 --- a/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs +++ b/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `GEN_TSTMP_B` writer"] pub type W = crate::W; -#[doc = "Field `CMPR0_B` reader - PWM generator 0 time stamp B's shadow register"] -pub type CMPR0_B_R = crate::FieldReader; -#[doc = "Field `CMPR0_B` writer - PWM generator 0 time stamp B's shadow register"] -pub type CMPR0_B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `B` reader - PWM generator 0 time stamp B's shadow register"] +pub type B_R = crate::FieldReader; +#[doc = "Field `B` writer - PWM generator 0 time stamp B's shadow register"] +pub type B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - PWM generator 0 time stamp B's shadow register"] #[inline(always)] - pub fn cmpr0_b(&self) -> CMPR0_B_R { - CMPR0_B_R::new((self.bits & 0xffff) as u16) + pub fn b(&self) -> B_R { + B_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_TSTMP_B") - .field("cmpr0_b", &format_args!("{}", self.cmpr0_b().bits())) + .field("b", &format_args!("{}", self.b().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - PWM generator 0 time stamp B's shadow register"] #[inline(always)] #[must_use] - pub fn cmpr0_b(&mut self) -> CMPR0_B_W { - CMPR0_B_W::new(self, 0) + pub fn b(&mut self) -> B_W { + B_W::new(self, 0) } } #[doc = "Shadow register for register B.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_b::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/carrier_cfg.rs b/esp32h2/src/mcpwm0/ch/carrier_cfg.rs index d81605bf26..52e906ba7a 100644 --- a/esp32h2/src/mcpwm0/ch/carrier_cfg.rs +++ b/esp32h2/src/mcpwm0/ch/carrier_cfg.rs @@ -2,87 +2,72 @@ pub type R = crate::R; #[doc = "Register `CARRIER_CFG` writer"] pub type W = crate::W; -#[doc = "Field `CHOPPER0_EN` reader - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] -pub type CHOPPER0_EN_R = crate::BitReader; -#[doc = "Field `CHOPPER0_EN` writer - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] -pub type CHOPPER0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CHOPPER0_PRESCALE` reader - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] -pub type CHOPPER0_PRESCALE_R = crate::FieldReader; -#[doc = "Field `CHOPPER0_PRESCALE` writer - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] -pub type CHOPPER0_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CHOPPER0_DUTY` reader - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] -pub type CHOPPER0_DUTY_R = crate::FieldReader; -#[doc = "Field `CHOPPER0_DUTY` writer - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] -pub type CHOPPER0_DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `CHOPPER0_OSHTWTH` reader - width of the first pulse in number of periods of the carrier"] -pub type CHOPPER0_OSHTWTH_R = crate::FieldReader; -#[doc = "Field `CHOPPER0_OSHTWTH` writer - width of the first pulse in number of periods of the carrier"] -pub type CHOPPER0_OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CHOPPER0_OUT_INVERT` reader - when set, invert the output of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_OUT_INVERT_R = crate::BitReader; -#[doc = "Field `CHOPPER0_OUT_INVERT` writer - when set, invert the output of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CHOPPER0_IN_INVERT` reader - when set, invert the input of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_IN_INVERT_R = crate::BitReader; -#[doc = "Field `CHOPPER0_IN_INVERT` writer - when set, invert the input of PWM0A and PWM0B for this submodule"] -pub type CHOPPER0_IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRESCALE` reader - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] +pub type PRESCALE_R = crate::FieldReader; +#[doc = "Field `PRESCALE` writer - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] +pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DUTY` reader - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] +pub type DUTY_R = crate::FieldReader; +#[doc = "Field `DUTY` writer - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] +pub type DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OSHTWTH` reader - width of the first pulse in number of periods of the carrier"] +pub type OSHTWTH_R = crate::FieldReader; +#[doc = "Field `OSHTWTH` writer - width of the first pulse in number of periods of the carrier"] +pub type OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `OUT_INVERT` reader - when set, invert the output of PWM0A and PWM0B for this submodule"] +pub type OUT_INVERT_R = crate::BitReader; +#[doc = "Field `OUT_INVERT` writer - when set, invert the output of PWM0A and PWM0B for this submodule"] +pub type OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_INVERT` reader - when set, invert the input of PWM0A and PWM0B for this submodule"] +pub type IN_INVERT_R = crate::BitReader; +#[doc = "Field `IN_INVERT` writer - when set, invert the input of PWM0A and PWM0B for this submodule"] +pub type IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] #[inline(always)] - pub fn chopper0_en(&self) -> CHOPPER0_EN_R { - CHOPPER0_EN_R::new((self.bits & 1) != 0) + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) } #[doc = "Bits 1:4 - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] #[inline(always)] - pub fn chopper0_prescale(&self) -> CHOPPER0_PRESCALE_R { - CHOPPER0_PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8) + pub fn prescale(&self) -> PRESCALE_R { + PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8) } #[doc = "Bits 5:7 - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] #[inline(always)] - pub fn chopper0_duty(&self) -> CHOPPER0_DUTY_R { - CHOPPER0_DUTY_R::new(((self.bits >> 5) & 7) as u8) + pub fn duty(&self) -> DUTY_R { + DUTY_R::new(((self.bits >> 5) & 7) as u8) } #[doc = "Bits 8:11 - width of the first pulse in number of periods of the carrier"] #[inline(always)] - pub fn chopper0_oshtwth(&self) -> CHOPPER0_OSHTWTH_R { - CHOPPER0_OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8) + pub fn oshtwth(&self) -> OSHTWTH_R { + OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bit 12 - when set, invert the output of PWM0A and PWM0B for this submodule"] #[inline(always)] - pub fn chopper0_out_invert(&self) -> CHOPPER0_OUT_INVERT_R { - CHOPPER0_OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_invert(&self) -> OUT_INVERT_R { + OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - when set, invert the input of PWM0A and PWM0B for this submodule"] #[inline(always)] - pub fn chopper0_in_invert(&self) -> CHOPPER0_IN_INVERT_R { - CHOPPER0_IN_INVERT_R::new(((self.bits >> 13) & 1) != 0) + pub fn in_invert(&self) -> IN_INVERT_R { + IN_INVERT_R::new(((self.bits >> 13) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("CARRIER_CFG") - .field("chopper0_en", &format_args!("{}", self.chopper0_en().bit())) - .field( - "chopper0_prescale", - &format_args!("{}", self.chopper0_prescale().bits()), - ) - .field( - "chopper0_duty", - &format_args!("{}", self.chopper0_duty().bits()), - ) - .field( - "chopper0_oshtwth", - &format_args!("{}", self.chopper0_oshtwth().bits()), - ) - .field( - "chopper0_out_invert", - &format_args!("{}", self.chopper0_out_invert().bit()), - ) - .field( - "chopper0_in_invert", - &format_args!("{}", self.chopper0_in_invert().bit()), - ) + .field("en", &format_args!("{}", self.en().bit())) + .field("prescale", &format_args!("{}", self.prescale().bits())) + .field("duty", &format_args!("{}", self.duty().bits())) + .field("oshtwth", &format_args!("{}", self.oshtwth().bits())) + .field("out_invert", &format_args!("{}", self.out_invert().bit())) + .field("in_invert", &format_args!("{}", self.in_invert().bit())) .finish() } } @@ -96,38 +81,38 @@ impl W { #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"] #[inline(always)] #[must_use] - pub fn chopper0_en(&mut self) -> CHOPPER0_EN_W { - CHOPPER0_EN_W::new(self, 0) + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) } #[doc = "Bits 1:4 - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"] #[inline(always)] #[must_use] - pub fn chopper0_prescale(&mut self) -> CHOPPER0_PRESCALE_W { - CHOPPER0_PRESCALE_W::new(self, 1) + pub fn prescale(&mut self) -> PRESCALE_W { + PRESCALE_W::new(self, 1) } #[doc = "Bits 5:7 - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"] #[inline(always)] #[must_use] - pub fn chopper0_duty(&mut self) -> CHOPPER0_DUTY_W { - CHOPPER0_DUTY_W::new(self, 5) + pub fn duty(&mut self) -> DUTY_W { + DUTY_W::new(self, 5) } #[doc = "Bits 8:11 - width of the first pulse in number of periods of the carrier"] #[inline(always)] #[must_use] - pub fn chopper0_oshtwth(&mut self) -> CHOPPER0_OSHTWTH_W { - CHOPPER0_OSHTWTH_W::new(self, 8) + pub fn oshtwth(&mut self) -> OSHTWTH_W { + OSHTWTH_W::new(self, 8) } #[doc = "Bit 12 - when set, invert the output of PWM0A and PWM0B for this submodule"] #[inline(always)] #[must_use] - pub fn chopper0_out_invert(&mut self) -> CHOPPER0_OUT_INVERT_W { - CHOPPER0_OUT_INVERT_W::new(self, 12) + pub fn out_invert(&mut self) -> OUT_INVERT_W { + OUT_INVERT_W::new(self, 12) } #[doc = "Bit 13 - when set, invert the input of PWM0A and PWM0B for this submodule"] #[inline(always)] #[must_use] - pub fn chopper0_in_invert(&mut self) -> CHOPPER0_IN_INVERT_W { - CHOPPER0_IN_INVERT_W::new(self, 13) + pub fn in_invert(&mut self) -> IN_INVERT_W { + IN_INVERT_W::new(self, 13) } } #[doc = "Carrier enable and configuratoin\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`carrier_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`carrier_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/dt_cfg.rs b/esp32h2/src/mcpwm0/ch/dt_cfg.rs index aceffcf960..1826d8ec55 100644 --- a/esp32h2/src/mcpwm0/ch/dt_cfg.rs +++ b/esp32h2/src/mcpwm0/ch/dt_cfg.rs @@ -2,114 +2,114 @@ pub type R = crate::R; #[doc = "Register `DT_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB0_FED_UPMETHOD` reader - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_FED_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `DB0_FED_UPMETHOD` writer - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DB0_RED_UPMETHOD` reader - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_RED_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `DB0_RED_UPMETHOD` writer - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] -pub type DB0_RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DB0_DEB_MODE` reader - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] -pub type DB0_DEB_MODE_R = crate::BitReader; -#[doc = "Field `DB0_DEB_MODE` writer - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] -pub type DB0_DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_A_OUTSWAP` reader - S6 in table"] -pub type DB0_A_OUTSWAP_R = crate::BitReader; -#[doc = "Field `DB0_A_OUTSWAP` writer - S6 in table"] -pub type DB0_A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_B_OUTSWAP` reader - S7 in table"] -pub type DB0_B_OUTSWAP_R = crate::BitReader; -#[doc = "Field `DB0_B_OUTSWAP` writer - S7 in table"] -pub type DB0_B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_RED_INSEL` reader - S4 in table"] -pub type DB0_RED_INSEL_R = crate::BitReader; -#[doc = "Field `DB0_RED_INSEL` writer - S4 in table"] -pub type DB0_RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_FED_INSEL` reader - S5 in table"] -pub type DB0_FED_INSEL_R = crate::BitReader; -#[doc = "Field `DB0_FED_INSEL` writer - S5 in table"] -pub type DB0_FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_RED_OUTINVERT` reader - S2 in table"] -pub type DB0_RED_OUTINVERT_R = crate::BitReader; -#[doc = "Field `DB0_RED_OUTINVERT` writer - S2 in table"] -pub type DB0_RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_FED_OUTINVERT` reader - S3 in table"] -pub type DB0_FED_OUTINVERT_R = crate::BitReader; -#[doc = "Field `DB0_FED_OUTINVERT` writer - S3 in table"] -pub type DB0_FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_A_OUTBYPASS` reader - S1 in table"] -pub type DB0_A_OUTBYPASS_R = crate::BitReader; -#[doc = "Field `DB0_A_OUTBYPASS` writer - S1 in table"] -pub type DB0_A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_B_OUTBYPASS` reader - S0 in table"] -pub type DB0_B_OUTBYPASS_R = crate::BitReader; -#[doc = "Field `DB0_B_OUTBYPASS` writer - S0 in table"] -pub type DB0_B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB0_CLK_SEL` reader - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] -pub type DB0_CLK_SEL_R = crate::BitReader; -#[doc = "Field `DB0_CLK_SEL` writer - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] -pub type DB0_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_UPMETHOD` reader - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type FED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `FED_UPMETHOD` writer - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RED_UPMETHOD` reader - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type RED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `RED_UPMETHOD` writer - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] +pub type RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DEB_MODE` reader - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DEB_MODE_R = crate::BitReader; +#[doc = "Field `DEB_MODE` writer - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_OUTSWAP` reader - S6 in table"] +pub type A_OUTSWAP_R = crate::BitReader; +#[doc = "Field `A_OUTSWAP` writer - S6 in table"] +pub type A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_OUTSWAP` reader - S7 in table"] +pub type B_OUTSWAP_R = crate::BitReader; +#[doc = "Field `B_OUTSWAP` writer - S7 in table"] +pub type B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RED_INSEL` reader - S4 in table"] +pub type RED_INSEL_R = crate::BitReader; +#[doc = "Field `RED_INSEL` writer - S4 in table"] +pub type RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_INSEL` reader - S5 in table"] +pub type FED_INSEL_R = crate::BitReader; +#[doc = "Field `FED_INSEL` writer - S5 in table"] +pub type FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RED_OUTINVERT` reader - S2 in table"] +pub type RED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `RED_OUTINVERT` writer - S2 in table"] +pub type RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_OUTINVERT` reader - S3 in table"] +pub type FED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `FED_OUTINVERT` writer - S3 in table"] +pub type FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_OUTBYPASS` reader - S1 in table"] +pub type A_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `A_OUTBYPASS` writer - S1 in table"] +pub type A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_OUTBYPASS` reader - S0 in table"] +pub type B_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `B_OUTBYPASS` writer - S0 in table"] +pub type B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SEL` reader - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] +pub type CLK_SEL_R = crate::BitReader; +#[doc = "Field `CLK_SEL` writer - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] +pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:3 - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] - pub fn db0_fed_upmethod(&self) -> DB0_FED_UPMETHOD_R { - DB0_FED_UPMETHOD_R::new((self.bits & 0x0f) as u8) + pub fn fed_upmethod(&self) -> FED_UPMETHOD_R { + FED_UPMETHOD_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] - pub fn db0_red_upmethod(&self) -> DB0_RED_UPMETHOD_R { - DB0_RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + pub fn red_upmethod(&self) -> RED_UPMETHOD_R { + RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bit 8 - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] #[inline(always)] - pub fn db0_deb_mode(&self) -> DB0_DEB_MODE_R { - DB0_DEB_MODE_R::new(((self.bits >> 8) & 1) != 0) + pub fn deb_mode(&self) -> DEB_MODE_R { + DEB_MODE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - S6 in table"] #[inline(always)] - pub fn db0_a_outswap(&self) -> DB0_A_OUTSWAP_R { - DB0_A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0) + pub fn a_outswap(&self) -> A_OUTSWAP_R { + A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - S7 in table"] #[inline(always)] - pub fn db0_b_outswap(&self) -> DB0_B_OUTSWAP_R { - DB0_B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0) + pub fn b_outswap(&self) -> B_OUTSWAP_R { + B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - S4 in table"] #[inline(always)] - pub fn db0_red_insel(&self) -> DB0_RED_INSEL_R { - DB0_RED_INSEL_R::new(((self.bits >> 11) & 1) != 0) + pub fn red_insel(&self) -> RED_INSEL_R { + RED_INSEL_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - S5 in table"] #[inline(always)] - pub fn db0_fed_insel(&self) -> DB0_FED_INSEL_R { - DB0_FED_INSEL_R::new(((self.bits >> 12) & 1) != 0) + pub fn fed_insel(&self) -> FED_INSEL_R { + FED_INSEL_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - S2 in table"] #[inline(always)] - pub fn db0_red_outinvert(&self) -> DB0_RED_OUTINVERT_R { - DB0_RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0) + pub fn red_outinvert(&self) -> RED_OUTINVERT_R { + RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - S3 in table"] #[inline(always)] - pub fn db0_fed_outinvert(&self) -> DB0_FED_OUTINVERT_R { - DB0_FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0) + pub fn fed_outinvert(&self) -> FED_OUTINVERT_R { + FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - S1 in table"] #[inline(always)] - pub fn db0_a_outbypass(&self) -> DB0_A_OUTBYPASS_R { - DB0_A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0) + pub fn a_outbypass(&self) -> A_OUTBYPASS_R { + A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - S0 in table"] #[inline(always)] - pub fn db0_b_outbypass(&self) -> DB0_B_OUTBYPASS_R { - DB0_B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0) + pub fn b_outbypass(&self) -> B_OUTBYPASS_R { + B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] #[inline(always)] - pub fn db0_clk_sel(&self) -> DB0_CLK_SEL_R { - DB0_CLK_SEL_R::new(((self.bits >> 17) & 1) != 0) + pub fn clk_sel(&self) -> CLK_SEL_R { + CLK_SEL_R::new(((self.bits >> 17) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -117,50 +117,29 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_CFG") .field( - "db0_fed_upmethod", - &format_args!("{}", self.db0_fed_upmethod().bits()), + "fed_upmethod", + &format_args!("{}", self.fed_upmethod().bits()), ) .field( - "db0_red_upmethod", - &format_args!("{}", self.db0_red_upmethod().bits()), + "red_upmethod", + &format_args!("{}", self.red_upmethod().bits()), ) + .field("deb_mode", &format_args!("{}", self.deb_mode().bit())) + .field("a_outswap", &format_args!("{}", self.a_outswap().bit())) + .field("b_outswap", &format_args!("{}", self.b_outswap().bit())) + .field("red_insel", &format_args!("{}", self.red_insel().bit())) + .field("fed_insel", &format_args!("{}", self.fed_insel().bit())) .field( - "db0_deb_mode", - &format_args!("{}", self.db0_deb_mode().bit()), + "red_outinvert", + &format_args!("{}", self.red_outinvert().bit()), ) .field( - "db0_a_outswap", - &format_args!("{}", self.db0_a_outswap().bit()), + "fed_outinvert", + &format_args!("{}", self.fed_outinvert().bit()), ) - .field( - "db0_b_outswap", - &format_args!("{}", self.db0_b_outswap().bit()), - ) - .field( - "db0_red_insel", - &format_args!("{}", self.db0_red_insel().bit()), - ) - .field( - "db0_fed_insel", - &format_args!("{}", self.db0_fed_insel().bit()), - ) - .field( - "db0_red_outinvert", - &format_args!("{}", self.db0_red_outinvert().bit()), - ) - .field( - "db0_fed_outinvert", - &format_args!("{}", self.db0_fed_outinvert().bit()), - ) - .field( - "db0_a_outbypass", - &format_args!("{}", self.db0_a_outbypass().bit()), - ) - .field( - "db0_b_outbypass", - &format_args!("{}", self.db0_b_outbypass().bit()), - ) - .field("db0_clk_sel", &format_args!("{}", self.db0_clk_sel().bit())) + .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit())) + .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit())) + .field("clk_sel", &format_args!("{}", self.clk_sel().bit())) .finish() } } @@ -174,74 +153,74 @@ impl W { #[doc = "Bits 0:3 - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] #[must_use] - pub fn db0_fed_upmethod(&mut self) -> DB0_FED_UPMETHOD_W { - DB0_FED_UPMETHOD_W::new(self, 0) + pub fn fed_upmethod(&mut self) -> FED_UPMETHOD_W { + FED_UPMETHOD_W::new(self, 0) } #[doc = "Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"] #[inline(always)] #[must_use] - pub fn db0_red_upmethod(&mut self) -> DB0_RED_UPMETHOD_W { - DB0_RED_UPMETHOD_W::new(self, 4) + pub fn red_upmethod(&mut self) -> RED_UPMETHOD_W { + RED_UPMETHOD_W::new(self, 4) } #[doc = "Bit 8 - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"] #[inline(always)] #[must_use] - pub fn db0_deb_mode(&mut self) -> DB0_DEB_MODE_W { - DB0_DEB_MODE_W::new(self, 8) + pub fn deb_mode(&mut self) -> DEB_MODE_W { + DEB_MODE_W::new(self, 8) } #[doc = "Bit 9 - S6 in table"] #[inline(always)] #[must_use] - pub fn db0_a_outswap(&mut self) -> DB0_A_OUTSWAP_W { - DB0_A_OUTSWAP_W::new(self, 9) + pub fn a_outswap(&mut self) -> A_OUTSWAP_W { + A_OUTSWAP_W::new(self, 9) } #[doc = "Bit 10 - S7 in table"] #[inline(always)] #[must_use] - pub fn db0_b_outswap(&mut self) -> DB0_B_OUTSWAP_W { - DB0_B_OUTSWAP_W::new(self, 10) + pub fn b_outswap(&mut self) -> B_OUTSWAP_W { + B_OUTSWAP_W::new(self, 10) } #[doc = "Bit 11 - S4 in table"] #[inline(always)] #[must_use] - pub fn db0_red_insel(&mut self) -> DB0_RED_INSEL_W { - DB0_RED_INSEL_W::new(self, 11) + pub fn red_insel(&mut self) -> RED_INSEL_W { + RED_INSEL_W::new(self, 11) } #[doc = "Bit 12 - S5 in table"] #[inline(always)] #[must_use] - pub fn db0_fed_insel(&mut self) -> DB0_FED_INSEL_W { - DB0_FED_INSEL_W::new(self, 12) + pub fn fed_insel(&mut self) -> FED_INSEL_W { + FED_INSEL_W::new(self, 12) } #[doc = "Bit 13 - S2 in table"] #[inline(always)] #[must_use] - pub fn db0_red_outinvert(&mut self) -> DB0_RED_OUTINVERT_W { - DB0_RED_OUTINVERT_W::new(self, 13) + pub fn red_outinvert(&mut self) -> RED_OUTINVERT_W { + RED_OUTINVERT_W::new(self, 13) } #[doc = "Bit 14 - S3 in table"] #[inline(always)] #[must_use] - pub fn db0_fed_outinvert(&mut self) -> DB0_FED_OUTINVERT_W { - DB0_FED_OUTINVERT_W::new(self, 14) + pub fn fed_outinvert(&mut self) -> FED_OUTINVERT_W { + FED_OUTINVERT_W::new(self, 14) } #[doc = "Bit 15 - S1 in table"] #[inline(always)] #[must_use] - pub fn db0_a_outbypass(&mut self) -> DB0_A_OUTBYPASS_W { - DB0_A_OUTBYPASS_W::new(self, 15) + pub fn a_outbypass(&mut self) -> A_OUTBYPASS_W { + A_OUTBYPASS_W::new(self, 15) } #[doc = "Bit 16 - S0 in table"] #[inline(always)] #[must_use] - pub fn db0_b_outbypass(&mut self) -> DB0_B_OUTBYPASS_W { - DB0_B_OUTBYPASS_W::new(self, 16) + pub fn b_outbypass(&mut self) -> B_OUTBYPASS_W { + B_OUTBYPASS_W::new(self, 16) } #[doc = "Bit 17 - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"] #[inline(always)] #[must_use] - pub fn db0_clk_sel(&mut self) -> DB0_CLK_SEL_W { - DB0_CLK_SEL_W::new(self, 17) + pub fn clk_sel(&mut self) -> CLK_SEL_W { + CLK_SEL_W::new(self, 17) } } #[doc = "Dead time type selection and configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs index be668ba898..32a5d442af 100644 --- a/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs +++ b/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `DT_FED_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB0_FED` reader - Shadow register for FED"] -pub type DB0_FED_R = crate::FieldReader; -#[doc = "Field `DB0_FED` writer - Shadow register for FED"] -pub type DB0_FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `FED` reader - Shadow register for FED"] +pub type FED_R = crate::FieldReader; +#[doc = "Field `FED` writer - Shadow register for FED"] +pub type FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Shadow register for FED"] #[inline(always)] - pub fn db0_fed(&self) -> DB0_FED_R { - DB0_FED_R::new((self.bits & 0xffff) as u16) + pub fn fed(&self) -> FED_R { + FED_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_FED_CFG") - .field("db0_fed", &format_args!("{}", self.db0_fed().bits())) + .field("fed", &format_args!("{}", self.fed().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Shadow register for FED"] #[inline(always)] #[must_use] - pub fn db0_fed(&mut self) -> DB0_FED_W { - DB0_FED_W::new(self, 0) + pub fn fed(&mut self) -> FED_W { + FED_W::new(self, 0) } } #[doc = "Shadow register for falling edge delay (FED).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_fed_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_fed_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs b/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs index a999d55351..cbd50cd7b4 100644 --- a/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs +++ b/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `DT_RED_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB0_RED` reader - Shadow register for RED"] -pub type DB0_RED_R = crate::FieldReader; -#[doc = "Field `DB0_RED` writer - Shadow register for RED"] -pub type DB0_RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `RED` reader - Shadow register for RED"] +pub type RED_R = crate::FieldReader; +#[doc = "Field `RED` writer - Shadow register for RED"] +pub type RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Shadow register for RED"] #[inline(always)] - pub fn db0_red(&self) -> DB0_RED_R { - DB0_RED_R::new((self.bits & 0xffff) as u16) + pub fn red(&self) -> RED_R { + RED_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_RED_CFG") - .field("db0_red", &format_args!("{}", self.db0_red().bits())) + .field("red", &format_args!("{}", self.red().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Shadow register for RED"] #[inline(always)] #[must_use] - pub fn db0_red(&mut self) -> DB0_RED_W { - DB0_RED_W::new(self, 0) + pub fn red(&mut self) -> RED_W { + RED_W::new(self, 0) } } #[doc = "Shadow register for rising edge delay (RED).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_red_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_red_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/fh_cfg0.rs b/esp32h2/src/mcpwm0/ch/fh_cfg0.rs index ff9a8f3ff5..16bf20dc2c 100644 --- a/esp32h2/src/mcpwm0/ch/fh_cfg0.rs +++ b/esp32h2/src/mcpwm0/ch/fh_cfg0.rs @@ -2,196 +2,172 @@ pub type R = crate::R; #[doc = "Register `FH_CFG0` writer"] pub type W = crate::W; -#[doc = "Field `TZ0_SW_CBC` reader - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_SW_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_SW_CBC` writer - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F2_CBC` reader - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F2_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_F2_CBC` writer - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F1_CBC` reader - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F1_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_F1_CBC` writer - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F0_CBC` reader - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F0_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_F0_CBC` writer - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] -pub type TZ0_F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_SW_OST` reader - Enable register for software force one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_SW_OST_R = crate::BitReader; -#[doc = "Field `TZ0_SW_OST` writer - Enable register for software force one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F2_OST` reader - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F2_OST_R = crate::BitReader; -#[doc = "Field `TZ0_F2_OST` writer - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F1_OST` reader - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F1_OST_R = crate::BitReader; -#[doc = "Field `TZ0_F1_OST` writer - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_F0_OST` reader - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F0_OST_R = crate::BitReader; -#[doc = "Field `TZ0_F0_OST` writer - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] -pub type TZ0_F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_A_CBC_D` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_D_R = crate::FieldReader; -#[doc = "Field `TZ0_A_CBC_D` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_A_CBC_U` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_U_R = crate::FieldReader; -#[doc = "Field `TZ0_A_CBC_U` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_A_OST_D` reader - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_D_R = crate::FieldReader; -#[doc = "Field `TZ0_A_OST_D` writer - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_A_OST_U` reader - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_U_R = crate::FieldReader; -#[doc = "Field `TZ0_A_OST_U` writer - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_CBC_D` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_D_R = crate::FieldReader; -#[doc = "Field `TZ0_B_CBC_D` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_CBC_U` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_U_R = crate::FieldReader; -#[doc = "Field `TZ0_B_CBC_U` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_OST_D` reader - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_D_R = crate::FieldReader; -#[doc = "Field `TZ0_B_OST_D` writer - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_B_OST_U` reader - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_U_R = crate::FieldReader; -#[doc = "Field `TZ0_B_OST_U` writer - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] -pub type TZ0_B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SW_CBC` reader - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type SW_CBC_R = crate::BitReader; +#[doc = "Field `SW_CBC` writer - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_CBC` reader - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F2_CBC_R = crate::BitReader; +#[doc = "Field `F2_CBC` writer - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_CBC` reader - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F1_CBC_R = crate::BitReader; +#[doc = "Field `F1_CBC` writer - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F0_CBC` reader - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F0_CBC_R = crate::BitReader; +#[doc = "Field `F0_CBC` writer - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] +pub type F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_OST` reader - Enable register for software force one-shot mode action. 0: disable, 1: enable"] +pub type SW_OST_R = crate::BitReader; +#[doc = "Field `SW_OST` writer - Enable register for software force one-shot mode action. 0: disable, 1: enable"] +pub type SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_OST` reader - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F2_OST_R = crate::BitReader; +#[doc = "Field `F2_OST` writer - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_OST` reader - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F1_OST_R = crate::BitReader; +#[doc = "Field `F1_OST` writer - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F0_OST` reader - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F0_OST_R = crate::BitReader; +#[doc = "Field `F0_OST` writer - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] +pub type F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_CBC_D` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_D_R = crate::FieldReader; +#[doc = "Field `A_CBC_D` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_CBC_U` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_U_R = crate::FieldReader; +#[doc = "Field `A_CBC_U` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_OST_D` reader - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_D_R = crate::FieldReader; +#[doc = "Field `A_OST_D` writer - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_OST_U` reader - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_U_R = crate::FieldReader; +#[doc = "Field `A_OST_U` writer - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_CBC_D` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_CBC_D_R = crate::FieldReader; +#[doc = "Field `B_CBC_D` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_CBC_U` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] +pub type B_CBC_U_R = crate::FieldReader; +#[doc = "Field `B_CBC_U` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] +pub type B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_OST_D` reader - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_D_R = crate::FieldReader; +#[doc = "Field `B_OST_D` writer - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_OST_U` reader - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_U_R = crate::FieldReader; +#[doc = "Field `B_OST_U` writer - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] +pub type B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_sw_cbc(&self) -> TZ0_SW_CBC_R { - TZ0_SW_CBC_R::new((self.bits & 1) != 0) + pub fn sw_cbc(&self) -> SW_CBC_R { + SW_CBC_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f2_cbc(&self) -> TZ0_F2_CBC_R { - TZ0_F2_CBC_R::new(((self.bits >> 1) & 1) != 0) + pub fn f2_cbc(&self) -> F2_CBC_R { + F2_CBC_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f1_cbc(&self) -> TZ0_F1_CBC_R { - TZ0_F1_CBC_R::new(((self.bits >> 2) & 1) != 0) + pub fn f1_cbc(&self) -> F1_CBC_R { + F1_CBC_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f0_cbc(&self) -> TZ0_F0_CBC_R { - TZ0_F0_CBC_R::new(((self.bits >> 3) & 1) != 0) + pub fn f0_cbc(&self) -> F0_CBC_R { + F0_CBC_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Enable register for software force one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_sw_ost(&self) -> TZ0_SW_OST_R { - TZ0_SW_OST_R::new(((self.bits >> 4) & 1) != 0) + pub fn sw_ost(&self) -> SW_OST_R { + SW_OST_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f2_ost(&self) -> TZ0_F2_OST_R { - TZ0_F2_OST_R::new(((self.bits >> 5) & 1) != 0) + pub fn f2_ost(&self) -> F2_OST_R { + F2_OST_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f1_ost(&self) -> TZ0_F1_OST_R { - TZ0_F1_OST_R::new(((self.bits >> 6) & 1) != 0) + pub fn f1_ost(&self) -> F1_OST_R { + F1_OST_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] - pub fn tz0_f0_ost(&self) -> TZ0_F0_OST_R { - TZ0_F0_OST_R::new(((self.bits >> 7) & 1) != 0) + pub fn f0_ost(&self) -> F0_OST_R { + F0_OST_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_cbc_d(&self) -> TZ0_A_CBC_D_R { - TZ0_A_CBC_D_R::new(((self.bits >> 8) & 3) as u8) + pub fn a_cbc_d(&self) -> A_CBC_D_R { + A_CBC_D_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_cbc_u(&self) -> TZ0_A_CBC_U_R { - TZ0_A_CBC_U_R::new(((self.bits >> 10) & 3) as u8) + pub fn a_cbc_u(&self) -> A_CBC_U_R { + A_CBC_U_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_ost_d(&self) -> TZ0_A_OST_D_R { - TZ0_A_OST_D_R::new(((self.bits >> 12) & 3) as u8) + pub fn a_ost_d(&self) -> A_OST_D_R { + A_OST_D_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_a_ost_u(&self) -> TZ0_A_OST_U_R { - TZ0_A_OST_U_R::new(((self.bits >> 14) & 3) as u8) + pub fn a_ost_u(&self) -> A_OST_U_R { + A_OST_U_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_cbc_d(&self) -> TZ0_B_CBC_D_R { - TZ0_B_CBC_D_R::new(((self.bits >> 16) & 3) as u8) + pub fn b_cbc_d(&self) -> B_CBC_D_R { + B_CBC_D_R::new(((self.bits >> 16) & 3) as u8) } #[doc = "Bits 18:19 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_cbc_u(&self) -> TZ0_B_CBC_U_R { - TZ0_B_CBC_U_R::new(((self.bits >> 18) & 3) as u8) + pub fn b_cbc_u(&self) -> B_CBC_U_R { + B_CBC_U_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:21 - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_ost_d(&self) -> TZ0_B_OST_D_R { - TZ0_B_OST_D_R::new(((self.bits >> 20) & 3) as u8) + pub fn b_ost_d(&self) -> B_OST_D_R { + B_OST_D_R::new(((self.bits >> 20) & 3) as u8) } #[doc = "Bits 22:23 - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] - pub fn tz0_b_ost_u(&self) -> TZ0_B_OST_U_R { - TZ0_B_OST_U_R::new(((self.bits >> 22) & 3) as u8) + pub fn b_ost_u(&self) -> B_OST_U_R { + B_OST_U_R::new(((self.bits >> 22) & 3) as u8) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_CFG0") - .field("tz0_sw_cbc", &format_args!("{}", self.tz0_sw_cbc().bit())) - .field("tz0_f2_cbc", &format_args!("{}", self.tz0_f2_cbc().bit())) - .field("tz0_f1_cbc", &format_args!("{}", self.tz0_f1_cbc().bit())) - .field("tz0_f0_cbc", &format_args!("{}", self.tz0_f0_cbc().bit())) - .field("tz0_sw_ost", &format_args!("{}", self.tz0_sw_ost().bit())) - .field("tz0_f2_ost", &format_args!("{}", self.tz0_f2_ost().bit())) - .field("tz0_f1_ost", &format_args!("{}", self.tz0_f1_ost().bit())) - .field("tz0_f0_ost", &format_args!("{}", self.tz0_f0_ost().bit())) - .field( - "tz0_a_cbc_d", - &format_args!("{}", self.tz0_a_cbc_d().bits()), - ) - .field( - "tz0_a_cbc_u", - &format_args!("{}", self.tz0_a_cbc_u().bits()), - ) - .field( - "tz0_a_ost_d", - &format_args!("{}", self.tz0_a_ost_d().bits()), - ) - .field( - "tz0_a_ost_u", - &format_args!("{}", self.tz0_a_ost_u().bits()), - ) - .field( - "tz0_b_cbc_d", - &format_args!("{}", self.tz0_b_cbc_d().bits()), - ) - .field( - "tz0_b_cbc_u", - &format_args!("{}", self.tz0_b_cbc_u().bits()), - ) - .field( - "tz0_b_ost_d", - &format_args!("{}", self.tz0_b_ost_d().bits()), - ) - .field( - "tz0_b_ost_u", - &format_args!("{}", self.tz0_b_ost_u().bits()), - ) + .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit())) + .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit())) + .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit())) + .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit())) + .field("sw_ost", &format_args!("{}", self.sw_ost().bit())) + .field("f2_ost", &format_args!("{}", self.f2_ost().bit())) + .field("f1_ost", &format_args!("{}", self.f1_ost().bit())) + .field("f0_ost", &format_args!("{}", self.f0_ost().bit())) + .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits())) + .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits())) + .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits())) + .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits())) + .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits())) + .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits())) + .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits())) + .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits())) .finish() } } @@ -205,98 +181,98 @@ impl W { #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_sw_cbc(&mut self) -> TZ0_SW_CBC_W { - TZ0_SW_CBC_W::new(self, 0) + pub fn sw_cbc(&mut self) -> SW_CBC_W { + SW_CBC_W::new(self, 0) } #[doc = "Bit 1 - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f2_cbc(&mut self) -> TZ0_F2_CBC_W { - TZ0_F2_CBC_W::new(self, 1) + pub fn f2_cbc(&mut self) -> F2_CBC_W { + F2_CBC_W::new(self, 1) } #[doc = "Bit 2 - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f1_cbc(&mut self) -> TZ0_F1_CBC_W { - TZ0_F1_CBC_W::new(self, 2) + pub fn f1_cbc(&mut self) -> F1_CBC_W { + F1_CBC_W::new(self, 2) } #[doc = "Bit 3 - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f0_cbc(&mut self) -> TZ0_F0_CBC_W { - TZ0_F0_CBC_W::new(self, 3) + pub fn f0_cbc(&mut self) -> F0_CBC_W { + F0_CBC_W::new(self, 3) } #[doc = "Bit 4 - Enable register for software force one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_sw_ost(&mut self) -> TZ0_SW_OST_W { - TZ0_SW_OST_W::new(self, 4) + pub fn sw_ost(&mut self) -> SW_OST_W { + SW_OST_W::new(self, 4) } #[doc = "Bit 5 - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f2_ost(&mut self) -> TZ0_F2_OST_W { - TZ0_F2_OST_W::new(self, 5) + pub fn f2_ost(&mut self) -> F2_OST_W { + F2_OST_W::new(self, 5) } #[doc = "Bit 6 - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f1_ost(&mut self) -> TZ0_F1_OST_W { - TZ0_F1_OST_W::new(self, 6) + pub fn f1_ost(&mut self) -> F1_OST_W { + F1_OST_W::new(self, 6) } #[doc = "Bit 7 - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"] #[inline(always)] #[must_use] - pub fn tz0_f0_ost(&mut self) -> TZ0_F0_OST_W { - TZ0_F0_OST_W::new(self, 7) + pub fn f0_ost(&mut self) -> F0_OST_W { + F0_OST_W::new(self, 7) } #[doc = "Bits 8:9 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_cbc_d(&mut self) -> TZ0_A_CBC_D_W { - TZ0_A_CBC_D_W::new(self, 8) + pub fn a_cbc_d(&mut self) -> A_CBC_D_W { + A_CBC_D_W::new(self, 8) } #[doc = "Bits 10:11 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_cbc_u(&mut self) -> TZ0_A_CBC_U_W { - TZ0_A_CBC_U_W::new(self, 10) + pub fn a_cbc_u(&mut self) -> A_CBC_U_W { + A_CBC_U_W::new(self, 10) } #[doc = "Bits 12:13 - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_ost_d(&mut self) -> TZ0_A_OST_D_W { - TZ0_A_OST_D_W::new(self, 12) + pub fn a_ost_d(&mut self) -> A_OST_D_W { + A_OST_D_W::new(self, 12) } #[doc = "Bits 14:15 - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_a_ost_u(&mut self) -> TZ0_A_OST_U_W { - TZ0_A_OST_U_W::new(self, 14) + pub fn a_ost_u(&mut self) -> A_OST_U_W { + A_OST_U_W::new(self, 14) } #[doc = "Bits 16:17 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_cbc_d(&mut self) -> TZ0_B_CBC_D_W { - TZ0_B_CBC_D_W::new(self, 16) + pub fn b_cbc_d(&mut self) -> B_CBC_D_W { + B_CBC_D_W::new(self, 16) } #[doc = "Bits 18:19 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_cbc_u(&mut self) -> TZ0_B_CBC_U_W { - TZ0_B_CBC_U_W::new(self, 18) + pub fn b_cbc_u(&mut self) -> B_CBC_U_W { + B_CBC_U_W::new(self, 18) } #[doc = "Bits 20:21 - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_ost_d(&mut self) -> TZ0_B_OST_D_W { - TZ0_B_OST_D_W::new(self, 20) + pub fn b_ost_d(&mut self) -> B_OST_D_W { + B_OST_D_W::new(self, 20) } #[doc = "Bits 22:23 - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle"] #[inline(always)] #[must_use] - pub fn tz0_b_ost_u(&mut self) -> TZ0_B_OST_U_W { - TZ0_B_OST_U_W::new(self, 22) + pub fn b_ost_u(&mut self) -> B_OST_U_W { + B_OST_U_W::new(self, 22) } } #[doc = "Actions on PWM0A and PWM0B trip events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/fh_cfg1.rs b/esp32h2/src/mcpwm0/ch/fh_cfg1.rs index 408cdfc7a2..01221dba64 100644 --- a/esp32h2/src/mcpwm0/ch/fh_cfg1.rs +++ b/esp32h2/src/mcpwm0/ch/fh_cfg1.rs @@ -2,61 +2,52 @@ pub type R = crate::R; #[doc = "Register `FH_CFG1` writer"] pub type W = crate::W; -#[doc = "Field `TZ0_CLR_OST` reader - a rising edge will clear on going one-shot mode action"] -pub type TZ0_CLR_OST_R = crate::BitReader; -#[doc = "Field `TZ0_CLR_OST` writer - a rising edge will clear on going one-shot mode action"] -pub type TZ0_CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_CBCPULSE` reader - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] -pub type TZ0_CBCPULSE_R = crate::FieldReader; -#[doc = "Field `TZ0_CBCPULSE` writer - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] -pub type TZ0_CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ0_FORCE_CBC` reader - a toggle trigger a cycle-by-cycle mode action"] -pub type TZ0_FORCE_CBC_R = crate::BitReader; -#[doc = "Field `TZ0_FORCE_CBC` writer - a toggle trigger a cycle-by-cycle mode action"] -pub type TZ0_FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ0_FORCE_OST` reader - a toggle (software negate its value) triggers a one-shot mode action"] -pub type TZ0_FORCE_OST_R = crate::BitReader; -#[doc = "Field `TZ0_FORCE_OST` writer - a toggle (software negate its value) triggers a one-shot mode action"] -pub type TZ0_FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR_OST` reader - a rising edge will clear on going one-shot mode action"] +pub type CLR_OST_R = crate::BitReader; +#[doc = "Field `CLR_OST` writer - a rising edge will clear on going one-shot mode action"] +pub type CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CBCPULSE` reader - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] +pub type CBCPULSE_R = crate::FieldReader; +#[doc = "Field `CBCPULSE` writer - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] +pub type CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FORCE_CBC` reader - a toggle trigger a cycle-by-cycle mode action"] +pub type FORCE_CBC_R = crate::BitReader; +#[doc = "Field `FORCE_CBC` writer - a toggle trigger a cycle-by-cycle mode action"] +pub type FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_OST` reader - a toggle (software negate its value) triggers a one-shot mode action"] +pub type FORCE_OST_R = crate::BitReader; +#[doc = "Field `FORCE_OST` writer - a toggle (software negate its value) triggers a one-shot mode action"] +pub type FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"] #[inline(always)] - pub fn tz0_clr_ost(&self) -> TZ0_CLR_OST_R { - TZ0_CLR_OST_R::new((self.bits & 1) != 0) + pub fn clr_ost(&self) -> CLR_OST_R { + CLR_OST_R::new((self.bits & 1) != 0) } #[doc = "Bits 1:2 - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] #[inline(always)] - pub fn tz0_cbcpulse(&self) -> TZ0_CBCPULSE_R { - TZ0_CBCPULSE_R::new(((self.bits >> 1) & 3) as u8) + pub fn cbcpulse(&self) -> CBCPULSE_R { + CBCPULSE_R::new(((self.bits >> 1) & 3) as u8) } #[doc = "Bit 3 - a toggle trigger a cycle-by-cycle mode action"] #[inline(always)] - pub fn tz0_force_cbc(&self) -> TZ0_FORCE_CBC_R { - TZ0_FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0) + pub fn force_cbc(&self) -> FORCE_CBC_R { + FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - a toggle (software negate its value) triggers a one-shot mode action"] #[inline(always)] - pub fn tz0_force_ost(&self) -> TZ0_FORCE_OST_R { - TZ0_FORCE_OST_R::new(((self.bits >> 4) & 1) != 0) + pub fn force_ost(&self) -> FORCE_OST_R { + FORCE_OST_R::new(((self.bits >> 4) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_CFG1") - .field("tz0_clr_ost", &format_args!("{}", self.tz0_clr_ost().bit())) - .field( - "tz0_cbcpulse", - &format_args!("{}", self.tz0_cbcpulse().bits()), - ) - .field( - "tz0_force_cbc", - &format_args!("{}", self.tz0_force_cbc().bit()), - ) - .field( - "tz0_force_ost", - &format_args!("{}", self.tz0_force_ost().bit()), - ) + .field("clr_ost", &format_args!("{}", self.clr_ost().bit())) + .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits())) + .field("force_cbc", &format_args!("{}", self.force_cbc().bit())) + .field("force_ost", &format_args!("{}", self.force_ost().bit())) .finish() } } @@ -70,26 +61,26 @@ impl W { #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"] #[inline(always)] #[must_use] - pub fn tz0_clr_ost(&mut self) -> TZ0_CLR_OST_W { - TZ0_CLR_OST_W::new(self, 0) + pub fn clr_ost(&mut self) -> CLR_OST_W { + CLR_OST_W::new(self, 0) } #[doc = "Bits 1:2 - cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP"] #[inline(always)] #[must_use] - pub fn tz0_cbcpulse(&mut self) -> TZ0_CBCPULSE_W { - TZ0_CBCPULSE_W::new(self, 1) + pub fn cbcpulse(&mut self) -> CBCPULSE_W { + CBCPULSE_W::new(self, 1) } #[doc = "Bit 3 - a toggle trigger a cycle-by-cycle mode action"] #[inline(always)] #[must_use] - pub fn tz0_force_cbc(&mut self) -> TZ0_FORCE_CBC_W { - TZ0_FORCE_CBC_W::new(self, 3) + pub fn force_cbc(&mut self) -> FORCE_CBC_W { + FORCE_CBC_W::new(self, 3) } #[doc = "Bit 4 - a toggle (software negate its value) triggers a one-shot mode action"] #[inline(always)] #[must_use] - pub fn tz0_force_ost(&mut self) -> TZ0_FORCE_OST_W { - TZ0_FORCE_OST_W::new(self, 4) + pub fn force_ost(&mut self) -> FORCE_OST_W { + FORCE_OST_W::new(self, 4) } } #[doc = "Software triggers for fault handler actions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/fh_status.rs b/esp32h2/src/mcpwm0/ch/fh_status.rs index d15095bb51..6c5fc8920f 100644 --- a/esp32h2/src/mcpwm0/ch/fh_status.rs +++ b/esp32h2/src/mcpwm0/ch/fh_status.rs @@ -1,27 +1,27 @@ #[doc = "Register `FH_STATUS` reader"] pub type R = crate::R; -#[doc = "Field `TZ0_CBC_ON` reader - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"] -pub type TZ0_CBC_ON_R = crate::BitReader; -#[doc = "Field `TZ0_OST_ON` reader - Set and reset by hardware. If set, an one-shot mode action is on going"] -pub type TZ0_OST_ON_R = crate::BitReader; +#[doc = "Field `CBC_ON` reader - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"] +pub type CBC_ON_R = crate::BitReader; +#[doc = "Field `OST_ON` reader - Set and reset by hardware. If set, an one-shot mode action is on going"] +pub type OST_ON_R = crate::BitReader; impl R { #[doc = "Bit 0 - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"] #[inline(always)] - pub fn tz0_cbc_on(&self) -> TZ0_CBC_ON_R { - TZ0_CBC_ON_R::new((self.bits & 1) != 0) + pub fn cbc_on(&self) -> CBC_ON_R { + CBC_ON_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Set and reset by hardware. If set, an one-shot mode action is on going"] #[inline(always)] - pub fn tz0_ost_on(&self) -> TZ0_OST_ON_R { - TZ0_OST_ON_R::new(((self.bits >> 1) & 1) != 0) + pub fn ost_on(&self) -> OST_ON_R { + OST_ON_R::new(((self.bits >> 1) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_STATUS") - .field("tz0_cbc_on", &format_args!("{}", self.tz0_cbc_on().bit())) - .field("tz0_ost_on", &format_args!("{}", self.tz0_ost_on().bit())) + .field("cbc_on", &format_args!("{}", self.cbc_on().bit())) + .field("ost_on", &format_args!("{}", self.ost_on().bit())) .finish() } } diff --git a/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs index 925b7219db..c8006017b2 100644 --- a/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs +++ b/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs @@ -2,64 +2,52 @@ pub type R = crate::R; #[doc = "Register `GEN_STMP_CFG` writer"] pub type W = crate::W; -#[doc = "Field `CMPR0_A_UPMETHOD` reader - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_A_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `CMPR0_A_UPMETHOD` writer - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CMPR0_B_UPMETHOD` reader - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_B_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `CMPR0_B_UPMETHOD` writer - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] -pub type CMPR0_B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CMPR0_A_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] -pub type CMPR0_A_SHDW_FULL_R = crate::BitReader; -#[doc = "Field `CMPR0_A_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] -pub type CMPR0_A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMPR0_B_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] -pub type CMPR0_B_SHDW_FULL_R = crate::BitReader; -#[doc = "Field `CMPR0_B_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] -pub type CMPR0_B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_UPMETHOD` reader - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type A_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `A_UPMETHOD` writer - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `B_UPMETHOD` reader - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type B_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `B_UPMETHOD` writer - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] +pub type B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `A_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] +pub type A_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `A_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] +pub type A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] +pub type B_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `B_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] +pub type B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] - pub fn cmpr0_a_upmethod(&self) -> CMPR0_A_UPMETHOD_R { - CMPR0_A_UPMETHOD_R::new((self.bits & 0x0f) as u8) + pub fn a_upmethod(&self) -> A_UPMETHOD_R { + A_UPMETHOD_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] - pub fn cmpr0_b_upmethod(&self) -> CMPR0_B_UPMETHOD_R { - CMPR0_B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + pub fn b_upmethod(&self) -> B_UPMETHOD_R { + B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bit 8 - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] #[inline(always)] - pub fn cmpr0_a_shdw_full(&self) -> CMPR0_A_SHDW_FULL_R { - CMPR0_A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0) + pub fn a_shdw_full(&self) -> A_SHDW_FULL_R { + A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] #[inline(always)] - pub fn cmpr0_b_shdw_full(&self) -> CMPR0_B_SHDW_FULL_R { - CMPR0_B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0) + pub fn b_shdw_full(&self) -> B_SHDW_FULL_R { + B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_STMP_CFG") - .field( - "cmpr0_a_upmethod", - &format_args!("{}", self.cmpr0_a_upmethod().bits()), - ) - .field( - "cmpr0_b_upmethod", - &format_args!("{}", self.cmpr0_b_upmethod().bits()), - ) - .field( - "cmpr0_a_shdw_full", - &format_args!("{}", self.cmpr0_a_shdw_full().bit()), - ) - .field( - "cmpr0_b_shdw_full", - &format_args!("{}", self.cmpr0_b_shdw_full().bit()), - ) + .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits())) + .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits())) + .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit())) + .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit())) .finish() } } @@ -73,26 +61,26 @@ impl W { #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] #[must_use] - pub fn cmpr0_a_upmethod(&mut self) -> CMPR0_A_UPMETHOD_W { - CMPR0_A_UPMETHOD_W::new(self, 0) + pub fn a_upmethod(&mut self) -> A_UPMETHOD_W { + A_UPMETHOD_W::new(self, 0) } #[doc = "Bits 4:7 - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."] #[inline(always)] #[must_use] - pub fn cmpr0_b_upmethod(&mut self) -> CMPR0_B_UPMETHOD_W { - CMPR0_B_UPMETHOD_W::new(self, 4) + pub fn b_upmethod(&mut self) -> B_UPMETHOD_W { + B_UPMETHOD_W::new(self, 4) } #[doc = "Bit 8 - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"] #[inline(always)] #[must_use] - pub fn cmpr0_a_shdw_full(&mut self) -> CMPR0_A_SHDW_FULL_W { - CMPR0_A_SHDW_FULL_W::new(self, 8) + pub fn a_shdw_full(&mut self) -> A_SHDW_FULL_W { + A_SHDW_FULL_W::new(self, 8) } #[doc = "Bit 9 - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"] #[inline(always)] #[must_use] - pub fn cmpr0_b_shdw_full(&mut self) -> CMPR0_B_SHDW_FULL_W { - CMPR0_B_SHDW_FULL_W::new(self, 9) + pub fn b_shdw_full(&mut self) -> B_SHDW_FULL_W { + B_SHDW_FULL_W::new(self, 9) } } #[doc = "Transfer status and update method for time stamp registers A and B\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_stmp_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_stmp_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs index d481964165..1dd337661a 100644 --- a/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs +++ b/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `GEN_TSTMP_A` writer"] pub type W = crate::W; -#[doc = "Field `CMPR0_A` reader - PWM generator 0 time stamp A's shadow register"] -pub type CMPR0_A_R = crate::FieldReader; -#[doc = "Field `CMPR0_A` writer - PWM generator 0 time stamp A's shadow register"] -pub type CMPR0_A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `A` reader - PWM generator 0 time stamp A's shadow register"] +pub type A_R = crate::FieldReader; +#[doc = "Field `A` writer - PWM generator 0 time stamp A's shadow register"] +pub type A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - PWM generator 0 time stamp A's shadow register"] #[inline(always)] - pub fn cmpr0_a(&self) -> CMPR0_A_R { - CMPR0_A_R::new((self.bits & 0xffff) as u16) + pub fn a(&self) -> A_R { + A_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_TSTMP_A") - .field("cmpr0_a", &format_args!("{}", self.cmpr0_a().bits())) + .field("a", &format_args!("{}", self.a().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - PWM generator 0 time stamp A's shadow register"] #[inline(always)] #[must_use] - pub fn cmpr0_a(&mut self) -> CMPR0_A_W { - CMPR0_A_W::new(self, 0) + pub fn a(&mut self) -> A_W { + A_W::new(self, 0) } } #[doc = "Shadow register for register A.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs index 6f92b43a5a..1d128d47ed 100644 --- a/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs +++ b/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `GEN_TSTMP_B` writer"] pub type W = crate::W; -#[doc = "Field `CMPR0_B` reader - PWM generator 0 time stamp B's shadow register"] -pub type CMPR0_B_R = crate::FieldReader; -#[doc = "Field `CMPR0_B` writer - PWM generator 0 time stamp B's shadow register"] -pub type CMPR0_B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `B` reader - PWM generator 0 time stamp B's shadow register"] +pub type B_R = crate::FieldReader; +#[doc = "Field `B` writer - PWM generator 0 time stamp B's shadow register"] +pub type B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - PWM generator 0 time stamp B's shadow register"] #[inline(always)] - pub fn cmpr0_b(&self) -> CMPR0_B_R { - CMPR0_B_R::new((self.bits & 0xffff) as u16) + pub fn b(&self) -> B_R { + B_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_TSTMP_B") - .field("cmpr0_b", &format_args!("{}", self.cmpr0_b().bits())) + .field("b", &format_args!("{}", self.b().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - PWM generator 0 time stamp B's shadow register"] #[inline(always)] #[must_use] - pub fn cmpr0_b(&mut self) -> CMPR0_B_W { - CMPR0_B_W::new(self, 0) + pub fn b(&mut self) -> B_W { + B_W::new(self, 0) } } #[doc = "Shadow register for register B.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_b::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/carrier_cfg.rs b/esp32p4/src/mcpwm0/ch/carrier_cfg.rs index f8451ce747..284965a480 100644 --- a/esp32p4/src/mcpwm0/ch/carrier_cfg.rs +++ b/esp32p4/src/mcpwm0/ch/carrier_cfg.rs @@ -2,87 +2,72 @@ pub type R = crate::R; #[doc = "Register `CARRIER_CFG` writer"] pub type W = crate::W; -#[doc = "Field `CHOPPER_EN` reader - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] -pub type CHOPPER_EN_R = crate::BitReader; -#[doc = "Field `CHOPPER_EN` writer - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] -pub type CHOPPER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CHOPPER_PRESCALE` reader - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] -pub type CHOPPER_PRESCALE_R = crate::FieldReader; -#[doc = "Field `CHOPPER_PRESCALE` writer - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] -pub type CHOPPER_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CHOPPER_DUTY` reader - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] -pub type CHOPPER_DUTY_R = crate::FieldReader; -#[doc = "Field `CHOPPER_DUTY` writer - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] -pub type CHOPPER_DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `CHOPPER_OSHTWTH` reader - Configures width of the first pulse. Measurement unit: Periods of the carrier."] -pub type CHOPPER_OSHTWTH_R = crate::FieldReader; -#[doc = "Field `CHOPPER_OSHTWTH` writer - Configures width of the first pulse. Measurement unit: Periods of the carrier."] -pub type CHOPPER_OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CHOPPER_OUT_INVERT` reader - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] -pub type CHOPPER_OUT_INVERT_R = crate::BitReader; -#[doc = "Field `CHOPPER_OUT_INVERT` writer - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] -pub type CHOPPER_OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CHOPPER_IN_INVERT` reader - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] -pub type CHOPPER_IN_INVERT_R = crate::BitReader; -#[doc = "Field `CHOPPER_IN_INVERT` writer - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] -pub type CHOPPER_IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRESCALE` reader - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] +pub type PRESCALE_R = crate::FieldReader; +#[doc = "Field `PRESCALE` writer - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] +pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DUTY` reader - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] +pub type DUTY_R = crate::FieldReader; +#[doc = "Field `DUTY` writer - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] +pub type DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OSHTWTH` reader - Configures width of the first pulse. Measurement unit: Periods of the carrier."] +pub type OSHTWTH_R = crate::FieldReader; +#[doc = "Field `OSHTWTH` writer - Configures width of the first pulse. Measurement unit: Periods of the carrier."] +pub type OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `OUT_INVERT` reader - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type OUT_INVERT_R = crate::BitReader; +#[doc = "Field `OUT_INVERT` writer - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_INVERT` reader - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type IN_INVERT_R = crate::BitReader; +#[doc = "Field `IN_INVERT` writer - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] #[inline(always)] - pub fn chopper_en(&self) -> CHOPPER_EN_R { - CHOPPER_EN_R::new((self.bits & 1) != 0) + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) } #[doc = "Bits 1:4 - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] #[inline(always)] - pub fn chopper_prescale(&self) -> CHOPPER_PRESCALE_R { - CHOPPER_PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8) + pub fn prescale(&self) -> PRESCALE_R { + PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8) } #[doc = "Bits 5:7 - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] #[inline(always)] - pub fn chopper_duty(&self) -> CHOPPER_DUTY_R { - CHOPPER_DUTY_R::new(((self.bits >> 5) & 7) as u8) + pub fn duty(&self) -> DUTY_R { + DUTY_R::new(((self.bits >> 5) & 7) as u8) } #[doc = "Bits 8:11 - Configures width of the first pulse. Measurement unit: Periods of the carrier."] #[inline(always)] - pub fn chopper_oshtwth(&self) -> CHOPPER_OSHTWTH_R { - CHOPPER_OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8) + pub fn oshtwth(&self) -> OSHTWTH_R { + OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bit 12 - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] #[inline(always)] - pub fn chopper_out_invert(&self) -> CHOPPER_OUT_INVERT_R { - CHOPPER_OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0) + pub fn out_invert(&self) -> OUT_INVERT_R { + OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] #[inline(always)] - pub fn chopper_in_invert(&self) -> CHOPPER_IN_INVERT_R { - CHOPPER_IN_INVERT_R::new(((self.bits >> 13) & 1) != 0) + pub fn in_invert(&self) -> IN_INVERT_R { + IN_INVERT_R::new(((self.bits >> 13) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("CARRIER_CFG") - .field("chopper_en", &format_args!("{}", self.chopper_en().bit())) - .field( - "chopper_prescale", - &format_args!("{}", self.chopper_prescale().bits()), - ) - .field( - "chopper_duty", - &format_args!("{}", self.chopper_duty().bits()), - ) - .field( - "chopper_oshtwth", - &format_args!("{}", self.chopper_oshtwth().bits()), - ) - .field( - "chopper_out_invert", - &format_args!("{}", self.chopper_out_invert().bit()), - ) - .field( - "chopper_in_invert", - &format_args!("{}", self.chopper_in_invert().bit()), - ) + .field("en", &format_args!("{}", self.en().bit())) + .field("prescale", &format_args!("{}", self.prescale().bits())) + .field("duty", &format_args!("{}", self.duty().bits())) + .field("oshtwth", &format_args!("{}", self.oshtwth().bits())) + .field("out_invert", &format_args!("{}", self.out_invert().bit())) + .field("in_invert", &format_args!("{}", self.in_invert().bit())) .finish() } } @@ -96,38 +81,38 @@ impl W { #[doc = "Bit 0 - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] #[inline(always)] #[must_use] - pub fn chopper_en(&mut self) -> CHOPPER_EN_W { - CHOPPER_EN_W::new(self, 0) + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) } #[doc = "Bits 1:4 - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] #[inline(always)] #[must_use] - pub fn chopper_prescale(&mut self) -> CHOPPER_PRESCALE_W { - CHOPPER_PRESCALE_W::new(self, 1) + pub fn prescale(&mut self) -> PRESCALE_W { + PRESCALE_W::new(self, 1) } #[doc = "Bits 5:7 - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] #[inline(always)] #[must_use] - pub fn chopper_duty(&mut self) -> CHOPPER_DUTY_W { - CHOPPER_DUTY_W::new(self, 5) + pub fn duty(&mut self) -> DUTY_W { + DUTY_W::new(self, 5) } #[doc = "Bits 8:11 - Configures width of the first pulse. Measurement unit: Periods of the carrier."] #[inline(always)] #[must_use] - pub fn chopper_oshtwth(&mut self) -> CHOPPER_OSHTWTH_W { - CHOPPER_OSHTWTH_W::new(self, 8) + pub fn oshtwth(&mut self) -> OSHTWTH_W { + OSHTWTH_W::new(self, 8) } #[doc = "Bit 12 - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] #[inline(always)] #[must_use] - pub fn chopper_out_invert(&mut self) -> CHOPPER_OUT_INVERT_W { - CHOPPER_OUT_INVERT_W::new(self, 12) + pub fn out_invert(&mut self) -> OUT_INVERT_W { + OUT_INVERT_W::new(self, 12) } #[doc = "Bit 13 - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] #[inline(always)] #[must_use] - pub fn chopper_in_invert(&mut self) -> CHOPPER_IN_INVERT_W { - CHOPPER_IN_INVERT_W::new(self, 13) + pub fn in_invert(&mut self) -> IN_INVERT_W { + IN_INVERT_W::new(self, 13) } } #[doc = "Carrier0 configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`carrier_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`carrier_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/dt_cfg.rs b/esp32p4/src/mcpwm0/ch/dt_cfg.rs index 22aa5a5ce4..b40359b687 100644 --- a/esp32p4/src/mcpwm0/ch/dt_cfg.rs +++ b/esp32p4/src/mcpwm0/ch/dt_cfg.rs @@ -2,114 +2,114 @@ pub type R = crate::R; #[doc = "Register `DT_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB_FED_UPMETHOD` reader - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type DB_FED_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `DB_FED_UPMETHOD` writer - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type DB_FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DB_RED_UPMETHOD` reader - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type DB_RED_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `DB_RED_UPMETHOD` writer - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type DB_RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DB_DEB_MODE` reader - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] -pub type DB_DEB_MODE_R = crate::BitReader; -#[doc = "Field `DB_DEB_MODE` writer - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] -pub type DB_DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_A_OUTSWAP` reader - Configures S6 in table."] -pub type DB_A_OUTSWAP_R = crate::BitReader; -#[doc = "Field `DB_A_OUTSWAP` writer - Configures S6 in table."] -pub type DB_A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_B_OUTSWAP` reader - Configures S7 in table."] -pub type DB_B_OUTSWAP_R = crate::BitReader; -#[doc = "Field `DB_B_OUTSWAP` writer - Configures S7 in table."] -pub type DB_B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_RED_INSEL` reader - Configures S4 in table."] -pub type DB_RED_INSEL_R = crate::BitReader; -#[doc = "Field `DB_RED_INSEL` writer - Configures S4 in table."] -pub type DB_RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_FED_INSEL` reader - Configures S5 in table."] -pub type DB_FED_INSEL_R = crate::BitReader; -#[doc = "Field `DB_FED_INSEL` writer - Configures S5 in table."] -pub type DB_FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_RED_OUTINVERT` reader - Configures S2 in table."] -pub type DB_RED_OUTINVERT_R = crate::BitReader; -#[doc = "Field `DB_RED_OUTINVERT` writer - Configures S2 in table."] -pub type DB_RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_FED_OUTINVERT` reader - Configures S3 in table."] -pub type DB_FED_OUTINVERT_R = crate::BitReader; -#[doc = "Field `DB_FED_OUTINVERT` writer - Configures S3 in table."] -pub type DB_FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_A_OUTBYPASS` reader - Configures S1 in table."] -pub type DB_A_OUTBYPASS_R = crate::BitReader; -#[doc = "Field `DB_A_OUTBYPASS` writer - Configures S1 in table."] -pub type DB_A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_B_OUTBYPASS` reader - Configures S0 in table."] -pub type DB_B_OUTBYPASS_R = crate::BitReader; -#[doc = "Field `DB_B_OUTBYPASS` writer - Configures S0 in table."] -pub type DB_B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DB_CLK_SEL` reader - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] -pub type DB_CLK_SEL_R = crate::BitReader; -#[doc = "Field `DB_CLK_SEL` writer - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] -pub type DB_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_UPMETHOD` reader - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type FED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `FED_UPMETHOD` writer - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RED_UPMETHOD` reader - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type RED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `RED_UPMETHOD` writer - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DEB_MODE` reader - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DEB_MODE_R = crate::BitReader; +#[doc = "Field `DEB_MODE` writer - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_OUTSWAP` reader - Configures S6 in table."] +pub type A_OUTSWAP_R = crate::BitReader; +#[doc = "Field `A_OUTSWAP` writer - Configures S6 in table."] +pub type A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_OUTSWAP` reader - Configures S7 in table."] +pub type B_OUTSWAP_R = crate::BitReader; +#[doc = "Field `B_OUTSWAP` writer - Configures S7 in table."] +pub type B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RED_INSEL` reader - Configures S4 in table."] +pub type RED_INSEL_R = crate::BitReader; +#[doc = "Field `RED_INSEL` writer - Configures S4 in table."] +pub type RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_INSEL` reader - Configures S5 in table."] +pub type FED_INSEL_R = crate::BitReader; +#[doc = "Field `FED_INSEL` writer - Configures S5 in table."] +pub type FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RED_OUTINVERT` reader - Configures S2 in table."] +pub type RED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `RED_OUTINVERT` writer - Configures S2 in table."] +pub type RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FED_OUTINVERT` reader - Configures S3 in table."] +pub type FED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `FED_OUTINVERT` writer - Configures S3 in table."] +pub type FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_OUTBYPASS` reader - Configures S1 in table."] +pub type A_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `A_OUTBYPASS` writer - Configures S1 in table."] +pub type A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_OUTBYPASS` reader - Configures S0 in table."] +pub type B_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `B_OUTBYPASS` writer - Configures S0 in table."] +pub type B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SEL` reader - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] +pub type CLK_SEL_R = crate::BitReader; +#[doc = "Field `CLK_SEL` writer - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] +pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:3 - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] - pub fn db_fed_upmethod(&self) -> DB_FED_UPMETHOD_R { - DB_FED_UPMETHOD_R::new((self.bits & 0x0f) as u8) + pub fn fed_upmethod(&self) -> FED_UPMETHOD_R { + FED_UPMETHOD_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] - pub fn db_red_upmethod(&self) -> DB_RED_UPMETHOD_R { - DB_RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + pub fn red_upmethod(&self) -> RED_UPMETHOD_R { + RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bit 8 - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] #[inline(always)] - pub fn db_deb_mode(&self) -> DB_DEB_MODE_R { - DB_DEB_MODE_R::new(((self.bits >> 8) & 1) != 0) + pub fn deb_mode(&self) -> DEB_MODE_R { + DEB_MODE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Configures S6 in table."] #[inline(always)] - pub fn db_a_outswap(&self) -> DB_A_OUTSWAP_R { - DB_A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0) + pub fn a_outswap(&self) -> A_OUTSWAP_R { + A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Configures S7 in table."] #[inline(always)] - pub fn db_b_outswap(&self) -> DB_B_OUTSWAP_R { - DB_B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0) + pub fn b_outswap(&self) -> B_OUTSWAP_R { + B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Configures S4 in table."] #[inline(always)] - pub fn db_red_insel(&self) -> DB_RED_INSEL_R { - DB_RED_INSEL_R::new(((self.bits >> 11) & 1) != 0) + pub fn red_insel(&self) -> RED_INSEL_R { + RED_INSEL_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Configures S5 in table."] #[inline(always)] - pub fn db_fed_insel(&self) -> DB_FED_INSEL_R { - DB_FED_INSEL_R::new(((self.bits >> 12) & 1) != 0) + pub fn fed_insel(&self) -> FED_INSEL_R { + FED_INSEL_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Configures S2 in table."] #[inline(always)] - pub fn db_red_outinvert(&self) -> DB_RED_OUTINVERT_R { - DB_RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0) + pub fn red_outinvert(&self) -> RED_OUTINVERT_R { + RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Configures S3 in table."] #[inline(always)] - pub fn db_fed_outinvert(&self) -> DB_FED_OUTINVERT_R { - DB_FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0) + pub fn fed_outinvert(&self) -> FED_OUTINVERT_R { + FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Configures S1 in table."] #[inline(always)] - pub fn db_a_outbypass(&self) -> DB_A_OUTBYPASS_R { - DB_A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0) + pub fn a_outbypass(&self) -> A_OUTBYPASS_R { + A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - Configures S0 in table."] #[inline(always)] - pub fn db_b_outbypass(&self) -> DB_B_OUTBYPASS_R { - DB_B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0) + pub fn b_outbypass(&self) -> B_OUTBYPASS_R { + B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] #[inline(always)] - pub fn db_clk_sel(&self) -> DB_CLK_SEL_R { - DB_CLK_SEL_R::new(((self.bits >> 17) & 1) != 0) + pub fn clk_sel(&self) -> CLK_SEL_R { + CLK_SEL_R::new(((self.bits >> 17) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -117,47 +117,29 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_CFG") .field( - "db_fed_upmethod", - &format_args!("{}", self.db_fed_upmethod().bits()), + "fed_upmethod", + &format_args!("{}", self.fed_upmethod().bits()), ) .field( - "db_red_upmethod", - &format_args!("{}", self.db_red_upmethod().bits()), + "red_upmethod", + &format_args!("{}", self.red_upmethod().bits()), ) - .field("db_deb_mode", &format_args!("{}", self.db_deb_mode().bit())) + .field("deb_mode", &format_args!("{}", self.deb_mode().bit())) + .field("a_outswap", &format_args!("{}", self.a_outswap().bit())) + .field("b_outswap", &format_args!("{}", self.b_outswap().bit())) + .field("red_insel", &format_args!("{}", self.red_insel().bit())) + .field("fed_insel", &format_args!("{}", self.fed_insel().bit())) .field( - "db_a_outswap", - &format_args!("{}", self.db_a_outswap().bit()), + "red_outinvert", + &format_args!("{}", self.red_outinvert().bit()), ) .field( - "db_b_outswap", - &format_args!("{}", self.db_b_outswap().bit()), + "fed_outinvert", + &format_args!("{}", self.fed_outinvert().bit()), ) - .field( - "db_red_insel", - &format_args!("{}", self.db_red_insel().bit()), - ) - .field( - "db_fed_insel", - &format_args!("{}", self.db_fed_insel().bit()), - ) - .field( - "db_red_outinvert", - &format_args!("{}", self.db_red_outinvert().bit()), - ) - .field( - "db_fed_outinvert", - &format_args!("{}", self.db_fed_outinvert().bit()), - ) - .field( - "db_a_outbypass", - &format_args!("{}", self.db_a_outbypass().bit()), - ) - .field( - "db_b_outbypass", - &format_args!("{}", self.db_b_outbypass().bit()), - ) - .field("db_clk_sel", &format_args!("{}", self.db_clk_sel().bit())) + .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit())) + .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit())) + .field("clk_sel", &format_args!("{}", self.clk_sel().bit())) .finish() } } @@ -171,74 +153,74 @@ impl W { #[doc = "Bits 0:3 - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] #[must_use] - pub fn db_fed_upmethod(&mut self) -> DB_FED_UPMETHOD_W { - DB_FED_UPMETHOD_W::new(self, 0) + pub fn fed_upmethod(&mut self) -> FED_UPMETHOD_W { + FED_UPMETHOD_W::new(self, 0) } #[doc = "Bits 4:7 - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] #[must_use] - pub fn db_red_upmethod(&mut self) -> DB_RED_UPMETHOD_W { - DB_RED_UPMETHOD_W::new(self, 4) + pub fn red_upmethod(&mut self) -> RED_UPMETHOD_W { + RED_UPMETHOD_W::new(self, 4) } #[doc = "Bit 8 - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] #[inline(always)] #[must_use] - pub fn db_deb_mode(&mut self) -> DB_DEB_MODE_W { - DB_DEB_MODE_W::new(self, 8) + pub fn deb_mode(&mut self) -> DEB_MODE_W { + DEB_MODE_W::new(self, 8) } #[doc = "Bit 9 - Configures S6 in table."] #[inline(always)] #[must_use] - pub fn db_a_outswap(&mut self) -> DB_A_OUTSWAP_W { - DB_A_OUTSWAP_W::new(self, 9) + pub fn a_outswap(&mut self) -> A_OUTSWAP_W { + A_OUTSWAP_W::new(self, 9) } #[doc = "Bit 10 - Configures S7 in table."] #[inline(always)] #[must_use] - pub fn db_b_outswap(&mut self) -> DB_B_OUTSWAP_W { - DB_B_OUTSWAP_W::new(self, 10) + pub fn b_outswap(&mut self) -> B_OUTSWAP_W { + B_OUTSWAP_W::new(self, 10) } #[doc = "Bit 11 - Configures S4 in table."] #[inline(always)] #[must_use] - pub fn db_red_insel(&mut self) -> DB_RED_INSEL_W { - DB_RED_INSEL_W::new(self, 11) + pub fn red_insel(&mut self) -> RED_INSEL_W { + RED_INSEL_W::new(self, 11) } #[doc = "Bit 12 - Configures S5 in table."] #[inline(always)] #[must_use] - pub fn db_fed_insel(&mut self) -> DB_FED_INSEL_W { - DB_FED_INSEL_W::new(self, 12) + pub fn fed_insel(&mut self) -> FED_INSEL_W { + FED_INSEL_W::new(self, 12) } #[doc = "Bit 13 - Configures S2 in table."] #[inline(always)] #[must_use] - pub fn db_red_outinvert(&mut self) -> DB_RED_OUTINVERT_W { - DB_RED_OUTINVERT_W::new(self, 13) + pub fn red_outinvert(&mut self) -> RED_OUTINVERT_W { + RED_OUTINVERT_W::new(self, 13) } #[doc = "Bit 14 - Configures S3 in table."] #[inline(always)] #[must_use] - pub fn db_fed_outinvert(&mut self) -> DB_FED_OUTINVERT_W { - DB_FED_OUTINVERT_W::new(self, 14) + pub fn fed_outinvert(&mut self) -> FED_OUTINVERT_W { + FED_OUTINVERT_W::new(self, 14) } #[doc = "Bit 15 - Configures S1 in table."] #[inline(always)] #[must_use] - pub fn db_a_outbypass(&mut self) -> DB_A_OUTBYPASS_W { - DB_A_OUTBYPASS_W::new(self, 15) + pub fn a_outbypass(&mut self) -> A_OUTBYPASS_W { + A_OUTBYPASS_W::new(self, 15) } #[doc = "Bit 16 - Configures S0 in table."] #[inline(always)] #[must_use] - pub fn db_b_outbypass(&mut self) -> DB_B_OUTBYPASS_W { - DB_B_OUTBYPASS_W::new(self, 16) + pub fn b_outbypass(&mut self) -> B_OUTBYPASS_W { + B_OUTBYPASS_W::new(self, 16) } #[doc = "Bit 17 - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] #[inline(always)] #[must_use] - pub fn db_clk_sel(&mut self) -> DB_CLK_SEL_W { - DB_CLK_SEL_W::new(self, 17) + pub fn clk_sel(&mut self) -> CLK_SEL_W { + CLK_SEL_W::new(self, 17) } } #[doc = "Dead time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs index 4003c94be8..2ebbae2fcf 100644 --- a/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs +++ b/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `DT_FED_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB_FED` reader - Configures shadow register for FED."] -pub type DB_FED_R = crate::FieldReader; -#[doc = "Field `DB_FED` writer - Configures shadow register for FED."] -pub type DB_FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `FED` reader - Configures shadow register for FED."] +pub type FED_R = crate::FieldReader; +#[doc = "Field `FED` writer - Configures shadow register for FED."] +pub type FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Configures shadow register for FED."] #[inline(always)] - pub fn db_fed(&self) -> DB_FED_R { - DB_FED_R::new((self.bits & 0xffff) as u16) + pub fn fed(&self) -> FED_R { + FED_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_FED_CFG") - .field("db_fed", &format_args!("{}", self.db_fed().bits())) + .field("fed", &format_args!("{}", self.fed().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Configures shadow register for FED."] #[inline(always)] #[must_use] - pub fn db_fed(&mut self) -> DB_FED_W { - DB_FED_W::new(self, 0) + pub fn fed(&mut self) -> FED_W { + FED_W::new(self, 0) } } #[doc = "Falling edge delay (FED) shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_fed_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_fed_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs b/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs index 633c5fa4cf..c0c2ff1cc7 100644 --- a/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs +++ b/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `DT_RED_CFG` writer"] pub type W = crate::W; -#[doc = "Field `DB_RED` reader - Configures shadow register for RED."] -pub type DB_RED_R = crate::FieldReader; -#[doc = "Field `DB_RED` writer - Configures shadow register for RED."] -pub type DB_RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `RED` reader - Configures shadow register for RED."] +pub type RED_R = crate::FieldReader; +#[doc = "Field `RED` writer - Configures shadow register for RED."] +pub type RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Configures shadow register for RED."] #[inline(always)] - pub fn db_red(&self) -> DB_RED_R { - DB_RED_R::new((self.bits & 0xffff) as u16) + pub fn red(&self) -> RED_R { + RED_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("DT_RED_CFG") - .field("db_red", &format_args!("{}", self.db_red().bits())) + .field("red", &format_args!("{}", self.red().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Configures shadow register for RED."] #[inline(always)] #[must_use] - pub fn db_red(&mut self) -> DB_RED_W { - DB_RED_W::new(self, 0) + pub fn red(&mut self) -> RED_W { + RED_W::new(self, 0) } } #[doc = "Rising edge delay (RED) shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_red_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_red_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/fh_cfg0.rs b/esp32p4/src/mcpwm0/ch/fh_cfg0.rs index f838f2787f..eb6f0e8a2a 100644 --- a/esp32p4/src/mcpwm0/ch/fh_cfg0.rs +++ b/esp32p4/src/mcpwm0/ch/fh_cfg0.rs @@ -2,172 +2,172 @@ pub type R = crate::R; #[doc = "Register `FH_CFG0` writer"] pub type W = crate::W; -#[doc = "Field `TZ_SW_CBC` reader - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_SW_CBC_R = crate::BitReader; -#[doc = "Field `TZ_SW_CBC` writer - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_F2_CBC` reader - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F2_CBC_R = crate::BitReader; -#[doc = "Field `TZ_F2_CBC` writer - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_F1_CBC` reader - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F1_CBC_R = crate::BitReader; -#[doc = "Field `TZ_F1_CBC` writer - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_F0_CBC` reader - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F0_CBC_R = crate::BitReader; -#[doc = "Field `TZ_F0_CBC` writer - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_SW_OST` reader - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_SW_OST_R = crate::BitReader; -#[doc = "Field `TZ_SW_OST` writer - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_F2_OST` reader - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F2_OST_R = crate::BitReader; -#[doc = "Field `TZ_F2_OST` writer - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_F1_OST` reader - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F1_OST_R = crate::BitReader; -#[doc = "Field `TZ_F1_OST` writer - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_F0_OST` reader - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F0_OST_R = crate::BitReader; -#[doc = "Field `TZ_F0_OST` writer - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] -pub type TZ_F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_A_CBC_D` reader - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_CBC_D_R = crate::FieldReader; -#[doc = "Field `TZ_A_CBC_D` writer - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_A_CBC_U` reader - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_CBC_U_R = crate::FieldReader; -#[doc = "Field `TZ_A_CBC_U` writer - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_A_OST_D` reader - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_OST_D_R = crate::FieldReader; -#[doc = "Field `TZ_A_OST_D` writer - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_A_OST_U` reader - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_OST_U_R = crate::FieldReader; -#[doc = "Field `TZ_A_OST_U` writer - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_B_CBC_D` reader - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_CBC_D_R = crate::FieldReader; -#[doc = "Field `TZ_B_CBC_D` writer - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_B_CBC_U` reader - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_CBC_U_R = crate::FieldReader; -#[doc = "Field `TZ_B_CBC_U` writer - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_B_OST_D` reader - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_OST_D_R = crate::FieldReader; -#[doc = "Field `TZ_B_OST_D` writer - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_B_OST_U` reader - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_OST_U_R = crate::FieldReader; -#[doc = "Field `TZ_B_OST_U` writer - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] -pub type TZ_B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SW_CBC` reader - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type SW_CBC_R = crate::BitReader; +#[doc = "Field `SW_CBC` writer - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_CBC` reader - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type F2_CBC_R = crate::BitReader; +#[doc = "Field `F2_CBC` writer - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_CBC` reader - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type F1_CBC_R = crate::BitReader; +#[doc = "Field `F1_CBC` writer - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F0_CBC` reader - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type F0_CBC_R = crate::BitReader; +#[doc = "Field `F0_CBC` writer - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_OST` reader - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type SW_OST_R = crate::BitReader; +#[doc = "Field `SW_OST` writer - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_OST` reader - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type F2_OST_R = crate::BitReader; +#[doc = "Field `F2_OST` writer - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_OST` reader - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type F1_OST_R = crate::BitReader; +#[doc = "Field `F1_OST` writer - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F0_OST` reader - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type F0_OST_R = crate::BitReader; +#[doc = "Field `F0_OST` writer - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_CBC_D` reader - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_CBC_D_R = crate::FieldReader; +#[doc = "Field `A_CBC_D` writer - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_CBC_U` reader - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_CBC_U_R = crate::FieldReader; +#[doc = "Field `A_CBC_U` writer - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_OST_D` reader - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_OST_D_R = crate::FieldReader; +#[doc = "Field `A_OST_D` writer - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `A_OST_U` reader - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_OST_U_R = crate::FieldReader; +#[doc = "Field `A_OST_U` writer - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_CBC_D` reader - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_CBC_D_R = crate::FieldReader; +#[doc = "Field `B_CBC_D` writer - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_CBC_U` reader - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_CBC_U_R = crate::FieldReader; +#[doc = "Field `B_CBC_U` writer - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_OST_D` reader - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_OST_D_R = crate::FieldReader; +#[doc = "Field `B_OST_D` writer - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `B_OST_U` reader - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_OST_U_R = crate::FieldReader; +#[doc = "Field `B_OST_U` writer - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bit 0 - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_sw_cbc(&self) -> TZ_SW_CBC_R { - TZ_SW_CBC_R::new((self.bits & 1) != 0) + pub fn sw_cbc(&self) -> SW_CBC_R { + SW_CBC_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_f2_cbc(&self) -> TZ_F2_CBC_R { - TZ_F2_CBC_R::new(((self.bits >> 1) & 1) != 0) + pub fn f2_cbc(&self) -> F2_CBC_R { + F2_CBC_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_f1_cbc(&self) -> TZ_F1_CBC_R { - TZ_F1_CBC_R::new(((self.bits >> 2) & 1) != 0) + pub fn f1_cbc(&self) -> F1_CBC_R { + F1_CBC_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_f0_cbc(&self) -> TZ_F0_CBC_R { - TZ_F0_CBC_R::new(((self.bits >> 3) & 1) != 0) + pub fn f0_cbc(&self) -> F0_CBC_R { + F0_CBC_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_sw_ost(&self) -> TZ_SW_OST_R { - TZ_SW_OST_R::new(((self.bits >> 4) & 1) != 0) + pub fn sw_ost(&self) -> SW_OST_R { + SW_OST_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_f2_ost(&self) -> TZ_F2_OST_R { - TZ_F2_OST_R::new(((self.bits >> 5) & 1) != 0) + pub fn f2_ost(&self) -> F2_OST_R { + F2_OST_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_f1_ost(&self) -> TZ_F1_OST_R { - TZ_F1_OST_R::new(((self.bits >> 6) & 1) != 0) + pub fn f1_ost(&self) -> F1_OST_R { + F1_OST_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] - pub fn tz_f0_ost(&self) -> TZ_F0_OST_R { - TZ_F0_OST_R::new(((self.bits >> 7) & 1) != 0) + pub fn f0_ost(&self) -> F0_OST_R { + F0_OST_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bits 8:9 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_a_cbc_d(&self) -> TZ_A_CBC_D_R { - TZ_A_CBC_D_R::new(((self.bits >> 8) & 3) as u8) + pub fn a_cbc_d(&self) -> A_CBC_D_R { + A_CBC_D_R::new(((self.bits >> 8) & 3) as u8) } #[doc = "Bits 10:11 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_a_cbc_u(&self) -> TZ_A_CBC_U_R { - TZ_A_CBC_U_R::new(((self.bits >> 10) & 3) as u8) + pub fn a_cbc_u(&self) -> A_CBC_U_R { + A_CBC_U_R::new(((self.bits >> 10) & 3) as u8) } #[doc = "Bits 12:13 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_a_ost_d(&self) -> TZ_A_OST_D_R { - TZ_A_OST_D_R::new(((self.bits >> 12) & 3) as u8) + pub fn a_ost_d(&self) -> A_OST_D_R { + A_OST_D_R::new(((self.bits >> 12) & 3) as u8) } #[doc = "Bits 14:15 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_a_ost_u(&self) -> TZ_A_OST_U_R { - TZ_A_OST_U_R::new(((self.bits >> 14) & 3) as u8) + pub fn a_ost_u(&self) -> A_OST_U_R { + A_OST_U_R::new(((self.bits >> 14) & 3) as u8) } #[doc = "Bits 16:17 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_b_cbc_d(&self) -> TZ_B_CBC_D_R { - TZ_B_CBC_D_R::new(((self.bits >> 16) & 3) as u8) + pub fn b_cbc_d(&self) -> B_CBC_D_R { + B_CBC_D_R::new(((self.bits >> 16) & 3) as u8) } #[doc = "Bits 18:19 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_b_cbc_u(&self) -> TZ_B_CBC_U_R { - TZ_B_CBC_U_R::new(((self.bits >> 18) & 3) as u8) + pub fn b_cbc_u(&self) -> B_CBC_U_R { + B_CBC_U_R::new(((self.bits >> 18) & 3) as u8) } #[doc = "Bits 20:21 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_b_ost_d(&self) -> TZ_B_OST_D_R { - TZ_B_OST_D_R::new(((self.bits >> 20) & 3) as u8) + pub fn b_ost_d(&self) -> B_OST_D_R { + B_OST_D_R::new(((self.bits >> 20) & 3) as u8) } #[doc = "Bits 22:23 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] - pub fn tz_b_ost_u(&self) -> TZ_B_OST_U_R { - TZ_B_OST_U_R::new(((self.bits >> 22) & 3) as u8) + pub fn b_ost_u(&self) -> B_OST_U_R { + B_OST_U_R::new(((self.bits >> 22) & 3) as u8) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_CFG0") - .field("tz_sw_cbc", &format_args!("{}", self.tz_sw_cbc().bit())) - .field("tz_f2_cbc", &format_args!("{}", self.tz_f2_cbc().bit())) - .field("tz_f1_cbc", &format_args!("{}", self.tz_f1_cbc().bit())) - .field("tz_f0_cbc", &format_args!("{}", self.tz_f0_cbc().bit())) - .field("tz_sw_ost", &format_args!("{}", self.tz_sw_ost().bit())) - .field("tz_f2_ost", &format_args!("{}", self.tz_f2_ost().bit())) - .field("tz_f1_ost", &format_args!("{}", self.tz_f1_ost().bit())) - .field("tz_f0_ost", &format_args!("{}", self.tz_f0_ost().bit())) - .field("tz_a_cbc_d", &format_args!("{}", self.tz_a_cbc_d().bits())) - .field("tz_a_cbc_u", &format_args!("{}", self.tz_a_cbc_u().bits())) - .field("tz_a_ost_d", &format_args!("{}", self.tz_a_ost_d().bits())) - .field("tz_a_ost_u", &format_args!("{}", self.tz_a_ost_u().bits())) - .field("tz_b_cbc_d", &format_args!("{}", self.tz_b_cbc_d().bits())) - .field("tz_b_cbc_u", &format_args!("{}", self.tz_b_cbc_u().bits())) - .field("tz_b_ost_d", &format_args!("{}", self.tz_b_ost_d().bits())) - .field("tz_b_ost_u", &format_args!("{}", self.tz_b_ost_u().bits())) + .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit())) + .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit())) + .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit())) + .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit())) + .field("sw_ost", &format_args!("{}", self.sw_ost().bit())) + .field("f2_ost", &format_args!("{}", self.f2_ost().bit())) + .field("f1_ost", &format_args!("{}", self.f1_ost().bit())) + .field("f0_ost", &format_args!("{}", self.f0_ost().bit())) + .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits())) + .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits())) + .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits())) + .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits())) + .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits())) + .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits())) + .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits())) + .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits())) .finish() } } @@ -181,98 +181,98 @@ impl W { #[doc = "Bit 0 - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_sw_cbc(&mut self) -> TZ_SW_CBC_W { - TZ_SW_CBC_W::new(self, 0) + pub fn sw_cbc(&mut self) -> SW_CBC_W { + SW_CBC_W::new(self, 0) } #[doc = "Bit 1 - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_f2_cbc(&mut self) -> TZ_F2_CBC_W { - TZ_F2_CBC_W::new(self, 1) + pub fn f2_cbc(&mut self) -> F2_CBC_W { + F2_CBC_W::new(self, 1) } #[doc = "Bit 2 - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_f1_cbc(&mut self) -> TZ_F1_CBC_W { - TZ_F1_CBC_W::new(self, 2) + pub fn f1_cbc(&mut self) -> F1_CBC_W { + F1_CBC_W::new(self, 2) } #[doc = "Bit 3 - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_f0_cbc(&mut self) -> TZ_F0_CBC_W { - TZ_F0_CBC_W::new(self, 3) + pub fn f0_cbc(&mut self) -> F0_CBC_W { + F0_CBC_W::new(self, 3) } #[doc = "Bit 4 - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_sw_ost(&mut self) -> TZ_SW_OST_W { - TZ_SW_OST_W::new(self, 4) + pub fn sw_ost(&mut self) -> SW_OST_W { + SW_OST_W::new(self, 4) } #[doc = "Bit 5 - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_f2_ost(&mut self) -> TZ_F2_OST_W { - TZ_F2_OST_W::new(self, 5) + pub fn f2_ost(&mut self) -> F2_OST_W { + F2_OST_W::new(self, 5) } #[doc = "Bit 6 - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_f1_ost(&mut self) -> TZ_F1_OST_W { - TZ_F1_OST_W::new(self, 6) + pub fn f1_ost(&mut self) -> F1_OST_W { + F1_OST_W::new(self, 6) } #[doc = "Bit 7 - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] #[inline(always)] #[must_use] - pub fn tz_f0_ost(&mut self) -> TZ_F0_OST_W { - TZ_F0_OST_W::new(self, 7) + pub fn f0_ost(&mut self) -> F0_OST_W { + F0_OST_W::new(self, 7) } #[doc = "Bits 8:9 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_a_cbc_d(&mut self) -> TZ_A_CBC_D_W { - TZ_A_CBC_D_W::new(self, 8) + pub fn a_cbc_d(&mut self) -> A_CBC_D_W { + A_CBC_D_W::new(self, 8) } #[doc = "Bits 10:11 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_a_cbc_u(&mut self) -> TZ_A_CBC_U_W { - TZ_A_CBC_U_W::new(self, 10) + pub fn a_cbc_u(&mut self) -> A_CBC_U_W { + A_CBC_U_W::new(self, 10) } #[doc = "Bits 12:13 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_a_ost_d(&mut self) -> TZ_A_OST_D_W { - TZ_A_OST_D_W::new(self, 12) + pub fn a_ost_d(&mut self) -> A_OST_D_W { + A_OST_D_W::new(self, 12) } #[doc = "Bits 14:15 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_a_ost_u(&mut self) -> TZ_A_OST_U_W { - TZ_A_OST_U_W::new(self, 14) + pub fn a_ost_u(&mut self) -> A_OST_U_W { + A_OST_U_W::new(self, 14) } #[doc = "Bits 16:17 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_b_cbc_d(&mut self) -> TZ_B_CBC_D_W { - TZ_B_CBC_D_W::new(self, 16) + pub fn b_cbc_d(&mut self) -> B_CBC_D_W { + B_CBC_D_W::new(self, 16) } #[doc = "Bits 18:19 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_b_cbc_u(&mut self) -> TZ_B_CBC_U_W { - TZ_B_CBC_U_W::new(self, 18) + pub fn b_cbc_u(&mut self) -> B_CBC_U_W { + B_CBC_U_W::new(self, 18) } #[doc = "Bits 20:21 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_b_ost_d(&mut self) -> TZ_B_OST_D_W { - TZ_B_OST_D_W::new(self, 20) + pub fn b_ost_d(&mut self) -> B_OST_D_W { + B_OST_D_W::new(self, 20) } #[doc = "Bits 22:23 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] #[inline(always)] #[must_use] - pub fn tz_b_ost_u(&mut self) -> TZ_B_OST_U_W { - TZ_B_OST_U_W::new(self, 22) + pub fn b_ost_u(&mut self) -> B_OST_U_W { + B_OST_U_W::new(self, 22) } } #[doc = "PWM0 A and PWM0 B trip events actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/fh_cfg1.rs b/esp32p4/src/mcpwm0/ch/fh_cfg1.rs index c18aa32865..1b7b8ab8ab 100644 --- a/esp32p4/src/mcpwm0/ch/fh_cfg1.rs +++ b/esp32p4/src/mcpwm0/ch/fh_cfg1.rs @@ -2,61 +2,52 @@ pub type R = crate::R; #[doc = "Register `FH_CFG1` writer"] pub type W = crate::W; -#[doc = "Field `TZ_CLR_OST` reader - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] -pub type TZ_CLR_OST_R = crate::BitReader; -#[doc = "Field `TZ_CLR_OST` writer - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] -pub type TZ_CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_CBCPULSE` reader - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] -pub type TZ_CBCPULSE_R = crate::FieldReader; -#[doc = "Field `TZ_CBCPULSE` writer - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] -pub type TZ_CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `TZ_FORCE_CBC` reader - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] -pub type TZ_FORCE_CBC_R = crate::BitReader; -#[doc = "Field `TZ_FORCE_CBC` writer - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] -pub type TZ_FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TZ_FORCE_OST` reader - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] -pub type TZ_FORCE_OST_R = crate::BitReader; -#[doc = "Field `TZ_FORCE_OST` writer - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] -pub type TZ_FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR_OST` reader - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] +pub type CLR_OST_R = crate::BitReader; +#[doc = "Field `CLR_OST` writer - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] +pub type CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CBCPULSE` reader - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] +pub type CBCPULSE_R = crate::FieldReader; +#[doc = "Field `CBCPULSE` writer - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] +pub type CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FORCE_CBC` reader - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] +pub type FORCE_CBC_R = crate::BitReader; +#[doc = "Field `FORCE_CBC` writer - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] +pub type FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_OST` reader - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] +pub type FORCE_OST_R = crate::BitReader; +#[doc = "Field `FORCE_OST` writer - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] +pub type FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] #[inline(always)] - pub fn tz_clr_ost(&self) -> TZ_CLR_OST_R { - TZ_CLR_OST_R::new((self.bits & 1) != 0) + pub fn clr_ost(&self) -> CLR_OST_R { + CLR_OST_R::new((self.bits & 1) != 0) } #[doc = "Bits 1:2 - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] #[inline(always)] - pub fn tz_cbcpulse(&self) -> TZ_CBCPULSE_R { - TZ_CBCPULSE_R::new(((self.bits >> 1) & 3) as u8) + pub fn cbcpulse(&self) -> CBCPULSE_R { + CBCPULSE_R::new(((self.bits >> 1) & 3) as u8) } #[doc = "Bit 3 - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] #[inline(always)] - pub fn tz_force_cbc(&self) -> TZ_FORCE_CBC_R { - TZ_FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0) + pub fn force_cbc(&self) -> FORCE_CBC_R { + FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] #[inline(always)] - pub fn tz_force_ost(&self) -> TZ_FORCE_OST_R { - TZ_FORCE_OST_R::new(((self.bits >> 4) & 1) != 0) + pub fn force_ost(&self) -> FORCE_OST_R { + FORCE_OST_R::new(((self.bits >> 4) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_CFG1") - .field("tz_clr_ost", &format_args!("{}", self.tz_clr_ost().bit())) - .field( - "tz_cbcpulse", - &format_args!("{}", self.tz_cbcpulse().bits()), - ) - .field( - "tz_force_cbc", - &format_args!("{}", self.tz_force_cbc().bit()), - ) - .field( - "tz_force_ost", - &format_args!("{}", self.tz_force_ost().bit()), - ) + .field("clr_ost", &format_args!("{}", self.clr_ost().bit())) + .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits())) + .field("force_cbc", &format_args!("{}", self.force_cbc().bit())) + .field("force_ost", &format_args!("{}", self.force_ost().bit())) .finish() } } @@ -70,26 +61,26 @@ impl W { #[doc = "Bit 0 - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] #[inline(always)] #[must_use] - pub fn tz_clr_ost(&mut self) -> TZ_CLR_OST_W { - TZ_CLR_OST_W::new(self, 0) + pub fn clr_ost(&mut self) -> CLR_OST_W { + CLR_OST_W::new(self, 0) } #[doc = "Bits 1:2 - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] #[inline(always)] #[must_use] - pub fn tz_cbcpulse(&mut self) -> TZ_CBCPULSE_W { - TZ_CBCPULSE_W::new(self, 1) + pub fn cbcpulse(&mut self) -> CBCPULSE_W { + CBCPULSE_W::new(self, 1) } #[doc = "Bit 3 - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] #[inline(always)] #[must_use] - pub fn tz_force_cbc(&mut self) -> TZ_FORCE_CBC_W { - TZ_FORCE_CBC_W::new(self, 3) + pub fn force_cbc(&mut self) -> FORCE_CBC_W { + FORCE_CBC_W::new(self, 3) } #[doc = "Bit 4 - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] #[inline(always)] #[must_use] - pub fn tz_force_ost(&mut self) -> TZ_FORCE_OST_W { - TZ_FORCE_OST_W::new(self, 4) + pub fn force_ost(&mut self) -> FORCE_OST_W { + FORCE_OST_W::new(self, 4) } } #[doc = "Software triggers for fault handler actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/fh_status.rs b/esp32p4/src/mcpwm0/ch/fh_status.rs index a486bc481f..dc84ac9ee3 100644 --- a/esp32p4/src/mcpwm0/ch/fh_status.rs +++ b/esp32p4/src/mcpwm0/ch/fh_status.rs @@ -1,27 +1,27 @@ #[doc = "Register `FH_STATUS` reader"] pub type R = crate::R; -#[doc = "Field `TZ_CBC_ON` reader - Represents whether or not an cycle-by-cycle mode action is on going.\\\\0:No action\\\\1: On going"] -pub type TZ_CBC_ON_R = crate::BitReader; -#[doc = "Field `TZ_OST_ON` reader - Represents whether or not an one-shot mode action is on going.\\\\0:No action\\\\1: On going"] -pub type TZ_OST_ON_R = crate::BitReader; +#[doc = "Field `CBC_ON` reader - Represents whether or not an cycle-by-cycle mode action is on going.\\\\0:No action\\\\1: On going"] +pub type CBC_ON_R = crate::BitReader; +#[doc = "Field `OST_ON` reader - Represents whether or not an one-shot mode action is on going.\\\\0:No action\\\\1: On going"] +pub type OST_ON_R = crate::BitReader; impl R { #[doc = "Bit 0 - Represents whether or not an cycle-by-cycle mode action is on going.\\\\0:No action\\\\1: On going"] #[inline(always)] - pub fn tz_cbc_on(&self) -> TZ_CBC_ON_R { - TZ_CBC_ON_R::new((self.bits & 1) != 0) + pub fn cbc_on(&self) -> CBC_ON_R { + CBC_ON_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Represents whether or not an one-shot mode action is on going.\\\\0:No action\\\\1: On going"] #[inline(always)] - pub fn tz_ost_on(&self) -> TZ_OST_ON_R { - TZ_OST_ON_R::new(((self.bits >> 1) & 1) != 0) + pub fn ost_on(&self) -> OST_ON_R { + OST_ON_R::new(((self.bits >> 1) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("FH_STATUS") - .field("tz_cbc_on", &format_args!("{}", self.tz_cbc_on().bit())) - .field("tz_ost_on", &format_args!("{}", self.tz_ost_on().bit())) + .field("cbc_on", &format_args!("{}", self.cbc_on().bit())) + .field("ost_on", &format_args!("{}", self.ost_on().bit())) .finish() } } diff --git a/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs index a8cec6d147..9f2eabbd91 100644 --- a/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs +++ b/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs @@ -2,64 +2,52 @@ pub type R = crate::R; #[doc = "Register `GEN_STMP_CFG` writer"] pub type W = crate::W; -#[doc = "Field `CMPR_A_UPMETHOD` reader - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type CMPR_A_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `CMPR_A_UPMETHOD` writer - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type CMPR_A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CMPR_B_UPMETHOD` reader - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type CMPR_B_UPMETHOD_R = crate::FieldReader; -#[doc = "Field `CMPR_B_UPMETHOD` writer - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] -pub type CMPR_B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CMPR_A_SHDW_FULL` reader - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] -pub type CMPR_A_SHDW_FULL_R = crate::BitReader; -#[doc = "Field `CMPR_A_SHDW_FULL` writer - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] -pub type CMPR_A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMPR_B_SHDW_FULL` reader - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] -pub type CMPR_B_SHDW_FULL_R = crate::BitReader; -#[doc = "Field `CMPR_B_SHDW_FULL` writer - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] -pub type CMPR_B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_UPMETHOD` reader - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type A_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `A_UPMETHOD` writer - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `B_UPMETHOD` reader - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type B_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `B_UPMETHOD` writer - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `A_SHDW_FULL` reader - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] +pub type A_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `A_SHDW_FULL` writer - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] +pub type A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_SHDW_FULL` reader - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] +pub type B_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `B_SHDW_FULL` writer - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] +pub type B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:3 - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] - pub fn cmpr_a_upmethod(&self) -> CMPR_A_UPMETHOD_R { - CMPR_A_UPMETHOD_R::new((self.bits & 0x0f) as u8) + pub fn a_upmethod(&self) -> A_UPMETHOD_R { + A_UPMETHOD_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] - pub fn cmpr_b_upmethod(&self) -> CMPR_B_UPMETHOD_R { - CMPR_B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + pub fn b_upmethod(&self) -> B_UPMETHOD_R { + B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bit 8 - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] #[inline(always)] - pub fn cmpr_a_shdw_full(&self) -> CMPR_A_SHDW_FULL_R { - CMPR_A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0) + pub fn a_shdw_full(&self) -> A_SHDW_FULL_R { + A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] #[inline(always)] - pub fn cmpr_b_shdw_full(&self) -> CMPR_B_SHDW_FULL_R { - CMPR_B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0) + pub fn b_shdw_full(&self) -> B_SHDW_FULL_R { + B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_STMP_CFG") - .field( - "cmpr_a_upmethod", - &format_args!("{}", self.cmpr_a_upmethod().bits()), - ) - .field( - "cmpr_b_upmethod", - &format_args!("{}", self.cmpr_b_upmethod().bits()), - ) - .field( - "cmpr_a_shdw_full", - &format_args!("{}", self.cmpr_a_shdw_full().bit()), - ) - .field( - "cmpr_b_shdw_full", - &format_args!("{}", self.cmpr_b_shdw_full().bit()), - ) + .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits())) + .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits())) + .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit())) + .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit())) .finish() } } @@ -73,26 +61,26 @@ impl W { #[doc = "Bits 0:3 - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] #[must_use] - pub fn cmpr_a_upmethod(&mut self) -> CMPR_A_UPMETHOD_W { - CMPR_A_UPMETHOD_W::new(self, 0) + pub fn a_upmethod(&mut self) -> A_UPMETHOD_W { + A_UPMETHOD_W::new(self, 0) } #[doc = "Bits 4:7 - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] #[inline(always)] #[must_use] - pub fn cmpr_b_upmethod(&mut self) -> CMPR_B_UPMETHOD_W { - CMPR_B_UPMETHOD_W::new(self, 4) + pub fn b_upmethod(&mut self) -> B_UPMETHOD_W { + B_UPMETHOD_W::new(self, 4) } #[doc = "Bit 8 - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] #[inline(always)] #[must_use] - pub fn cmpr_a_shdw_full(&mut self) -> CMPR_A_SHDW_FULL_W { - CMPR_A_SHDW_FULL_W::new(self, 8) + pub fn a_shdw_full(&mut self) -> A_SHDW_FULL_W { + A_SHDW_FULL_W::new(self, 8) } #[doc = "Bit 9 - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] #[inline(always)] #[must_use] - pub fn cmpr_b_shdw_full(&mut self) -> CMPR_B_SHDW_FULL_W { - CMPR_B_SHDW_FULL_W::new(self, 9) + pub fn b_shdw_full(&mut self) -> B_SHDW_FULL_W { + B_SHDW_FULL_W::new(self, 9) } } #[doc = "Generator0 time stamp registers A and B transfer status and update method register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_stmp_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_stmp_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs index 9350ae448f..6f4cfe411a 100644 --- a/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs +++ b/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `GEN_TSTMP_A` writer"] pub type W = crate::W; -#[doc = "Field `CMPR_A` reader - Configures the value of PWM generator %s time stamp A's shadow register."] -pub type CMPR_A_R = crate::FieldReader; -#[doc = "Field `CMPR_A` writer - Configures the value of PWM generator %s time stamp A's shadow register."] -pub type CMPR_A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `A` reader - Configures the value of PWM generator %s time stamp A's shadow register."] +pub type A_R = crate::FieldReader; +#[doc = "Field `A` writer - Configures the value of PWM generator %s time stamp A's shadow register."] +pub type A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp A's shadow register."] #[inline(always)] - pub fn cmpr_a(&self) -> CMPR_A_R { - CMPR_A_R::new((self.bits & 0xffff) as u16) + pub fn a(&self) -> A_R { + A_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_TSTMP_A") - .field("cmpr_a", &format_args!("{}", self.cmpr_a().bits())) + .field("a", &format_args!("{}", self.a().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp A's shadow register."] #[inline(always)] #[must_use] - pub fn cmpr_a(&mut self) -> CMPR_A_W { - CMPR_A_W::new(self, 0) + pub fn a(&mut self) -> A_W { + A_W::new(self, 0) } } #[doc = "Generator0 time stamp A's shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs index 118df2f14b..7e48408c0c 100644 --- a/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs +++ b/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs @@ -2,22 +2,22 @@ pub type R = crate::R; #[doc = "Register `GEN_TSTMP_B` writer"] pub type W = crate::W; -#[doc = "Field `CMPR_B` reader - Configures the value of PWM generator %s time stamp B's shadow register."] -pub type CMPR_B_R = crate::FieldReader; -#[doc = "Field `CMPR_B` writer - Configures the value of PWM generator %s time stamp B's shadow register."] -pub type CMPR_B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `B` reader - Configures the value of PWM generator %s time stamp B's shadow register."] +pub type B_R = crate::FieldReader; +#[doc = "Field `B` writer - Configures the value of PWM generator %s time stamp B's shadow register."] +pub type B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp B's shadow register."] #[inline(always)] - pub fn cmpr_b(&self) -> CMPR_B_R { - CMPR_B_R::new((self.bits & 0xffff) as u16) + pub fn b(&self) -> B_R { + B_R::new((self.bits & 0xffff) as u16) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("GEN_TSTMP_B") - .field("cmpr_b", &format_args!("{}", self.cmpr_b().bits())) + .field("b", &format_args!("{}", self.b().bits())) .finish() } } @@ -31,8 +31,8 @@ impl W { #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp B's shadow register."] #[inline(always)] #[must_use] - pub fn cmpr_b(&mut self) -> CMPR_B_W { - CMPR_B_W::new(self, 0) + pub fn b(&mut self) -> B_W { + B_W::new(self, 0) } } #[doc = "Generator0 time stamp B's shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_b::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/svd/patches/esp32p4.yaml b/esp32p4/svd/patches/esp32p4.yaml index a6a346f546..da444d3838 100644 --- a/esp32p4/svd/patches/esp32p4.yaml +++ b/esp32p4/svd/patches/esp32p4.yaml @@ -93,11 +93,11 @@ MCPWM0: name: GEN%s GEN?_STMP_CFG: - _strip: GEN_ + _strip: CMPR_ GEN?_TSTMP_A: - _strip: GEN_ + _strip: CMPR_ GEN?_TSTMP_B: - _strip: GEN_ + _strip: CMPR_ GEN?_CFG0: _strip: GEN_ GEN?_FORCE: @@ -107,19 +107,19 @@ MCPWM0: GEN?_B: description: Actions triggered by events on PWMxB DT?_CFG: - _strip: DT_ + _strip: DB_ DT?_FED_CFG: - _strip: DT_ + _strip: DB_ DT?_RED_CFG: - _strip: DT_ + _strip: DB_ CARRIER?_CFG: - _strip: CARRIER_ + _strip: CHOPPER_ FH?_CFG0: - _strip: FH_ + _strip: TZ_ FH?_CFG1: - _strip: FH_ + _strip: TZ_ FH?_STATUS: - _strip: FH_ + _strip: TZ_