From 9b948e727fefb527d48b970399dc7fb0e9d424d5 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Mon, 1 Apr 2024 18:39:40 +0300 Subject: [PATCH] P4: JPEG+INT --- esp32p4/src/i3c_mst.rs | 12 +- esp32p4/src/i3c_mst/int_clr.rs | 130 +++---- esp32p4/src/i3c_mst/int_ena.rs | 336 +++++++++++++++++ esp32p4/src/i3c_mst/int_raw.rs | 322 ++++++++-------- esp32p4/src/i3c_mst/int_st.rs | 194 +++++----- esp32p4/src/i3c_mst/int_st_ena.rs | 342 ----------------- esp32p4/src/isp/int_clr.rs | 240 ++++++------ esp32p4/src/isp/int_ena.rs | 600 ++++++++++++++---------------- esp32p4/src/isp/int_raw.rs | 362 ++++++++---------- esp32p4/src/isp/int_st.rs | 362 ++++++++---------- esp32p4/src/jpeg.rs | 48 +-- esp32p4/src/jpeg/{c0.rs => c.rs} | 38 +- esp32p4/src/jpeg/c1.rs | 105 ------ esp32p4/src/jpeg/c2.rs | 105 ------ esp32p4/src/jpeg/c3.rs | 105 ------ esp32p4/src/jpeg/int_clr.rs | 204 +++++----- esp32p4/src/jpeg/int_ena.rs | 509 ++++++++++++------------- esp32p4/src/jpeg/int_raw.rs | 509 ++++++++++++------------- esp32p4/src/jpeg/int_st.rs | 304 +++++++-------- esp32p4/src/lp_huk/int_clr.rs | 26 +- esp32p4/src/lp_huk/int_ena.rs | 63 ++-- esp32p4/src/lp_huk/int_raw.rs | 39 +- esp32p4/src/lp_huk/int_st.rs | 39 +- esp32p4/src/lp_i2c0/int_clr.rs | 130 +++---- esp32p4/src/lp_i2c0/int_ena.rs | 331 ++++++++-------- esp32p4/src/lp_i2c0/int_raw.rs | 203 +++++----- esp32p4/src/lp_i2c0/int_st.rs | 200 +++++----- esp32p4/src/lp_i2s0/int_clr.rs | 50 +-- esp32p4/src/lp_i2s0/int_ena.rs | 123 +++--- esp32p4/src/lp_i2s0/int_raw.rs | 75 ++-- esp32p4/src/lp_i2s0/int_st.rs | 75 ++-- esp32p4/src/lp_uart/int_clr.rs | 138 +++---- esp32p4/src/lp_uart/int_ena.rs | 354 ++++++++---------- esp32p4/src/lp_uart/int_raw.rs | 354 ++++++++---------- esp32p4/src/lp_uart/int_st.rs | 218 +++++------ esp32p4/svd/patches/esp32p4.yaml | 16 +- 36 files changed, 3219 insertions(+), 4042 deletions(-) create mode 100644 esp32p4/src/i3c_mst/int_ena.rs delete mode 100644 esp32p4/src/i3c_mst/int_st_ena.rs rename esp32p4/src/jpeg/{c0.rs => c.rs} (73%) delete mode 100644 esp32p4/src/jpeg/c1.rs delete mode 100644 esp32p4/src/jpeg/c2.rs delete mode 100644 esp32p4/src/jpeg/c3.rs diff --git a/esp32p4/src/i3c_mst.rs b/esp32p4/src/i3c_mst.rs index 8472328827..d5f6a98e05 100644 --- a/esp32p4/src/i3c_mst.rs +++ b/esp32p4/src/i3c_mst.rs @@ -12,7 +12,7 @@ pub struct RegisterBlock { int_clr: INT_CLR, int_raw: INT_RAW, int_st: INT_ST, - int_st_ena: INT_ST_ENA, + int_ena: INT_ENA, _reserved10: [u8; 0x04], reset_ctrl: RESET_CTRL, buffer_status_level: BUFFER_STATUS_LEVEL, @@ -92,8 +92,8 @@ impl RegisterBlock { } #[doc = "0x3c - The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set."] #[inline(always)] - pub const fn int_st_ena(&self) -> &INT_ST_ENA { - &self.int_st_ena + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena } #[doc = "0x44 - NA"] #[inline(always)] @@ -262,10 +262,10 @@ pub mod int_raw; pub type INT_ST = crate::Reg; #[doc = "NA"] pub mod int_st; -#[doc = "INT_ST_ENA (rw) register accessor: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_ena`] module"] -pub type INT_ST_ENA = crate::Reg; +#[doc = "INT_ENA (rw) register accessor: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; #[doc = "The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set."] -pub mod int_st_ena; +pub mod int_ena; #[doc = "RESET_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_ctrl`] module"] pub type RESET_CTRL = crate::Reg; #[doc = "NA"] diff --git a/esp32p4/src/i3c_mst/int_clr.rs b/esp32p4/src/i3c_mst/int_clr.rs index be0b3bac69..ab328b0f5c 100644 --- a/esp32p4/src/i3c_mst/int_clr.rs +++ b/esp32p4/src/i3c_mst/int_clr.rs @@ -1,37 +1,37 @@ #[doc = "Register `INT_CLR` writer"] pub type W = crate::W; -#[doc = "Field `TX_DATA_BUF_THLD_INT_CLR` writer - NA"] -pub type TX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_DATA_BUF_THLD_INT_CLR` writer - NA"] -pub type RX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_STATUS_THLD_INT_CLR` writer - NA"] -pub type IBI_STATUS_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_CLR` writer - NA"] -pub type CMD_BUF_EMPTY_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESP_READY_INT_CLR` writer - NA"] -pub type RESP_READY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `NXT_CMD_REQ_ERR_INT_CLR` writer - NA"] -pub type NXT_CMD_REQ_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANSFER_ERR_INT_CLR` writer - NA"] -pub type TRANSFER_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANSFER_COMPLETE_INT_CLR` writer - NA"] -pub type TRANSFER_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `COMMAND_DONE_INT_CLR` writer - NA"] -pub type COMMAND_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DETECT_START_INT_CLR` writer - NA"] -pub type DETECT_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESP_BUF_OVF_INT_CLR` writer - NA"] -pub type RESP_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_DATA_BUF_OVF_INT_CLR` writer - NA"] -pub type IBI_DATA_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_STATUS_BUF_OVF_INT_CLR` writer - NA"] -pub type IBI_STATUS_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_HANDLE_DONE_INT_CLR` writer - NA"] -pub type IBI_HANDLE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_DETECT_INT_CLR` writer - NA"] -pub type IBI_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMD_CCC_MISMATCH_INT_CLR` writer - NA"] -pub type CMD_CCC_MISMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DATA_BUF_THLD` writer - NA"] +pub type TX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RX_DATA_BUF_THLD` writer - NA"] +pub type RX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IBI_STATUS_THLD` writer - NA"] +pub type IBI_STATUS_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CMD_BUF_EMPTY_THLD` writer - NA"] +pub type CMD_BUF_EMPTY_THLD_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RESP_READY` writer - NA"] +pub type RESP_READY_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `NXT_CMD_REQ_ERR` writer - NA"] +pub type NXT_CMD_REQ_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TRANSFER_ERR` writer - NA"] +pub type TRANSFER_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TRANSFER_COMPLETE` writer - NA"] +pub type TRANSFER_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `COMMAND_DONE` writer - NA"] +pub type COMMAND_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DETECT_START` writer - NA"] +pub type DETECT_START_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RESP_BUF_OVF` writer - NA"] +pub type RESP_BUF_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IBI_DATA_BUF_OVF` writer - NA"] +pub type IBI_DATA_BUF_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IBI_STATUS_BUF_OVF` writer - NA"] +pub type IBI_STATUS_BUF_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IBI_HANDLE_DONE` writer - NA"] +pub type IBI_HANDLE_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IBI_DETECT` writer - NA"] +pub type IBI_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CMD_CCC_MISMATCH` writer - NA"] +pub type CMD_CCC_MISMATCH_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -42,98 +42,98 @@ impl W { #[doc = "Bit 0 - NA"] #[inline(always)] #[must_use] - pub fn tx_data_buf_thld_int_clr(&mut self) -> TX_DATA_BUF_THLD_INT_CLR_W { - TX_DATA_BUF_THLD_INT_CLR_W::new(self, 0) + pub fn tx_data_buf_thld(&mut self) -> TX_DATA_BUF_THLD_W { + TX_DATA_BUF_THLD_W::new(self, 0) } #[doc = "Bit 1 - NA"] #[inline(always)] #[must_use] - pub fn rx_data_buf_thld_int_clr(&mut self) -> RX_DATA_BUF_THLD_INT_CLR_W { - RX_DATA_BUF_THLD_INT_CLR_W::new(self, 1) + pub fn rx_data_buf_thld(&mut self) -> RX_DATA_BUF_THLD_W { + RX_DATA_BUF_THLD_W::new(self, 1) } #[doc = "Bit 2 - NA"] #[inline(always)] #[must_use] - pub fn ibi_status_thld_int_clr(&mut self) -> IBI_STATUS_THLD_INT_CLR_W { - IBI_STATUS_THLD_INT_CLR_W::new(self, 2) + pub fn ibi_status_thld(&mut self) -> IBI_STATUS_THLD_W { + IBI_STATUS_THLD_W::new(self, 2) } #[doc = "Bit 3 - NA"] #[inline(always)] #[must_use] - pub fn cmd_buf_empty_thld_int_clr(&mut self) -> CMD_BUF_EMPTY_THLD_INT_CLR_W { - CMD_BUF_EMPTY_THLD_INT_CLR_W::new(self, 3) + pub fn cmd_buf_empty_thld(&mut self) -> CMD_BUF_EMPTY_THLD_W { + CMD_BUF_EMPTY_THLD_W::new(self, 3) } #[doc = "Bit 4 - NA"] #[inline(always)] #[must_use] - pub fn resp_ready_int_clr(&mut self) -> RESP_READY_INT_CLR_W { - RESP_READY_INT_CLR_W::new(self, 4) + pub fn resp_ready(&mut self) -> RESP_READY_W { + RESP_READY_W::new(self, 4) } #[doc = "Bit 5 - NA"] #[inline(always)] #[must_use] - pub fn nxt_cmd_req_err_int_clr(&mut self) -> NXT_CMD_REQ_ERR_INT_CLR_W { - NXT_CMD_REQ_ERR_INT_CLR_W::new(self, 5) + pub fn nxt_cmd_req_err(&mut self) -> NXT_CMD_REQ_ERR_W { + NXT_CMD_REQ_ERR_W::new(self, 5) } #[doc = "Bit 6 - NA"] #[inline(always)] #[must_use] - pub fn transfer_err_int_clr(&mut self) -> TRANSFER_ERR_INT_CLR_W { - TRANSFER_ERR_INT_CLR_W::new(self, 6) + pub fn transfer_err(&mut self) -> TRANSFER_ERR_W { + TRANSFER_ERR_W::new(self, 6) } #[doc = "Bit 7 - NA"] #[inline(always)] #[must_use] - pub fn transfer_complete_int_clr(&mut self) -> TRANSFER_COMPLETE_INT_CLR_W { - TRANSFER_COMPLETE_INT_CLR_W::new(self, 7) + pub fn transfer_complete(&mut self) -> TRANSFER_COMPLETE_W { + TRANSFER_COMPLETE_W::new(self, 7) } #[doc = "Bit 8 - NA"] #[inline(always)] #[must_use] - pub fn command_done_int_clr(&mut self) -> COMMAND_DONE_INT_CLR_W { - COMMAND_DONE_INT_CLR_W::new(self, 8) + pub fn command_done(&mut self) -> COMMAND_DONE_W { + COMMAND_DONE_W::new(self, 8) } #[doc = "Bit 9 - NA"] #[inline(always)] #[must_use] - pub fn detect_start_int_clr(&mut self) -> DETECT_START_INT_CLR_W { - DETECT_START_INT_CLR_W::new(self, 9) + pub fn detect_start(&mut self) -> DETECT_START_W { + DETECT_START_W::new(self, 9) } #[doc = "Bit 10 - NA"] #[inline(always)] #[must_use] - pub fn resp_buf_ovf_int_clr(&mut self) -> RESP_BUF_OVF_INT_CLR_W { - RESP_BUF_OVF_INT_CLR_W::new(self, 10) + pub fn resp_buf_ovf(&mut self) -> RESP_BUF_OVF_W { + RESP_BUF_OVF_W::new(self, 10) } #[doc = "Bit 11 - NA"] #[inline(always)] #[must_use] - pub fn ibi_data_buf_ovf_int_clr(&mut self) -> IBI_DATA_BUF_OVF_INT_CLR_W { - IBI_DATA_BUF_OVF_INT_CLR_W::new(self, 11) + pub fn ibi_data_buf_ovf(&mut self) -> IBI_DATA_BUF_OVF_W { + IBI_DATA_BUF_OVF_W::new(self, 11) } #[doc = "Bit 12 - NA"] #[inline(always)] #[must_use] - pub fn ibi_status_buf_ovf_int_clr(&mut self) -> IBI_STATUS_BUF_OVF_INT_CLR_W { - IBI_STATUS_BUF_OVF_INT_CLR_W::new(self, 12) + pub fn ibi_status_buf_ovf(&mut self) -> IBI_STATUS_BUF_OVF_W { + IBI_STATUS_BUF_OVF_W::new(self, 12) } #[doc = "Bit 13 - NA"] #[inline(always)] #[must_use] - pub fn ibi_handle_done_int_clr(&mut self) -> IBI_HANDLE_DONE_INT_CLR_W { - IBI_HANDLE_DONE_INT_CLR_W::new(self, 13) + pub fn ibi_handle_done(&mut self) -> IBI_HANDLE_DONE_W { + IBI_HANDLE_DONE_W::new(self, 13) } #[doc = "Bit 14 - NA"] #[inline(always)] #[must_use] - pub fn ibi_detect_int_clr(&mut self) -> IBI_DETECT_INT_CLR_W { - IBI_DETECT_INT_CLR_W::new(self, 14) + pub fn ibi_detect(&mut self) -> IBI_DETECT_W { + IBI_DETECT_W::new(self, 14) } #[doc = "Bit 15 - NA"] #[inline(always)] #[must_use] - pub fn cmd_ccc_mismatch_int_clr(&mut self) -> CMD_CCC_MISMATCH_INT_CLR_W { - CMD_CCC_MISMATCH_INT_CLR_W::new(self, 15) + pub fn cmd_ccc_mismatch(&mut self) -> CMD_CCC_MISMATCH_W { + CMD_CCC_MISMATCH_W::new(self, 15) } } #[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -145,7 +145,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC { impl crate::Writable for INT_CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; } #[doc = "`reset()` method sets INT_CLR to value 0"] impl crate::Resettable for INT_CLR_SPEC { diff --git a/esp32p4/src/i3c_mst/int_ena.rs b/esp32p4/src/i3c_mst/int_ena.rs new file mode 100644 index 0000000000..245d59f9e2 --- /dev/null +++ b/esp32p4/src/i3c_mst/int_ena.rs @@ -0,0 +1,336 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `TX_DATA_BUF_THLD` reader - Transmit Buffer threshold status enable."] +pub type TX_DATA_BUF_THLD_R = crate::BitReader; +#[doc = "Field `TX_DATA_BUF_THLD` writer - Transmit Buffer threshold status enable."] +pub type TX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DATA_BUF_THLD` reader - Receive Buffer threshold status enable."] +pub type RX_DATA_BUF_THLD_R = crate::BitReader; +#[doc = "Field `RX_DATA_BUF_THLD` writer - Receive Buffer threshold status enable."] +pub type RX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_THLD` reader - Only used in master mode. IBI Buffer threshold status enable."] +pub type IBI_STATUS_THLD_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_THLD` writer - Only used in master mode. IBI Buffer threshold status enable."] +pub type IBI_STATUS_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_BUF_EMPTY_THLD` reader - Command buffer ready status enable."] +pub type CMD_BUF_EMPTY_THLD_R = crate::BitReader; +#[doc = "Field `CMD_BUF_EMPTY_THLD` writer - Command buffer ready status enable."] +pub type CMD_BUF_EMPTY_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_READY` reader - Response buffer ready status enable."] +pub type RESP_READY_R = crate::BitReader; +#[doc = "Field `RESP_READY` writer - Response buffer ready status enable."] +pub type RESP_READY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NXT_CMD_REQ_ERR` reader - next command request error status enable"] +pub type NXT_CMD_REQ_ERR_R = crate::BitReader; +#[doc = "Field `NXT_CMD_REQ_ERR` writer - next command request error status enable"] +pub type NXT_CMD_REQ_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_ERR` reader - Transfer error status enable"] +pub type TRANSFER_ERR_R = crate::BitReader; +#[doc = "Field `TRANSFER_ERR` writer - Transfer error status enable"] +pub type TRANSFER_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_COMPLETE` reader - NA"] +pub type TRANSFER_COMPLETE_R = crate::BitReader; +#[doc = "Field `TRANSFER_COMPLETE` writer - NA"] +pub type TRANSFER_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMMAND_DONE` reader - NA"] +pub type COMMAND_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND_DONE` writer - NA"] +pub type COMMAND_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DETECT_START` reader - NA"] +pub type DETECT_START_R = crate::BitReader; +#[doc = "Field `DETECT_START` writer - NA"] +pub type DETECT_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_BUF_OVF` reader - NA"] +pub type RESP_BUF_OVF_R = crate::BitReader; +#[doc = "Field `RESP_BUF_OVF` writer - NA"] +pub type RESP_BUF_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DATA_BUF_OVF` reader - NA"] +pub type IBI_DATA_BUF_OVF_R = crate::BitReader; +#[doc = "Field `IBI_DATA_BUF_OVF` writer - NA"] +pub type IBI_DATA_BUF_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_BUF_OVF` reader - NA"] +pub type IBI_STATUS_BUF_OVF_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_BUF_OVF` writer - NA"] +pub type IBI_STATUS_BUF_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_HANDLE_DONE` reader - NA"] +pub type IBI_HANDLE_DONE_R = crate::BitReader; +#[doc = "Field `IBI_HANDLE_DONE` writer - NA"] +pub type IBI_HANDLE_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DETECT` reader - NA"] +pub type IBI_DETECT_R = crate::BitReader; +#[doc = "Field `IBI_DETECT` writer - NA"] +pub type IBI_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_CCC_MISMATCH` reader - NA"] +pub type CMD_CCC_MISMATCH_R = crate::BitReader; +#[doc = "Field `CMD_CCC_MISMATCH` writer - NA"] +pub type CMD_CCC_MISMATCH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Transmit Buffer threshold status enable."] + #[inline(always)] + pub fn tx_data_buf_thld(&self) -> TX_DATA_BUF_THLD_R { + TX_DATA_BUF_THLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Buffer threshold status enable."] + #[inline(always)] + pub fn rx_data_buf_thld(&self) -> RX_DATA_BUF_THLD_R { + RX_DATA_BUF_THLD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."] + #[inline(always)] + pub fn ibi_status_thld(&self) -> IBI_STATUS_THLD_R { + IBI_STATUS_THLD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Command buffer ready status enable."] + #[inline(always)] + pub fn cmd_buf_empty_thld(&self) -> CMD_BUF_EMPTY_THLD_R { + CMD_BUF_EMPTY_THLD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Response buffer ready status enable."] + #[inline(always)] + pub fn resp_ready(&self) -> RESP_READY_R { + RESP_READY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - next command request error status enable"] + #[inline(always)] + pub fn nxt_cmd_req_err(&self) -> NXT_CMD_REQ_ERR_R { + NXT_CMD_REQ_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transfer error status enable"] + #[inline(always)] + pub fn transfer_err(&self) -> TRANSFER_ERR_R { + TRANSFER_ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn transfer_complete(&self) -> TRANSFER_COMPLETE_R { + TRANSFER_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn command_done(&self) -> COMMAND_DONE_R { + COMMAND_DONE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn detect_start(&self) -> DETECT_START_R { + DETECT_START_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn resp_buf_ovf(&self) -> RESP_BUF_OVF_R { + RESP_BUF_OVF_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ibi_data_buf_ovf(&self) -> IBI_DATA_BUF_OVF_R { + IBI_DATA_BUF_OVF_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ibi_status_buf_ovf(&self) -> IBI_STATUS_BUF_OVF_R { + IBI_STATUS_BUF_OVF_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ibi_handle_done(&self) -> IBI_HANDLE_DONE_R { + IBI_HANDLE_DONE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ibi_detect(&self) -> IBI_DETECT_R { + IBI_DETECT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn cmd_ccc_mismatch(&self) -> CMD_CCC_MISMATCH_R { + CMD_CCC_MISMATCH_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "tx_data_buf_thld", + &format_args!("{}", self.tx_data_buf_thld().bit()), + ) + .field( + "rx_data_buf_thld", + &format_args!("{}", self.rx_data_buf_thld().bit()), + ) + .field( + "ibi_status_thld", + &format_args!("{}", self.ibi_status_thld().bit()), + ) + .field( + "cmd_buf_empty_thld", + &format_args!("{}", self.cmd_buf_empty_thld().bit()), + ) + .field("resp_ready", &format_args!("{}", self.resp_ready().bit())) + .field( + "nxt_cmd_req_err", + &format_args!("{}", self.nxt_cmd_req_err().bit()), + ) + .field( + "transfer_err", + &format_args!("{}", self.transfer_err().bit()), + ) + .field( + "transfer_complete", + &format_args!("{}", self.transfer_complete().bit()), + ) + .field( + "command_done", + &format_args!("{}", self.command_done().bit()), + ) + .field( + "detect_start", + &format_args!("{}", self.detect_start().bit()), + ) + .field( + "resp_buf_ovf", + &format_args!("{}", self.resp_buf_ovf().bit()), + ) + .field( + "ibi_data_buf_ovf", + &format_args!("{}", self.ibi_data_buf_ovf().bit()), + ) + .field( + "ibi_status_buf_ovf", + &format_args!("{}", self.ibi_status_buf_ovf().bit()), + ) + .field( + "ibi_handle_done", + &format_args!("{}", self.ibi_handle_done().bit()), + ) + .field("ibi_detect", &format_args!("{}", self.ibi_detect().bit())) + .field( + "cmd_ccc_mismatch", + &format_args!("{}", self.cmd_ccc_mismatch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Transmit Buffer threshold status enable."] + #[inline(always)] + #[must_use] + pub fn tx_data_buf_thld(&mut self) -> TX_DATA_BUF_THLD_W { + TX_DATA_BUF_THLD_W::new(self, 0) + } + #[doc = "Bit 1 - Receive Buffer threshold status enable."] + #[inline(always)] + #[must_use] + pub fn rx_data_buf_thld(&mut self) -> RX_DATA_BUF_THLD_W { + RX_DATA_BUF_THLD_W::new(self, 1) + } + #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."] + #[inline(always)] + #[must_use] + pub fn ibi_status_thld(&mut self) -> IBI_STATUS_THLD_W { + IBI_STATUS_THLD_W::new(self, 2) + } + #[doc = "Bit 3 - Command buffer ready status enable."] + #[inline(always)] + #[must_use] + pub fn cmd_buf_empty_thld(&mut self) -> CMD_BUF_EMPTY_THLD_W { + CMD_BUF_EMPTY_THLD_W::new(self, 3) + } + #[doc = "Bit 4 - Response buffer ready status enable."] + #[inline(always)] + #[must_use] + pub fn resp_ready(&mut self) -> RESP_READY_W { + RESP_READY_W::new(self, 4) + } + #[doc = "Bit 5 - next command request error status enable"] + #[inline(always)] + #[must_use] + pub fn nxt_cmd_req_err(&mut self) -> NXT_CMD_REQ_ERR_W { + NXT_CMD_REQ_ERR_W::new(self, 5) + } + #[doc = "Bit 6 - Transfer error status enable"] + #[inline(always)] + #[must_use] + pub fn transfer_err(&mut self) -> TRANSFER_ERR_W { + TRANSFER_ERR_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn transfer_complete(&mut self) -> TRANSFER_COMPLETE_W { + TRANSFER_COMPLETE_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn command_done(&mut self) -> COMMAND_DONE_W { + COMMAND_DONE_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn detect_start(&mut self) -> DETECT_START_W { + DETECT_START_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn resp_buf_ovf(&mut self) -> RESP_BUF_OVF_W { + RESP_BUF_OVF_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_data_buf_ovf(&mut self) -> IBI_DATA_BUF_OVF_W { + IBI_DATA_BUF_OVF_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_status_buf_ovf(&mut self) -> IBI_STATUS_BUF_OVF_W { + IBI_STATUS_BUF_OVF_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_handle_done(&mut self) -> IBI_HANDLE_DONE_W { + IBI_HANDLE_DONE_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_detect(&mut self) -> IBI_DETECT_W { + IBI_DETECT_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn cmd_ccc_mismatch(&mut self) -> CMD_CCC_MISMATCH_W { + CMD_CCC_MISMATCH_W::new(self, 15) + } +} +#[doc = "The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32p4/src/i3c_mst/int_raw.rs b/esp32p4/src/i3c_mst/int_raw.rs index 2717dd8dfd..1454c1fe8d 100644 --- a/esp32p4/src/i3c_mst/int_raw.rs +++ b/esp32p4/src/i3c_mst/int_raw.rs @@ -2,150 +2,150 @@ pub type R = crate::R; #[doc = "Register `INT_RAW` writer"] pub type W = crate::W; -#[doc = "Field `TX_DATA_BUF_THLD_INT_RAW` reader - NA"] -pub type TX_DATA_BUF_THLD_INT_RAW_R = crate::BitReader; -#[doc = "Field `TX_DATA_BUF_THLD_INT_RAW` writer - NA"] -pub type TX_DATA_BUF_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_DATA_BUF_THLD_INT_RAW` reader - NA"] -pub type RX_DATA_BUF_THLD_INT_RAW_R = crate::BitReader; -#[doc = "Field `RX_DATA_BUF_THLD_INT_RAW` writer - NA"] -pub type RX_DATA_BUF_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_STATUS_THLD_INT_RAW` reader - NA"] -pub type IBI_STATUS_THLD_INT_RAW_R = crate::BitReader; -#[doc = "Field `IBI_STATUS_THLD_INT_RAW` writer - NA"] -pub type IBI_STATUS_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_RAW` reader - NA"] -pub type CMD_BUF_EMPTY_THLD_INT_RAW_R = crate::BitReader; -#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_RAW` writer - NA"] -pub type CMD_BUF_EMPTY_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESP_READY_INT_RAW` reader - NA"] -pub type RESP_READY_INT_RAW_R = crate::BitReader; -#[doc = "Field `RESP_READY_INT_RAW` writer - NA"] -pub type RESP_READY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `NXT_CMD_REQ_ERR_INT_RAW` reader - NA"] -pub type NXT_CMD_REQ_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `NXT_CMD_REQ_ERR_INT_RAW` writer - NA"] -pub type NXT_CMD_REQ_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANSFER_ERR_INT_RAW` reader - NA"] -pub type TRANSFER_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `TRANSFER_ERR_INT_RAW` writer - NA"] -pub type TRANSFER_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANSFER_COMPLETE_INT_RAW` reader - NA"] -pub type TRANSFER_COMPLETE_INT_RAW_R = crate::BitReader; -#[doc = "Field `TRANSFER_COMPLETE_INT_RAW` writer - NA"] -pub type TRANSFER_COMPLETE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `COMMAND_DONE_INT_RAW` reader - NA"] -pub type COMMAND_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `COMMAND_DONE_INT_RAW` writer - NA"] -pub type COMMAND_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DETECT_START_INT_RAW` reader - NA"] -pub type DETECT_START_INT_RAW_R = crate::BitReader; -#[doc = "Field `DETECT_START_INT_RAW` writer - NA"] -pub type DETECT_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESP_BUF_OVF_INT_RAW` reader - NA"] -pub type RESP_BUF_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `RESP_BUF_OVF_INT_RAW` writer - NA"] -pub type RESP_BUF_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_DATA_BUF_OVF_INT_RAW` reader - NA"] -pub type IBI_DATA_BUF_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `IBI_DATA_BUF_OVF_INT_RAW` writer - NA"] -pub type IBI_DATA_BUF_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_STATUS_BUF_OVF_INT_RAW` reader - NA"] -pub type IBI_STATUS_BUF_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `IBI_STATUS_BUF_OVF_INT_RAW` writer - NA"] -pub type IBI_STATUS_BUF_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_HANDLE_DONE_INT_RAW` reader - NA"] -pub type IBI_HANDLE_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `IBI_HANDLE_DONE_INT_RAW` writer - NA"] -pub type IBI_HANDLE_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_DETECT_INT_RAW` reader - NA"] -pub type IBI_DETECT_INT_RAW_R = crate::BitReader; -#[doc = "Field `IBI_DETECT_INT_RAW` writer - NA"] -pub type IBI_DETECT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMD_CCC_MISMATCH_INT_RAW` reader - NA"] -pub type CMD_CCC_MISMATCH_INT_RAW_R = crate::BitReader; -#[doc = "Field `CMD_CCC_MISMATCH_INT_RAW` writer - NA"] -pub type CMD_CCC_MISMATCH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DATA_BUF_THLD` reader - NA"] +pub type TX_DATA_BUF_THLD_R = crate::BitReader; +#[doc = "Field `TX_DATA_BUF_THLD` writer - NA"] +pub type TX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DATA_BUF_THLD` reader - NA"] +pub type RX_DATA_BUF_THLD_R = crate::BitReader; +#[doc = "Field `RX_DATA_BUF_THLD` writer - NA"] +pub type RX_DATA_BUF_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_THLD` reader - NA"] +pub type IBI_STATUS_THLD_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_THLD` writer - NA"] +pub type IBI_STATUS_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_BUF_EMPTY_THLD` reader - NA"] +pub type CMD_BUF_EMPTY_THLD_R = crate::BitReader; +#[doc = "Field `CMD_BUF_EMPTY_THLD` writer - NA"] +pub type CMD_BUF_EMPTY_THLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_READY` reader - NA"] +pub type RESP_READY_R = crate::BitReader; +#[doc = "Field `RESP_READY` writer - NA"] +pub type RESP_READY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NXT_CMD_REQ_ERR` reader - NA"] +pub type NXT_CMD_REQ_ERR_R = crate::BitReader; +#[doc = "Field `NXT_CMD_REQ_ERR` writer - NA"] +pub type NXT_CMD_REQ_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_ERR` reader - NA"] +pub type TRANSFER_ERR_R = crate::BitReader; +#[doc = "Field `TRANSFER_ERR` writer - NA"] +pub type TRANSFER_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_COMPLETE` reader - NA"] +pub type TRANSFER_COMPLETE_R = crate::BitReader; +#[doc = "Field `TRANSFER_COMPLETE` writer - NA"] +pub type TRANSFER_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMMAND_DONE` reader - NA"] +pub type COMMAND_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND_DONE` writer - NA"] +pub type COMMAND_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DETECT_START` reader - NA"] +pub type DETECT_START_R = crate::BitReader; +#[doc = "Field `DETECT_START` writer - NA"] +pub type DETECT_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_BUF_OVF` reader - NA"] +pub type RESP_BUF_OVF_R = crate::BitReader; +#[doc = "Field `RESP_BUF_OVF` writer - NA"] +pub type RESP_BUF_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DATA_BUF_OVF` reader - NA"] +pub type IBI_DATA_BUF_OVF_R = crate::BitReader; +#[doc = "Field `IBI_DATA_BUF_OVF` writer - NA"] +pub type IBI_DATA_BUF_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_BUF_OVF` reader - NA"] +pub type IBI_STATUS_BUF_OVF_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_BUF_OVF` writer - NA"] +pub type IBI_STATUS_BUF_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_HANDLE_DONE` reader - NA"] +pub type IBI_HANDLE_DONE_R = crate::BitReader; +#[doc = "Field `IBI_HANDLE_DONE` writer - NA"] +pub type IBI_HANDLE_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DETECT` reader - NA"] +pub type IBI_DETECT_R = crate::BitReader; +#[doc = "Field `IBI_DETECT` writer - NA"] +pub type IBI_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_CCC_MISMATCH` reader - NA"] +pub type CMD_CCC_MISMATCH_R = crate::BitReader; +#[doc = "Field `CMD_CCC_MISMATCH` writer - NA"] +pub type CMD_CCC_MISMATCH_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - NA"] #[inline(always)] - pub fn tx_data_buf_thld_int_raw(&self) -> TX_DATA_BUF_THLD_INT_RAW_R { - TX_DATA_BUF_THLD_INT_RAW_R::new((self.bits & 1) != 0) + pub fn tx_data_buf_thld(&self) -> TX_DATA_BUF_THLD_R { + TX_DATA_BUF_THLD_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - NA"] #[inline(always)] - pub fn rx_data_buf_thld_int_raw(&self) -> RX_DATA_BUF_THLD_INT_RAW_R { - RX_DATA_BUF_THLD_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn rx_data_buf_thld(&self) -> RX_DATA_BUF_THLD_R { + RX_DATA_BUF_THLD_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - NA"] #[inline(always)] - pub fn ibi_status_thld_int_raw(&self) -> IBI_STATUS_THLD_INT_RAW_R { - IBI_STATUS_THLD_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn ibi_status_thld(&self) -> IBI_STATUS_THLD_R { + IBI_STATUS_THLD_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - NA"] #[inline(always)] - pub fn cmd_buf_empty_thld_int_raw(&self) -> CMD_BUF_EMPTY_THLD_INT_RAW_R { - CMD_BUF_EMPTY_THLD_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn cmd_buf_empty_thld(&self) -> CMD_BUF_EMPTY_THLD_R { + CMD_BUF_EMPTY_THLD_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - NA"] #[inline(always)] - pub fn resp_ready_int_raw(&self) -> RESP_READY_INT_RAW_R { - RESP_READY_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn resp_ready(&self) -> RESP_READY_R { + RESP_READY_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - NA"] #[inline(always)] - pub fn nxt_cmd_req_err_int_raw(&self) -> NXT_CMD_REQ_ERR_INT_RAW_R { - NXT_CMD_REQ_ERR_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn nxt_cmd_req_err(&self) -> NXT_CMD_REQ_ERR_R { + NXT_CMD_REQ_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - NA"] #[inline(always)] - pub fn transfer_err_int_raw(&self) -> TRANSFER_ERR_INT_RAW_R { - TRANSFER_ERR_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn transfer_err(&self) -> TRANSFER_ERR_R { + TRANSFER_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - NA"] #[inline(always)] - pub fn transfer_complete_int_raw(&self) -> TRANSFER_COMPLETE_INT_RAW_R { - TRANSFER_COMPLETE_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn transfer_complete(&self) -> TRANSFER_COMPLETE_R { + TRANSFER_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - NA"] #[inline(always)] - pub fn command_done_int_raw(&self) -> COMMAND_DONE_INT_RAW_R { - COMMAND_DONE_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn command_done(&self) -> COMMAND_DONE_R { + COMMAND_DONE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - NA"] #[inline(always)] - pub fn detect_start_int_raw(&self) -> DETECT_START_INT_RAW_R { - DETECT_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn detect_start(&self) -> DETECT_START_R { + DETECT_START_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - NA"] #[inline(always)] - pub fn resp_buf_ovf_int_raw(&self) -> RESP_BUF_OVF_INT_RAW_R { - RESP_BUF_OVF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn resp_buf_ovf(&self) -> RESP_BUF_OVF_R { + RESP_BUF_OVF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - NA"] #[inline(always)] - pub fn ibi_data_buf_ovf_int_raw(&self) -> IBI_DATA_BUF_OVF_INT_RAW_R { - IBI_DATA_BUF_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn ibi_data_buf_ovf(&self) -> IBI_DATA_BUF_OVF_R { + IBI_DATA_BUF_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - NA"] #[inline(always)] - pub fn ibi_status_buf_ovf_int_raw(&self) -> IBI_STATUS_BUF_OVF_INT_RAW_R { - IBI_STATUS_BUF_OVF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn ibi_status_buf_ovf(&self) -> IBI_STATUS_BUF_OVF_R { + IBI_STATUS_BUF_OVF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - NA"] #[inline(always)] - pub fn ibi_handle_done_int_raw(&self) -> IBI_HANDLE_DONE_INT_RAW_R { - IBI_HANDLE_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + pub fn ibi_handle_done(&self) -> IBI_HANDLE_DONE_R { + IBI_HANDLE_DONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - NA"] #[inline(always)] - pub fn ibi_detect_int_raw(&self) -> IBI_DETECT_INT_RAW_R { - IBI_DETECT_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + pub fn ibi_detect(&self) -> IBI_DETECT_R { + IBI_DETECT_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - NA"] #[inline(always)] - pub fn cmd_ccc_mismatch_int_raw(&self) -> CMD_CCC_MISMATCH_INT_RAW_R { - CMD_CCC_MISMATCH_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + pub fn cmd_ccc_mismatch(&self) -> CMD_CCC_MISMATCH_R { + CMD_CCC_MISMATCH_R::new(((self.bits >> 15) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -153,68 +153,62 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_RAW") .field( - "tx_data_buf_thld_int_raw", - &format_args!("{}", self.tx_data_buf_thld_int_raw().bit()), + "tx_data_buf_thld", + &format_args!("{}", self.tx_data_buf_thld().bit()), ) .field( - "rx_data_buf_thld_int_raw", - &format_args!("{}", self.rx_data_buf_thld_int_raw().bit()), + "rx_data_buf_thld", + &format_args!("{}", self.rx_data_buf_thld().bit()), ) .field( - "ibi_status_thld_int_raw", - &format_args!("{}", self.ibi_status_thld_int_raw().bit()), + "ibi_status_thld", + &format_args!("{}", self.ibi_status_thld().bit()), ) .field( - "cmd_buf_empty_thld_int_raw", - &format_args!("{}", self.cmd_buf_empty_thld_int_raw().bit()), + "cmd_buf_empty_thld", + &format_args!("{}", self.cmd_buf_empty_thld().bit()), ) + .field("resp_ready", &format_args!("{}", self.resp_ready().bit())) .field( - "resp_ready_int_raw", - &format_args!("{}", self.resp_ready_int_raw().bit()), + "nxt_cmd_req_err", + &format_args!("{}", self.nxt_cmd_req_err().bit()), ) .field( - "nxt_cmd_req_err_int_raw", - &format_args!("{}", self.nxt_cmd_req_err_int_raw().bit()), + "transfer_err", + &format_args!("{}", self.transfer_err().bit()), ) .field( - "transfer_err_int_raw", - &format_args!("{}", self.transfer_err_int_raw().bit()), + "transfer_complete", + &format_args!("{}", self.transfer_complete().bit()), ) .field( - "transfer_complete_int_raw", - &format_args!("{}", self.transfer_complete_int_raw().bit()), + "command_done", + &format_args!("{}", self.command_done().bit()), ) .field( - "command_done_int_raw", - &format_args!("{}", self.command_done_int_raw().bit()), + "detect_start", + &format_args!("{}", self.detect_start().bit()), ) .field( - "detect_start_int_raw", - &format_args!("{}", self.detect_start_int_raw().bit()), + "resp_buf_ovf", + &format_args!("{}", self.resp_buf_ovf().bit()), ) .field( - "resp_buf_ovf_int_raw", - &format_args!("{}", self.resp_buf_ovf_int_raw().bit()), + "ibi_data_buf_ovf", + &format_args!("{}", self.ibi_data_buf_ovf().bit()), ) .field( - "ibi_data_buf_ovf_int_raw", - &format_args!("{}", self.ibi_data_buf_ovf_int_raw().bit()), + "ibi_status_buf_ovf", + &format_args!("{}", self.ibi_status_buf_ovf().bit()), ) .field( - "ibi_status_buf_ovf_int_raw", - &format_args!("{}", self.ibi_status_buf_ovf_int_raw().bit()), + "ibi_handle_done", + &format_args!("{}", self.ibi_handle_done().bit()), ) + .field("ibi_detect", &format_args!("{}", self.ibi_detect().bit())) .field( - "ibi_handle_done_int_raw", - &format_args!("{}", self.ibi_handle_done_int_raw().bit()), - ) - .field( - "ibi_detect_int_raw", - &format_args!("{}", self.ibi_detect_int_raw().bit()), - ) - .field( - "cmd_ccc_mismatch_int_raw", - &format_args!("{}", self.cmd_ccc_mismatch_int_raw().bit()), + "cmd_ccc_mismatch", + &format_args!("{}", self.cmd_ccc_mismatch().bit()), ) .finish() } @@ -229,98 +223,98 @@ impl W { #[doc = "Bit 0 - NA"] #[inline(always)] #[must_use] - pub fn tx_data_buf_thld_int_raw(&mut self) -> TX_DATA_BUF_THLD_INT_RAW_W { - TX_DATA_BUF_THLD_INT_RAW_W::new(self, 0) + pub fn tx_data_buf_thld(&mut self) -> TX_DATA_BUF_THLD_W { + TX_DATA_BUF_THLD_W::new(self, 0) } #[doc = "Bit 1 - NA"] #[inline(always)] #[must_use] - pub fn rx_data_buf_thld_int_raw(&mut self) -> RX_DATA_BUF_THLD_INT_RAW_W { - RX_DATA_BUF_THLD_INT_RAW_W::new(self, 1) + pub fn rx_data_buf_thld(&mut self) -> RX_DATA_BUF_THLD_W { + RX_DATA_BUF_THLD_W::new(self, 1) } #[doc = "Bit 2 - NA"] #[inline(always)] #[must_use] - pub fn ibi_status_thld_int_raw(&mut self) -> IBI_STATUS_THLD_INT_RAW_W { - IBI_STATUS_THLD_INT_RAW_W::new(self, 2) + pub fn ibi_status_thld(&mut self) -> IBI_STATUS_THLD_W { + IBI_STATUS_THLD_W::new(self, 2) } #[doc = "Bit 3 - NA"] #[inline(always)] #[must_use] - pub fn cmd_buf_empty_thld_int_raw(&mut self) -> CMD_BUF_EMPTY_THLD_INT_RAW_W { - CMD_BUF_EMPTY_THLD_INT_RAW_W::new(self, 3) + pub fn cmd_buf_empty_thld(&mut self) -> CMD_BUF_EMPTY_THLD_W { + CMD_BUF_EMPTY_THLD_W::new(self, 3) } #[doc = "Bit 4 - NA"] #[inline(always)] #[must_use] - pub fn resp_ready_int_raw(&mut self) -> RESP_READY_INT_RAW_W { - RESP_READY_INT_RAW_W::new(self, 4) + pub fn resp_ready(&mut self) -> RESP_READY_W { + RESP_READY_W::new(self, 4) } #[doc = "Bit 5 - NA"] #[inline(always)] #[must_use] - pub fn nxt_cmd_req_err_int_raw(&mut self) -> NXT_CMD_REQ_ERR_INT_RAW_W { - NXT_CMD_REQ_ERR_INT_RAW_W::new(self, 5) + pub fn nxt_cmd_req_err(&mut self) -> NXT_CMD_REQ_ERR_W { + NXT_CMD_REQ_ERR_W::new(self, 5) } #[doc = "Bit 6 - NA"] #[inline(always)] #[must_use] - pub fn transfer_err_int_raw(&mut self) -> TRANSFER_ERR_INT_RAW_W { - TRANSFER_ERR_INT_RAW_W::new(self, 6) + pub fn transfer_err(&mut self) -> TRANSFER_ERR_W { + TRANSFER_ERR_W::new(self, 6) } #[doc = "Bit 7 - NA"] #[inline(always)] #[must_use] - pub fn transfer_complete_int_raw(&mut self) -> TRANSFER_COMPLETE_INT_RAW_W { - TRANSFER_COMPLETE_INT_RAW_W::new(self, 7) + pub fn transfer_complete(&mut self) -> TRANSFER_COMPLETE_W { + TRANSFER_COMPLETE_W::new(self, 7) } #[doc = "Bit 8 - NA"] #[inline(always)] #[must_use] - pub fn command_done_int_raw(&mut self) -> COMMAND_DONE_INT_RAW_W { - COMMAND_DONE_INT_RAW_W::new(self, 8) + pub fn command_done(&mut self) -> COMMAND_DONE_W { + COMMAND_DONE_W::new(self, 8) } #[doc = "Bit 9 - NA"] #[inline(always)] #[must_use] - pub fn detect_start_int_raw(&mut self) -> DETECT_START_INT_RAW_W { - DETECT_START_INT_RAW_W::new(self, 9) + pub fn detect_start(&mut self) -> DETECT_START_W { + DETECT_START_W::new(self, 9) } #[doc = "Bit 10 - NA"] #[inline(always)] #[must_use] - pub fn resp_buf_ovf_int_raw(&mut self) -> RESP_BUF_OVF_INT_RAW_W { - RESP_BUF_OVF_INT_RAW_W::new(self, 10) + pub fn resp_buf_ovf(&mut self) -> RESP_BUF_OVF_W { + RESP_BUF_OVF_W::new(self, 10) } #[doc = "Bit 11 - NA"] #[inline(always)] #[must_use] - pub fn ibi_data_buf_ovf_int_raw(&mut self) -> IBI_DATA_BUF_OVF_INT_RAW_W { - IBI_DATA_BUF_OVF_INT_RAW_W::new(self, 11) + pub fn ibi_data_buf_ovf(&mut self) -> IBI_DATA_BUF_OVF_W { + IBI_DATA_BUF_OVF_W::new(self, 11) } #[doc = "Bit 12 - NA"] #[inline(always)] #[must_use] - pub fn ibi_status_buf_ovf_int_raw(&mut self) -> IBI_STATUS_BUF_OVF_INT_RAW_W { - IBI_STATUS_BUF_OVF_INT_RAW_W::new(self, 12) + pub fn ibi_status_buf_ovf(&mut self) -> IBI_STATUS_BUF_OVF_W { + IBI_STATUS_BUF_OVF_W::new(self, 12) } #[doc = "Bit 13 - NA"] #[inline(always)] #[must_use] - pub fn ibi_handle_done_int_raw(&mut self) -> IBI_HANDLE_DONE_INT_RAW_W { - IBI_HANDLE_DONE_INT_RAW_W::new(self, 13) + pub fn ibi_handle_done(&mut self) -> IBI_HANDLE_DONE_W { + IBI_HANDLE_DONE_W::new(self, 13) } #[doc = "Bit 14 - NA"] #[inline(always)] #[must_use] - pub fn ibi_detect_int_raw(&mut self) -> IBI_DETECT_INT_RAW_W { - IBI_DETECT_INT_RAW_W::new(self, 14) + pub fn ibi_detect(&mut self) -> IBI_DETECT_W { + IBI_DETECT_W::new(self, 14) } #[doc = "Bit 15 - NA"] #[inline(always)] #[must_use] - pub fn cmd_ccc_mismatch_int_raw(&mut self) -> CMD_CCC_MISMATCH_INT_RAW_W { - CMD_CCC_MISMATCH_INT_RAW_W::new(self, 15) + pub fn cmd_ccc_mismatch(&mut self) -> CMD_CCC_MISMATCH_W { + CMD_CCC_MISMATCH_W::new(self, 15) } } #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/i3c_mst/int_st.rs b/esp32p4/src/i3c_mst/int_st.rs index d87a95aae1..5def15f933 100644 --- a/esp32p4/src/i3c_mst/int_st.rs +++ b/esp32p4/src/i3c_mst/int_st.rs @@ -1,117 +1,117 @@ #[doc = "Register `INT_ST` reader"] pub type R = crate::R; -#[doc = "Field `TX_DATA_BUF_THLD_INT_ST` reader - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value."] -pub type TX_DATA_BUF_THLD_INT_ST_R = crate::BitReader; -#[doc = "Field `RX_DATA_BUF_THLD_INT_ST` reader - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value."] -pub type RX_DATA_BUF_THLD_INT_ST_R = crate::BitReader; -#[doc = "Field `IBI_STATUS_THLD_INT_ST` reader - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value."] -pub type IBI_STATUS_THLD_INT_ST_R = crate::BitReader; -#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ST` reader - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value."] -pub type CMD_BUF_EMPTY_THLD_INT_ST_R = crate::BitReader; -#[doc = "Field `RESP_READY_INT_ST` reader - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value."] -pub type RESP_READY_INT_ST_R = crate::BitReader; -#[doc = "Field `NXT_CMD_REQ_ERR_INT_ST` reader - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty."] -pub type NXT_CMD_REQ_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `TRANSFER_ERR_INT_ST` reader - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1."] -pub type TRANSFER_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `TRANSFER_COMPLETE_INT_ST` reader - NA"] -pub type TRANSFER_COMPLETE_INT_ST_R = crate::BitReader; -#[doc = "Field `COMMAND_DONE_INT_ST` reader - NA"] -pub type COMMAND_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `DETECT_START_INT_ST` reader - NA"] -pub type DETECT_START_INT_ST_R = crate::BitReader; -#[doc = "Field `RESP_BUF_OVF_INT_ST` reader - NA"] -pub type RESP_BUF_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `IBI_DATA_BUF_OVF_INT_ST` reader - NA"] -pub type IBI_DATA_BUF_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ST` reader - NA"] -pub type IBI_STATUS_BUF_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `IBI_HANDLE_DONE_INT_ST` reader - NA"] -pub type IBI_HANDLE_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `IBI_DETECT_INT_ST` reader - NA"] -pub type IBI_DETECT_INT_ST_R = crate::BitReader; -#[doc = "Field `CMD_CCC_MISMATCH_INT_ST` reader - NA"] -pub type CMD_CCC_MISMATCH_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_DATA_BUF_THLD` reader - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value."] +pub type TX_DATA_BUF_THLD_R = crate::BitReader; +#[doc = "Field `RX_DATA_BUF_THLD` reader - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value."] +pub type RX_DATA_BUF_THLD_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_THLD` reader - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value."] +pub type IBI_STATUS_THLD_R = crate::BitReader; +#[doc = "Field `CMD_BUF_EMPTY_THLD` reader - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value."] +pub type CMD_BUF_EMPTY_THLD_R = crate::BitReader; +#[doc = "Field `RESP_READY` reader - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value."] +pub type RESP_READY_R = crate::BitReader; +#[doc = "Field `NXT_CMD_REQ_ERR` reader - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty."] +pub type NXT_CMD_REQ_ERR_R = crate::BitReader; +#[doc = "Field `TRANSFER_ERR` reader - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1."] +pub type TRANSFER_ERR_R = crate::BitReader; +#[doc = "Field `TRANSFER_COMPLETE` reader - NA"] +pub type TRANSFER_COMPLETE_R = crate::BitReader; +#[doc = "Field `COMMAND_DONE` reader - NA"] +pub type COMMAND_DONE_R = crate::BitReader; +#[doc = "Field `DETECT_START` reader - NA"] +pub type DETECT_START_R = crate::BitReader; +#[doc = "Field `RESP_BUF_OVF` reader - NA"] +pub type RESP_BUF_OVF_R = crate::BitReader; +#[doc = "Field `IBI_DATA_BUF_OVF` reader - NA"] +pub type IBI_DATA_BUF_OVF_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_BUF_OVF` reader - NA"] +pub type IBI_STATUS_BUF_OVF_R = crate::BitReader; +#[doc = "Field `IBI_HANDLE_DONE` reader - NA"] +pub type IBI_HANDLE_DONE_R = crate::BitReader; +#[doc = "Field `IBI_DETECT` reader - NA"] +pub type IBI_DETECT_R = crate::BitReader; +#[doc = "Field `CMD_CCC_MISMATCH` reader - NA"] +pub type CMD_CCC_MISMATCH_R = crate::BitReader; impl R { #[doc = "Bit 0 - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value."] #[inline(always)] - pub fn tx_data_buf_thld_int_st(&self) -> TX_DATA_BUF_THLD_INT_ST_R { - TX_DATA_BUF_THLD_INT_ST_R::new((self.bits & 1) != 0) + pub fn tx_data_buf_thld(&self) -> TX_DATA_BUF_THLD_R { + TX_DATA_BUF_THLD_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value."] #[inline(always)] - pub fn rx_data_buf_thld_int_st(&self) -> RX_DATA_BUF_THLD_INT_ST_R { - RX_DATA_BUF_THLD_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn rx_data_buf_thld(&self) -> RX_DATA_BUF_THLD_R { + RX_DATA_BUF_THLD_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value."] #[inline(always)] - pub fn ibi_status_thld_int_st(&self) -> IBI_STATUS_THLD_INT_ST_R { - IBI_STATUS_THLD_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn ibi_status_thld(&self) -> IBI_STATUS_THLD_R { + IBI_STATUS_THLD_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value."] #[inline(always)] - pub fn cmd_buf_empty_thld_int_st(&self) -> CMD_BUF_EMPTY_THLD_INT_ST_R { - CMD_BUF_EMPTY_THLD_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn cmd_buf_empty_thld(&self) -> CMD_BUF_EMPTY_THLD_R { + CMD_BUF_EMPTY_THLD_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value."] #[inline(always)] - pub fn resp_ready_int_st(&self) -> RESP_READY_INT_ST_R { - RESP_READY_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn resp_ready(&self) -> RESP_READY_R { + RESP_READY_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty."] #[inline(always)] - pub fn nxt_cmd_req_err_int_st(&self) -> NXT_CMD_REQ_ERR_INT_ST_R { - NXT_CMD_REQ_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn nxt_cmd_req_err(&self) -> NXT_CMD_REQ_ERR_R { + NXT_CMD_REQ_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1."] #[inline(always)] - pub fn transfer_err_int_st(&self) -> TRANSFER_ERR_INT_ST_R { - TRANSFER_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn transfer_err(&self) -> TRANSFER_ERR_R { + TRANSFER_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - NA"] #[inline(always)] - pub fn transfer_complete_int_st(&self) -> TRANSFER_COMPLETE_INT_ST_R { - TRANSFER_COMPLETE_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn transfer_complete(&self) -> TRANSFER_COMPLETE_R { + TRANSFER_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - NA"] #[inline(always)] - pub fn command_done_int_st(&self) -> COMMAND_DONE_INT_ST_R { - COMMAND_DONE_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn command_done(&self) -> COMMAND_DONE_R { + COMMAND_DONE_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - NA"] #[inline(always)] - pub fn detect_start_int_st(&self) -> DETECT_START_INT_ST_R { - DETECT_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn detect_start(&self) -> DETECT_START_R { + DETECT_START_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - NA"] #[inline(always)] - pub fn resp_buf_ovf_int_st(&self) -> RESP_BUF_OVF_INT_ST_R { - RESP_BUF_OVF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn resp_buf_ovf(&self) -> RESP_BUF_OVF_R { + RESP_BUF_OVF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - NA"] #[inline(always)] - pub fn ibi_data_buf_ovf_int_st(&self) -> IBI_DATA_BUF_OVF_INT_ST_R { - IBI_DATA_BUF_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn ibi_data_buf_ovf(&self) -> IBI_DATA_BUF_OVF_R { + IBI_DATA_BUF_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - NA"] #[inline(always)] - pub fn ibi_status_buf_ovf_int_st(&self) -> IBI_STATUS_BUF_OVF_INT_ST_R { - IBI_STATUS_BUF_OVF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn ibi_status_buf_ovf(&self) -> IBI_STATUS_BUF_OVF_R { + IBI_STATUS_BUF_OVF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - NA"] #[inline(always)] - pub fn ibi_handle_done_int_st(&self) -> IBI_HANDLE_DONE_INT_ST_R { - IBI_HANDLE_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + pub fn ibi_handle_done(&self) -> IBI_HANDLE_DONE_R { + IBI_HANDLE_DONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - NA"] #[inline(always)] - pub fn ibi_detect_int_st(&self) -> IBI_DETECT_INT_ST_R { - IBI_DETECT_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + pub fn ibi_detect(&self) -> IBI_DETECT_R { + IBI_DETECT_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - NA"] #[inline(always)] - pub fn cmd_ccc_mismatch_int_st(&self) -> CMD_CCC_MISMATCH_INT_ST_R { - CMD_CCC_MISMATCH_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + pub fn cmd_ccc_mismatch(&self) -> CMD_CCC_MISMATCH_R { + CMD_CCC_MISMATCH_R::new(((self.bits >> 15) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -119,68 +119,62 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ST") .field( - "tx_data_buf_thld_int_st", - &format_args!("{}", self.tx_data_buf_thld_int_st().bit()), + "tx_data_buf_thld", + &format_args!("{}", self.tx_data_buf_thld().bit()), ) .field( - "rx_data_buf_thld_int_st", - &format_args!("{}", self.rx_data_buf_thld_int_st().bit()), + "rx_data_buf_thld", + &format_args!("{}", self.rx_data_buf_thld().bit()), ) .field( - "ibi_status_thld_int_st", - &format_args!("{}", self.ibi_status_thld_int_st().bit()), + "ibi_status_thld", + &format_args!("{}", self.ibi_status_thld().bit()), ) .field( - "cmd_buf_empty_thld_int_st", - &format_args!("{}", self.cmd_buf_empty_thld_int_st().bit()), + "cmd_buf_empty_thld", + &format_args!("{}", self.cmd_buf_empty_thld().bit()), ) + .field("resp_ready", &format_args!("{}", self.resp_ready().bit())) .field( - "resp_ready_int_st", - &format_args!("{}", self.resp_ready_int_st().bit()), + "nxt_cmd_req_err", + &format_args!("{}", self.nxt_cmd_req_err().bit()), ) .field( - "nxt_cmd_req_err_int_st", - &format_args!("{}", self.nxt_cmd_req_err_int_st().bit()), + "transfer_err", + &format_args!("{}", self.transfer_err().bit()), ) .field( - "transfer_err_int_st", - &format_args!("{}", self.transfer_err_int_st().bit()), + "transfer_complete", + &format_args!("{}", self.transfer_complete().bit()), ) .field( - "transfer_complete_int_st", - &format_args!("{}", self.transfer_complete_int_st().bit()), + "command_done", + &format_args!("{}", self.command_done().bit()), ) .field( - "command_done_int_st", - &format_args!("{}", self.command_done_int_st().bit()), + "detect_start", + &format_args!("{}", self.detect_start().bit()), ) .field( - "detect_start_int_st", - &format_args!("{}", self.detect_start_int_st().bit()), + "resp_buf_ovf", + &format_args!("{}", self.resp_buf_ovf().bit()), ) .field( - "resp_buf_ovf_int_st", - &format_args!("{}", self.resp_buf_ovf_int_st().bit()), + "ibi_data_buf_ovf", + &format_args!("{}", self.ibi_data_buf_ovf().bit()), ) .field( - "ibi_data_buf_ovf_int_st", - &format_args!("{}", self.ibi_data_buf_ovf_int_st().bit()), + "ibi_status_buf_ovf", + &format_args!("{}", self.ibi_status_buf_ovf().bit()), ) .field( - "ibi_status_buf_ovf_int_st", - &format_args!("{}", self.ibi_status_buf_ovf_int_st().bit()), + "ibi_handle_done", + &format_args!("{}", self.ibi_handle_done().bit()), ) + .field("ibi_detect", &format_args!("{}", self.ibi_detect().bit())) .field( - "ibi_handle_done_int_st", - &format_args!("{}", self.ibi_handle_done_int_st().bit()), - ) - .field( - "ibi_detect_int_st", - &format_args!("{}", self.ibi_detect_int_st().bit()), - ) - .field( - "cmd_ccc_mismatch_int_st", - &format_args!("{}", self.cmd_ccc_mismatch_int_st().bit()), + "cmd_ccc_mismatch", + &format_args!("{}", self.cmd_ccc_mismatch().bit()), ) .finish() } diff --git a/esp32p4/src/i3c_mst/int_st_ena.rs b/esp32p4/src/i3c_mst/int_st_ena.rs deleted file mode 100644 index 567ba211ac..0000000000 --- a/esp32p4/src/i3c_mst/int_st_ena.rs +++ /dev/null @@ -1,342 +0,0 @@ -#[doc = "Register `INT_ST_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `INT_ST_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `TX_DATA_BUF_THLD_INT_ENA` reader - Transmit Buffer threshold status enable."] -pub type TX_DATA_BUF_THLD_INT_ENA_R = crate::BitReader; -#[doc = "Field `TX_DATA_BUF_THLD_INT_ENA` writer - Transmit Buffer threshold status enable."] -pub type TX_DATA_BUF_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_DATA_BUF_THLD_INT_ENA` reader - Receive Buffer threshold status enable."] -pub type RX_DATA_BUF_THLD_INT_ENA_R = crate::BitReader; -#[doc = "Field `RX_DATA_BUF_THLD_INT_ENA` writer - Receive Buffer threshold status enable."] -pub type RX_DATA_BUF_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_STATUS_THLD_INT_ENA` reader - Only used in master mode. IBI Buffer threshold status enable."] -pub type IBI_STATUS_THLD_INT_ENA_R = crate::BitReader; -#[doc = "Field `IBI_STATUS_THLD_INT_ENA` writer - Only used in master mode. IBI Buffer threshold status enable."] -pub type IBI_STATUS_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ENA` reader - Command buffer ready status enable."] -pub type CMD_BUF_EMPTY_THLD_INT_ENA_R = crate::BitReader; -#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ENA` writer - Command buffer ready status enable."] -pub type CMD_BUF_EMPTY_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESP_READY_INT_ENA` reader - Response buffer ready status enable."] -pub type RESP_READY_INT_ENA_R = crate::BitReader; -#[doc = "Field `RESP_READY_INT_ENA` writer - Response buffer ready status enable."] -pub type RESP_READY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `NXT_CMD_REQ_ERR_INT_ENA` reader - next command request error status enable"] -pub type NXT_CMD_REQ_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `NXT_CMD_REQ_ERR_INT_ENA` writer - next command request error status enable"] -pub type NXT_CMD_REQ_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANSFER_ERR_INT_ENA` reader - Transfer error status enable"] -pub type TRANSFER_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `TRANSFER_ERR_INT_ENA` writer - Transfer error status enable"] -pub type TRANSFER_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANSFER_COMPLETE_INT_ENA` reader - NA"] -pub type TRANSFER_COMPLETE_INT_ENA_R = crate::BitReader; -#[doc = "Field `TRANSFER_COMPLETE_INT_ENA` writer - NA"] -pub type TRANSFER_COMPLETE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `COMMAND_DONE_INT_ENA` reader - NA"] -pub type COMMAND_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `COMMAND_DONE_INT_ENA` writer - NA"] -pub type COMMAND_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DETECT_START_INT_ENA` reader - NA"] -pub type DETECT_START_INT_ENA_R = crate::BitReader; -#[doc = "Field `DETECT_START_INT_ENA` writer - NA"] -pub type DETECT_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESP_BUF_OVF_INT_ENA` reader - NA"] -pub type RESP_BUF_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `RESP_BUF_OVF_INT_ENA` writer - NA"] -pub type RESP_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_DATA_BUF_OVF_INT_ENA` reader - NA"] -pub type IBI_DATA_BUF_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `IBI_DATA_BUF_OVF_INT_ENA` writer - NA"] -pub type IBI_DATA_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ENA` reader - NA"] -pub type IBI_STATUS_BUF_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ENA` writer - NA"] -pub type IBI_STATUS_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_HANDLE_DONE_INT_ENA` reader - NA"] -pub type IBI_HANDLE_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `IBI_HANDLE_DONE_INT_ENA` writer - NA"] -pub type IBI_HANDLE_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `IBI_DETECT_INT_ENA` reader - NA"] -pub type IBI_DETECT_INT_ENA_R = crate::BitReader; -#[doc = "Field `IBI_DETECT_INT_ENA` writer - NA"] -pub type IBI_DETECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CMD_CCC_MISMATCH_INT_ENA` reader - NA"] -pub type CMD_CCC_MISMATCH_INT_ENA_R = crate::BitReader; -#[doc = "Field `CMD_CCC_MISMATCH_INT_ENA` writer - NA"] -pub type CMD_CCC_MISMATCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Transmit Buffer threshold status enable."] - #[inline(always)] - pub fn tx_data_buf_thld_int_ena(&self) -> TX_DATA_BUF_THLD_INT_ENA_R { - TX_DATA_BUF_THLD_INT_ENA_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Receive Buffer threshold status enable."] - #[inline(always)] - pub fn rx_data_buf_thld_int_ena(&self) -> RX_DATA_BUF_THLD_INT_ENA_R { - RX_DATA_BUF_THLD_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."] - #[inline(always)] - pub fn ibi_status_thld_int_ena(&self) -> IBI_STATUS_THLD_INT_ENA_R { - IBI_STATUS_THLD_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Command buffer ready status enable."] - #[inline(always)] - pub fn cmd_buf_empty_thld_int_ena(&self) -> CMD_BUF_EMPTY_THLD_INT_ENA_R { - CMD_BUF_EMPTY_THLD_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - Response buffer ready status enable."] - #[inline(always)] - pub fn resp_ready_int_ena(&self) -> RESP_READY_INT_ENA_R { - RESP_READY_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - next command request error status enable"] - #[inline(always)] - pub fn nxt_cmd_req_err_int_ena(&self) -> NXT_CMD_REQ_ERR_INT_ENA_R { - NXT_CMD_REQ_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Transfer error status enable"] - #[inline(always)] - pub fn transfer_err_int_ena(&self) -> TRANSFER_ERR_INT_ENA_R { - TRANSFER_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - NA"] - #[inline(always)] - pub fn transfer_complete_int_ena(&self) -> TRANSFER_COMPLETE_INT_ENA_R { - TRANSFER_COMPLETE_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - NA"] - #[inline(always)] - pub fn command_done_int_ena(&self) -> COMMAND_DONE_INT_ENA_R { - COMMAND_DONE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - NA"] - #[inline(always)] - pub fn detect_start_int_ena(&self) -> DETECT_START_INT_ENA_R { - DETECT_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - NA"] - #[inline(always)] - pub fn resp_buf_ovf_int_ena(&self) -> RESP_BUF_OVF_INT_ENA_R { - RESP_BUF_OVF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - NA"] - #[inline(always)] - pub fn ibi_data_buf_ovf_int_ena(&self) -> IBI_DATA_BUF_OVF_INT_ENA_R { - IBI_DATA_BUF_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - NA"] - #[inline(always)] - pub fn ibi_status_buf_ovf_int_ena(&self) -> IBI_STATUS_BUF_OVF_INT_ENA_R { - IBI_STATUS_BUF_OVF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - NA"] - #[inline(always)] - pub fn ibi_handle_done_int_ena(&self) -> IBI_HANDLE_DONE_INT_ENA_R { - IBI_HANDLE_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - NA"] - #[inline(always)] - pub fn ibi_detect_int_ena(&self) -> IBI_DETECT_INT_ENA_R { - IBI_DETECT_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - NA"] - #[inline(always)] - pub fn cmd_ccc_mismatch_int_ena(&self) -> CMD_CCC_MISMATCH_INT_ENA_R { - CMD_CCC_MISMATCH_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("INT_ST_ENA") - .field( - "tx_data_buf_thld_int_ena", - &format_args!("{}", self.tx_data_buf_thld_int_ena().bit()), - ) - .field( - "rx_data_buf_thld_int_ena", - &format_args!("{}", self.rx_data_buf_thld_int_ena().bit()), - ) - .field( - "ibi_status_thld_int_ena", - &format_args!("{}", self.ibi_status_thld_int_ena().bit()), - ) - .field( - "cmd_buf_empty_thld_int_ena", - &format_args!("{}", self.cmd_buf_empty_thld_int_ena().bit()), - ) - .field( - "resp_ready_int_ena", - &format_args!("{}", self.resp_ready_int_ena().bit()), - ) - .field( - "nxt_cmd_req_err_int_ena", - &format_args!("{}", self.nxt_cmd_req_err_int_ena().bit()), - ) - .field( - "transfer_err_int_ena", - &format_args!("{}", self.transfer_err_int_ena().bit()), - ) - .field( - "transfer_complete_int_ena", - &format_args!("{}", self.transfer_complete_int_ena().bit()), - ) - .field( - "command_done_int_ena", - &format_args!("{}", self.command_done_int_ena().bit()), - ) - .field( - "detect_start_int_ena", - &format_args!("{}", self.detect_start_int_ena().bit()), - ) - .field( - "resp_buf_ovf_int_ena", - &format_args!("{}", self.resp_buf_ovf_int_ena().bit()), - ) - .field( - "ibi_data_buf_ovf_int_ena", - &format_args!("{}", self.ibi_data_buf_ovf_int_ena().bit()), - ) - .field( - "ibi_status_buf_ovf_int_ena", - &format_args!("{}", self.ibi_status_buf_ovf_int_ena().bit()), - ) - .field( - "ibi_handle_done_int_ena", - &format_args!("{}", self.ibi_handle_done_int_ena().bit()), - ) - .field( - "ibi_detect_int_ena", - &format_args!("{}", self.ibi_detect_int_ena().bit()), - ) - .field( - "cmd_ccc_mismatch_int_ena", - &format_args!("{}", self.cmd_ccc_mismatch_int_ena().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - Transmit Buffer threshold status enable."] - #[inline(always)] - #[must_use] - pub fn tx_data_buf_thld_int_ena(&mut self) -> TX_DATA_BUF_THLD_INT_ENA_W { - TX_DATA_BUF_THLD_INT_ENA_W::new(self, 0) - } - #[doc = "Bit 1 - Receive Buffer threshold status enable."] - #[inline(always)] - #[must_use] - pub fn rx_data_buf_thld_int_ena(&mut self) -> RX_DATA_BUF_THLD_INT_ENA_W { - RX_DATA_BUF_THLD_INT_ENA_W::new(self, 1) - } - #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."] - #[inline(always)] - #[must_use] - pub fn ibi_status_thld_int_ena(&mut self) -> IBI_STATUS_THLD_INT_ENA_W { - IBI_STATUS_THLD_INT_ENA_W::new(self, 2) - } - #[doc = "Bit 3 - Command buffer ready status enable."] - #[inline(always)] - #[must_use] - pub fn cmd_buf_empty_thld_int_ena(&mut self) -> CMD_BUF_EMPTY_THLD_INT_ENA_W { - CMD_BUF_EMPTY_THLD_INT_ENA_W::new(self, 3) - } - #[doc = "Bit 4 - Response buffer ready status enable."] - #[inline(always)] - #[must_use] - pub fn resp_ready_int_ena(&mut self) -> RESP_READY_INT_ENA_W { - RESP_READY_INT_ENA_W::new(self, 4) - } - #[doc = "Bit 5 - next command request error status enable"] - #[inline(always)] - #[must_use] - pub fn nxt_cmd_req_err_int_ena(&mut self) -> NXT_CMD_REQ_ERR_INT_ENA_W { - NXT_CMD_REQ_ERR_INT_ENA_W::new(self, 5) - } - #[doc = "Bit 6 - Transfer error status enable"] - #[inline(always)] - #[must_use] - pub fn transfer_err_int_ena(&mut self) -> TRANSFER_ERR_INT_ENA_W { - TRANSFER_ERR_INT_ENA_W::new(self, 6) - } - #[doc = "Bit 7 - NA"] - #[inline(always)] - #[must_use] - pub fn transfer_complete_int_ena(&mut self) -> TRANSFER_COMPLETE_INT_ENA_W { - TRANSFER_COMPLETE_INT_ENA_W::new(self, 7) - } - #[doc = "Bit 8 - NA"] - #[inline(always)] - #[must_use] - pub fn command_done_int_ena(&mut self) -> COMMAND_DONE_INT_ENA_W { - COMMAND_DONE_INT_ENA_W::new(self, 8) - } - #[doc = "Bit 9 - NA"] - #[inline(always)] - #[must_use] - pub fn detect_start_int_ena(&mut self) -> DETECT_START_INT_ENA_W { - DETECT_START_INT_ENA_W::new(self, 9) - } - #[doc = "Bit 10 - NA"] - #[inline(always)] - #[must_use] - pub fn resp_buf_ovf_int_ena(&mut self) -> RESP_BUF_OVF_INT_ENA_W { - RESP_BUF_OVF_INT_ENA_W::new(self, 10) - } - #[doc = "Bit 11 - NA"] - #[inline(always)] - #[must_use] - pub fn ibi_data_buf_ovf_int_ena(&mut self) -> IBI_DATA_BUF_OVF_INT_ENA_W { - IBI_DATA_BUF_OVF_INT_ENA_W::new(self, 11) - } - #[doc = "Bit 12 - NA"] - #[inline(always)] - #[must_use] - pub fn ibi_status_buf_ovf_int_ena(&mut self) -> IBI_STATUS_BUF_OVF_INT_ENA_W { - IBI_STATUS_BUF_OVF_INT_ENA_W::new(self, 12) - } - #[doc = "Bit 13 - NA"] - #[inline(always)] - #[must_use] - pub fn ibi_handle_done_int_ena(&mut self) -> IBI_HANDLE_DONE_INT_ENA_W { - IBI_HANDLE_DONE_INT_ENA_W::new(self, 13) - } - #[doc = "Bit 14 - NA"] - #[inline(always)] - #[must_use] - pub fn ibi_detect_int_ena(&mut self) -> IBI_DETECT_INT_ENA_W { - IBI_DETECT_INT_ENA_W::new(self, 14) - } - #[doc = "Bit 15 - NA"] - #[inline(always)] - #[must_use] - pub fn cmd_ccc_mismatch_int_ena(&mut self) -> CMD_CCC_MISMATCH_INT_ENA_W { - CMD_CCC_MISMATCH_INT_ENA_W::new(self, 15) - } -} -#[doc = "The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct INT_ST_ENA_SPEC; -impl crate::RegisterSpec for INT_ST_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`int_st_ena::R`](R) reader structure"] -impl crate::Readable for INT_ST_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`int_st_ena::W`](W) writer structure"] -impl crate::Writable for INT_ST_ENA_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets INT_ST_ENA to value 0"] -impl crate::Resettable for INT_ST_ENA_SPEC { - const RESET_VALUE: u32 = 0; -} diff --git a/esp32p4/src/isp/int_clr.rs b/esp32p4/src/isp/int_clr.rs index 65ebb87a2c..8c2ab01a5a 100644 --- a/esp32p4/src/isp/int_clr.rs +++ b/esp32p4/src/isp/int_clr.rs @@ -1,63 +1,63 @@ #[doc = "Register `INT_CLR` writer"] pub type W = crate::W; -#[doc = "Field `ISP_DATA_TYPE_ERR_INT_CLR` writer - write 1 to clear input data type error"] -pub type ISP_DATA_TYPE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_CLR` writer - write 1 to clear isp input fifo overflow"] -pub type ISP_ASYNC_FIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_BUF_FULL_INT_CLR` writer - write 1 to clear isp input buffer full"] -pub type ISP_BUF_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_CLR` writer - write 1 to clear hnum and vnum setting format error"] -pub type ISP_HVNUM_SETTING_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_CLR` writer - write 1 to clear setting invalid reg_data_type"] -pub type ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_CLR` writer - write 1 to clear hnum setting unmatch with mipi input"] -pub type ISP_MIPI_HNUM_UNMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DPC_CHECK_DONE_INT_CLR` writer - write 1 to clear dpc check done"] -pub type DPC_CHECK_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GAMMA_XCOORD_ERR_INT_CLR` writer - write 1 to clear gamma setting error"] -pub type GAMMA_XCOORD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AE_MONITOR_INT_CLR` writer - write 1 to clear ae monitor"] -pub type AE_MONITOR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AE_FRAME_DONE_INT_CLR` writer - write 1 to clear ae"] -pub type AE_FRAME_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AF_FDONE_INT_CLR` writer - write 1 to clear af statistic"] -pub type AF_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AF_ENV_INT_CLR` writer - write 1 to clear af monitor"] -pub type AF_ENV_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AWB_FDONE_INT_CLR` writer - write 1 to clear awb"] -pub type AWB_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HIST_FDONE_INT_CLR` writer - write 1 to clear histogram"] -pub type HIST_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FRAME_INT_CLR` writer - write 1 to clear isp frame end"] -pub type FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BLC_FRAME_INT_CLR` writer - write 1 to clear blc frame done"] -pub type BLC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LSC_FRAME_INT_CLR` writer - write 1 to clear lsc frame done"] -pub type LSC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DPC_FRAME_INT_CLR` writer - write 1 to clear dpc frame done"] -pub type DPC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BF_FRAME_INT_CLR` writer - write 1 to clear bf frame done"] -pub type BF_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DEMOSAIC_FRAME_INT_CLR` writer - write 1 to clear demosaic frame done"] -pub type DEMOSAIC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MEDIAN_FRAME_INT_CLR` writer - write 1 to clear median frame done"] -pub type MEDIAN_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CCM_FRAME_INT_CLR` writer - write 1 to clear ccm frame done"] -pub type CCM_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GAMMA_FRAME_INT_CLR` writer - write 1 to clear gamma frame done"] -pub type GAMMA_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RGB2YUV_FRAME_INT_CLR` writer - write 1 to clear rgb2yuv frame done"] -pub type RGB2YUV_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SHARP_FRAME_INT_CLR` writer - write 1 to clear sharp frame done"] -pub type SHARP_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `COLOR_FRAME_INT_CLR` writer - write 1 to clear color frame done"] -pub type COLOR_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `YUV2RGB_FRAME_INT_CLR` writer - write 1 to clear yuv2rgb frame done"] -pub type YUV2RGB_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TAIL_IDI_FRAME_INT_CLR` writer - write 1 to clear isp_tail idi frame_end"] -pub type TAIL_IDI_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HEADER_IDI_FRAME_INT_CLR` writer - write 1 to clear real input frame end of isp_input"] -pub type HEADER_IDI_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_DATA_TYPE_ERR` writer - write 1 to clear input data type error"] +pub type ISP_DATA_TYPE_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ISP_ASYNC_FIFO_OVF` writer - write 1 to clear isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ISP_BUF_FULL` writer - write 1 to clear isp input buffer full"] +pub type ISP_BUF_FULL_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ISP_HVNUM_SETTING_ERR` writer - write 1 to clear hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR` writer - write 1 to clear setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH` writer - write 1 to clear hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DPC_CHECK_DONE` writer - write 1 to clear dpc check done"] +pub type DPC_CHECK_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GAMMA_XCOORD_ERR` writer - write 1 to clear gamma setting error"] +pub type GAMMA_XCOORD_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AE_MONITOR` writer - write 1 to clear ae monitor"] +pub type AE_MONITOR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AE_FRAME_DONE` writer - write 1 to clear ae"] +pub type AE_FRAME_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AF_FDONE` writer - write 1 to clear af statistic"] +pub type AF_FDONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AF_ENV` writer - write 1 to clear af monitor"] +pub type AF_ENV_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AWB_FDONE` writer - write 1 to clear awb"] +pub type AWB_FDONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `HIST_FDONE` writer - write 1 to clear histogram"] +pub type HIST_FDONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `FRAME` writer - write 1 to clear isp frame end"] +pub type FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BLC_FRAME` writer - write 1 to clear blc frame done"] +pub type BLC_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `LSC_FRAME` writer - write 1 to clear lsc frame done"] +pub type LSC_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DPC_FRAME` writer - write 1 to clear dpc frame done"] +pub type DPC_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BF_FRAME` writer - write 1 to clear bf frame done"] +pub type BF_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DEMOSAIC_FRAME` writer - write 1 to clear demosaic frame done"] +pub type DEMOSAIC_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `MEDIAN_FRAME` writer - write 1 to clear median frame done"] +pub type MEDIAN_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CCM_FRAME` writer - write 1 to clear ccm frame done"] +pub type CCM_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GAMMA_FRAME` writer - write 1 to clear gamma frame done"] +pub type GAMMA_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RGB2YUV_FRAME` writer - write 1 to clear rgb2yuv frame done"] +pub type RGB2YUV_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SHARP_FRAME` writer - write 1 to clear sharp frame done"] +pub type SHARP_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `COLOR_FRAME` writer - write 1 to clear color frame done"] +pub type COLOR_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `YUV2RGB_FRAME` writer - write 1 to clear yuv2rgb frame done"] +pub type YUV2RGB_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TAIL_IDI_FRAME` writer - write 1 to clear isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `HEADER_IDI_FRAME` writer - write 1 to clear real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -68,182 +68,176 @@ impl W { #[doc = "Bit 0 - write 1 to clear input data type error"] #[inline(always)] #[must_use] - pub fn isp_data_type_err_int_clr(&mut self) -> ISP_DATA_TYPE_ERR_INT_CLR_W { - ISP_DATA_TYPE_ERR_INT_CLR_W::new(self, 0) + pub fn isp_data_type_err(&mut self) -> ISP_DATA_TYPE_ERR_W { + ISP_DATA_TYPE_ERR_W::new(self, 0) } #[doc = "Bit 1 - write 1 to clear isp input fifo overflow"] #[inline(always)] #[must_use] - pub fn isp_async_fifo_ovf_int_clr(&mut self) -> ISP_ASYNC_FIFO_OVF_INT_CLR_W { - ISP_ASYNC_FIFO_OVF_INT_CLR_W::new(self, 1) + pub fn isp_async_fifo_ovf(&mut self) -> ISP_ASYNC_FIFO_OVF_W { + ISP_ASYNC_FIFO_OVF_W::new(self, 1) } #[doc = "Bit 2 - write 1 to clear isp input buffer full"] #[inline(always)] #[must_use] - pub fn isp_buf_full_int_clr(&mut self) -> ISP_BUF_FULL_INT_CLR_W { - ISP_BUF_FULL_INT_CLR_W::new(self, 2) + pub fn isp_buf_full(&mut self) -> ISP_BUF_FULL_W { + ISP_BUF_FULL_W::new(self, 2) } #[doc = "Bit 3 - write 1 to clear hnum and vnum setting format error"] #[inline(always)] #[must_use] - pub fn isp_hvnum_setting_err_int_clr( - &mut self, - ) -> ISP_HVNUM_SETTING_ERR_INT_CLR_W { - ISP_HVNUM_SETTING_ERR_INT_CLR_W::new(self, 3) + pub fn isp_hvnum_setting_err(&mut self) -> ISP_HVNUM_SETTING_ERR_W { + ISP_HVNUM_SETTING_ERR_W::new(self, 3) } #[doc = "Bit 4 - write 1 to clear setting invalid reg_data_type"] #[inline(always)] #[must_use] - pub fn isp_data_type_setting_err_int_clr( - &mut self, - ) -> ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W { - ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W::new(self, 4) + pub fn isp_data_type_setting_err(&mut self) -> ISP_DATA_TYPE_SETTING_ERR_W { + ISP_DATA_TYPE_SETTING_ERR_W::new(self, 4) } #[doc = "Bit 5 - write 1 to clear hnum setting unmatch with mipi input"] #[inline(always)] #[must_use] - pub fn isp_mipi_hnum_unmatch_int_clr( - &mut self, - ) -> ISP_MIPI_HNUM_UNMATCH_INT_CLR_W { - ISP_MIPI_HNUM_UNMATCH_INT_CLR_W::new(self, 5) + pub fn isp_mipi_hnum_unmatch(&mut self) -> ISP_MIPI_HNUM_UNMATCH_W { + ISP_MIPI_HNUM_UNMATCH_W::new(self, 5) } #[doc = "Bit 6 - write 1 to clear dpc check done"] #[inline(always)] #[must_use] - pub fn dpc_check_done_int_clr(&mut self) -> DPC_CHECK_DONE_INT_CLR_W { - DPC_CHECK_DONE_INT_CLR_W::new(self, 6) + pub fn dpc_check_done(&mut self) -> DPC_CHECK_DONE_W { + DPC_CHECK_DONE_W::new(self, 6) } #[doc = "Bit 7 - write 1 to clear gamma setting error"] #[inline(always)] #[must_use] - pub fn gamma_xcoord_err_int_clr(&mut self) -> GAMMA_XCOORD_ERR_INT_CLR_W { - GAMMA_XCOORD_ERR_INT_CLR_W::new(self, 7) + pub fn gamma_xcoord_err(&mut self) -> GAMMA_XCOORD_ERR_W { + GAMMA_XCOORD_ERR_W::new(self, 7) } #[doc = "Bit 8 - write 1 to clear ae monitor"] #[inline(always)] #[must_use] - pub fn ae_monitor_int_clr(&mut self) -> AE_MONITOR_INT_CLR_W { - AE_MONITOR_INT_CLR_W::new(self, 8) + pub fn ae_monitor(&mut self) -> AE_MONITOR_W { + AE_MONITOR_W::new(self, 8) } #[doc = "Bit 9 - write 1 to clear ae"] #[inline(always)] #[must_use] - pub fn ae_frame_done_int_clr(&mut self) -> AE_FRAME_DONE_INT_CLR_W { - AE_FRAME_DONE_INT_CLR_W::new(self, 9) + pub fn ae_frame_done(&mut self) -> AE_FRAME_DONE_W { + AE_FRAME_DONE_W::new(self, 9) } #[doc = "Bit 10 - write 1 to clear af statistic"] #[inline(always)] #[must_use] - pub fn af_fdone_int_clr(&mut self) -> AF_FDONE_INT_CLR_W { - AF_FDONE_INT_CLR_W::new(self, 10) + pub fn af_fdone(&mut self) -> AF_FDONE_W { + AF_FDONE_W::new(self, 10) } #[doc = "Bit 11 - write 1 to clear af monitor"] #[inline(always)] #[must_use] - pub fn af_env_int_clr(&mut self) -> AF_ENV_INT_CLR_W { - AF_ENV_INT_CLR_W::new(self, 11) + pub fn af_env(&mut self) -> AF_ENV_W { + AF_ENV_W::new(self, 11) } #[doc = "Bit 12 - write 1 to clear awb"] #[inline(always)] #[must_use] - pub fn awb_fdone_int_clr(&mut self) -> AWB_FDONE_INT_CLR_W { - AWB_FDONE_INT_CLR_W::new(self, 12) + pub fn awb_fdone(&mut self) -> AWB_FDONE_W { + AWB_FDONE_W::new(self, 12) } #[doc = "Bit 13 - write 1 to clear histogram"] #[inline(always)] #[must_use] - pub fn hist_fdone_int_clr(&mut self) -> HIST_FDONE_INT_CLR_W { - HIST_FDONE_INT_CLR_W::new(self, 13) + pub fn hist_fdone(&mut self) -> HIST_FDONE_W { + HIST_FDONE_W::new(self, 13) } #[doc = "Bit 14 - write 1 to clear isp frame end"] #[inline(always)] #[must_use] - pub fn frame_int_clr(&mut self) -> FRAME_INT_CLR_W { - FRAME_INT_CLR_W::new(self, 14) + pub fn frame(&mut self) -> FRAME_W { + FRAME_W::new(self, 14) } #[doc = "Bit 15 - write 1 to clear blc frame done"] #[inline(always)] #[must_use] - pub fn blc_frame_int_clr(&mut self) -> BLC_FRAME_INT_CLR_W { - BLC_FRAME_INT_CLR_W::new(self, 15) + pub fn blc_frame(&mut self) -> BLC_FRAME_W { + BLC_FRAME_W::new(self, 15) } #[doc = "Bit 16 - write 1 to clear lsc frame done"] #[inline(always)] #[must_use] - pub fn lsc_frame_int_clr(&mut self) -> LSC_FRAME_INT_CLR_W { - LSC_FRAME_INT_CLR_W::new(self, 16) + pub fn lsc_frame(&mut self) -> LSC_FRAME_W { + LSC_FRAME_W::new(self, 16) } #[doc = "Bit 17 - write 1 to clear dpc frame done"] #[inline(always)] #[must_use] - pub fn dpc_frame_int_clr(&mut self) -> DPC_FRAME_INT_CLR_W { - DPC_FRAME_INT_CLR_W::new(self, 17) + pub fn dpc_frame(&mut self) -> DPC_FRAME_W { + DPC_FRAME_W::new(self, 17) } #[doc = "Bit 18 - write 1 to clear bf frame done"] #[inline(always)] #[must_use] - pub fn bf_frame_int_clr(&mut self) -> BF_FRAME_INT_CLR_W { - BF_FRAME_INT_CLR_W::new(self, 18) + pub fn bf_frame(&mut self) -> BF_FRAME_W { + BF_FRAME_W::new(self, 18) } #[doc = "Bit 19 - write 1 to clear demosaic frame done"] #[inline(always)] #[must_use] - pub fn demosaic_frame_int_clr(&mut self) -> DEMOSAIC_FRAME_INT_CLR_W { - DEMOSAIC_FRAME_INT_CLR_W::new(self, 19) + pub fn demosaic_frame(&mut self) -> DEMOSAIC_FRAME_W { + DEMOSAIC_FRAME_W::new(self, 19) } #[doc = "Bit 20 - write 1 to clear median frame done"] #[inline(always)] #[must_use] - pub fn median_frame_int_clr(&mut self) -> MEDIAN_FRAME_INT_CLR_W { - MEDIAN_FRAME_INT_CLR_W::new(self, 20) + pub fn median_frame(&mut self) -> MEDIAN_FRAME_W { + MEDIAN_FRAME_W::new(self, 20) } #[doc = "Bit 21 - write 1 to clear ccm frame done"] #[inline(always)] #[must_use] - pub fn ccm_frame_int_clr(&mut self) -> CCM_FRAME_INT_CLR_W { - CCM_FRAME_INT_CLR_W::new(self, 21) + pub fn ccm_frame(&mut self) -> CCM_FRAME_W { + CCM_FRAME_W::new(self, 21) } #[doc = "Bit 22 - write 1 to clear gamma frame done"] #[inline(always)] #[must_use] - pub fn gamma_frame_int_clr(&mut self) -> GAMMA_FRAME_INT_CLR_W { - GAMMA_FRAME_INT_CLR_W::new(self, 22) + pub fn gamma_frame(&mut self) -> GAMMA_FRAME_W { + GAMMA_FRAME_W::new(self, 22) } #[doc = "Bit 23 - write 1 to clear rgb2yuv frame done"] #[inline(always)] #[must_use] - pub fn rgb2yuv_frame_int_clr(&mut self) -> RGB2YUV_FRAME_INT_CLR_W { - RGB2YUV_FRAME_INT_CLR_W::new(self, 23) + pub fn rgb2yuv_frame(&mut self) -> RGB2YUV_FRAME_W { + RGB2YUV_FRAME_W::new(self, 23) } #[doc = "Bit 24 - write 1 to clear sharp frame done"] #[inline(always)] #[must_use] - pub fn sharp_frame_int_clr(&mut self) -> SHARP_FRAME_INT_CLR_W { - SHARP_FRAME_INT_CLR_W::new(self, 24) + pub fn sharp_frame(&mut self) -> SHARP_FRAME_W { + SHARP_FRAME_W::new(self, 24) } #[doc = "Bit 25 - write 1 to clear color frame done"] #[inline(always)] #[must_use] - pub fn color_frame_int_clr(&mut self) -> COLOR_FRAME_INT_CLR_W { - COLOR_FRAME_INT_CLR_W::new(self, 25) + pub fn color_frame(&mut self) -> COLOR_FRAME_W { + COLOR_FRAME_W::new(self, 25) } #[doc = "Bit 26 - write 1 to clear yuv2rgb frame done"] #[inline(always)] #[must_use] - pub fn yuv2rgb_frame_int_clr(&mut self) -> YUV2RGB_FRAME_INT_CLR_W { - YUV2RGB_FRAME_INT_CLR_W::new(self, 26) + pub fn yuv2rgb_frame(&mut self) -> YUV2RGB_FRAME_W { + YUV2RGB_FRAME_W::new(self, 26) } #[doc = "Bit 27 - write 1 to clear isp_tail idi frame_end"] #[inline(always)] #[must_use] - pub fn tail_idi_frame_int_clr(&mut self) -> TAIL_IDI_FRAME_INT_CLR_W { - TAIL_IDI_FRAME_INT_CLR_W::new(self, 27) + pub fn tail_idi_frame(&mut self) -> TAIL_IDI_FRAME_W { + TAIL_IDI_FRAME_W::new(self, 27) } #[doc = "Bit 28 - write 1 to clear real input frame end of isp_input"] #[inline(always)] #[must_use] - pub fn header_idi_frame_int_clr(&mut self) -> HEADER_IDI_FRAME_INT_CLR_W { - HEADER_IDI_FRAME_INT_CLR_W::new(self, 28) + pub fn header_idi_frame(&mut self) -> HEADER_IDI_FRAME_W { + HEADER_IDI_FRAME_W::new(self, 28) } } #[doc = "interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -255,7 +249,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC { impl crate::Writable for INT_CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1fff_ffff; } #[doc = "`reset()` method sets INT_CLR to value 0"] impl crate::Resettable for INT_CLR_SPEC { diff --git a/esp32p4/src/isp/int_ena.rs b/esp32p4/src/isp/int_ena.rs index e504c3c791..4720288426 100644 --- a/esp32p4/src/isp/int_ena.rs +++ b/esp32p4/src/isp/int_ena.rs @@ -2,267 +2,267 @@ pub type R = crate::R; #[doc = "Register `INT_ENA` writer"] pub type W = crate::W; -#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ENA` reader - write 1 to enable input data type error"] -pub type ISP_DATA_TYPE_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ENA` writer - write 1 to enable input data type error"] -pub type ISP_DATA_TYPE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ENA` reader - write 1 to enable isp input fifo overflow"] -pub type ISP_ASYNC_FIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ENA` writer - write 1 to enable isp input fifo overflow"] -pub type ISP_ASYNC_FIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_BUF_FULL_INT_ENA` reader - write 1 to enable isp input buffer full"] -pub type ISP_BUF_FULL_INT_ENA_R = crate::BitReader; -#[doc = "Field `ISP_BUF_FULL_INT_ENA` writer - write 1 to enable isp input buffer full"] -pub type ISP_BUF_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ENA` reader - write 1 to enable hnum and vnum setting format error"] -pub type ISP_HVNUM_SETTING_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ENA` writer - write 1 to enable hnum and vnum setting format error"] -pub type ISP_HVNUM_SETTING_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ENA` reader - write 1 to enable setting invalid reg_data_type"] -pub type ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ENA` writer - write 1 to enable setting invalid reg_data_type"] -pub type ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ENA` reader - write 1 to enable hnum setting unmatch with mipi input"] -pub type ISP_MIPI_HNUM_UNMATCH_INT_ENA_R = crate::BitReader; -#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ENA` writer - write 1 to enable hnum setting unmatch with mipi input"] -pub type ISP_MIPI_HNUM_UNMATCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DPC_CHECK_DONE_INT_ENA` reader - write 1 to enable dpc check done"] -pub type DPC_CHECK_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `DPC_CHECK_DONE_INT_ENA` writer - write 1 to enable dpc check done"] -pub type DPC_CHECK_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GAMMA_XCOORD_ERR_INT_ENA` reader - write 1 to enable gamma setting error"] -pub type GAMMA_XCOORD_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `GAMMA_XCOORD_ERR_INT_ENA` writer - write 1 to enable gamma setting error"] -pub type GAMMA_XCOORD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AE_MONITOR_INT_ENA` reader - write 1 to enable ae monitor"] -pub type AE_MONITOR_INT_ENA_R = crate::BitReader; -#[doc = "Field `AE_MONITOR_INT_ENA` writer - write 1 to enable ae monitor"] -pub type AE_MONITOR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AE_FRAME_DONE_INT_ENA` reader - write 1 to enable ae"] -pub type AE_FRAME_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `AE_FRAME_DONE_INT_ENA` writer - write 1 to enable ae"] -pub type AE_FRAME_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AF_FDONE_INT_ENA` reader - write 1 to enable af statistic"] -pub type AF_FDONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `AF_FDONE_INT_ENA` writer - write 1 to enable af statistic"] -pub type AF_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AF_ENV_INT_ENA` reader - write 1 to enable af monitor"] -pub type AF_ENV_INT_ENA_R = crate::BitReader; -#[doc = "Field `AF_ENV_INT_ENA` writer - write 1 to enable af monitor"] -pub type AF_ENV_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AWB_FDONE_INT_ENA` reader - write 1 to enable awb"] -pub type AWB_FDONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `AWB_FDONE_INT_ENA` writer - write 1 to enable awb"] -pub type AWB_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HIST_FDONE_INT_ENA` reader - write 1 to enable histogram"] -pub type HIST_FDONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `HIST_FDONE_INT_ENA` writer - write 1 to enable histogram"] -pub type HIST_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FRAME_INT_ENA` reader - write 1 to enable isp frame end"] -pub type FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `FRAME_INT_ENA` writer - write 1 to enable isp frame end"] -pub type FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BLC_FRAME_INT_ENA` reader - write 1 to enable blc frame done"] -pub type BLC_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `BLC_FRAME_INT_ENA` writer - write 1 to enable blc frame done"] -pub type BLC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LSC_FRAME_INT_ENA` reader - write 1 to enable lsc frame done"] -pub type LSC_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `LSC_FRAME_INT_ENA` writer - write 1 to enable lsc frame done"] -pub type LSC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DPC_FRAME_INT_ENA` reader - write 1 to enable dpc frame done"] -pub type DPC_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `DPC_FRAME_INT_ENA` writer - write 1 to enable dpc frame done"] -pub type DPC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BF_FRAME_INT_ENA` reader - write 1 to enable bf frame done"] -pub type BF_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `BF_FRAME_INT_ENA` writer - write 1 to enable bf frame done"] -pub type BF_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DEMOSAIC_FRAME_INT_ENA` reader - write 1 to enable demosaic frame done"] -pub type DEMOSAIC_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `DEMOSAIC_FRAME_INT_ENA` writer - write 1 to enable demosaic frame done"] -pub type DEMOSAIC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MEDIAN_FRAME_INT_ENA` reader - write 1 to enable median frame done"] -pub type MEDIAN_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `MEDIAN_FRAME_INT_ENA` writer - write 1 to enable median frame done"] -pub type MEDIAN_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CCM_FRAME_INT_ENA` reader - write 1 to enable ccm frame done"] -pub type CCM_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `CCM_FRAME_INT_ENA` writer - write 1 to enable ccm frame done"] -pub type CCM_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GAMMA_FRAME_INT_ENA` reader - write 1 to enable gamma frame done"] -pub type GAMMA_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `GAMMA_FRAME_INT_ENA` writer - write 1 to enable gamma frame done"] -pub type GAMMA_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RGB2YUV_FRAME_INT_ENA` reader - write 1 to enable rgb2yuv frame done"] -pub type RGB2YUV_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `RGB2YUV_FRAME_INT_ENA` writer - write 1 to enable rgb2yuv frame done"] -pub type RGB2YUV_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SHARP_FRAME_INT_ENA` reader - write 1 to enable sharp frame done"] -pub type SHARP_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `SHARP_FRAME_INT_ENA` writer - write 1 to enable sharp frame done"] -pub type SHARP_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `COLOR_FRAME_INT_ENA` reader - write 1 to enable color frame done"] -pub type COLOR_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `COLOR_FRAME_INT_ENA` writer - write 1 to enable color frame done"] -pub type COLOR_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `YUV2RGB_FRAME_INT_ENA` reader - write 1 to enable yuv2rgb frame done"] -pub type YUV2RGB_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `YUV2RGB_FRAME_INT_ENA` writer - write 1 to enable yuv2rgb frame done"] -pub type YUV2RGB_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TAIL_IDI_FRAME_INT_ENA` reader - write 1 to enable isp_tail idi frame_end"] -pub type TAIL_IDI_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `TAIL_IDI_FRAME_INT_ENA` writer - write 1 to enable isp_tail idi frame_end"] -pub type TAIL_IDI_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HEADER_IDI_FRAME_INT_ENA` reader - write 1 to enable real input frame end of isp_input"] -pub type HEADER_IDI_FRAME_INT_ENA_R = crate::BitReader; -#[doc = "Field `HEADER_IDI_FRAME_INT_ENA` writer - write 1 to enable real input frame end of isp_input"] -pub type HEADER_IDI_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_DATA_TYPE_ERR` reader - write 1 to enable input data type error"] +pub type ISP_DATA_TYPE_ERR_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_ERR` writer - write 1 to enable input data type error"] +pub type ISP_DATA_TYPE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_ASYNC_FIFO_OVF` reader - write 1 to enable isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_R = crate::BitReader; +#[doc = "Field `ISP_ASYNC_FIFO_OVF` writer - write 1 to enable isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_BUF_FULL` reader - write 1 to enable isp input buffer full"] +pub type ISP_BUF_FULL_R = crate::BitReader; +#[doc = "Field `ISP_BUF_FULL` writer - write 1 to enable isp input buffer full"] +pub type ISP_BUF_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_HVNUM_SETTING_ERR` reader - write 1 to enable hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_R = crate::BitReader; +#[doc = "Field `ISP_HVNUM_SETTING_ERR` writer - write 1 to enable hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR` reader - write 1 to enable setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR` writer - write 1 to enable setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH` reader - write 1 to enable hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_R = crate::BitReader; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH` writer - write 1 to enable hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_CHECK_DONE` reader - write 1 to enable dpc check done"] +pub type DPC_CHECK_DONE_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_DONE` writer - write 1 to enable dpc check done"] +pub type DPC_CHECK_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_XCOORD_ERR` reader - write 1 to enable gamma setting error"] +pub type GAMMA_XCOORD_ERR_R = crate::BitReader; +#[doc = "Field `GAMMA_XCOORD_ERR` writer - write 1 to enable gamma setting error"] +pub type GAMMA_XCOORD_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_MONITOR` reader - write 1 to enable ae monitor"] +pub type AE_MONITOR_R = crate::BitReader; +#[doc = "Field `AE_MONITOR` writer - write 1 to enable ae monitor"] +pub type AE_MONITOR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_FRAME_DONE` reader - write 1 to enable ae"] +pub type AE_FRAME_DONE_R = crate::BitReader; +#[doc = "Field `AE_FRAME_DONE` writer - write 1 to enable ae"] +pub type AE_FRAME_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_FDONE` reader - write 1 to enable af statistic"] +pub type AF_FDONE_R = crate::BitReader; +#[doc = "Field `AF_FDONE` writer - write 1 to enable af statistic"] +pub type AF_FDONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_ENV` reader - write 1 to enable af monitor"] +pub type AF_ENV_R = crate::BitReader; +#[doc = "Field `AF_ENV` writer - write 1 to enable af monitor"] +pub type AF_ENV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AWB_FDONE` reader - write 1 to enable awb"] +pub type AWB_FDONE_R = crate::BitReader; +#[doc = "Field `AWB_FDONE` writer - write 1 to enable awb"] +pub type AWB_FDONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIST_FDONE` reader - write 1 to enable histogram"] +pub type HIST_FDONE_R = crate::BitReader; +#[doc = "Field `HIST_FDONE` writer - write 1 to enable histogram"] +pub type HIST_FDONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME` reader - write 1 to enable isp frame end"] +pub type FRAME_R = crate::BitReader; +#[doc = "Field `FRAME` writer - write 1 to enable isp frame end"] +pub type FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLC_FRAME` reader - write 1 to enable blc frame done"] +pub type BLC_FRAME_R = crate::BitReader; +#[doc = "Field `BLC_FRAME` writer - write 1 to enable blc frame done"] +pub type BLC_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSC_FRAME` reader - write 1 to enable lsc frame done"] +pub type LSC_FRAME_R = crate::BitReader; +#[doc = "Field `LSC_FRAME` writer - write 1 to enable lsc frame done"] +pub type LSC_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_FRAME` reader - write 1 to enable dpc frame done"] +pub type DPC_FRAME_R = crate::BitReader; +#[doc = "Field `DPC_FRAME` writer - write 1 to enable dpc frame done"] +pub type DPC_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BF_FRAME` reader - write 1 to enable bf frame done"] +pub type BF_FRAME_R = crate::BitReader; +#[doc = "Field `BF_FRAME` writer - write 1 to enable bf frame done"] +pub type BF_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEMOSAIC_FRAME` reader - write 1 to enable demosaic frame done"] +pub type DEMOSAIC_FRAME_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_FRAME` writer - write 1 to enable demosaic frame done"] +pub type DEMOSAIC_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEDIAN_FRAME` reader - write 1 to enable median frame done"] +pub type MEDIAN_FRAME_R = crate::BitReader; +#[doc = "Field `MEDIAN_FRAME` writer - write 1 to enable median frame done"] +pub type MEDIAN_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCM_FRAME` reader - write 1 to enable ccm frame done"] +pub type CCM_FRAME_R = crate::BitReader; +#[doc = "Field `CCM_FRAME` writer - write 1 to enable ccm frame done"] +pub type CCM_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_FRAME` reader - write 1 to enable gamma frame done"] +pub type GAMMA_FRAME_R = crate::BitReader; +#[doc = "Field `GAMMA_FRAME` writer - write 1 to enable gamma frame done"] +pub type GAMMA_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RGB2YUV_FRAME` reader - write 1 to enable rgb2yuv frame done"] +pub type RGB2YUV_FRAME_R = crate::BitReader; +#[doc = "Field `RGB2YUV_FRAME` writer - write 1 to enable rgb2yuv frame done"] +pub type RGB2YUV_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHARP_FRAME` reader - write 1 to enable sharp frame done"] +pub type SHARP_FRAME_R = crate::BitReader; +#[doc = "Field `SHARP_FRAME` writer - write 1 to enable sharp frame done"] +pub type SHARP_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COLOR_FRAME` reader - write 1 to enable color frame done"] +pub type COLOR_FRAME_R = crate::BitReader; +#[doc = "Field `COLOR_FRAME` writer - write 1 to enable color frame done"] +pub type COLOR_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV2RGB_FRAME` reader - write 1 to enable yuv2rgb frame done"] +pub type YUV2RGB_FRAME_R = crate::BitReader; +#[doc = "Field `YUV2RGB_FRAME` writer - write 1 to enable yuv2rgb frame done"] +pub type YUV2RGB_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TAIL_IDI_FRAME` reader - write 1 to enable isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_R = crate::BitReader; +#[doc = "Field `TAIL_IDI_FRAME` writer - write 1 to enable isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HEADER_IDI_FRAME` reader - write 1 to enable real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_R = crate::BitReader; +#[doc = "Field `HEADER_IDI_FRAME` writer - write 1 to enable real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - write 1 to enable input data type error"] #[inline(always)] - pub fn isp_data_type_err_int_ena(&self) -> ISP_DATA_TYPE_ERR_INT_ENA_R { - ISP_DATA_TYPE_ERR_INT_ENA_R::new((self.bits & 1) != 0) + pub fn isp_data_type_err(&self) -> ISP_DATA_TYPE_ERR_R { + ISP_DATA_TYPE_ERR_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - write 1 to enable isp input fifo overflow"] #[inline(always)] - pub fn isp_async_fifo_ovf_int_ena(&self) -> ISP_ASYNC_FIFO_OVF_INT_ENA_R { - ISP_ASYNC_FIFO_OVF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn isp_async_fifo_ovf(&self) -> ISP_ASYNC_FIFO_OVF_R { + ISP_ASYNC_FIFO_OVF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - write 1 to enable isp input buffer full"] #[inline(always)] - pub fn isp_buf_full_int_ena(&self) -> ISP_BUF_FULL_INT_ENA_R { - ISP_BUF_FULL_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn isp_buf_full(&self) -> ISP_BUF_FULL_R { + ISP_BUF_FULL_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - write 1 to enable hnum and vnum setting format error"] #[inline(always)] - pub fn isp_hvnum_setting_err_int_ena(&self) -> ISP_HVNUM_SETTING_ERR_INT_ENA_R { - ISP_HVNUM_SETTING_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn isp_hvnum_setting_err(&self) -> ISP_HVNUM_SETTING_ERR_R { + ISP_HVNUM_SETTING_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - write 1 to enable setting invalid reg_data_type"] #[inline(always)] - pub fn isp_data_type_setting_err_int_ena(&self) -> ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R { - ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn isp_data_type_setting_err(&self) -> ISP_DATA_TYPE_SETTING_ERR_R { + ISP_DATA_TYPE_SETTING_ERR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - write 1 to enable hnum setting unmatch with mipi input"] #[inline(always)] - pub fn isp_mipi_hnum_unmatch_int_ena(&self) -> ISP_MIPI_HNUM_UNMATCH_INT_ENA_R { - ISP_MIPI_HNUM_UNMATCH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn isp_mipi_hnum_unmatch(&self) -> ISP_MIPI_HNUM_UNMATCH_R { + ISP_MIPI_HNUM_UNMATCH_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - write 1 to enable dpc check done"] #[inline(always)] - pub fn dpc_check_done_int_ena(&self) -> DPC_CHECK_DONE_INT_ENA_R { - DPC_CHECK_DONE_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn dpc_check_done(&self) -> DPC_CHECK_DONE_R { + DPC_CHECK_DONE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - write 1 to enable gamma setting error"] #[inline(always)] - pub fn gamma_xcoord_err_int_ena(&self) -> GAMMA_XCOORD_ERR_INT_ENA_R { - GAMMA_XCOORD_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn gamma_xcoord_err(&self) -> GAMMA_XCOORD_ERR_R { + GAMMA_XCOORD_ERR_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - write 1 to enable ae monitor"] #[inline(always)] - pub fn ae_monitor_int_ena(&self) -> AE_MONITOR_INT_ENA_R { - AE_MONITOR_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn ae_monitor(&self) -> AE_MONITOR_R { + AE_MONITOR_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - write 1 to enable ae"] #[inline(always)] - pub fn ae_frame_done_int_ena(&self) -> AE_FRAME_DONE_INT_ENA_R { - AE_FRAME_DONE_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn ae_frame_done(&self) -> AE_FRAME_DONE_R { + AE_FRAME_DONE_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - write 1 to enable af statistic"] #[inline(always)] - pub fn af_fdone_int_ena(&self) -> AF_FDONE_INT_ENA_R { - AF_FDONE_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn af_fdone(&self) -> AF_FDONE_R { + AF_FDONE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - write 1 to enable af monitor"] #[inline(always)] - pub fn af_env_int_ena(&self) -> AF_ENV_INT_ENA_R { - AF_ENV_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn af_env(&self) -> AF_ENV_R { + AF_ENV_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - write 1 to enable awb"] #[inline(always)] - pub fn awb_fdone_int_ena(&self) -> AWB_FDONE_INT_ENA_R { - AWB_FDONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn awb_fdone(&self) -> AWB_FDONE_R { + AWB_FDONE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - write 1 to enable histogram"] #[inline(always)] - pub fn hist_fdone_int_ena(&self) -> HIST_FDONE_INT_ENA_R { - HIST_FDONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + pub fn hist_fdone(&self) -> HIST_FDONE_R { + HIST_FDONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - write 1 to enable isp frame end"] #[inline(always)] - pub fn frame_int_ena(&self) -> FRAME_INT_ENA_R { - FRAME_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + pub fn frame(&self) -> FRAME_R { + FRAME_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - write 1 to enable blc frame done"] #[inline(always)] - pub fn blc_frame_int_ena(&self) -> BLC_FRAME_INT_ENA_R { - BLC_FRAME_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + pub fn blc_frame(&self) -> BLC_FRAME_R { + BLC_FRAME_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - write 1 to enable lsc frame done"] #[inline(always)] - pub fn lsc_frame_int_ena(&self) -> LSC_FRAME_INT_ENA_R { - LSC_FRAME_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + pub fn lsc_frame(&self) -> LSC_FRAME_R { + LSC_FRAME_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - write 1 to enable dpc frame done"] #[inline(always)] - pub fn dpc_frame_int_ena(&self) -> DPC_FRAME_INT_ENA_R { - DPC_FRAME_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + pub fn dpc_frame(&self) -> DPC_FRAME_R { + DPC_FRAME_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - write 1 to enable bf frame done"] #[inline(always)] - pub fn bf_frame_int_ena(&self) -> BF_FRAME_INT_ENA_R { - BF_FRAME_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + pub fn bf_frame(&self) -> BF_FRAME_R { + BF_FRAME_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - write 1 to enable demosaic frame done"] #[inline(always)] - pub fn demosaic_frame_int_ena(&self) -> DEMOSAIC_FRAME_INT_ENA_R { - DEMOSAIC_FRAME_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + pub fn demosaic_frame(&self) -> DEMOSAIC_FRAME_R { + DEMOSAIC_FRAME_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 20 - write 1 to enable median frame done"] #[inline(always)] - pub fn median_frame_int_ena(&self) -> MEDIAN_FRAME_INT_ENA_R { - MEDIAN_FRAME_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + pub fn median_frame(&self) -> MEDIAN_FRAME_R { + MEDIAN_FRAME_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - write 1 to enable ccm frame done"] #[inline(always)] - pub fn ccm_frame_int_ena(&self) -> CCM_FRAME_INT_ENA_R { - CCM_FRAME_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + pub fn ccm_frame(&self) -> CCM_FRAME_R { + CCM_FRAME_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - write 1 to enable gamma frame done"] #[inline(always)] - pub fn gamma_frame_int_ena(&self) -> GAMMA_FRAME_INT_ENA_R { - GAMMA_FRAME_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + pub fn gamma_frame(&self) -> GAMMA_FRAME_R { + GAMMA_FRAME_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - write 1 to enable rgb2yuv frame done"] #[inline(always)] - pub fn rgb2yuv_frame_int_ena(&self) -> RGB2YUV_FRAME_INT_ENA_R { - RGB2YUV_FRAME_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + pub fn rgb2yuv_frame(&self) -> RGB2YUV_FRAME_R { + RGB2YUV_FRAME_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - write 1 to enable sharp frame done"] #[inline(always)] - pub fn sharp_frame_int_ena(&self) -> SHARP_FRAME_INT_ENA_R { - SHARP_FRAME_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + pub fn sharp_frame(&self) -> SHARP_FRAME_R { + SHARP_FRAME_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - write 1 to enable color frame done"] #[inline(always)] - pub fn color_frame_int_ena(&self) -> COLOR_FRAME_INT_ENA_R { - COLOR_FRAME_INT_ENA_R::new(((self.bits >> 25) & 1) != 0) + pub fn color_frame(&self) -> COLOR_FRAME_R { + COLOR_FRAME_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - write 1 to enable yuv2rgb frame done"] #[inline(always)] - pub fn yuv2rgb_frame_int_ena(&self) -> YUV2RGB_FRAME_INT_ENA_R { - YUV2RGB_FRAME_INT_ENA_R::new(((self.bits >> 26) & 1) != 0) + pub fn yuv2rgb_frame(&self) -> YUV2RGB_FRAME_R { + YUV2RGB_FRAME_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - write 1 to enable isp_tail idi frame_end"] #[inline(always)] - pub fn tail_idi_frame_int_ena(&self) -> TAIL_IDI_FRAME_INT_ENA_R { - TAIL_IDI_FRAME_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + pub fn tail_idi_frame(&self) -> TAIL_IDI_FRAME_R { + TAIL_IDI_FRAME_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - write 1 to enable real input frame end of isp_input"] #[inline(always)] - pub fn header_idi_frame_int_ena(&self) -> HEADER_IDI_FRAME_INT_ENA_R { - HEADER_IDI_FRAME_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + pub fn header_idi_frame(&self) -> HEADER_IDI_FRAME_R { + HEADER_IDI_FRAME_R::new(((self.bits >> 28) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -270,120 +270,78 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ENA") .field( - "isp_data_type_err_int_ena", - &format_args!("{}", self.isp_data_type_err_int_ena().bit()), + "isp_data_type_err", + &format_args!("{}", self.isp_data_type_err().bit()), ) .field( - "isp_async_fifo_ovf_int_ena", - &format_args!("{}", self.isp_async_fifo_ovf_int_ena().bit()), + "isp_async_fifo_ovf", + &format_args!("{}", self.isp_async_fifo_ovf().bit()), ) .field( - "isp_buf_full_int_ena", - &format_args!("{}", self.isp_buf_full_int_ena().bit()), + "isp_buf_full", + &format_args!("{}", self.isp_buf_full().bit()), ) .field( - "isp_hvnum_setting_err_int_ena", - &format_args!("{}", self.isp_hvnum_setting_err_int_ena().bit()), + "isp_hvnum_setting_err", + &format_args!("{}", self.isp_hvnum_setting_err().bit()), ) .field( - "isp_data_type_setting_err_int_ena", - &format_args!("{}", self.isp_data_type_setting_err_int_ena().bit()), + "isp_data_type_setting_err", + &format_args!("{}", self.isp_data_type_setting_err().bit()), ) .field( - "isp_mipi_hnum_unmatch_int_ena", - &format_args!("{}", self.isp_mipi_hnum_unmatch_int_ena().bit()), + "isp_mipi_hnum_unmatch", + &format_args!("{}", self.isp_mipi_hnum_unmatch().bit()), ) .field( - "dpc_check_done_int_ena", - &format_args!("{}", self.dpc_check_done_int_ena().bit()), + "dpc_check_done", + &format_args!("{}", self.dpc_check_done().bit()), ) .field( - "gamma_xcoord_err_int_ena", - &format_args!("{}", self.gamma_xcoord_err_int_ena().bit()), + "gamma_xcoord_err", + &format_args!("{}", self.gamma_xcoord_err().bit()), ) + .field("ae_monitor", &format_args!("{}", self.ae_monitor().bit())) .field( - "ae_monitor_int_ena", - &format_args!("{}", self.ae_monitor_int_ena().bit()), + "ae_frame_done", + &format_args!("{}", self.ae_frame_done().bit()), ) + .field("af_fdone", &format_args!("{}", self.af_fdone().bit())) + .field("af_env", &format_args!("{}", self.af_env().bit())) + .field("awb_fdone", &format_args!("{}", self.awb_fdone().bit())) + .field("hist_fdone", &format_args!("{}", self.hist_fdone().bit())) + .field("frame", &format_args!("{}", self.frame().bit())) + .field("blc_frame", &format_args!("{}", self.blc_frame().bit())) + .field("lsc_frame", &format_args!("{}", self.lsc_frame().bit())) + .field("dpc_frame", &format_args!("{}", self.dpc_frame().bit())) + .field("bf_frame", &format_args!("{}", self.bf_frame().bit())) .field( - "ae_frame_done_int_ena", - &format_args!("{}", self.ae_frame_done_int_ena().bit()), + "demosaic_frame", + &format_args!("{}", self.demosaic_frame().bit()), ) .field( - "af_fdone_int_ena", - &format_args!("{}", self.af_fdone_int_ena().bit()), + "median_frame", + &format_args!("{}", self.median_frame().bit()), ) + .field("ccm_frame", &format_args!("{}", self.ccm_frame().bit())) + .field("gamma_frame", &format_args!("{}", self.gamma_frame().bit())) .field( - "af_env_int_ena", - &format_args!("{}", self.af_env_int_ena().bit()), + "rgb2yuv_frame", + &format_args!("{}", self.rgb2yuv_frame().bit()), ) + .field("sharp_frame", &format_args!("{}", self.sharp_frame().bit())) + .field("color_frame", &format_args!("{}", self.color_frame().bit())) .field( - "awb_fdone_int_ena", - &format_args!("{}", self.awb_fdone_int_ena().bit()), + "yuv2rgb_frame", + &format_args!("{}", self.yuv2rgb_frame().bit()), ) .field( - "hist_fdone_int_ena", - &format_args!("{}", self.hist_fdone_int_ena().bit()), + "tail_idi_frame", + &format_args!("{}", self.tail_idi_frame().bit()), ) .field( - "frame_int_ena", - &format_args!("{}", self.frame_int_ena().bit()), - ) - .field( - "blc_frame_int_ena", - &format_args!("{}", self.blc_frame_int_ena().bit()), - ) - .field( - "lsc_frame_int_ena", - &format_args!("{}", self.lsc_frame_int_ena().bit()), - ) - .field( - "dpc_frame_int_ena", - &format_args!("{}", self.dpc_frame_int_ena().bit()), - ) - .field( - "bf_frame_int_ena", - &format_args!("{}", self.bf_frame_int_ena().bit()), - ) - .field( - "demosaic_frame_int_ena", - &format_args!("{}", self.demosaic_frame_int_ena().bit()), - ) - .field( - "median_frame_int_ena", - &format_args!("{}", self.median_frame_int_ena().bit()), - ) - .field( - "ccm_frame_int_ena", - &format_args!("{}", self.ccm_frame_int_ena().bit()), - ) - .field( - "gamma_frame_int_ena", - &format_args!("{}", self.gamma_frame_int_ena().bit()), - ) - .field( - "rgb2yuv_frame_int_ena", - &format_args!("{}", self.rgb2yuv_frame_int_ena().bit()), - ) - .field( - "sharp_frame_int_ena", - &format_args!("{}", self.sharp_frame_int_ena().bit()), - ) - .field( - "color_frame_int_ena", - &format_args!("{}", self.color_frame_int_ena().bit()), - ) - .field( - "yuv2rgb_frame_int_ena", - &format_args!("{}", self.yuv2rgb_frame_int_ena().bit()), - ) - .field( - "tail_idi_frame_int_ena", - &format_args!("{}", self.tail_idi_frame_int_ena().bit()), - ) - .field( - "header_idi_frame_int_ena", - &format_args!("{}", self.header_idi_frame_int_ena().bit()), + "header_idi_frame", + &format_args!("{}", self.header_idi_frame().bit()), ) .finish() } @@ -398,182 +356,176 @@ impl W { #[doc = "Bit 0 - write 1 to enable input data type error"] #[inline(always)] #[must_use] - pub fn isp_data_type_err_int_ena(&mut self) -> ISP_DATA_TYPE_ERR_INT_ENA_W { - ISP_DATA_TYPE_ERR_INT_ENA_W::new(self, 0) + pub fn isp_data_type_err(&mut self) -> ISP_DATA_TYPE_ERR_W { + ISP_DATA_TYPE_ERR_W::new(self, 0) } #[doc = "Bit 1 - write 1 to enable isp input fifo overflow"] #[inline(always)] #[must_use] - pub fn isp_async_fifo_ovf_int_ena(&mut self) -> ISP_ASYNC_FIFO_OVF_INT_ENA_W { - ISP_ASYNC_FIFO_OVF_INT_ENA_W::new(self, 1) + pub fn isp_async_fifo_ovf(&mut self) -> ISP_ASYNC_FIFO_OVF_W { + ISP_ASYNC_FIFO_OVF_W::new(self, 1) } #[doc = "Bit 2 - write 1 to enable isp input buffer full"] #[inline(always)] #[must_use] - pub fn isp_buf_full_int_ena(&mut self) -> ISP_BUF_FULL_INT_ENA_W { - ISP_BUF_FULL_INT_ENA_W::new(self, 2) + pub fn isp_buf_full(&mut self) -> ISP_BUF_FULL_W { + ISP_BUF_FULL_W::new(self, 2) } #[doc = "Bit 3 - write 1 to enable hnum and vnum setting format error"] #[inline(always)] #[must_use] - pub fn isp_hvnum_setting_err_int_ena( - &mut self, - ) -> ISP_HVNUM_SETTING_ERR_INT_ENA_W { - ISP_HVNUM_SETTING_ERR_INT_ENA_W::new(self, 3) + pub fn isp_hvnum_setting_err(&mut self) -> ISP_HVNUM_SETTING_ERR_W { + ISP_HVNUM_SETTING_ERR_W::new(self, 3) } #[doc = "Bit 4 - write 1 to enable setting invalid reg_data_type"] #[inline(always)] #[must_use] - pub fn isp_data_type_setting_err_int_ena( - &mut self, - ) -> ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W { - ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W::new(self, 4) + pub fn isp_data_type_setting_err(&mut self) -> ISP_DATA_TYPE_SETTING_ERR_W { + ISP_DATA_TYPE_SETTING_ERR_W::new(self, 4) } #[doc = "Bit 5 - write 1 to enable hnum setting unmatch with mipi input"] #[inline(always)] #[must_use] - pub fn isp_mipi_hnum_unmatch_int_ena( - &mut self, - ) -> ISP_MIPI_HNUM_UNMATCH_INT_ENA_W { - ISP_MIPI_HNUM_UNMATCH_INT_ENA_W::new(self, 5) + pub fn isp_mipi_hnum_unmatch(&mut self) -> ISP_MIPI_HNUM_UNMATCH_W { + ISP_MIPI_HNUM_UNMATCH_W::new(self, 5) } #[doc = "Bit 6 - write 1 to enable dpc check done"] #[inline(always)] #[must_use] - pub fn dpc_check_done_int_ena(&mut self) -> DPC_CHECK_DONE_INT_ENA_W { - DPC_CHECK_DONE_INT_ENA_W::new(self, 6) + pub fn dpc_check_done(&mut self) -> DPC_CHECK_DONE_W { + DPC_CHECK_DONE_W::new(self, 6) } #[doc = "Bit 7 - write 1 to enable gamma setting error"] #[inline(always)] #[must_use] - pub fn gamma_xcoord_err_int_ena(&mut self) -> GAMMA_XCOORD_ERR_INT_ENA_W { - GAMMA_XCOORD_ERR_INT_ENA_W::new(self, 7) + pub fn gamma_xcoord_err(&mut self) -> GAMMA_XCOORD_ERR_W { + GAMMA_XCOORD_ERR_W::new(self, 7) } #[doc = "Bit 8 - write 1 to enable ae monitor"] #[inline(always)] #[must_use] - pub fn ae_monitor_int_ena(&mut self) -> AE_MONITOR_INT_ENA_W { - AE_MONITOR_INT_ENA_W::new(self, 8) + pub fn ae_monitor(&mut self) -> AE_MONITOR_W { + AE_MONITOR_W::new(self, 8) } #[doc = "Bit 9 - write 1 to enable ae"] #[inline(always)] #[must_use] - pub fn ae_frame_done_int_ena(&mut self) -> AE_FRAME_DONE_INT_ENA_W { - AE_FRAME_DONE_INT_ENA_W::new(self, 9) + pub fn ae_frame_done(&mut self) -> AE_FRAME_DONE_W { + AE_FRAME_DONE_W::new(self, 9) } #[doc = "Bit 10 - write 1 to enable af statistic"] #[inline(always)] #[must_use] - pub fn af_fdone_int_ena(&mut self) -> AF_FDONE_INT_ENA_W { - AF_FDONE_INT_ENA_W::new(self, 10) + pub fn af_fdone(&mut self) -> AF_FDONE_W { + AF_FDONE_W::new(self, 10) } #[doc = "Bit 11 - write 1 to enable af monitor"] #[inline(always)] #[must_use] - pub fn af_env_int_ena(&mut self) -> AF_ENV_INT_ENA_W { - AF_ENV_INT_ENA_W::new(self, 11) + pub fn af_env(&mut self) -> AF_ENV_W { + AF_ENV_W::new(self, 11) } #[doc = "Bit 12 - write 1 to enable awb"] #[inline(always)] #[must_use] - pub fn awb_fdone_int_ena(&mut self) -> AWB_FDONE_INT_ENA_W { - AWB_FDONE_INT_ENA_W::new(self, 12) + pub fn awb_fdone(&mut self) -> AWB_FDONE_W { + AWB_FDONE_W::new(self, 12) } #[doc = "Bit 13 - write 1 to enable histogram"] #[inline(always)] #[must_use] - pub fn hist_fdone_int_ena(&mut self) -> HIST_FDONE_INT_ENA_W { - HIST_FDONE_INT_ENA_W::new(self, 13) + pub fn hist_fdone(&mut self) -> HIST_FDONE_W { + HIST_FDONE_W::new(self, 13) } #[doc = "Bit 14 - write 1 to enable isp frame end"] #[inline(always)] #[must_use] - pub fn frame_int_ena(&mut self) -> FRAME_INT_ENA_W { - FRAME_INT_ENA_W::new(self, 14) + pub fn frame(&mut self) -> FRAME_W { + FRAME_W::new(self, 14) } #[doc = "Bit 15 - write 1 to enable blc frame done"] #[inline(always)] #[must_use] - pub fn blc_frame_int_ena(&mut self) -> BLC_FRAME_INT_ENA_W { - BLC_FRAME_INT_ENA_W::new(self, 15) + pub fn blc_frame(&mut self) -> BLC_FRAME_W { + BLC_FRAME_W::new(self, 15) } #[doc = "Bit 16 - write 1 to enable lsc frame done"] #[inline(always)] #[must_use] - pub fn lsc_frame_int_ena(&mut self) -> LSC_FRAME_INT_ENA_W { - LSC_FRAME_INT_ENA_W::new(self, 16) + pub fn lsc_frame(&mut self) -> LSC_FRAME_W { + LSC_FRAME_W::new(self, 16) } #[doc = "Bit 17 - write 1 to enable dpc frame done"] #[inline(always)] #[must_use] - pub fn dpc_frame_int_ena(&mut self) -> DPC_FRAME_INT_ENA_W { - DPC_FRAME_INT_ENA_W::new(self, 17) + pub fn dpc_frame(&mut self) -> DPC_FRAME_W { + DPC_FRAME_W::new(self, 17) } #[doc = "Bit 18 - write 1 to enable bf frame done"] #[inline(always)] #[must_use] - pub fn bf_frame_int_ena(&mut self) -> BF_FRAME_INT_ENA_W { - BF_FRAME_INT_ENA_W::new(self, 18) + pub fn bf_frame(&mut self) -> BF_FRAME_W { + BF_FRAME_W::new(self, 18) } #[doc = "Bit 19 - write 1 to enable demosaic frame done"] #[inline(always)] #[must_use] - pub fn demosaic_frame_int_ena(&mut self) -> DEMOSAIC_FRAME_INT_ENA_W { - DEMOSAIC_FRAME_INT_ENA_W::new(self, 19) + pub fn demosaic_frame(&mut self) -> DEMOSAIC_FRAME_W { + DEMOSAIC_FRAME_W::new(self, 19) } #[doc = "Bit 20 - write 1 to enable median frame done"] #[inline(always)] #[must_use] - pub fn median_frame_int_ena(&mut self) -> MEDIAN_FRAME_INT_ENA_W { - MEDIAN_FRAME_INT_ENA_W::new(self, 20) + pub fn median_frame(&mut self) -> MEDIAN_FRAME_W { + MEDIAN_FRAME_W::new(self, 20) } #[doc = "Bit 21 - write 1 to enable ccm frame done"] #[inline(always)] #[must_use] - pub fn ccm_frame_int_ena(&mut self) -> CCM_FRAME_INT_ENA_W { - CCM_FRAME_INT_ENA_W::new(self, 21) + pub fn ccm_frame(&mut self) -> CCM_FRAME_W { + CCM_FRAME_W::new(self, 21) } #[doc = "Bit 22 - write 1 to enable gamma frame done"] #[inline(always)] #[must_use] - pub fn gamma_frame_int_ena(&mut self) -> GAMMA_FRAME_INT_ENA_W { - GAMMA_FRAME_INT_ENA_W::new(self, 22) + pub fn gamma_frame(&mut self) -> GAMMA_FRAME_W { + GAMMA_FRAME_W::new(self, 22) } #[doc = "Bit 23 - write 1 to enable rgb2yuv frame done"] #[inline(always)] #[must_use] - pub fn rgb2yuv_frame_int_ena(&mut self) -> RGB2YUV_FRAME_INT_ENA_W { - RGB2YUV_FRAME_INT_ENA_W::new(self, 23) + pub fn rgb2yuv_frame(&mut self) -> RGB2YUV_FRAME_W { + RGB2YUV_FRAME_W::new(self, 23) } #[doc = "Bit 24 - write 1 to enable sharp frame done"] #[inline(always)] #[must_use] - pub fn sharp_frame_int_ena(&mut self) -> SHARP_FRAME_INT_ENA_W { - SHARP_FRAME_INT_ENA_W::new(self, 24) + pub fn sharp_frame(&mut self) -> SHARP_FRAME_W { + SHARP_FRAME_W::new(self, 24) } #[doc = "Bit 25 - write 1 to enable color frame done"] #[inline(always)] #[must_use] - pub fn color_frame_int_ena(&mut self) -> COLOR_FRAME_INT_ENA_W { - COLOR_FRAME_INT_ENA_W::new(self, 25) + pub fn color_frame(&mut self) -> COLOR_FRAME_W { + COLOR_FRAME_W::new(self, 25) } #[doc = "Bit 26 - write 1 to enable yuv2rgb frame done"] #[inline(always)] #[must_use] - pub fn yuv2rgb_frame_int_ena(&mut self) -> YUV2RGB_FRAME_INT_ENA_W { - YUV2RGB_FRAME_INT_ENA_W::new(self, 26) + pub fn yuv2rgb_frame(&mut self) -> YUV2RGB_FRAME_W { + YUV2RGB_FRAME_W::new(self, 26) } #[doc = "Bit 27 - write 1 to enable isp_tail idi frame_end"] #[inline(always)] #[must_use] - pub fn tail_idi_frame_int_ena(&mut self) -> TAIL_IDI_FRAME_INT_ENA_W { - TAIL_IDI_FRAME_INT_ENA_W::new(self, 27) + pub fn tail_idi_frame(&mut self) -> TAIL_IDI_FRAME_W { + TAIL_IDI_FRAME_W::new(self, 27) } #[doc = "Bit 28 - write 1 to enable real input frame end of isp_input"] #[inline(always)] #[must_use] - pub fn header_idi_frame_int_ena(&mut self) -> HEADER_IDI_FRAME_INT_ENA_W { - HEADER_IDI_FRAME_INT_ENA_W::new(self, 28) + pub fn header_idi_frame(&mut self) -> HEADER_IDI_FRAME_W { + HEADER_IDI_FRAME_W::new(self, 28) } } #[doc = "interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/isp/int_raw.rs b/esp32p4/src/isp/int_raw.rs index 86ac55f732..15a6720475 100644 --- a/esp32p4/src/isp/int_raw.rs +++ b/esp32p4/src/isp/int_raw.rs @@ -1,208 +1,208 @@ #[doc = "Register `INT_RAW` reader"] pub type R = crate::R; -#[doc = "Field `ISP_DATA_TYPE_ERR_INT_RAW` reader - the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int"] -pub type ISP_DATA_TYPE_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_RAW` reader - the raw interrupt status of isp input fifo overflow"] -pub type ISP_ASYNC_FIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `ISP_BUF_FULL_INT_RAW` reader - the raw interrupt status of isp input buffer full"] -pub type ISP_BUF_FULL_INT_RAW_R = crate::BitReader; -#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_RAW` reader - the raw interrupt status of hnum and vnum setting format error"] -pub type ISP_HVNUM_SETTING_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_RAW` reader - the raw interrupt status of setting invalid reg_data_type"] -pub type ISP_DATA_TYPE_SETTING_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_RAW` reader - the raw interrupt status of hnum setting unmatch with mipi input"] -pub type ISP_MIPI_HNUM_UNMATCH_INT_RAW_R = crate::BitReader; -#[doc = "Field `DPC_CHECK_DONE_INT_RAW` reader - the raw interrupt status of dpc check done"] -pub type DPC_CHECK_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `GAMMA_XCOORD_ERR_INT_RAW` reader - the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256"] -pub type GAMMA_XCOORD_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `AE_MONITOR_INT_RAW` reader - the raw interrupt status of ae monitor"] -pub type AE_MONITOR_INT_RAW_R = crate::BitReader; -#[doc = "Field `AE_FRAME_DONE_INT_RAW` reader - the raw interrupt status of ae."] -pub type AE_FRAME_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `AF_FDONE_INT_RAW` reader - the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done"] -pub type AF_FDONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `AF_ENV_INT_RAW` reader - the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected"] -pub type AF_ENV_INT_RAW_R = crate::BitReader; -#[doc = "Field `AWB_FDONE_INT_RAW` reader - the raw interrupt status of awb. send a int pulse when statistic of one awb frame done"] -pub type AWB_FDONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `HIST_FDONE_INT_RAW` reader - the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done"] -pub type HIST_FDONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `FRAME_INT_RAW` reader - the raw interrupt status of isp frame end"] -pub type FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `BLC_FRAME_INT_RAW` reader - the raw interrupt status of blc frame done"] -pub type BLC_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `LSC_FRAME_INT_RAW` reader - the raw interrupt status of lsc frame done"] -pub type LSC_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `DPC_FRAME_INT_RAW` reader - the raw interrupt status of dpc frame done"] -pub type DPC_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `BF_FRAME_INT_RAW` reader - the raw interrupt status of bf frame done"] -pub type BF_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `DEMOSAIC_FRAME_INT_RAW` reader - the raw interrupt status of demosaic frame done"] -pub type DEMOSAIC_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `MEDIAN_FRAME_INT_RAW` reader - the raw interrupt status of median frame done"] -pub type MEDIAN_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `CCM_FRAME_INT_RAW` reader - the raw interrupt status of ccm frame done"] -pub type CCM_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `GAMMA_FRAME_INT_RAW` reader - the raw interrupt status of gamma frame done"] -pub type GAMMA_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `RGB2YUV_FRAME_INT_RAW` reader - the raw interrupt status of rgb2yuv frame done"] -pub type RGB2YUV_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `SHARP_FRAME_INT_RAW` reader - the raw interrupt status of sharp frame done"] -pub type SHARP_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `COLOR_FRAME_INT_RAW` reader - the raw interrupt status of color frame done"] -pub type COLOR_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `YUV2RGB_FRAME_INT_RAW` reader - the raw interrupt status of yuv2rgb frame done"] -pub type YUV2RGB_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `TAIL_IDI_FRAME_INT_RAW` reader - the raw interrupt status of isp_tail idi frame_end"] -pub type TAIL_IDI_FRAME_INT_RAW_R = crate::BitReader; -#[doc = "Field `HEADER_IDI_FRAME_INT_RAW` reader - the raw interrupt status of real input frame end of isp_input"] -pub type HEADER_IDI_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_ERR` reader - the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int"] +pub type ISP_DATA_TYPE_ERR_R = crate::BitReader; +#[doc = "Field `ISP_ASYNC_FIFO_OVF` reader - the raw interrupt status of isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_R = crate::BitReader; +#[doc = "Field `ISP_BUF_FULL` reader - the raw interrupt status of isp input buffer full"] +pub type ISP_BUF_FULL_R = crate::BitReader; +#[doc = "Field `ISP_HVNUM_SETTING_ERR` reader - the raw interrupt status of hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR` reader - the raw interrupt status of setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_R = crate::BitReader; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH` reader - the raw interrupt status of hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_DONE` reader - the raw interrupt status of dpc check done"] +pub type DPC_CHECK_DONE_R = crate::BitReader; +#[doc = "Field `GAMMA_XCOORD_ERR` reader - the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256"] +pub type GAMMA_XCOORD_ERR_R = crate::BitReader; +#[doc = "Field `AE_MONITOR` reader - the raw interrupt status of ae monitor"] +pub type AE_MONITOR_R = crate::BitReader; +#[doc = "Field `AE_FRAME_DONE` reader - the raw interrupt status of ae."] +pub type AE_FRAME_DONE_R = crate::BitReader; +#[doc = "Field `AF_FDONE` reader - the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done"] +pub type AF_FDONE_R = crate::BitReader; +#[doc = "Field `AF_ENV` reader - the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected"] +pub type AF_ENV_R = crate::BitReader; +#[doc = "Field `AWB_FDONE` reader - the raw interrupt status of awb. send a int pulse when statistic of one awb frame done"] +pub type AWB_FDONE_R = crate::BitReader; +#[doc = "Field `HIST_FDONE` reader - the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done"] +pub type HIST_FDONE_R = crate::BitReader; +#[doc = "Field `FRAME` reader - the raw interrupt status of isp frame end"] +pub type FRAME_R = crate::BitReader; +#[doc = "Field `BLC_FRAME` reader - the raw interrupt status of blc frame done"] +pub type BLC_FRAME_R = crate::BitReader; +#[doc = "Field `LSC_FRAME` reader - the raw interrupt status of lsc frame done"] +pub type LSC_FRAME_R = crate::BitReader; +#[doc = "Field `DPC_FRAME` reader - the raw interrupt status of dpc frame done"] +pub type DPC_FRAME_R = crate::BitReader; +#[doc = "Field `BF_FRAME` reader - the raw interrupt status of bf frame done"] +pub type BF_FRAME_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_FRAME` reader - the raw interrupt status of demosaic frame done"] +pub type DEMOSAIC_FRAME_R = crate::BitReader; +#[doc = "Field `MEDIAN_FRAME` reader - the raw interrupt status of median frame done"] +pub type MEDIAN_FRAME_R = crate::BitReader; +#[doc = "Field `CCM_FRAME` reader - the raw interrupt status of ccm frame done"] +pub type CCM_FRAME_R = crate::BitReader; +#[doc = "Field `GAMMA_FRAME` reader - the raw interrupt status of gamma frame done"] +pub type GAMMA_FRAME_R = crate::BitReader; +#[doc = "Field `RGB2YUV_FRAME` reader - the raw interrupt status of rgb2yuv frame done"] +pub type RGB2YUV_FRAME_R = crate::BitReader; +#[doc = "Field `SHARP_FRAME` reader - the raw interrupt status of sharp frame done"] +pub type SHARP_FRAME_R = crate::BitReader; +#[doc = "Field `COLOR_FRAME` reader - the raw interrupt status of color frame done"] +pub type COLOR_FRAME_R = crate::BitReader; +#[doc = "Field `YUV2RGB_FRAME` reader - the raw interrupt status of yuv2rgb frame done"] +pub type YUV2RGB_FRAME_R = crate::BitReader; +#[doc = "Field `TAIL_IDI_FRAME` reader - the raw interrupt status of isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_R = crate::BitReader; +#[doc = "Field `HEADER_IDI_FRAME` reader - the raw interrupt status of real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_R = crate::BitReader; impl R { #[doc = "Bit 0 - the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int"] #[inline(always)] - pub fn isp_data_type_err_int_raw(&self) -> ISP_DATA_TYPE_ERR_INT_RAW_R { - ISP_DATA_TYPE_ERR_INT_RAW_R::new((self.bits & 1) != 0) + pub fn isp_data_type_err(&self) -> ISP_DATA_TYPE_ERR_R { + ISP_DATA_TYPE_ERR_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - the raw interrupt status of isp input fifo overflow"] #[inline(always)] - pub fn isp_async_fifo_ovf_int_raw(&self) -> ISP_ASYNC_FIFO_OVF_INT_RAW_R { - ISP_ASYNC_FIFO_OVF_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn isp_async_fifo_ovf(&self) -> ISP_ASYNC_FIFO_OVF_R { + ISP_ASYNC_FIFO_OVF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - the raw interrupt status of isp input buffer full"] #[inline(always)] - pub fn isp_buf_full_int_raw(&self) -> ISP_BUF_FULL_INT_RAW_R { - ISP_BUF_FULL_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn isp_buf_full(&self) -> ISP_BUF_FULL_R { + ISP_BUF_FULL_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - the raw interrupt status of hnum and vnum setting format error"] #[inline(always)] - pub fn isp_hvnum_setting_err_int_raw(&self) -> ISP_HVNUM_SETTING_ERR_INT_RAW_R { - ISP_HVNUM_SETTING_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn isp_hvnum_setting_err(&self) -> ISP_HVNUM_SETTING_ERR_R { + ISP_HVNUM_SETTING_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - the raw interrupt status of setting invalid reg_data_type"] #[inline(always)] - pub fn isp_data_type_setting_err_int_raw(&self) -> ISP_DATA_TYPE_SETTING_ERR_INT_RAW_R { - ISP_DATA_TYPE_SETTING_ERR_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn isp_data_type_setting_err(&self) -> ISP_DATA_TYPE_SETTING_ERR_R { + ISP_DATA_TYPE_SETTING_ERR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - the raw interrupt status of hnum setting unmatch with mipi input"] #[inline(always)] - pub fn isp_mipi_hnum_unmatch_int_raw(&self) -> ISP_MIPI_HNUM_UNMATCH_INT_RAW_R { - ISP_MIPI_HNUM_UNMATCH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn isp_mipi_hnum_unmatch(&self) -> ISP_MIPI_HNUM_UNMATCH_R { + ISP_MIPI_HNUM_UNMATCH_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - the raw interrupt status of dpc check done"] #[inline(always)] - pub fn dpc_check_done_int_raw(&self) -> DPC_CHECK_DONE_INT_RAW_R { - DPC_CHECK_DONE_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn dpc_check_done(&self) -> DPC_CHECK_DONE_R { + DPC_CHECK_DONE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256"] #[inline(always)] - pub fn gamma_xcoord_err_int_raw(&self) -> GAMMA_XCOORD_ERR_INT_RAW_R { - GAMMA_XCOORD_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn gamma_xcoord_err(&self) -> GAMMA_XCOORD_ERR_R { + GAMMA_XCOORD_ERR_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - the raw interrupt status of ae monitor"] #[inline(always)] - pub fn ae_monitor_int_raw(&self) -> AE_MONITOR_INT_RAW_R { - AE_MONITOR_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn ae_monitor(&self) -> AE_MONITOR_R { + AE_MONITOR_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - the raw interrupt status of ae."] #[inline(always)] - pub fn ae_frame_done_int_raw(&self) -> AE_FRAME_DONE_INT_RAW_R { - AE_FRAME_DONE_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn ae_frame_done(&self) -> AE_FRAME_DONE_R { + AE_FRAME_DONE_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done"] #[inline(always)] - pub fn af_fdone_int_raw(&self) -> AF_FDONE_INT_RAW_R { - AF_FDONE_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn af_fdone(&self) -> AF_FDONE_R { + AF_FDONE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected"] #[inline(always)] - pub fn af_env_int_raw(&self) -> AF_ENV_INT_RAW_R { - AF_ENV_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn af_env(&self) -> AF_ENV_R { + AF_ENV_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - the raw interrupt status of awb. send a int pulse when statistic of one awb frame done"] #[inline(always)] - pub fn awb_fdone_int_raw(&self) -> AWB_FDONE_INT_RAW_R { - AWB_FDONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn awb_fdone(&self) -> AWB_FDONE_R { + AWB_FDONE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done"] #[inline(always)] - pub fn hist_fdone_int_raw(&self) -> HIST_FDONE_INT_RAW_R { - HIST_FDONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + pub fn hist_fdone(&self) -> HIST_FDONE_R { + HIST_FDONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - the raw interrupt status of isp frame end"] #[inline(always)] - pub fn frame_int_raw(&self) -> FRAME_INT_RAW_R { - FRAME_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + pub fn frame(&self) -> FRAME_R { + FRAME_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - the raw interrupt status of blc frame done"] #[inline(always)] - pub fn blc_frame_int_raw(&self) -> BLC_FRAME_INT_RAW_R { - BLC_FRAME_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + pub fn blc_frame(&self) -> BLC_FRAME_R { + BLC_FRAME_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - the raw interrupt status of lsc frame done"] #[inline(always)] - pub fn lsc_frame_int_raw(&self) -> LSC_FRAME_INT_RAW_R { - LSC_FRAME_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + pub fn lsc_frame(&self) -> LSC_FRAME_R { + LSC_FRAME_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - the raw interrupt status of dpc frame done"] #[inline(always)] - pub fn dpc_frame_int_raw(&self) -> DPC_FRAME_INT_RAW_R { - DPC_FRAME_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + pub fn dpc_frame(&self) -> DPC_FRAME_R { + DPC_FRAME_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - the raw interrupt status of bf frame done"] #[inline(always)] - pub fn bf_frame_int_raw(&self) -> BF_FRAME_INT_RAW_R { - BF_FRAME_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + pub fn bf_frame(&self) -> BF_FRAME_R { + BF_FRAME_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - the raw interrupt status of demosaic frame done"] #[inline(always)] - pub fn demosaic_frame_int_raw(&self) -> DEMOSAIC_FRAME_INT_RAW_R { - DEMOSAIC_FRAME_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + pub fn demosaic_frame(&self) -> DEMOSAIC_FRAME_R { + DEMOSAIC_FRAME_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 20 - the raw interrupt status of median frame done"] #[inline(always)] - pub fn median_frame_int_raw(&self) -> MEDIAN_FRAME_INT_RAW_R { - MEDIAN_FRAME_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + pub fn median_frame(&self) -> MEDIAN_FRAME_R { + MEDIAN_FRAME_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - the raw interrupt status of ccm frame done"] #[inline(always)] - pub fn ccm_frame_int_raw(&self) -> CCM_FRAME_INT_RAW_R { - CCM_FRAME_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + pub fn ccm_frame(&self) -> CCM_FRAME_R { + CCM_FRAME_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - the raw interrupt status of gamma frame done"] #[inline(always)] - pub fn gamma_frame_int_raw(&self) -> GAMMA_FRAME_INT_RAW_R { - GAMMA_FRAME_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + pub fn gamma_frame(&self) -> GAMMA_FRAME_R { + GAMMA_FRAME_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - the raw interrupt status of rgb2yuv frame done"] #[inline(always)] - pub fn rgb2yuv_frame_int_raw(&self) -> RGB2YUV_FRAME_INT_RAW_R { - RGB2YUV_FRAME_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + pub fn rgb2yuv_frame(&self) -> RGB2YUV_FRAME_R { + RGB2YUV_FRAME_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - the raw interrupt status of sharp frame done"] #[inline(always)] - pub fn sharp_frame_int_raw(&self) -> SHARP_FRAME_INT_RAW_R { - SHARP_FRAME_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + pub fn sharp_frame(&self) -> SHARP_FRAME_R { + SHARP_FRAME_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - the raw interrupt status of color frame done"] #[inline(always)] - pub fn color_frame_int_raw(&self) -> COLOR_FRAME_INT_RAW_R { - COLOR_FRAME_INT_RAW_R::new(((self.bits >> 25) & 1) != 0) + pub fn color_frame(&self) -> COLOR_FRAME_R { + COLOR_FRAME_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - the raw interrupt status of yuv2rgb frame done"] #[inline(always)] - pub fn yuv2rgb_frame_int_raw(&self) -> YUV2RGB_FRAME_INT_RAW_R { - YUV2RGB_FRAME_INT_RAW_R::new(((self.bits >> 26) & 1) != 0) + pub fn yuv2rgb_frame(&self) -> YUV2RGB_FRAME_R { + YUV2RGB_FRAME_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - the raw interrupt status of isp_tail idi frame_end"] #[inline(always)] - pub fn tail_idi_frame_int_raw(&self) -> TAIL_IDI_FRAME_INT_RAW_R { - TAIL_IDI_FRAME_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + pub fn tail_idi_frame(&self) -> TAIL_IDI_FRAME_R { + TAIL_IDI_FRAME_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - the raw interrupt status of real input frame end of isp_input"] #[inline(always)] - pub fn header_idi_frame_int_raw(&self) -> HEADER_IDI_FRAME_INT_RAW_R { - HEADER_IDI_FRAME_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + pub fn header_idi_frame(&self) -> HEADER_IDI_FRAME_R { + HEADER_IDI_FRAME_R::new(((self.bits >> 28) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -210,120 +210,78 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_RAW") .field( - "isp_data_type_err_int_raw", - &format_args!("{}", self.isp_data_type_err_int_raw().bit()), + "isp_data_type_err", + &format_args!("{}", self.isp_data_type_err().bit()), ) .field( - "isp_async_fifo_ovf_int_raw", - &format_args!("{}", self.isp_async_fifo_ovf_int_raw().bit()), + "isp_async_fifo_ovf", + &format_args!("{}", self.isp_async_fifo_ovf().bit()), ) .field( - "isp_buf_full_int_raw", - &format_args!("{}", self.isp_buf_full_int_raw().bit()), + "isp_buf_full", + &format_args!("{}", self.isp_buf_full().bit()), ) .field( - "isp_hvnum_setting_err_int_raw", - &format_args!("{}", self.isp_hvnum_setting_err_int_raw().bit()), + "isp_hvnum_setting_err", + &format_args!("{}", self.isp_hvnum_setting_err().bit()), ) .field( - "isp_data_type_setting_err_int_raw", - &format_args!("{}", self.isp_data_type_setting_err_int_raw().bit()), + "isp_data_type_setting_err", + &format_args!("{}", self.isp_data_type_setting_err().bit()), ) .field( - "isp_mipi_hnum_unmatch_int_raw", - &format_args!("{}", self.isp_mipi_hnum_unmatch_int_raw().bit()), + "isp_mipi_hnum_unmatch", + &format_args!("{}", self.isp_mipi_hnum_unmatch().bit()), ) .field( - "dpc_check_done_int_raw", - &format_args!("{}", self.dpc_check_done_int_raw().bit()), + "dpc_check_done", + &format_args!("{}", self.dpc_check_done().bit()), ) .field( - "gamma_xcoord_err_int_raw", - &format_args!("{}", self.gamma_xcoord_err_int_raw().bit()), + "gamma_xcoord_err", + &format_args!("{}", self.gamma_xcoord_err().bit()), ) + .field("ae_monitor", &format_args!("{}", self.ae_monitor().bit())) .field( - "ae_monitor_int_raw", - &format_args!("{}", self.ae_monitor_int_raw().bit()), + "ae_frame_done", + &format_args!("{}", self.ae_frame_done().bit()), ) + .field("af_fdone", &format_args!("{}", self.af_fdone().bit())) + .field("af_env", &format_args!("{}", self.af_env().bit())) + .field("awb_fdone", &format_args!("{}", self.awb_fdone().bit())) + .field("hist_fdone", &format_args!("{}", self.hist_fdone().bit())) + .field("frame", &format_args!("{}", self.frame().bit())) + .field("blc_frame", &format_args!("{}", self.blc_frame().bit())) + .field("lsc_frame", &format_args!("{}", self.lsc_frame().bit())) + .field("dpc_frame", &format_args!("{}", self.dpc_frame().bit())) + .field("bf_frame", &format_args!("{}", self.bf_frame().bit())) .field( - "ae_frame_done_int_raw", - &format_args!("{}", self.ae_frame_done_int_raw().bit()), + "demosaic_frame", + &format_args!("{}", self.demosaic_frame().bit()), ) .field( - "af_fdone_int_raw", - &format_args!("{}", self.af_fdone_int_raw().bit()), + "median_frame", + &format_args!("{}", self.median_frame().bit()), ) + .field("ccm_frame", &format_args!("{}", self.ccm_frame().bit())) + .field("gamma_frame", &format_args!("{}", self.gamma_frame().bit())) .field( - "af_env_int_raw", - &format_args!("{}", self.af_env_int_raw().bit()), + "rgb2yuv_frame", + &format_args!("{}", self.rgb2yuv_frame().bit()), ) + .field("sharp_frame", &format_args!("{}", self.sharp_frame().bit())) + .field("color_frame", &format_args!("{}", self.color_frame().bit())) .field( - "awb_fdone_int_raw", - &format_args!("{}", self.awb_fdone_int_raw().bit()), + "yuv2rgb_frame", + &format_args!("{}", self.yuv2rgb_frame().bit()), ) .field( - "hist_fdone_int_raw", - &format_args!("{}", self.hist_fdone_int_raw().bit()), + "tail_idi_frame", + &format_args!("{}", self.tail_idi_frame().bit()), ) .field( - "frame_int_raw", - &format_args!("{}", self.frame_int_raw().bit()), - ) - .field( - "blc_frame_int_raw", - &format_args!("{}", self.blc_frame_int_raw().bit()), - ) - .field( - "lsc_frame_int_raw", - &format_args!("{}", self.lsc_frame_int_raw().bit()), - ) - .field( - "dpc_frame_int_raw", - &format_args!("{}", self.dpc_frame_int_raw().bit()), - ) - .field( - "bf_frame_int_raw", - &format_args!("{}", self.bf_frame_int_raw().bit()), - ) - .field( - "demosaic_frame_int_raw", - &format_args!("{}", self.demosaic_frame_int_raw().bit()), - ) - .field( - "median_frame_int_raw", - &format_args!("{}", self.median_frame_int_raw().bit()), - ) - .field( - "ccm_frame_int_raw", - &format_args!("{}", self.ccm_frame_int_raw().bit()), - ) - .field( - "gamma_frame_int_raw", - &format_args!("{}", self.gamma_frame_int_raw().bit()), - ) - .field( - "rgb2yuv_frame_int_raw", - &format_args!("{}", self.rgb2yuv_frame_int_raw().bit()), - ) - .field( - "sharp_frame_int_raw", - &format_args!("{}", self.sharp_frame_int_raw().bit()), - ) - .field( - "color_frame_int_raw", - &format_args!("{}", self.color_frame_int_raw().bit()), - ) - .field( - "yuv2rgb_frame_int_raw", - &format_args!("{}", self.yuv2rgb_frame_int_raw().bit()), - ) - .field( - "tail_idi_frame_int_raw", - &format_args!("{}", self.tail_idi_frame_int_raw().bit()), - ) - .field( - "header_idi_frame_int_raw", - &format_args!("{}", self.header_idi_frame_int_raw().bit()), + "header_idi_frame", + &format_args!("{}", self.header_idi_frame().bit()), ) .finish() } diff --git a/esp32p4/src/isp/int_st.rs b/esp32p4/src/isp/int_st.rs index a0e27edf4f..226f44e9c7 100644 --- a/esp32p4/src/isp/int_st.rs +++ b/esp32p4/src/isp/int_st.rs @@ -1,208 +1,208 @@ #[doc = "Register `INT_ST` reader"] pub type R = crate::R; -#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ST` reader - the masked interrupt status of input data type error"] -pub type ISP_DATA_TYPE_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ST` reader - the masked interrupt status of isp input fifo overflow"] -pub type ISP_ASYNC_FIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `ISP_BUF_FULL_INT_ST` reader - the masked interrupt status of isp input buffer full"] -pub type ISP_BUF_FULL_INT_ST_R = crate::BitReader; -#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ST` reader - the masked interrupt status of hnum and vnum setting format error"] -pub type ISP_HVNUM_SETTING_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ST` reader - the masked interrupt status of setting invalid reg_data_type"] -pub type ISP_DATA_TYPE_SETTING_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ST` reader - the masked interrupt status of hnum setting unmatch with mipi input"] -pub type ISP_MIPI_HNUM_UNMATCH_INT_ST_R = crate::BitReader; -#[doc = "Field `DPC_CHECK_DONE_INT_ST` reader - the masked interrupt status of dpc check done"] -pub type DPC_CHECK_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `GAMMA_XCOORD_ERR_INT_ST` reader - the masked interrupt status of gamma setting error"] -pub type GAMMA_XCOORD_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `AE_MONITOR_INT_ST` reader - the masked interrupt status of ae monitor"] -pub type AE_MONITOR_INT_ST_R = crate::BitReader; -#[doc = "Field `AE_FRAME_DONE_INT_ST` reader - the masked interrupt status of ae"] -pub type AE_FRAME_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `AF_FDONE_INT_ST` reader - the masked interrupt status of af statistic"] -pub type AF_FDONE_INT_ST_R = crate::BitReader; -#[doc = "Field `AF_ENV_INT_ST` reader - the masked interrupt status of af monitor"] -pub type AF_ENV_INT_ST_R = crate::BitReader; -#[doc = "Field `AWB_FDONE_INT_ST` reader - the masked interrupt status of awb"] -pub type AWB_FDONE_INT_ST_R = crate::BitReader; -#[doc = "Field `HIST_FDONE_INT_ST` reader - the masked interrupt status of histogram"] -pub type HIST_FDONE_INT_ST_R = crate::BitReader; -#[doc = "Field `FRAME_INT_ST` reader - the masked interrupt status of isp frame end"] -pub type FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `BLC_FRAME_INT_ST` reader - the masked interrupt status of blc frame done"] -pub type BLC_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `LSC_FRAME_INT_ST` reader - the masked interrupt status of lsc frame done"] -pub type LSC_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `DPC_FRAME_INT_ST` reader - the masked interrupt status of dpc frame done"] -pub type DPC_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `BF_FRAME_INT_ST` reader - the masked interrupt status of bf frame done"] -pub type BF_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `DEMOSAIC_FRAME_INT_ST` reader - the masked interrupt status of demosaic frame done"] -pub type DEMOSAIC_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `MEDIAN_FRAME_INT_ST` reader - the masked interrupt status of median frame done"] -pub type MEDIAN_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `CCM_FRAME_INT_ST` reader - the masked interrupt status of ccm frame done"] -pub type CCM_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `GAMMA_FRAME_INT_ST` reader - the masked interrupt status of gamma frame done"] -pub type GAMMA_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `RGB2YUV_FRAME_INT_ST` reader - the masked interrupt status of rgb2yuv frame done"] -pub type RGB2YUV_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `SHARP_FRAME_INT_ST` reader - the masked interrupt status of sharp frame done"] -pub type SHARP_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `COLOR_FRAME_INT_ST` reader - the masked interrupt status of color frame done"] -pub type COLOR_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `YUV2RGB_FRAME_INT_ST` reader - the masked interrupt status of yuv2rgb frame done"] -pub type YUV2RGB_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `TAIL_IDI_FRAME_INT_ST` reader - the masked interrupt status of isp_tail idi frame_end"] -pub type TAIL_IDI_FRAME_INT_ST_R = crate::BitReader; -#[doc = "Field `HEADER_IDI_FRAME_INT_ST` reader - the masked interrupt status of real input frame end of isp_input"] -pub type HEADER_IDI_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_ERR` reader - the masked interrupt status of input data type error"] +pub type ISP_DATA_TYPE_ERR_R = crate::BitReader; +#[doc = "Field `ISP_ASYNC_FIFO_OVF` reader - the masked interrupt status of isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_R = crate::BitReader; +#[doc = "Field `ISP_BUF_FULL` reader - the masked interrupt status of isp input buffer full"] +pub type ISP_BUF_FULL_R = crate::BitReader; +#[doc = "Field `ISP_HVNUM_SETTING_ERR` reader - the masked interrupt status of hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR` reader - the masked interrupt status of setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_R = crate::BitReader; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH` reader - the masked interrupt status of hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_DONE` reader - the masked interrupt status of dpc check done"] +pub type DPC_CHECK_DONE_R = crate::BitReader; +#[doc = "Field `GAMMA_XCOORD_ERR` reader - the masked interrupt status of gamma setting error"] +pub type GAMMA_XCOORD_ERR_R = crate::BitReader; +#[doc = "Field `AE_MONITOR` reader - the masked interrupt status of ae monitor"] +pub type AE_MONITOR_R = crate::BitReader; +#[doc = "Field `AE_FRAME_DONE` reader - the masked interrupt status of ae"] +pub type AE_FRAME_DONE_R = crate::BitReader; +#[doc = "Field `AF_FDONE` reader - the masked interrupt status of af statistic"] +pub type AF_FDONE_R = crate::BitReader; +#[doc = "Field `AF_ENV` reader - the masked interrupt status of af monitor"] +pub type AF_ENV_R = crate::BitReader; +#[doc = "Field `AWB_FDONE` reader - the masked interrupt status of awb"] +pub type AWB_FDONE_R = crate::BitReader; +#[doc = "Field `HIST_FDONE` reader - the masked interrupt status of histogram"] +pub type HIST_FDONE_R = crate::BitReader; +#[doc = "Field `FRAME` reader - the masked interrupt status of isp frame end"] +pub type FRAME_R = crate::BitReader; +#[doc = "Field `BLC_FRAME` reader - the masked interrupt status of blc frame done"] +pub type BLC_FRAME_R = crate::BitReader; +#[doc = "Field `LSC_FRAME` reader - the masked interrupt status of lsc frame done"] +pub type LSC_FRAME_R = crate::BitReader; +#[doc = "Field `DPC_FRAME` reader - the masked interrupt status of dpc frame done"] +pub type DPC_FRAME_R = crate::BitReader; +#[doc = "Field `BF_FRAME` reader - the masked interrupt status of bf frame done"] +pub type BF_FRAME_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_FRAME` reader - the masked interrupt status of demosaic frame done"] +pub type DEMOSAIC_FRAME_R = crate::BitReader; +#[doc = "Field `MEDIAN_FRAME` reader - the masked interrupt status of median frame done"] +pub type MEDIAN_FRAME_R = crate::BitReader; +#[doc = "Field `CCM_FRAME` reader - the masked interrupt status of ccm frame done"] +pub type CCM_FRAME_R = crate::BitReader; +#[doc = "Field `GAMMA_FRAME` reader - the masked interrupt status of gamma frame done"] +pub type GAMMA_FRAME_R = crate::BitReader; +#[doc = "Field `RGB2YUV_FRAME` reader - the masked interrupt status of rgb2yuv frame done"] +pub type RGB2YUV_FRAME_R = crate::BitReader; +#[doc = "Field `SHARP_FRAME` reader - the masked interrupt status of sharp frame done"] +pub type SHARP_FRAME_R = crate::BitReader; +#[doc = "Field `COLOR_FRAME` reader - the masked interrupt status of color frame done"] +pub type COLOR_FRAME_R = crate::BitReader; +#[doc = "Field `YUV2RGB_FRAME` reader - the masked interrupt status of yuv2rgb frame done"] +pub type YUV2RGB_FRAME_R = crate::BitReader; +#[doc = "Field `TAIL_IDI_FRAME` reader - the masked interrupt status of isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_R = crate::BitReader; +#[doc = "Field `HEADER_IDI_FRAME` reader - the masked interrupt status of real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_R = crate::BitReader; impl R { #[doc = "Bit 0 - the masked interrupt status of input data type error"] #[inline(always)] - pub fn isp_data_type_err_int_st(&self) -> ISP_DATA_TYPE_ERR_INT_ST_R { - ISP_DATA_TYPE_ERR_INT_ST_R::new((self.bits & 1) != 0) + pub fn isp_data_type_err(&self) -> ISP_DATA_TYPE_ERR_R { + ISP_DATA_TYPE_ERR_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - the masked interrupt status of isp input fifo overflow"] #[inline(always)] - pub fn isp_async_fifo_ovf_int_st(&self) -> ISP_ASYNC_FIFO_OVF_INT_ST_R { - ISP_ASYNC_FIFO_OVF_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn isp_async_fifo_ovf(&self) -> ISP_ASYNC_FIFO_OVF_R { + ISP_ASYNC_FIFO_OVF_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - the masked interrupt status of isp input buffer full"] #[inline(always)] - pub fn isp_buf_full_int_st(&self) -> ISP_BUF_FULL_INT_ST_R { - ISP_BUF_FULL_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn isp_buf_full(&self) -> ISP_BUF_FULL_R { + ISP_BUF_FULL_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - the masked interrupt status of hnum and vnum setting format error"] #[inline(always)] - pub fn isp_hvnum_setting_err_int_st(&self) -> ISP_HVNUM_SETTING_ERR_INT_ST_R { - ISP_HVNUM_SETTING_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn isp_hvnum_setting_err(&self) -> ISP_HVNUM_SETTING_ERR_R { + ISP_HVNUM_SETTING_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - the masked interrupt status of setting invalid reg_data_type"] #[inline(always)] - pub fn isp_data_type_setting_err_int_st(&self) -> ISP_DATA_TYPE_SETTING_ERR_INT_ST_R { - ISP_DATA_TYPE_SETTING_ERR_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn isp_data_type_setting_err(&self) -> ISP_DATA_TYPE_SETTING_ERR_R { + ISP_DATA_TYPE_SETTING_ERR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - the masked interrupt status of hnum setting unmatch with mipi input"] #[inline(always)] - pub fn isp_mipi_hnum_unmatch_int_st(&self) -> ISP_MIPI_HNUM_UNMATCH_INT_ST_R { - ISP_MIPI_HNUM_UNMATCH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn isp_mipi_hnum_unmatch(&self) -> ISP_MIPI_HNUM_UNMATCH_R { + ISP_MIPI_HNUM_UNMATCH_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - the masked interrupt status of dpc check done"] #[inline(always)] - pub fn dpc_check_done_int_st(&self) -> DPC_CHECK_DONE_INT_ST_R { - DPC_CHECK_DONE_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn dpc_check_done(&self) -> DPC_CHECK_DONE_R { + DPC_CHECK_DONE_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - the masked interrupt status of gamma setting error"] #[inline(always)] - pub fn gamma_xcoord_err_int_st(&self) -> GAMMA_XCOORD_ERR_INT_ST_R { - GAMMA_XCOORD_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn gamma_xcoord_err(&self) -> GAMMA_XCOORD_ERR_R { + GAMMA_XCOORD_ERR_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - the masked interrupt status of ae monitor"] #[inline(always)] - pub fn ae_monitor_int_st(&self) -> AE_MONITOR_INT_ST_R { - AE_MONITOR_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn ae_monitor(&self) -> AE_MONITOR_R { + AE_MONITOR_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - the masked interrupt status of ae"] #[inline(always)] - pub fn ae_frame_done_int_st(&self) -> AE_FRAME_DONE_INT_ST_R { - AE_FRAME_DONE_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn ae_frame_done(&self) -> AE_FRAME_DONE_R { + AE_FRAME_DONE_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - the masked interrupt status of af statistic"] #[inline(always)] - pub fn af_fdone_int_st(&self) -> AF_FDONE_INT_ST_R { - AF_FDONE_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn af_fdone(&self) -> AF_FDONE_R { + AF_FDONE_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - the masked interrupt status of af monitor"] #[inline(always)] - pub fn af_env_int_st(&self) -> AF_ENV_INT_ST_R { - AF_ENV_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn af_env(&self) -> AF_ENV_R { + AF_ENV_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - the masked interrupt status of awb"] #[inline(always)] - pub fn awb_fdone_int_st(&self) -> AWB_FDONE_INT_ST_R { - AWB_FDONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn awb_fdone(&self) -> AWB_FDONE_R { + AWB_FDONE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - the masked interrupt status of histogram"] #[inline(always)] - pub fn hist_fdone_int_st(&self) -> HIST_FDONE_INT_ST_R { - HIST_FDONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + pub fn hist_fdone(&self) -> HIST_FDONE_R { + HIST_FDONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - the masked interrupt status of isp frame end"] #[inline(always)] - pub fn frame_int_st(&self) -> FRAME_INT_ST_R { - FRAME_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + pub fn frame(&self) -> FRAME_R { + FRAME_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - the masked interrupt status of blc frame done"] #[inline(always)] - pub fn blc_frame_int_st(&self) -> BLC_FRAME_INT_ST_R { - BLC_FRAME_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + pub fn blc_frame(&self) -> BLC_FRAME_R { + BLC_FRAME_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - the masked interrupt status of lsc frame done"] #[inline(always)] - pub fn lsc_frame_int_st(&self) -> LSC_FRAME_INT_ST_R { - LSC_FRAME_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + pub fn lsc_frame(&self) -> LSC_FRAME_R { + LSC_FRAME_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - the masked interrupt status of dpc frame done"] #[inline(always)] - pub fn dpc_frame_int_st(&self) -> DPC_FRAME_INT_ST_R { - DPC_FRAME_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + pub fn dpc_frame(&self) -> DPC_FRAME_R { + DPC_FRAME_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - the masked interrupt status of bf frame done"] #[inline(always)] - pub fn bf_frame_int_st(&self) -> BF_FRAME_INT_ST_R { - BF_FRAME_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + pub fn bf_frame(&self) -> BF_FRAME_R { + BF_FRAME_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - the masked interrupt status of demosaic frame done"] #[inline(always)] - pub fn demosaic_frame_int_st(&self) -> DEMOSAIC_FRAME_INT_ST_R { - DEMOSAIC_FRAME_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + pub fn demosaic_frame(&self) -> DEMOSAIC_FRAME_R { + DEMOSAIC_FRAME_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 20 - the masked interrupt status of median frame done"] #[inline(always)] - pub fn median_frame_int_st(&self) -> MEDIAN_FRAME_INT_ST_R { - MEDIAN_FRAME_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + pub fn median_frame(&self) -> MEDIAN_FRAME_R { + MEDIAN_FRAME_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - the masked interrupt status of ccm frame done"] #[inline(always)] - pub fn ccm_frame_int_st(&self) -> CCM_FRAME_INT_ST_R { - CCM_FRAME_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + pub fn ccm_frame(&self) -> CCM_FRAME_R { + CCM_FRAME_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - the masked interrupt status of gamma frame done"] #[inline(always)] - pub fn gamma_frame_int_st(&self) -> GAMMA_FRAME_INT_ST_R { - GAMMA_FRAME_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + pub fn gamma_frame(&self) -> GAMMA_FRAME_R { + GAMMA_FRAME_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - the masked interrupt status of rgb2yuv frame done"] #[inline(always)] - pub fn rgb2yuv_frame_int_st(&self) -> RGB2YUV_FRAME_INT_ST_R { - RGB2YUV_FRAME_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + pub fn rgb2yuv_frame(&self) -> RGB2YUV_FRAME_R { + RGB2YUV_FRAME_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - the masked interrupt status of sharp frame done"] #[inline(always)] - pub fn sharp_frame_int_st(&self) -> SHARP_FRAME_INT_ST_R { - SHARP_FRAME_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + pub fn sharp_frame(&self) -> SHARP_FRAME_R { + SHARP_FRAME_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - the masked interrupt status of color frame done"] #[inline(always)] - pub fn color_frame_int_st(&self) -> COLOR_FRAME_INT_ST_R { - COLOR_FRAME_INT_ST_R::new(((self.bits >> 25) & 1) != 0) + pub fn color_frame(&self) -> COLOR_FRAME_R { + COLOR_FRAME_R::new(((self.bits >> 25) & 1) != 0) } #[doc = "Bit 26 - the masked interrupt status of yuv2rgb frame done"] #[inline(always)] - pub fn yuv2rgb_frame_int_st(&self) -> YUV2RGB_FRAME_INT_ST_R { - YUV2RGB_FRAME_INT_ST_R::new(((self.bits >> 26) & 1) != 0) + pub fn yuv2rgb_frame(&self) -> YUV2RGB_FRAME_R { + YUV2RGB_FRAME_R::new(((self.bits >> 26) & 1) != 0) } #[doc = "Bit 27 - the masked interrupt status of isp_tail idi frame_end"] #[inline(always)] - pub fn tail_idi_frame_int_st(&self) -> TAIL_IDI_FRAME_INT_ST_R { - TAIL_IDI_FRAME_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + pub fn tail_idi_frame(&self) -> TAIL_IDI_FRAME_R { + TAIL_IDI_FRAME_R::new(((self.bits >> 27) & 1) != 0) } #[doc = "Bit 28 - the masked interrupt status of real input frame end of isp_input"] #[inline(always)] - pub fn header_idi_frame_int_st(&self) -> HEADER_IDI_FRAME_INT_ST_R { - HEADER_IDI_FRAME_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + pub fn header_idi_frame(&self) -> HEADER_IDI_FRAME_R { + HEADER_IDI_FRAME_R::new(((self.bits >> 28) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] @@ -210,120 +210,78 @@ impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ST") .field( - "isp_data_type_err_int_st", - &format_args!("{}", self.isp_data_type_err_int_st().bit()), + "isp_data_type_err", + &format_args!("{}", self.isp_data_type_err().bit()), ) .field( - "isp_async_fifo_ovf_int_st", - &format_args!("{}", self.isp_async_fifo_ovf_int_st().bit()), + "isp_async_fifo_ovf", + &format_args!("{}", self.isp_async_fifo_ovf().bit()), ) .field( - "isp_buf_full_int_st", - &format_args!("{}", self.isp_buf_full_int_st().bit()), + "isp_buf_full", + &format_args!("{}", self.isp_buf_full().bit()), ) .field( - "isp_hvnum_setting_err_int_st", - &format_args!("{}", self.isp_hvnum_setting_err_int_st().bit()), + "isp_hvnum_setting_err", + &format_args!("{}", self.isp_hvnum_setting_err().bit()), ) .field( - "isp_data_type_setting_err_int_st", - &format_args!("{}", self.isp_data_type_setting_err_int_st().bit()), + "isp_data_type_setting_err", + &format_args!("{}", self.isp_data_type_setting_err().bit()), ) .field( - "isp_mipi_hnum_unmatch_int_st", - &format_args!("{}", self.isp_mipi_hnum_unmatch_int_st().bit()), + "isp_mipi_hnum_unmatch", + &format_args!("{}", self.isp_mipi_hnum_unmatch().bit()), ) .field( - "dpc_check_done_int_st", - &format_args!("{}", self.dpc_check_done_int_st().bit()), + "dpc_check_done", + &format_args!("{}", self.dpc_check_done().bit()), ) .field( - "gamma_xcoord_err_int_st", - &format_args!("{}", self.gamma_xcoord_err_int_st().bit()), + "gamma_xcoord_err", + &format_args!("{}", self.gamma_xcoord_err().bit()), ) + .field("ae_monitor", &format_args!("{}", self.ae_monitor().bit())) .field( - "ae_monitor_int_st", - &format_args!("{}", self.ae_monitor_int_st().bit()), + "ae_frame_done", + &format_args!("{}", self.ae_frame_done().bit()), ) + .field("af_fdone", &format_args!("{}", self.af_fdone().bit())) + .field("af_env", &format_args!("{}", self.af_env().bit())) + .field("awb_fdone", &format_args!("{}", self.awb_fdone().bit())) + .field("hist_fdone", &format_args!("{}", self.hist_fdone().bit())) + .field("frame", &format_args!("{}", self.frame().bit())) + .field("blc_frame", &format_args!("{}", self.blc_frame().bit())) + .field("lsc_frame", &format_args!("{}", self.lsc_frame().bit())) + .field("dpc_frame", &format_args!("{}", self.dpc_frame().bit())) + .field("bf_frame", &format_args!("{}", self.bf_frame().bit())) .field( - "ae_frame_done_int_st", - &format_args!("{}", self.ae_frame_done_int_st().bit()), + "demosaic_frame", + &format_args!("{}", self.demosaic_frame().bit()), ) .field( - "af_fdone_int_st", - &format_args!("{}", self.af_fdone_int_st().bit()), + "median_frame", + &format_args!("{}", self.median_frame().bit()), ) + .field("ccm_frame", &format_args!("{}", self.ccm_frame().bit())) + .field("gamma_frame", &format_args!("{}", self.gamma_frame().bit())) .field( - "af_env_int_st", - &format_args!("{}", self.af_env_int_st().bit()), + "rgb2yuv_frame", + &format_args!("{}", self.rgb2yuv_frame().bit()), ) + .field("sharp_frame", &format_args!("{}", self.sharp_frame().bit())) + .field("color_frame", &format_args!("{}", self.color_frame().bit())) .field( - "awb_fdone_int_st", - &format_args!("{}", self.awb_fdone_int_st().bit()), + "yuv2rgb_frame", + &format_args!("{}", self.yuv2rgb_frame().bit()), ) .field( - "hist_fdone_int_st", - &format_args!("{}", self.hist_fdone_int_st().bit()), + "tail_idi_frame", + &format_args!("{}", self.tail_idi_frame().bit()), ) .field( - "frame_int_st", - &format_args!("{}", self.frame_int_st().bit()), - ) - .field( - "blc_frame_int_st", - &format_args!("{}", self.blc_frame_int_st().bit()), - ) - .field( - "lsc_frame_int_st", - &format_args!("{}", self.lsc_frame_int_st().bit()), - ) - .field( - "dpc_frame_int_st", - &format_args!("{}", self.dpc_frame_int_st().bit()), - ) - .field( - "bf_frame_int_st", - &format_args!("{}", self.bf_frame_int_st().bit()), - ) - .field( - "demosaic_frame_int_st", - &format_args!("{}", self.demosaic_frame_int_st().bit()), - ) - .field( - "median_frame_int_st", - &format_args!("{}", self.median_frame_int_st().bit()), - ) - .field( - "ccm_frame_int_st", - &format_args!("{}", self.ccm_frame_int_st().bit()), - ) - .field( - "gamma_frame_int_st", - &format_args!("{}", self.gamma_frame_int_st().bit()), - ) - .field( - "rgb2yuv_frame_int_st", - &format_args!("{}", self.rgb2yuv_frame_int_st().bit()), - ) - .field( - "sharp_frame_int_st", - &format_args!("{}", self.sharp_frame_int_st().bit()), - ) - .field( - "color_frame_int_st", - &format_args!("{}", self.color_frame_int_st().bit()), - ) - .field( - "yuv2rgb_frame_int_st", - &format_args!("{}", self.yuv2rgb_frame_int_st().bit()), - ) - .field( - "tail_idi_frame_int_st", - &format_args!("{}", self.tail_idi_frame_int_st().bit()), - ) - .field( - "header_idi_frame_int_st", - &format_args!("{}", self.header_idi_frame_int_st().bit()), + "header_idi_frame", + &format_args!("{}", self.header_idi_frame().bit()), ) .finish() } diff --git a/esp32p4/src/jpeg.rs b/esp32p4/src/jpeg.rs index 31f1a6306a..8a2f54613d 100644 --- a/esp32p4/src/jpeg.rs +++ b/esp32p4/src/jpeg.rs @@ -11,10 +11,7 @@ pub struct RegisterBlock { t2qnr: T2QNR, t3qnr: T3QNR, decode_conf: DECODE_CONF, - c0: C0, - c1: C1, - c2: C2, - c3: C3, + c: [C; 4], dht_info: DHT_INFO, int_raw: INT_RAW, int_ena: INT_ENA, @@ -45,7 +42,7 @@ pub struct RegisterBlock { status5: STATUS5, eco_low: ECO_LOW, eco_high: ECO_HIGH, - _reserved42: [u8; 0x4c], + _reserved39: [u8; 0x4c], sys: SYS, version: VERSION, } @@ -90,25 +87,16 @@ impl RegisterBlock { pub const fn decode_conf(&self) -> &DECODE_CONF { &self.decode_conf } - #[doc = "0x24 - Control and configuration registers"] + #[doc = "0x24..0x34 - Control and configuration registers"] #[inline(always)] - pub const fn c0(&self) -> &C0 { - &self.c0 + pub const fn c(&self, n: usize) -> &C { + &self.c[n] } - #[doc = "0x28 - Control and configuration registers"] + #[doc = "Iterator for array of:"] + #[doc = "0x24..0x34 - Control and configuration registers"] #[inline(always)] - pub const fn c1(&self) -> &C1 { - &self.c1 - } - #[doc = "0x2c - Control and configuration registers"] - #[inline(always)] - pub const fn c2(&self) -> &C2 { - &self.c2 - } - #[doc = "0x30 - Control and configuration registers"] - #[inline(always)] - pub const fn c3(&self) -> &C3 { - &self.c3 + pub fn c_iter(&self) -> impl Iterator { + self.c.iter() } #[doc = "0x34 - Control and configuration registers"] #[inline(always)] @@ -303,22 +291,10 @@ pub mod t3qnr; pub type DECODE_CONF = crate::Reg; #[doc = "Control and configuration registers"] pub mod decode_conf; -#[doc = "C0 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c0`] module"] -pub type C0 = crate::Reg; -#[doc = "Control and configuration registers"] -pub mod c0; -#[doc = "C1 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c1`] module"] -pub type C1 = crate::Reg; -#[doc = "Control and configuration registers"] -pub mod c1; -#[doc = "C2 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c2`] module"] -pub type C2 = crate::Reg; -#[doc = "Control and configuration registers"] -pub mod c2; -#[doc = "C3 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c3`] module"] -pub type C3 = crate::Reg; +#[doc = "C (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c`] module"] +pub type C = crate::Reg; #[doc = "Control and configuration registers"] -pub mod c3; +pub mod c; #[doc = "DHT_INFO (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_info::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dht_info::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_info`] module"] pub type DHT_INFO = crate::Reg; #[doc = "Control and configuration registers"] diff --git a/esp32p4/src/jpeg/c0.rs b/esp32p4/src/jpeg/c.rs similarity index 73% rename from esp32p4/src/jpeg/c0.rs rename to esp32p4/src/jpeg/c.rs index cbf799d52a..64f2677b9a 100644 --- a/esp32p4/src/jpeg/c0.rs +++ b/esp32p4/src/jpeg/c.rs @@ -1,7 +1,7 @@ -#[doc = "Register `C0` reader"] -pub type R = crate::R; -#[doc = "Register `C0` writer"] -pub type W = crate::W; +#[doc = "Register `C%s` reader"] +pub type R = crate::R; +#[doc = "Register `C%s` writer"] +pub type W = crate::W; #[doc = "Field `DQT_TBL_SEL` reader - choose c0 quntization table id (TBD)"] pub type DQT_TBL_SEL_R = crate::FieldReader; #[doc = "Field `DQT_TBL_SEL` writer - choose c0 quntization table id (TBD)"] @@ -43,7 +43,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("C0") + f.debug_struct("C") .field( "dqt_tbl_sel", &format_args!("{}", self.dqt_tbl_sel().bits()), @@ -55,7 +55,7 @@ impl core::fmt::Debug for R { } } #[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { +impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { core::fmt::Debug::fmt(&self.read(), f) } @@ -64,42 +64,42 @@ impl W { #[doc = "Bits 0:7 - choose c0 quntization table id (TBD)"] #[inline(always)] #[must_use] - pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { + pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { DQT_TBL_SEL_W::new(self, 0) } #[doc = "Bits 8:11 - vertical sampling factor of c0"] #[inline(always)] #[must_use] - pub fn y_factor(&mut self) -> Y_FACTOR_W { + pub fn y_factor(&mut self) -> Y_FACTOR_W { Y_FACTOR_W::new(self, 8) } #[doc = "Bits 12:15 - horizontal sampling factor of c0"] #[inline(always)] #[must_use] - pub fn x_factor(&mut self) -> X_FACTOR_W { + pub fn x_factor(&mut self) -> X_FACTOR_W { X_FACTOR_W::new(self, 12) } #[doc = "Bits 16:23 - the identifier of c0"] #[inline(always)] #[must_use] - pub fn id(&mut self) -> ID_W { + pub fn id(&mut self) -> ID_W { ID_W::new(self, 16) } } -#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct C0_SPEC; -impl crate::RegisterSpec for C0_SPEC { +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct C_SPEC; +impl crate::RegisterSpec for C_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`c0::R`](R) reader structure"] -impl crate::Readable for C0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`c0::W`](W) writer structure"] -impl crate::Writable for C0_SPEC { +#[doc = "`read()` method returns [`c::R`](R) reader structure"] +impl crate::Readable for C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c::W`](W) writer structure"] +impl crate::Writable for C_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets C0 to value 0x1100"] -impl crate::Resettable for C0_SPEC { +#[doc = "`reset()` method sets C%s to value 0x1100"] +impl crate::Resettable for C_SPEC { const RESET_VALUE: u32 = 0x1100; } diff --git a/esp32p4/src/jpeg/c1.rs b/esp32p4/src/jpeg/c1.rs deleted file mode 100644 index 30d32ce64c..0000000000 --- a/esp32p4/src/jpeg/c1.rs +++ /dev/null @@ -1,105 +0,0 @@ -#[doc = "Register `C1` reader"] -pub type R = crate::R; -#[doc = "Register `C1` writer"] -pub type W = crate::W; -#[doc = "Field `DQT_TBL_SEL` reader - choose c1 quntization table id (TBD)"] -pub type DQT_TBL_SEL_R = crate::FieldReader; -#[doc = "Field `DQT_TBL_SEL` writer - choose c1 quntization table id (TBD)"] -pub type DQT_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Y_FACTOR` reader - vertical sampling factor of c1"] -pub type Y_FACTOR_R = crate::FieldReader; -#[doc = "Field `Y_FACTOR` writer - vertical sampling factor of c1"] -pub type Y_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `X_FACTOR` reader - horizontal sampling factor of c1"] -pub type X_FACTOR_R = crate::FieldReader; -#[doc = "Field `X_FACTOR` writer - horizontal sampling factor of c1"] -pub type X_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ID` reader - the identifier of c1"] -pub type ID_R = crate::FieldReader; -#[doc = "Field `ID` writer - the identifier of c1"] -pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - choose c1 quntization table id (TBD)"] - #[inline(always)] - pub fn dqt_tbl_sel(&self) -> DQT_TBL_SEL_R { - DQT_TBL_SEL_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:11 - vertical sampling factor of c1"] - #[inline(always)] - pub fn y_factor(&self) -> Y_FACTOR_R { - Y_FACTOR_R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - horizontal sampling factor of c1"] - #[inline(always)] - pub fn x_factor(&self) -> X_FACTOR_R { - X_FACTOR_R::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:23 - the identifier of c1"] - #[inline(always)] - pub fn id(&self) -> ID_R { - ID_R::new(((self.bits >> 16) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("C1") - .field( - "dqt_tbl_sel", - &format_args!("{}", self.dqt_tbl_sel().bits()), - ) - .field("y_factor", &format_args!("{}", self.y_factor().bits())) - .field("x_factor", &format_args!("{}", self.x_factor().bits())) - .field("id", &format_args!("{}", self.id().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - choose c1 quntization table id (TBD)"] - #[inline(always)] - #[must_use] - pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { - DQT_TBL_SEL_W::new(self, 0) - } - #[doc = "Bits 8:11 - vertical sampling factor of c1"] - #[inline(always)] - #[must_use] - pub fn y_factor(&mut self) -> Y_FACTOR_W { - Y_FACTOR_W::new(self, 8) - } - #[doc = "Bits 12:15 - horizontal sampling factor of c1"] - #[inline(always)] - #[must_use] - pub fn x_factor(&mut self) -> X_FACTOR_W { - X_FACTOR_W::new(self, 12) - } - #[doc = "Bits 16:23 - the identifier of c1"] - #[inline(always)] - #[must_use] - pub fn id(&mut self) -> ID_W { - ID_W::new(self, 16) - } -} -#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct C1_SPEC; -impl crate::RegisterSpec for C1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`c1::R`](R) reader structure"] -impl crate::Readable for C1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`c1::W`](W) writer structure"] -impl crate::Writable for C1_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets C1 to value 0x1100"] -impl crate::Resettable for C1_SPEC { - const RESET_VALUE: u32 = 0x1100; -} diff --git a/esp32p4/src/jpeg/c2.rs b/esp32p4/src/jpeg/c2.rs deleted file mode 100644 index 428cec88c5..0000000000 --- a/esp32p4/src/jpeg/c2.rs +++ /dev/null @@ -1,105 +0,0 @@ -#[doc = "Register `C2` reader"] -pub type R = crate::R; -#[doc = "Register `C2` writer"] -pub type W = crate::W; -#[doc = "Field `DQT_TBL_SEL` reader - choose c2 quntization table id (TBD)"] -pub type DQT_TBL_SEL_R = crate::FieldReader; -#[doc = "Field `DQT_TBL_SEL` writer - choose c2 quntization table id (TBD)"] -pub type DQT_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Y_FACTOR` reader - vertical sampling factor of c2"] -pub type Y_FACTOR_R = crate::FieldReader; -#[doc = "Field `Y_FACTOR` writer - vertical sampling factor of c2"] -pub type Y_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `X_FACTOR` reader - horizontal sampling factor of c2"] -pub type X_FACTOR_R = crate::FieldReader; -#[doc = "Field `X_FACTOR` writer - horizontal sampling factor of c2"] -pub type X_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ID` reader - the identifier of c2"] -pub type ID_R = crate::FieldReader; -#[doc = "Field `ID` writer - the identifier of c2"] -pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - choose c2 quntization table id (TBD)"] - #[inline(always)] - pub fn dqt_tbl_sel(&self) -> DQT_TBL_SEL_R { - DQT_TBL_SEL_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:11 - vertical sampling factor of c2"] - #[inline(always)] - pub fn y_factor(&self) -> Y_FACTOR_R { - Y_FACTOR_R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - horizontal sampling factor of c2"] - #[inline(always)] - pub fn x_factor(&self) -> X_FACTOR_R { - X_FACTOR_R::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:23 - the identifier of c2"] - #[inline(always)] - pub fn id(&self) -> ID_R { - ID_R::new(((self.bits >> 16) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("C2") - .field( - "dqt_tbl_sel", - &format_args!("{}", self.dqt_tbl_sel().bits()), - ) - .field("y_factor", &format_args!("{}", self.y_factor().bits())) - .field("x_factor", &format_args!("{}", self.x_factor().bits())) - .field("id", &format_args!("{}", self.id().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - choose c2 quntization table id (TBD)"] - #[inline(always)] - #[must_use] - pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { - DQT_TBL_SEL_W::new(self, 0) - } - #[doc = "Bits 8:11 - vertical sampling factor of c2"] - #[inline(always)] - #[must_use] - pub fn y_factor(&mut self) -> Y_FACTOR_W { - Y_FACTOR_W::new(self, 8) - } - #[doc = "Bits 12:15 - horizontal sampling factor of c2"] - #[inline(always)] - #[must_use] - pub fn x_factor(&mut self) -> X_FACTOR_W { - X_FACTOR_W::new(self, 12) - } - #[doc = "Bits 16:23 - the identifier of c2"] - #[inline(always)] - #[must_use] - pub fn id(&mut self) -> ID_W { - ID_W::new(self, 16) - } -} -#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct C2_SPEC; -impl crate::RegisterSpec for C2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`c2::R`](R) reader structure"] -impl crate::Readable for C2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`c2::W`](W) writer structure"] -impl crate::Writable for C2_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets C2 to value 0x1100"] -impl crate::Resettable for C2_SPEC { - const RESET_VALUE: u32 = 0x1100; -} diff --git a/esp32p4/src/jpeg/c3.rs b/esp32p4/src/jpeg/c3.rs deleted file mode 100644 index 7ba91a5be2..0000000000 --- a/esp32p4/src/jpeg/c3.rs +++ /dev/null @@ -1,105 +0,0 @@ -#[doc = "Register `C3` reader"] -pub type R = crate::R; -#[doc = "Register `C3` writer"] -pub type W = crate::W; -#[doc = "Field `DQT_TBL_SEL` reader - choose c3 quntization table id (TBD)"] -pub type DQT_TBL_SEL_R = crate::FieldReader; -#[doc = "Field `DQT_TBL_SEL` writer - choose c3 quntization table id (TBD)"] -pub type DQT_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `Y_FACTOR` reader - vertical sampling factor of c3"] -pub type Y_FACTOR_R = crate::FieldReader; -#[doc = "Field `Y_FACTOR` writer - vertical sampling factor of c3"] -pub type Y_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `X_FACTOR` reader - horizontal sampling factor of c3"] -pub type X_FACTOR_R = crate::FieldReader; -#[doc = "Field `X_FACTOR` writer - horizontal sampling factor of c3"] -pub type X_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `ID` reader - the identifier of c3"] -pub type ID_R = crate::FieldReader; -#[doc = "Field `ID` writer - the identifier of c3"] -pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - choose c3 quntization table id (TBD)"] - #[inline(always)] - pub fn dqt_tbl_sel(&self) -> DQT_TBL_SEL_R { - DQT_TBL_SEL_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:11 - vertical sampling factor of c3"] - #[inline(always)] - pub fn y_factor(&self) -> Y_FACTOR_R { - Y_FACTOR_R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - horizontal sampling factor of c3"] - #[inline(always)] - pub fn x_factor(&self) -> X_FACTOR_R { - X_FACTOR_R::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:23 - the identifier of c3"] - #[inline(always)] - pub fn id(&self) -> ID_R { - ID_R::new(((self.bits >> 16) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("C3") - .field( - "dqt_tbl_sel", - &format_args!("{}", self.dqt_tbl_sel().bits()), - ) - .field("y_factor", &format_args!("{}", self.y_factor().bits())) - .field("x_factor", &format_args!("{}", self.x_factor().bits())) - .field("id", &format_args!("{}", self.id().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - choose c3 quntization table id (TBD)"] - #[inline(always)] - #[must_use] - pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { - DQT_TBL_SEL_W::new(self, 0) - } - #[doc = "Bits 8:11 - vertical sampling factor of c3"] - #[inline(always)] - #[must_use] - pub fn y_factor(&mut self) -> Y_FACTOR_W { - Y_FACTOR_W::new(self, 8) - } - #[doc = "Bits 12:15 - horizontal sampling factor of c3"] - #[inline(always)] - #[must_use] - pub fn x_factor(&mut self) -> X_FACTOR_W { - X_FACTOR_W::new(self, 12) - } - #[doc = "Bits 16:23 - the identifier of c3"] - #[inline(always)] - #[must_use] - pub fn id(&mut self) -> ID_W { - ID_W::new(self, 16) - } -} -#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct C3_SPEC; -impl crate::RegisterSpec for C3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`c3::R`](R) reader structure"] -impl crate::Readable for C3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`c3::W`](W) writer structure"] -impl crate::Writable for C3_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets C3 to value 0x1100"] -impl crate::Resettable for C3_SPEC { - const RESET_VALUE: u32 = 0x1100; -} diff --git a/esp32p4/src/jpeg/int_clr.rs b/esp32p4/src/jpeg/int_clr.rs index 67026175fc..d237849f70 100644 --- a/esp32p4/src/jpeg/int_clr.rs +++ b/esp32p4/src/jpeg/int_clr.rs @@ -1,55 +1,55 @@ #[doc = "Register `INT_CLR` writer"] pub type W = crate::W; -#[doc = "Field `DONE_INT_CLR` writer - This clear interrupt bit turns to high level when JPEG finishes encoding a picture.."] -pub type DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RLE_PARALLEL_ERR_INT_CLR` writer - The clear interrupt bit to sign that rle parallel error when decoding."] -pub type RLE_PARALLEL_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan id check with component fails when decoding."] -pub type CID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DHT_DC_ID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] -pub type C_DHT_DC_ID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DHT_AC_ID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] -pub type C_DHT_AC_ID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DQT_ID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] -pub type C_DQT_ID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_UXP_ERR_INT_CLR` writer - The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] -pub type RST_UXP_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_CHECK_NONE_ERR_INT_CLR` writer - The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] -pub type RST_CHECK_NONE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_CHECK_POS_ERR_INT_CLR` writer - The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] -pub type RST_CHECK_POS_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `OUT_EOF_INT_CLR` writer - The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] -pub type OUT_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SR_COLOR_MODE_ERR_INT_CLR` writer - The clear interrupt bit to sign that the selected source color mode is not supported."] -pub type SR_COLOR_MODE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DCT_DONE_INT_CLR` writer - The clear interrupt bit to sign that one dct calculation is finished."] -pub type DCT_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BS_LAST_BLOCK_EOF_INT_CLR` writer - The clear interrupt bit to sign that the coding process for last block is finished."] -pub type BS_LAST_BLOCK_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_CLR` writer - The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] -pub type SCAN_CHECK_NONE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCAN_CHECK_POS_ERR_INT_CLR` writer - The clear interrupt bit to sign that SOS header marker position wrong when decoding."] -pub type SCAN_CHECK_POS_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UXP_DET_INT_CLR` writer - The clear interrupt bit to sign that unsupported header marker is detected when decoding."] -pub type UXP_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EN_FRAME_EOF_ERR_INT_CLR` writer - The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] -pub type EN_FRAME_EOF_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EN_FRAME_EOF_LACK_INT_CLR` writer - The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] -pub type EN_FRAME_EOF_LACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DE_FRAME_EOF_ERR_INT_CLR` writer - The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding."] -pub type DE_FRAME_EOF_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DE_FRAME_EOF_LACK_INT_CLR` writer - The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] -pub type DE_FRAME_EOF_LACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SOS_UNMATCH_ERR_INT_CLR` writer - The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] -pub type SOS_UNMATCH_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MARKER_ERR_FST_SCAN_INT_CLR` writer - The clear interrupt bit to sign that the first scan has header marker error when decoding."] -pub type MARKER_ERR_FST_SCAN_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_CLR` writer - The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] -pub type MARKER_ERR_OTHER_SCAN_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UNDET_INT_CLR` writer - The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] -pub type UNDET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DECODE_TIMEOUT_INT_CLR` writer - The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] -pub type DECODE_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE` writer - This clear interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RLE_PARALLEL_ERR` writer - The clear interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CID_ERR` writer - The clear interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `C_DHT_DC_ID_ERR` writer - The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `C_DHT_AC_ID_ERR` writer - The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `C_DQT_ID_ERR` writer - The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RST_UXP_ERR` writer - The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RST_CHECK_NONE_ERR` writer - The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RST_CHECK_POS_ERR` writer - The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_EOF` writer - The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SR_COLOR_MODE_ERR` writer - The clear interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DCT_DONE` writer - The clear interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BS_LAST_BLOCK_EOF` writer - The clear interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SCAN_CHECK_NONE_ERR` writer - The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SCAN_CHECK_POS_ERR` writer - The clear interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `UXP_DET` writer - The clear interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_ERR` writer - The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_LACK` writer - The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_ERR` writer - The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_LACK` writer - The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SOS_UNMATCH_ERR` writer - The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `MARKER_ERR_FST_SCAN` writer - The clear interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `MARKER_ERR_OTHER_SCAN` writer - The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `UNDET` writer - The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DECODE_TIMEOUT` writer - The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -60,154 +60,152 @@ impl W { #[doc = "Bit 0 - This clear interrupt bit turns to high level when JPEG finishes encoding a picture.."] #[inline(always)] #[must_use] - pub fn done_int_clr(&mut self) -> DONE_INT_CLR_W { - DONE_INT_CLR_W::new(self, 0) + pub fn done(&mut self) -> DONE_W { + DONE_W::new(self, 0) } #[doc = "Bit 1 - The clear interrupt bit to sign that rle parallel error when decoding."] #[inline(always)] #[must_use] - pub fn rle_parallel_err_int_clr(&mut self) -> RLE_PARALLEL_ERR_INT_CLR_W { - RLE_PARALLEL_ERR_INT_CLR_W::new(self, 1) + pub fn rle_parallel_err(&mut self) -> RLE_PARALLEL_ERR_W { + RLE_PARALLEL_ERR_W::new(self, 1) } #[doc = "Bit 2 - The clear interrupt bit to sign that scan id check with component fails when decoding."] #[inline(always)] #[must_use] - pub fn cid_err_int_clr(&mut self) -> CID_ERR_INT_CLR_W { - CID_ERR_INT_CLR_W::new(self, 2) + pub fn cid_err(&mut self) -> CID_ERR_W { + CID_ERR_W::new(self, 2) } #[doc = "Bit 3 - The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dht_dc_id_err_int_clr(&mut self) -> C_DHT_DC_ID_ERR_INT_CLR_W { - C_DHT_DC_ID_ERR_INT_CLR_W::new(self, 3) + pub fn c_dht_dc_id_err(&mut self) -> C_DHT_DC_ID_ERR_W { + C_DHT_DC_ID_ERR_W::new(self, 3) } #[doc = "Bit 4 - The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dht_ac_id_err_int_clr(&mut self) -> C_DHT_AC_ID_ERR_INT_CLR_W { - C_DHT_AC_ID_ERR_INT_CLR_W::new(self, 4) + pub fn c_dht_ac_id_err(&mut self) -> C_DHT_AC_ID_ERR_W { + C_DHT_AC_ID_ERR_W::new(self, 4) } #[doc = "Bit 5 - The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dqt_id_err_int_clr(&mut self) -> C_DQT_ID_ERR_INT_CLR_W { - C_DQT_ID_ERR_INT_CLR_W::new(self, 5) + pub fn c_dqt_id_err(&mut self) -> C_DQT_ID_ERR_W { + C_DQT_ID_ERR_W::new(self, 5) } #[doc = "Bit 6 - The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] #[inline(always)] #[must_use] - pub fn rst_uxp_err_int_clr(&mut self) -> RST_UXP_ERR_INT_CLR_W { - RST_UXP_ERR_INT_CLR_W::new(self, 6) + pub fn rst_uxp_err(&mut self) -> RST_UXP_ERR_W { + RST_UXP_ERR_W::new(self, 6) } #[doc = "Bit 7 - The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] #[inline(always)] #[must_use] - pub fn rst_check_none_err_int_clr(&mut self) -> RST_CHECK_NONE_ERR_INT_CLR_W { - RST_CHECK_NONE_ERR_INT_CLR_W::new(self, 7) + pub fn rst_check_none_err(&mut self) -> RST_CHECK_NONE_ERR_W { + RST_CHECK_NONE_ERR_W::new(self, 7) } #[doc = "Bit 8 - The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] #[inline(always)] #[must_use] - pub fn rst_check_pos_err_int_clr(&mut self) -> RST_CHECK_POS_ERR_INT_CLR_W { - RST_CHECK_POS_ERR_INT_CLR_W::new(self, 8) + pub fn rst_check_pos_err(&mut self) -> RST_CHECK_POS_ERR_W { + RST_CHECK_POS_ERR_W::new(self, 8) } #[doc = "Bit 9 - The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] #[inline(always)] #[must_use] - pub fn out_eof_int_clr(&mut self) -> OUT_EOF_INT_CLR_W { - OUT_EOF_INT_CLR_W::new(self, 9) + pub fn out_eof(&mut self) -> OUT_EOF_W { + OUT_EOF_W::new(self, 9) } #[doc = "Bit 10 - The clear interrupt bit to sign that the selected source color mode is not supported."] #[inline(always)] #[must_use] - pub fn sr_color_mode_err_int_clr(&mut self) -> SR_COLOR_MODE_ERR_INT_CLR_W { - SR_COLOR_MODE_ERR_INT_CLR_W::new(self, 10) + pub fn sr_color_mode_err(&mut self) -> SR_COLOR_MODE_ERR_W { + SR_COLOR_MODE_ERR_W::new(self, 10) } #[doc = "Bit 11 - The clear interrupt bit to sign that one dct calculation is finished."] #[inline(always)] #[must_use] - pub fn dct_done_int_clr(&mut self) -> DCT_DONE_INT_CLR_W { - DCT_DONE_INT_CLR_W::new(self, 11) + pub fn dct_done(&mut self) -> DCT_DONE_W { + DCT_DONE_W::new(self, 11) } #[doc = "Bit 12 - The clear interrupt bit to sign that the coding process for last block is finished."] #[inline(always)] #[must_use] - pub fn bs_last_block_eof_int_clr(&mut self) -> BS_LAST_BLOCK_EOF_INT_CLR_W { - BS_LAST_BLOCK_EOF_INT_CLR_W::new(self, 12) + pub fn bs_last_block_eof(&mut self) -> BS_LAST_BLOCK_EOF_W { + BS_LAST_BLOCK_EOF_W::new(self, 12) } #[doc = "Bit 13 - The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] #[inline(always)] #[must_use] - pub fn scan_check_none_err_int_clr(&mut self) -> SCAN_CHECK_NONE_ERR_INT_CLR_W { - SCAN_CHECK_NONE_ERR_INT_CLR_W::new(self, 13) + pub fn scan_check_none_err(&mut self) -> SCAN_CHECK_NONE_ERR_W { + SCAN_CHECK_NONE_ERR_W::new(self, 13) } #[doc = "Bit 14 - The clear interrupt bit to sign that SOS header marker position wrong when decoding."] #[inline(always)] #[must_use] - pub fn scan_check_pos_err_int_clr(&mut self) -> SCAN_CHECK_POS_ERR_INT_CLR_W { - SCAN_CHECK_POS_ERR_INT_CLR_W::new(self, 14) + pub fn scan_check_pos_err(&mut self) -> SCAN_CHECK_POS_ERR_W { + SCAN_CHECK_POS_ERR_W::new(self, 14) } #[doc = "Bit 15 - The clear interrupt bit to sign that unsupported header marker is detected when decoding."] #[inline(always)] #[must_use] - pub fn uxp_det_int_clr(&mut self) -> UXP_DET_INT_CLR_W { - UXP_DET_INT_CLR_W::new(self, 15) + pub fn uxp_det(&mut self) -> UXP_DET_W { + UXP_DET_W::new(self, 15) } #[doc = "Bit 16 - The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] #[inline(always)] #[must_use] - pub fn en_frame_eof_err_int_clr(&mut self) -> EN_FRAME_EOF_ERR_INT_CLR_W { - EN_FRAME_EOF_ERR_INT_CLR_W::new(self, 16) + pub fn en_frame_eof_err(&mut self) -> EN_FRAME_EOF_ERR_W { + EN_FRAME_EOF_ERR_W::new(self, 16) } #[doc = "Bit 17 - The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] #[inline(always)] #[must_use] - pub fn en_frame_eof_lack_int_clr(&mut self) -> EN_FRAME_EOF_LACK_INT_CLR_W { - EN_FRAME_EOF_LACK_INT_CLR_W::new(self, 17) + pub fn en_frame_eof_lack(&mut self) -> EN_FRAME_EOF_LACK_W { + EN_FRAME_EOF_LACK_W::new(self, 17) } #[doc = "Bit 18 - The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding."] #[inline(always)] #[must_use] - pub fn de_frame_eof_err_int_clr(&mut self) -> DE_FRAME_EOF_ERR_INT_CLR_W { - DE_FRAME_EOF_ERR_INT_CLR_W::new(self, 18) + pub fn de_frame_eof_err(&mut self) -> DE_FRAME_EOF_ERR_W { + DE_FRAME_EOF_ERR_W::new(self, 18) } #[doc = "Bit 19 - The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] #[inline(always)] #[must_use] - pub fn de_frame_eof_lack_int_clr(&mut self) -> DE_FRAME_EOF_LACK_INT_CLR_W { - DE_FRAME_EOF_LACK_INT_CLR_W::new(self, 19) + pub fn de_frame_eof_lack(&mut self) -> DE_FRAME_EOF_LACK_W { + DE_FRAME_EOF_LACK_W::new(self, 19) } #[doc = "Bit 20 - The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] #[inline(always)] #[must_use] - pub fn sos_unmatch_err_int_clr(&mut self) -> SOS_UNMATCH_ERR_INT_CLR_W { - SOS_UNMATCH_ERR_INT_CLR_W::new(self, 20) + pub fn sos_unmatch_err(&mut self) -> SOS_UNMATCH_ERR_W { + SOS_UNMATCH_ERR_W::new(self, 20) } #[doc = "Bit 21 - The clear interrupt bit to sign that the first scan has header marker error when decoding."] #[inline(always)] #[must_use] - pub fn marker_err_fst_scan_int_clr(&mut self) -> MARKER_ERR_FST_SCAN_INT_CLR_W { - MARKER_ERR_FST_SCAN_INT_CLR_W::new(self, 21) + pub fn marker_err_fst_scan(&mut self) -> MARKER_ERR_FST_SCAN_W { + MARKER_ERR_FST_SCAN_W::new(self, 21) } #[doc = "Bit 22 - The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] #[inline(always)] #[must_use] - pub fn marker_err_other_scan_int_clr( - &mut self, - ) -> MARKER_ERR_OTHER_SCAN_INT_CLR_W { - MARKER_ERR_OTHER_SCAN_INT_CLR_W::new(self, 22) + pub fn marker_err_other_scan(&mut self) -> MARKER_ERR_OTHER_SCAN_W { + MARKER_ERR_OTHER_SCAN_W::new(self, 22) } #[doc = "Bit 23 - The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] #[inline(always)] #[must_use] - pub fn undet_int_clr(&mut self) -> UNDET_INT_CLR_W { - UNDET_INT_CLR_W::new(self, 23) + pub fn undet(&mut self) -> UNDET_W { + UNDET_W::new(self, 23) } #[doc = "Bit 24 - The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] #[inline(always)] #[must_use] - pub fn decode_timeout_int_clr(&mut self) -> DECODE_TIMEOUT_INT_CLR_W { - DECODE_TIMEOUT_INT_CLR_W::new(self, 24) + pub fn decode_timeout(&mut self) -> DECODE_TIMEOUT_W { + DECODE_TIMEOUT_W::new(self, 24) } } #[doc = "Interrupt clear registers\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -219,7 +217,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC { impl crate::Writable for INT_CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff_ffff; } #[doc = "`reset()` method sets INT_CLR to value 0"] impl crate::Resettable for INT_CLR_SPEC { diff --git a/esp32p4/src/jpeg/int_ena.rs b/esp32p4/src/jpeg/int_ena.rs index a7b3c4ecca..6da6f4a8c7 100644 --- a/esp32p4/src/jpeg/int_ena.rs +++ b/esp32p4/src/jpeg/int_ena.rs @@ -2,336 +2,315 @@ pub type R = crate::R; #[doc = "Register `INT_ENA` writer"] pub type W = crate::W; -#[doc = "Field `DONE_INT_ENA` reader - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] -pub type DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `DONE_INT_ENA` writer - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] -pub type DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RLE_PARALLEL_ERR_INT_ENA` reader - The enable interrupt bit to sign that rle parallel error when decoding."] -pub type RLE_PARALLEL_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `RLE_PARALLEL_ERR_INT_ENA` writer - The enable interrupt bit to sign that rle parallel error when decoding."] -pub type RLE_PARALLEL_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan id check with component fails when decoding."] -pub type CID_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `CID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan id check with component fails when decoding."] -pub type CID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DHT_DC_ID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] -pub type C_DHT_DC_ID_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `C_DHT_DC_ID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] -pub type C_DHT_DC_ID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DHT_AC_ID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] -pub type C_DHT_AC_ID_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `C_DHT_AC_ID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] -pub type C_DHT_AC_ID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DQT_ID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] -pub type C_DQT_ID_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `C_DQT_ID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] -pub type C_DQT_ID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_UXP_ERR_INT_ENA` reader - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] -pub type RST_UXP_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `RST_UXP_ERR_INT_ENA` writer - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] -pub type RST_UXP_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_CHECK_NONE_ERR_INT_ENA` reader - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] -pub type RST_CHECK_NONE_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `RST_CHECK_NONE_ERR_INT_ENA` writer - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] -pub type RST_CHECK_NONE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_CHECK_POS_ERR_INT_ENA` reader - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] -pub type RST_CHECK_POS_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `RST_CHECK_POS_ERR_INT_ENA` writer - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] -pub type RST_CHECK_POS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `OUT_EOF_INT_ENA` reader - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] -pub type OUT_EOF_INT_ENA_R = crate::BitReader; -#[doc = "Field `OUT_EOF_INT_ENA` writer - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] -pub type OUT_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SR_COLOR_MODE_ERR_INT_ENA` reader - The enable interrupt bit to sign that the selected source color mode is not supported."] -pub type SR_COLOR_MODE_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `SR_COLOR_MODE_ERR_INT_ENA` writer - The enable interrupt bit to sign that the selected source color mode is not supported."] -pub type SR_COLOR_MODE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DCT_DONE_INT_ENA` reader - The enable interrupt bit to sign that one dct calculation is finished."] -pub type DCT_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `DCT_DONE_INT_ENA` writer - The enable interrupt bit to sign that one dct calculation is finished."] -pub type DCT_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BS_LAST_BLOCK_EOF_INT_ENA` reader - The enable interrupt bit to sign that the coding process for last block is finished."] -pub type BS_LAST_BLOCK_EOF_INT_ENA_R = crate::BitReader; -#[doc = "Field `BS_LAST_BLOCK_EOF_INT_ENA` writer - The enable interrupt bit to sign that the coding process for last block is finished."] -pub type BS_LAST_BLOCK_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_ENA` reader - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] -pub type SCAN_CHECK_NONE_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_ENA` writer - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] -pub type SCAN_CHECK_NONE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCAN_CHECK_POS_ERR_INT_ENA` reader - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] -pub type SCAN_CHECK_POS_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `SCAN_CHECK_POS_ERR_INT_ENA` writer - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] -pub type SCAN_CHECK_POS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UXP_DET_INT_ENA` reader - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] -pub type UXP_DET_INT_ENA_R = crate::BitReader; -#[doc = "Field `UXP_DET_INT_ENA` writer - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] -pub type UXP_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EN_FRAME_EOF_ERR_INT_ENA` reader - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] -pub type EN_FRAME_EOF_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `EN_FRAME_EOF_ERR_INT_ENA` writer - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] -pub type EN_FRAME_EOF_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EN_FRAME_EOF_LACK_INT_ENA` reader - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] -pub type EN_FRAME_EOF_LACK_INT_ENA_R = crate::BitReader; -#[doc = "Field `EN_FRAME_EOF_LACK_INT_ENA` writer - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] -pub type EN_FRAME_EOF_LACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DE_FRAME_EOF_ERR_INT_ENA` reader - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] -pub type DE_FRAME_EOF_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `DE_FRAME_EOF_ERR_INT_ENA` writer - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] -pub type DE_FRAME_EOF_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DE_FRAME_EOF_LACK_INT_ENA` reader - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] -pub type DE_FRAME_EOF_LACK_INT_ENA_R = crate::BitReader; -#[doc = "Field `DE_FRAME_EOF_LACK_INT_ENA` writer - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] -pub type DE_FRAME_EOF_LACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SOS_UNMATCH_ERR_INT_ENA` reader - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] -pub type SOS_UNMATCH_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `SOS_UNMATCH_ERR_INT_ENA` writer - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] -pub type SOS_UNMATCH_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MARKER_ERR_FST_SCAN_INT_ENA` reader - The enable interrupt bit to sign that the first scan has header marker error when decoding."] -pub type MARKER_ERR_FST_SCAN_INT_ENA_R = crate::BitReader; -#[doc = "Field `MARKER_ERR_FST_SCAN_INT_ENA` writer - The enable interrupt bit to sign that the first scan has header marker error when decoding."] -pub type MARKER_ERR_FST_SCAN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_ENA` reader - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] -pub type MARKER_ERR_OTHER_SCAN_INT_ENA_R = crate::BitReader; -#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_ENA` writer - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] -pub type MARKER_ERR_OTHER_SCAN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UNDET_INT_ENA` reader - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] -pub type UNDET_INT_ENA_R = crate::BitReader; -#[doc = "Field `UNDET_INT_ENA` writer - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] -pub type UNDET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DECODE_TIMEOUT_INT_ENA` reader - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] -pub type DECODE_TIMEOUT_INT_ENA_R = crate::BitReader; -#[doc = "Field `DECODE_TIMEOUT_INT_ENA` writer - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] -pub type DECODE_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE` reader - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RLE_PARALLEL_ERR` reader - The enable interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_R = crate::BitReader; +#[doc = "Field `RLE_PARALLEL_ERR` writer - The enable interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CID_ERR` reader - The enable interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_R = crate::BitReader; +#[doc = "Field `CID_ERR` writer - The enable interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_DC_ID_ERR` reader - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DHT_DC_ID_ERR` writer - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_AC_ID_ERR` reader - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DHT_AC_ID_ERR` writer - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DQT_ID_ERR` reader - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DQT_ID_ERR` writer - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_UXP_ERR` reader - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_R = crate::BitReader; +#[doc = "Field `RST_UXP_ERR` writer - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_NONE_ERR` reader - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_R = crate::BitReader; +#[doc = "Field `RST_CHECK_NONE_ERR` writer - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_POS_ERR` reader - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_R = crate::BitReader; +#[doc = "Field `RST_CHECK_POS_ERR` writer - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF` reader - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_COLOR_MODE_ERR` reader - The enable interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_R = crate::BitReader; +#[doc = "Field `SR_COLOR_MODE_ERR` writer - The enable interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCT_DONE` reader - The enable interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_R = crate::BitReader; +#[doc = "Field `DCT_DONE` writer - The enable interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BS_LAST_BLOCK_EOF` reader - The enable interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_R = crate::BitReader; +#[doc = "Field `BS_LAST_BLOCK_EOF` writer - The enable interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_NONE_ERR` reader - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_NONE_ERR` writer - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_POS_ERR` reader - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_POS_ERR` writer - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UXP_DET` reader - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_R = crate::BitReader; +#[doc = "Field `UXP_DET` writer - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_ERR` reader - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_ERR` writer - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_LACK` reader - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_LACK` writer - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_ERR` reader - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_ERR` writer - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_LACK` reader - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_LACK` writer - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOS_UNMATCH_ERR` reader - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_R = crate::BitReader; +#[doc = "Field `SOS_UNMATCH_ERR` writer - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_FST_SCAN` reader - The enable interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_FST_SCAN` writer - The enable interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_OTHER_SCAN` reader - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_OTHER_SCAN` writer - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNDET` reader - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_R = crate::BitReader; +#[doc = "Field `UNDET` writer - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DECODE_TIMEOUT` reader - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_R = crate::BitReader; +#[doc = "Field `DECODE_TIMEOUT` writer - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] #[inline(always)] - pub fn done_int_ena(&self) -> DONE_INT_ENA_R { - DONE_INT_ENA_R::new((self.bits & 1) != 0) + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The enable interrupt bit to sign that rle parallel error when decoding."] #[inline(always)] - pub fn rle_parallel_err_int_ena(&self) -> RLE_PARALLEL_ERR_INT_ENA_R { - RLE_PARALLEL_ERR_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn rle_parallel_err(&self) -> RLE_PARALLEL_ERR_R { + RLE_PARALLEL_ERR_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The enable interrupt bit to sign that scan id check with component fails when decoding."] #[inline(always)] - pub fn cid_err_int_ena(&self) -> CID_ERR_INT_ENA_R { - CID_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn cid_err(&self) -> CID_ERR_R { + CID_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] #[inline(always)] - pub fn c_dht_dc_id_err_int_ena(&self) -> C_DHT_DC_ID_ERR_INT_ENA_R { - C_DHT_DC_ID_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn c_dht_dc_id_err(&self) -> C_DHT_DC_ID_ERR_R { + C_DHT_DC_ID_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] #[inline(always)] - pub fn c_dht_ac_id_err_int_ena(&self) -> C_DHT_AC_ID_ERR_INT_ENA_R { - C_DHT_AC_ID_ERR_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn c_dht_ac_id_err(&self) -> C_DHT_AC_ID_ERR_R { + C_DHT_AC_ID_ERR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] #[inline(always)] - pub fn c_dqt_id_err_int_ena(&self) -> C_DQT_ID_ERR_INT_ENA_R { - C_DQT_ID_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn c_dqt_id_err(&self) -> C_DQT_ID_ERR_R { + C_DQT_ID_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] #[inline(always)] - pub fn rst_uxp_err_int_ena(&self) -> RST_UXP_ERR_INT_ENA_R { - RST_UXP_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn rst_uxp_err(&self) -> RST_UXP_ERR_R { + RST_UXP_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] #[inline(always)] - pub fn rst_check_none_err_int_ena(&self) -> RST_CHECK_NONE_ERR_INT_ENA_R { - RST_CHECK_NONE_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn rst_check_none_err(&self) -> RST_CHECK_NONE_ERR_R { + RST_CHECK_NONE_ERR_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] #[inline(always)] - pub fn rst_check_pos_err_int_ena(&self) -> RST_CHECK_POS_ERR_INT_ENA_R { - RST_CHECK_POS_ERR_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn rst_check_pos_err(&self) -> RST_CHECK_POS_ERR_R { + RST_CHECK_POS_ERR_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] #[inline(always)] - pub fn out_eof_int_ena(&self) -> OUT_EOF_INT_ENA_R { - OUT_EOF_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The enable interrupt bit to sign that the selected source color mode is not supported."] #[inline(always)] - pub fn sr_color_mode_err_int_ena(&self) -> SR_COLOR_MODE_ERR_INT_ENA_R { - SR_COLOR_MODE_ERR_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn sr_color_mode_err(&self) -> SR_COLOR_MODE_ERR_R { + SR_COLOR_MODE_ERR_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The enable interrupt bit to sign that one dct calculation is finished."] #[inline(always)] - pub fn dct_done_int_ena(&self) -> DCT_DONE_INT_ENA_R { - DCT_DONE_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn dct_done(&self) -> DCT_DONE_R { + DCT_DONE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The enable interrupt bit to sign that the coding process for last block is finished."] #[inline(always)] - pub fn bs_last_block_eof_int_ena(&self) -> BS_LAST_BLOCK_EOF_INT_ENA_R { - BS_LAST_BLOCK_EOF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn bs_last_block_eof(&self) -> BS_LAST_BLOCK_EOF_R { + BS_LAST_BLOCK_EOF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] #[inline(always)] - pub fn scan_check_none_err_int_ena(&self) -> SCAN_CHECK_NONE_ERR_INT_ENA_R { - SCAN_CHECK_NONE_ERR_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + pub fn scan_check_none_err(&self) -> SCAN_CHECK_NONE_ERR_R { + SCAN_CHECK_NONE_ERR_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] #[inline(always)] - pub fn scan_check_pos_err_int_ena(&self) -> SCAN_CHECK_POS_ERR_INT_ENA_R { - SCAN_CHECK_POS_ERR_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + pub fn scan_check_pos_err(&self) -> SCAN_CHECK_POS_ERR_R { + SCAN_CHECK_POS_ERR_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] #[inline(always)] - pub fn uxp_det_int_ena(&self) -> UXP_DET_INT_ENA_R { - UXP_DET_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + pub fn uxp_det(&self) -> UXP_DET_R { + UXP_DET_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] #[inline(always)] - pub fn en_frame_eof_err_int_ena(&self) -> EN_FRAME_EOF_ERR_INT_ENA_R { - EN_FRAME_EOF_ERR_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + pub fn en_frame_eof_err(&self) -> EN_FRAME_EOF_ERR_R { + EN_FRAME_EOF_ERR_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] #[inline(always)] - pub fn en_frame_eof_lack_int_ena(&self) -> EN_FRAME_EOF_LACK_INT_ENA_R { - EN_FRAME_EOF_LACK_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + pub fn en_frame_eof_lack(&self) -> EN_FRAME_EOF_LACK_R { + EN_FRAME_EOF_LACK_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] #[inline(always)] - pub fn de_frame_eof_err_int_ena(&self) -> DE_FRAME_EOF_ERR_INT_ENA_R { - DE_FRAME_EOF_ERR_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + pub fn de_frame_eof_err(&self) -> DE_FRAME_EOF_ERR_R { + DE_FRAME_EOF_ERR_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] #[inline(always)] - pub fn de_frame_eof_lack_int_ena(&self) -> DE_FRAME_EOF_LACK_INT_ENA_R { - DE_FRAME_EOF_LACK_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + pub fn de_frame_eof_lack(&self) -> DE_FRAME_EOF_LACK_R { + DE_FRAME_EOF_LACK_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 20 - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] #[inline(always)] - pub fn sos_unmatch_err_int_ena(&self) -> SOS_UNMATCH_ERR_INT_ENA_R { - SOS_UNMATCH_ERR_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + pub fn sos_unmatch_err(&self) -> SOS_UNMATCH_ERR_R { + SOS_UNMATCH_ERR_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - The enable interrupt bit to sign that the first scan has header marker error when decoding."] #[inline(always)] - pub fn marker_err_fst_scan_int_ena(&self) -> MARKER_ERR_FST_SCAN_INT_ENA_R { - MARKER_ERR_FST_SCAN_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + pub fn marker_err_fst_scan(&self) -> MARKER_ERR_FST_SCAN_R { + MARKER_ERR_FST_SCAN_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] #[inline(always)] - pub fn marker_err_other_scan_int_ena(&self) -> MARKER_ERR_OTHER_SCAN_INT_ENA_R { - MARKER_ERR_OTHER_SCAN_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + pub fn marker_err_other_scan(&self) -> MARKER_ERR_OTHER_SCAN_R { + MARKER_ERR_OTHER_SCAN_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] #[inline(always)] - pub fn undet_int_ena(&self) -> UNDET_INT_ENA_R { - UNDET_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + pub fn undet(&self) -> UNDET_R { + UNDET_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] #[inline(always)] - pub fn decode_timeout_int_ena(&self) -> DECODE_TIMEOUT_INT_ENA_R { - DECODE_TIMEOUT_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + pub fn decode_timeout(&self) -> DECODE_TIMEOUT_R { + DECODE_TIMEOUT_R::new(((self.bits >> 24) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ENA") + .field("done", &format_args!("{}", self.done().bit())) .field( - "done_int_ena", - &format_args!("{}", self.done_int_ena().bit()), + "rle_parallel_err", + &format_args!("{}", self.rle_parallel_err().bit()), ) + .field("cid_err", &format_args!("{}", self.cid_err().bit())) .field( - "rle_parallel_err_int_ena", - &format_args!("{}", self.rle_parallel_err_int_ena().bit()), + "c_dht_dc_id_err", + &format_args!("{}", self.c_dht_dc_id_err().bit()), ) .field( - "cid_err_int_ena", - &format_args!("{}", self.cid_err_int_ena().bit()), + "c_dht_ac_id_err", + &format_args!("{}", self.c_dht_ac_id_err().bit()), ) .field( - "c_dht_dc_id_err_int_ena", - &format_args!("{}", self.c_dht_dc_id_err_int_ena().bit()), + "c_dqt_id_err", + &format_args!("{}", self.c_dqt_id_err().bit()), ) + .field("rst_uxp_err", &format_args!("{}", self.rst_uxp_err().bit())) .field( - "c_dht_ac_id_err_int_ena", - &format_args!("{}", self.c_dht_ac_id_err_int_ena().bit()), + "rst_check_none_err", + &format_args!("{}", self.rst_check_none_err().bit()), ) .field( - "c_dqt_id_err_int_ena", - &format_args!("{}", self.c_dqt_id_err_int_ena().bit()), + "rst_check_pos_err", + &format_args!("{}", self.rst_check_pos_err().bit()), ) + .field("out_eof", &format_args!("{}", self.out_eof().bit())) .field( - "rst_uxp_err_int_ena", - &format_args!("{}", self.rst_uxp_err_int_ena().bit()), + "sr_color_mode_err", + &format_args!("{}", self.sr_color_mode_err().bit()), ) + .field("dct_done", &format_args!("{}", self.dct_done().bit())) .field( - "rst_check_none_err_int_ena", - &format_args!("{}", self.rst_check_none_err_int_ena().bit()), + "bs_last_block_eof", + &format_args!("{}", self.bs_last_block_eof().bit()), ) .field( - "rst_check_pos_err_int_ena", - &format_args!("{}", self.rst_check_pos_err_int_ena().bit()), + "scan_check_none_err", + &format_args!("{}", self.scan_check_none_err().bit()), ) .field( - "out_eof_int_ena", - &format_args!("{}", self.out_eof_int_ena().bit()), + "scan_check_pos_err", + &format_args!("{}", self.scan_check_pos_err().bit()), ) + .field("uxp_det", &format_args!("{}", self.uxp_det().bit())) .field( - "sr_color_mode_err_int_ena", - &format_args!("{}", self.sr_color_mode_err_int_ena().bit()), + "en_frame_eof_err", + &format_args!("{}", self.en_frame_eof_err().bit()), ) .field( - "dct_done_int_ena", - &format_args!("{}", self.dct_done_int_ena().bit()), + "en_frame_eof_lack", + &format_args!("{}", self.en_frame_eof_lack().bit()), ) .field( - "bs_last_block_eof_int_ena", - &format_args!("{}", self.bs_last_block_eof_int_ena().bit()), + "de_frame_eof_err", + &format_args!("{}", self.de_frame_eof_err().bit()), ) .field( - "scan_check_none_err_int_ena", - &format_args!("{}", self.scan_check_none_err_int_ena().bit()), + "de_frame_eof_lack", + &format_args!("{}", self.de_frame_eof_lack().bit()), ) .field( - "scan_check_pos_err_int_ena", - &format_args!("{}", self.scan_check_pos_err_int_ena().bit()), + "sos_unmatch_err", + &format_args!("{}", self.sos_unmatch_err().bit()), ) .field( - "uxp_det_int_ena", - &format_args!("{}", self.uxp_det_int_ena().bit()), + "marker_err_fst_scan", + &format_args!("{}", self.marker_err_fst_scan().bit()), ) .field( - "en_frame_eof_err_int_ena", - &format_args!("{}", self.en_frame_eof_err_int_ena().bit()), + "marker_err_other_scan", + &format_args!("{}", self.marker_err_other_scan().bit()), ) + .field("undet", &format_args!("{}", self.undet().bit())) .field( - "en_frame_eof_lack_int_ena", - &format_args!("{}", self.en_frame_eof_lack_int_ena().bit()), - ) - .field( - "de_frame_eof_err_int_ena", - &format_args!("{}", self.de_frame_eof_err_int_ena().bit()), - ) - .field( - "de_frame_eof_lack_int_ena", - &format_args!("{}", self.de_frame_eof_lack_int_ena().bit()), - ) - .field( - "sos_unmatch_err_int_ena", - &format_args!("{}", self.sos_unmatch_err_int_ena().bit()), - ) - .field( - "marker_err_fst_scan_int_ena", - &format_args!("{}", self.marker_err_fst_scan_int_ena().bit()), - ) - .field( - "marker_err_other_scan_int_ena", - &format_args!("{}", self.marker_err_other_scan_int_ena().bit()), - ) - .field( - "undet_int_ena", - &format_args!("{}", self.undet_int_ena().bit()), - ) - .field( - "decode_timeout_int_ena", - &format_args!("{}", self.decode_timeout_int_ena().bit()), + "decode_timeout", + &format_args!("{}", self.decode_timeout().bit()), ) .finish() } @@ -346,154 +325,152 @@ impl W { #[doc = "Bit 0 - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] #[inline(always)] #[must_use] - pub fn done_int_ena(&mut self) -> DONE_INT_ENA_W { - DONE_INT_ENA_W::new(self, 0) + pub fn done(&mut self) -> DONE_W { + DONE_W::new(self, 0) } #[doc = "Bit 1 - The enable interrupt bit to sign that rle parallel error when decoding."] #[inline(always)] #[must_use] - pub fn rle_parallel_err_int_ena(&mut self) -> RLE_PARALLEL_ERR_INT_ENA_W { - RLE_PARALLEL_ERR_INT_ENA_W::new(self, 1) + pub fn rle_parallel_err(&mut self) -> RLE_PARALLEL_ERR_W { + RLE_PARALLEL_ERR_W::new(self, 1) } #[doc = "Bit 2 - The enable interrupt bit to sign that scan id check with component fails when decoding."] #[inline(always)] #[must_use] - pub fn cid_err_int_ena(&mut self) -> CID_ERR_INT_ENA_W { - CID_ERR_INT_ENA_W::new(self, 2) + pub fn cid_err(&mut self) -> CID_ERR_W { + CID_ERR_W::new(self, 2) } #[doc = "Bit 3 - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dht_dc_id_err_int_ena(&mut self) -> C_DHT_DC_ID_ERR_INT_ENA_W { - C_DHT_DC_ID_ERR_INT_ENA_W::new(self, 3) + pub fn c_dht_dc_id_err(&mut self) -> C_DHT_DC_ID_ERR_W { + C_DHT_DC_ID_ERR_W::new(self, 3) } #[doc = "Bit 4 - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dht_ac_id_err_int_ena(&mut self) -> C_DHT_AC_ID_ERR_INT_ENA_W { - C_DHT_AC_ID_ERR_INT_ENA_W::new(self, 4) + pub fn c_dht_ac_id_err(&mut self) -> C_DHT_AC_ID_ERR_W { + C_DHT_AC_ID_ERR_W::new(self, 4) } #[doc = "Bit 5 - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dqt_id_err_int_ena(&mut self) -> C_DQT_ID_ERR_INT_ENA_W { - C_DQT_ID_ERR_INT_ENA_W::new(self, 5) + pub fn c_dqt_id_err(&mut self) -> C_DQT_ID_ERR_W { + C_DQT_ID_ERR_W::new(self, 5) } #[doc = "Bit 6 - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] #[inline(always)] #[must_use] - pub fn rst_uxp_err_int_ena(&mut self) -> RST_UXP_ERR_INT_ENA_W { - RST_UXP_ERR_INT_ENA_W::new(self, 6) + pub fn rst_uxp_err(&mut self) -> RST_UXP_ERR_W { + RST_UXP_ERR_W::new(self, 6) } #[doc = "Bit 7 - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] #[inline(always)] #[must_use] - pub fn rst_check_none_err_int_ena(&mut self) -> RST_CHECK_NONE_ERR_INT_ENA_W { - RST_CHECK_NONE_ERR_INT_ENA_W::new(self, 7) + pub fn rst_check_none_err(&mut self) -> RST_CHECK_NONE_ERR_W { + RST_CHECK_NONE_ERR_W::new(self, 7) } #[doc = "Bit 8 - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] #[inline(always)] #[must_use] - pub fn rst_check_pos_err_int_ena(&mut self) -> RST_CHECK_POS_ERR_INT_ENA_W { - RST_CHECK_POS_ERR_INT_ENA_W::new(self, 8) + pub fn rst_check_pos_err(&mut self) -> RST_CHECK_POS_ERR_W { + RST_CHECK_POS_ERR_W::new(self, 8) } #[doc = "Bit 9 - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] #[inline(always)] #[must_use] - pub fn out_eof_int_ena(&mut self) -> OUT_EOF_INT_ENA_W { - OUT_EOF_INT_ENA_W::new(self, 9) + pub fn out_eof(&mut self) -> OUT_EOF_W { + OUT_EOF_W::new(self, 9) } #[doc = "Bit 10 - The enable interrupt bit to sign that the selected source color mode is not supported."] #[inline(always)] #[must_use] - pub fn sr_color_mode_err_int_ena(&mut self) -> SR_COLOR_MODE_ERR_INT_ENA_W { - SR_COLOR_MODE_ERR_INT_ENA_W::new(self, 10) + pub fn sr_color_mode_err(&mut self) -> SR_COLOR_MODE_ERR_W { + SR_COLOR_MODE_ERR_W::new(self, 10) } #[doc = "Bit 11 - The enable interrupt bit to sign that one dct calculation is finished."] #[inline(always)] #[must_use] - pub fn dct_done_int_ena(&mut self) -> DCT_DONE_INT_ENA_W { - DCT_DONE_INT_ENA_W::new(self, 11) + pub fn dct_done(&mut self) -> DCT_DONE_W { + DCT_DONE_W::new(self, 11) } #[doc = "Bit 12 - The enable interrupt bit to sign that the coding process for last block is finished."] #[inline(always)] #[must_use] - pub fn bs_last_block_eof_int_ena(&mut self) -> BS_LAST_BLOCK_EOF_INT_ENA_W { - BS_LAST_BLOCK_EOF_INT_ENA_W::new(self, 12) + pub fn bs_last_block_eof(&mut self) -> BS_LAST_BLOCK_EOF_W { + BS_LAST_BLOCK_EOF_W::new(self, 12) } #[doc = "Bit 13 - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] #[inline(always)] #[must_use] - pub fn scan_check_none_err_int_ena(&mut self) -> SCAN_CHECK_NONE_ERR_INT_ENA_W { - SCAN_CHECK_NONE_ERR_INT_ENA_W::new(self, 13) + pub fn scan_check_none_err(&mut self) -> SCAN_CHECK_NONE_ERR_W { + SCAN_CHECK_NONE_ERR_W::new(self, 13) } #[doc = "Bit 14 - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] #[inline(always)] #[must_use] - pub fn scan_check_pos_err_int_ena(&mut self) -> SCAN_CHECK_POS_ERR_INT_ENA_W { - SCAN_CHECK_POS_ERR_INT_ENA_W::new(self, 14) + pub fn scan_check_pos_err(&mut self) -> SCAN_CHECK_POS_ERR_W { + SCAN_CHECK_POS_ERR_W::new(self, 14) } #[doc = "Bit 15 - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] #[inline(always)] #[must_use] - pub fn uxp_det_int_ena(&mut self) -> UXP_DET_INT_ENA_W { - UXP_DET_INT_ENA_W::new(self, 15) + pub fn uxp_det(&mut self) -> UXP_DET_W { + UXP_DET_W::new(self, 15) } #[doc = "Bit 16 - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] #[inline(always)] #[must_use] - pub fn en_frame_eof_err_int_ena(&mut self) -> EN_FRAME_EOF_ERR_INT_ENA_W { - EN_FRAME_EOF_ERR_INT_ENA_W::new(self, 16) + pub fn en_frame_eof_err(&mut self) -> EN_FRAME_EOF_ERR_W { + EN_FRAME_EOF_ERR_W::new(self, 16) } #[doc = "Bit 17 - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] #[inline(always)] #[must_use] - pub fn en_frame_eof_lack_int_ena(&mut self) -> EN_FRAME_EOF_LACK_INT_ENA_W { - EN_FRAME_EOF_LACK_INT_ENA_W::new(self, 17) + pub fn en_frame_eof_lack(&mut self) -> EN_FRAME_EOF_LACK_W { + EN_FRAME_EOF_LACK_W::new(self, 17) } #[doc = "Bit 18 - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] #[inline(always)] #[must_use] - pub fn de_frame_eof_err_int_ena(&mut self) -> DE_FRAME_EOF_ERR_INT_ENA_W { - DE_FRAME_EOF_ERR_INT_ENA_W::new(self, 18) + pub fn de_frame_eof_err(&mut self) -> DE_FRAME_EOF_ERR_W { + DE_FRAME_EOF_ERR_W::new(self, 18) } #[doc = "Bit 19 - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] #[inline(always)] #[must_use] - pub fn de_frame_eof_lack_int_ena(&mut self) -> DE_FRAME_EOF_LACK_INT_ENA_W { - DE_FRAME_EOF_LACK_INT_ENA_W::new(self, 19) + pub fn de_frame_eof_lack(&mut self) -> DE_FRAME_EOF_LACK_W { + DE_FRAME_EOF_LACK_W::new(self, 19) } #[doc = "Bit 20 - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] #[inline(always)] #[must_use] - pub fn sos_unmatch_err_int_ena(&mut self) -> SOS_UNMATCH_ERR_INT_ENA_W { - SOS_UNMATCH_ERR_INT_ENA_W::new(self, 20) + pub fn sos_unmatch_err(&mut self) -> SOS_UNMATCH_ERR_W { + SOS_UNMATCH_ERR_W::new(self, 20) } #[doc = "Bit 21 - The enable interrupt bit to sign that the first scan has header marker error when decoding."] #[inline(always)] #[must_use] - pub fn marker_err_fst_scan_int_ena(&mut self) -> MARKER_ERR_FST_SCAN_INT_ENA_W { - MARKER_ERR_FST_SCAN_INT_ENA_W::new(self, 21) + pub fn marker_err_fst_scan(&mut self) -> MARKER_ERR_FST_SCAN_W { + MARKER_ERR_FST_SCAN_W::new(self, 21) } #[doc = "Bit 22 - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] #[inline(always)] #[must_use] - pub fn marker_err_other_scan_int_ena( - &mut self, - ) -> MARKER_ERR_OTHER_SCAN_INT_ENA_W { - MARKER_ERR_OTHER_SCAN_INT_ENA_W::new(self, 22) + pub fn marker_err_other_scan(&mut self) -> MARKER_ERR_OTHER_SCAN_W { + MARKER_ERR_OTHER_SCAN_W::new(self, 22) } #[doc = "Bit 23 - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] #[inline(always)] #[must_use] - pub fn undet_int_ena(&mut self) -> UNDET_INT_ENA_W { - UNDET_INT_ENA_W::new(self, 23) + pub fn undet(&mut self) -> UNDET_W { + UNDET_W::new(self, 23) } #[doc = "Bit 24 - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] #[inline(always)] #[must_use] - pub fn decode_timeout_int_ena(&mut self) -> DECODE_TIMEOUT_INT_ENA_W { - DECODE_TIMEOUT_INT_ENA_W::new(self, 24) + pub fn decode_timeout(&mut self) -> DECODE_TIMEOUT_W { + DECODE_TIMEOUT_W::new(self, 24) } } #[doc = "Interrupt enable registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/jpeg/int_raw.rs b/esp32p4/src/jpeg/int_raw.rs index d2bab50158..f235a30134 100644 --- a/esp32p4/src/jpeg/int_raw.rs +++ b/esp32p4/src/jpeg/int_raw.rs @@ -2,336 +2,315 @@ pub type R = crate::R; #[doc = "Register `INT_RAW` writer"] pub type W = crate::W; -#[doc = "Field `DONE_INT_RAW` reader - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] -pub type DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `DONE_INT_RAW` writer - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] -pub type DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RLE_PARALLEL_ERR_INT_RAW` reader - The raw interrupt bit to sign that rle parallel error when decoding."] -pub type RLE_PARALLEL_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `RLE_PARALLEL_ERR_INT_RAW` writer - The raw interrupt bit to sign that rle parallel error when decoding."] -pub type RLE_PARALLEL_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan id check with component fails when decoding."] -pub type CID_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `CID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan id check with component fails when decoding."] -pub type CID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DHT_DC_ID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] -pub type C_DHT_DC_ID_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `C_DHT_DC_ID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] -pub type C_DHT_DC_ID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DHT_AC_ID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] -pub type C_DHT_AC_ID_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `C_DHT_AC_ID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] -pub type C_DHT_AC_ID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `C_DQT_ID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] -pub type C_DQT_ID_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `C_DQT_ID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] -pub type C_DQT_ID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_UXP_ERR_INT_RAW` reader - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] -pub type RST_UXP_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `RST_UXP_ERR_INT_RAW` writer - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] -pub type RST_UXP_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_CHECK_NONE_ERR_INT_RAW` reader - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] -pub type RST_CHECK_NONE_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `RST_CHECK_NONE_ERR_INT_RAW` writer - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] -pub type RST_CHECK_NONE_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RST_CHECK_POS_ERR_INT_RAW` reader - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] -pub type RST_CHECK_POS_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `RST_CHECK_POS_ERR_INT_RAW` writer - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] -pub type RST_CHECK_POS_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `OUT_EOF_INT_RAW` reader - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] -pub type OUT_EOF_INT_RAW_R = crate::BitReader; -#[doc = "Field `OUT_EOF_INT_RAW` writer - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] -pub type OUT_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SR_COLOR_MODE_ERR_INT_RAW` reader - The raw interrupt bit to sign that the selected source color mode is not supported."] -pub type SR_COLOR_MODE_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `SR_COLOR_MODE_ERR_INT_RAW` writer - The raw interrupt bit to sign that the selected source color mode is not supported."] -pub type SR_COLOR_MODE_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DCT_DONE_INT_RAW` reader - The raw interrupt bit to sign that one dct calculation is finished."] -pub type DCT_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `DCT_DONE_INT_RAW` writer - The raw interrupt bit to sign that one dct calculation is finished."] -pub type DCT_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BS_LAST_BLOCK_EOF_INT_RAW` reader - The raw interrupt bit to sign that the coding process for last block is finished."] -pub type BS_LAST_BLOCK_EOF_INT_RAW_R = crate::BitReader; -#[doc = "Field `BS_LAST_BLOCK_EOF_INT_RAW` writer - The raw interrupt bit to sign that the coding process for last block is finished."] -pub type BS_LAST_BLOCK_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_RAW` reader - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] -pub type SCAN_CHECK_NONE_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_RAW` writer - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] -pub type SCAN_CHECK_NONE_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCAN_CHECK_POS_ERR_INT_RAW` reader - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] -pub type SCAN_CHECK_POS_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `SCAN_CHECK_POS_ERR_INT_RAW` writer - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] -pub type SCAN_CHECK_POS_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UXP_DET_INT_RAW` reader - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] -pub type UXP_DET_INT_RAW_R = crate::BitReader; -#[doc = "Field `UXP_DET_INT_RAW` writer - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] -pub type UXP_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EN_FRAME_EOF_ERR_INT_RAW` reader - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] -pub type EN_FRAME_EOF_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `EN_FRAME_EOF_ERR_INT_RAW` writer - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] -pub type EN_FRAME_EOF_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `EN_FRAME_EOF_LACK_INT_RAW` reader - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] -pub type EN_FRAME_EOF_LACK_INT_RAW_R = crate::BitReader; -#[doc = "Field `EN_FRAME_EOF_LACK_INT_RAW` writer - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] -pub type EN_FRAME_EOF_LACK_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DE_FRAME_EOF_ERR_INT_RAW` reader - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] -pub type DE_FRAME_EOF_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `DE_FRAME_EOF_ERR_INT_RAW` writer - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] -pub type DE_FRAME_EOF_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DE_FRAME_EOF_LACK_INT_RAW` reader - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] -pub type DE_FRAME_EOF_LACK_INT_RAW_R = crate::BitReader; -#[doc = "Field `DE_FRAME_EOF_LACK_INT_RAW` writer - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] -pub type DE_FRAME_EOF_LACK_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SOS_UNMATCH_ERR_INT_RAW` reader - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] -pub type SOS_UNMATCH_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `SOS_UNMATCH_ERR_INT_RAW` writer - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] -pub type SOS_UNMATCH_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MARKER_ERR_FST_SCAN_INT_RAW` reader - The raw interrupt bit to sign that the first scan has header marker error when decoding."] -pub type MARKER_ERR_FST_SCAN_INT_RAW_R = crate::BitReader; -#[doc = "Field `MARKER_ERR_FST_SCAN_INT_RAW` writer - The raw interrupt bit to sign that the first scan has header marker error when decoding."] -pub type MARKER_ERR_FST_SCAN_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_RAW` reader - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] -pub type MARKER_ERR_OTHER_SCAN_INT_RAW_R = crate::BitReader; -#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_RAW` writer - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] -pub type MARKER_ERR_OTHER_SCAN_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UNDET_INT_RAW` reader - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] -pub type UNDET_INT_RAW_R = crate::BitReader; -#[doc = "Field `UNDET_INT_RAW` writer - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] -pub type UNDET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DECODE_TIMEOUT_INT_RAW` reader - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] -pub type DECODE_TIMEOUT_INT_RAW_R = crate::BitReader; -#[doc = "Field `DECODE_TIMEOUT_INT_RAW` writer - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] -pub type DECODE_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE` reader - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RLE_PARALLEL_ERR` reader - The raw interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_R = crate::BitReader; +#[doc = "Field `RLE_PARALLEL_ERR` writer - The raw interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CID_ERR` reader - The raw interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_R = crate::BitReader; +#[doc = "Field `CID_ERR` writer - The raw interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_DC_ID_ERR` reader - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DHT_DC_ID_ERR` writer - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_AC_ID_ERR` reader - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DHT_AC_ID_ERR` writer - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DQT_ID_ERR` reader - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DQT_ID_ERR` writer - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_UXP_ERR` reader - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_R = crate::BitReader; +#[doc = "Field `RST_UXP_ERR` writer - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_NONE_ERR` reader - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_R = crate::BitReader; +#[doc = "Field `RST_CHECK_NONE_ERR` writer - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_POS_ERR` reader - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_R = crate::BitReader; +#[doc = "Field `RST_CHECK_POS_ERR` writer - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_COLOR_MODE_ERR` reader - The raw interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_R = crate::BitReader; +#[doc = "Field `SR_COLOR_MODE_ERR` writer - The raw interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCT_DONE` reader - The raw interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_R = crate::BitReader; +#[doc = "Field `DCT_DONE` writer - The raw interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BS_LAST_BLOCK_EOF` reader - The raw interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_R = crate::BitReader; +#[doc = "Field `BS_LAST_BLOCK_EOF` writer - The raw interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_NONE_ERR` reader - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_NONE_ERR` writer - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_POS_ERR` reader - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_POS_ERR` writer - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UXP_DET` reader - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_R = crate::BitReader; +#[doc = "Field `UXP_DET` writer - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_ERR` reader - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_ERR` writer - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_LACK` reader - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_LACK` writer - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_ERR` reader - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_ERR` writer - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_LACK` reader - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_LACK` writer - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOS_UNMATCH_ERR` reader - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_R = crate::BitReader; +#[doc = "Field `SOS_UNMATCH_ERR` writer - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_FST_SCAN` reader - The raw interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_FST_SCAN` writer - The raw interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_OTHER_SCAN` reader - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_OTHER_SCAN` writer - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNDET` reader - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_R = crate::BitReader; +#[doc = "Field `UNDET` writer - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DECODE_TIMEOUT` reader - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_R = crate::BitReader; +#[doc = "Field `DECODE_TIMEOUT` writer - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] #[inline(always)] - pub fn done_int_raw(&self) -> DONE_INT_RAW_R { - DONE_INT_RAW_R::new((self.bits & 1) != 0) + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt bit to sign that rle parallel error when decoding."] #[inline(always)] - pub fn rle_parallel_err_int_raw(&self) -> RLE_PARALLEL_ERR_INT_RAW_R { - RLE_PARALLEL_ERR_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn rle_parallel_err(&self) -> RLE_PARALLEL_ERR_R { + RLE_PARALLEL_ERR_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt bit to sign that scan id check with component fails when decoding."] #[inline(always)] - pub fn cid_err_int_raw(&self) -> CID_ERR_INT_RAW_R { - CID_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn cid_err(&self) -> CID_ERR_R { + CID_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] #[inline(always)] - pub fn c_dht_dc_id_err_int_raw(&self) -> C_DHT_DC_ID_ERR_INT_RAW_R { - C_DHT_DC_ID_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn c_dht_dc_id_err(&self) -> C_DHT_DC_ID_ERR_R { + C_DHT_DC_ID_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] #[inline(always)] - pub fn c_dht_ac_id_err_int_raw(&self) -> C_DHT_AC_ID_ERR_INT_RAW_R { - C_DHT_AC_ID_ERR_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn c_dht_ac_id_err(&self) -> C_DHT_AC_ID_ERR_R { + C_DHT_AC_ID_ERR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] #[inline(always)] - pub fn c_dqt_id_err_int_raw(&self) -> C_DQT_ID_ERR_INT_RAW_R { - C_DQT_ID_ERR_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn c_dqt_id_err(&self) -> C_DQT_ID_ERR_R { + C_DQT_ID_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] #[inline(always)] - pub fn rst_uxp_err_int_raw(&self) -> RST_UXP_ERR_INT_RAW_R { - RST_UXP_ERR_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn rst_uxp_err(&self) -> RST_UXP_ERR_R { + RST_UXP_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] #[inline(always)] - pub fn rst_check_none_err_int_raw(&self) -> RST_CHECK_NONE_ERR_INT_RAW_R { - RST_CHECK_NONE_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn rst_check_none_err(&self) -> RST_CHECK_NONE_ERR_R { + RST_CHECK_NONE_ERR_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] #[inline(always)] - pub fn rst_check_pos_err_int_raw(&self) -> RST_CHECK_POS_ERR_INT_RAW_R { - RST_CHECK_POS_ERR_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn rst_check_pos_err(&self) -> RST_CHECK_POS_ERR_R { + RST_CHECK_POS_ERR_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] #[inline(always)] - pub fn out_eof_int_raw(&self) -> OUT_EOF_INT_RAW_R { - OUT_EOF_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The raw interrupt bit to sign that the selected source color mode is not supported."] #[inline(always)] - pub fn sr_color_mode_err_int_raw(&self) -> SR_COLOR_MODE_ERR_INT_RAW_R { - SR_COLOR_MODE_ERR_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn sr_color_mode_err(&self) -> SR_COLOR_MODE_ERR_R { + SR_COLOR_MODE_ERR_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The raw interrupt bit to sign that one dct calculation is finished."] #[inline(always)] - pub fn dct_done_int_raw(&self) -> DCT_DONE_INT_RAW_R { - DCT_DONE_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn dct_done(&self) -> DCT_DONE_R { + DCT_DONE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The raw interrupt bit to sign that the coding process for last block is finished."] #[inline(always)] - pub fn bs_last_block_eof_int_raw(&self) -> BS_LAST_BLOCK_EOF_INT_RAW_R { - BS_LAST_BLOCK_EOF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn bs_last_block_eof(&self) -> BS_LAST_BLOCK_EOF_R { + BS_LAST_BLOCK_EOF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] #[inline(always)] - pub fn scan_check_none_err_int_raw(&self) -> SCAN_CHECK_NONE_ERR_INT_RAW_R { - SCAN_CHECK_NONE_ERR_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + pub fn scan_check_none_err(&self) -> SCAN_CHECK_NONE_ERR_R { + SCAN_CHECK_NONE_ERR_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] #[inline(always)] - pub fn scan_check_pos_err_int_raw(&self) -> SCAN_CHECK_POS_ERR_INT_RAW_R { - SCAN_CHECK_POS_ERR_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + pub fn scan_check_pos_err(&self) -> SCAN_CHECK_POS_ERR_R { + SCAN_CHECK_POS_ERR_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] #[inline(always)] - pub fn uxp_det_int_raw(&self) -> UXP_DET_INT_RAW_R { - UXP_DET_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + pub fn uxp_det(&self) -> UXP_DET_R { + UXP_DET_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] #[inline(always)] - pub fn en_frame_eof_err_int_raw(&self) -> EN_FRAME_EOF_ERR_INT_RAW_R { - EN_FRAME_EOF_ERR_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + pub fn en_frame_eof_err(&self) -> EN_FRAME_EOF_ERR_R { + EN_FRAME_EOF_ERR_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] #[inline(always)] - pub fn en_frame_eof_lack_int_raw(&self) -> EN_FRAME_EOF_LACK_INT_RAW_R { - EN_FRAME_EOF_LACK_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + pub fn en_frame_eof_lack(&self) -> EN_FRAME_EOF_LACK_R { + EN_FRAME_EOF_LACK_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] #[inline(always)] - pub fn de_frame_eof_err_int_raw(&self) -> DE_FRAME_EOF_ERR_INT_RAW_R { - DE_FRAME_EOF_ERR_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + pub fn de_frame_eof_err(&self) -> DE_FRAME_EOF_ERR_R { + DE_FRAME_EOF_ERR_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] #[inline(always)] - pub fn de_frame_eof_lack_int_raw(&self) -> DE_FRAME_EOF_LACK_INT_RAW_R { - DE_FRAME_EOF_LACK_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + pub fn de_frame_eof_lack(&self) -> DE_FRAME_EOF_LACK_R { + DE_FRAME_EOF_LACK_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 20 - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] #[inline(always)] - pub fn sos_unmatch_err_int_raw(&self) -> SOS_UNMATCH_ERR_INT_RAW_R { - SOS_UNMATCH_ERR_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + pub fn sos_unmatch_err(&self) -> SOS_UNMATCH_ERR_R { + SOS_UNMATCH_ERR_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - The raw interrupt bit to sign that the first scan has header marker error when decoding."] #[inline(always)] - pub fn marker_err_fst_scan_int_raw(&self) -> MARKER_ERR_FST_SCAN_INT_RAW_R { - MARKER_ERR_FST_SCAN_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + pub fn marker_err_fst_scan(&self) -> MARKER_ERR_FST_SCAN_R { + MARKER_ERR_FST_SCAN_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] #[inline(always)] - pub fn marker_err_other_scan_int_raw(&self) -> MARKER_ERR_OTHER_SCAN_INT_RAW_R { - MARKER_ERR_OTHER_SCAN_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + pub fn marker_err_other_scan(&self) -> MARKER_ERR_OTHER_SCAN_R { + MARKER_ERR_OTHER_SCAN_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] #[inline(always)] - pub fn undet_int_raw(&self) -> UNDET_INT_RAW_R { - UNDET_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + pub fn undet(&self) -> UNDET_R { + UNDET_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] #[inline(always)] - pub fn decode_timeout_int_raw(&self) -> DECODE_TIMEOUT_INT_RAW_R { - DECODE_TIMEOUT_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + pub fn decode_timeout(&self) -> DECODE_TIMEOUT_R { + DECODE_TIMEOUT_R::new(((self.bits >> 24) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_RAW") + .field("done", &format_args!("{}", self.done().bit())) .field( - "done_int_raw", - &format_args!("{}", self.done_int_raw().bit()), + "rle_parallel_err", + &format_args!("{}", self.rle_parallel_err().bit()), ) + .field("cid_err", &format_args!("{}", self.cid_err().bit())) .field( - "rle_parallel_err_int_raw", - &format_args!("{}", self.rle_parallel_err_int_raw().bit()), + "c_dht_dc_id_err", + &format_args!("{}", self.c_dht_dc_id_err().bit()), ) .field( - "cid_err_int_raw", - &format_args!("{}", self.cid_err_int_raw().bit()), + "c_dht_ac_id_err", + &format_args!("{}", self.c_dht_ac_id_err().bit()), ) .field( - "c_dht_dc_id_err_int_raw", - &format_args!("{}", self.c_dht_dc_id_err_int_raw().bit()), + "c_dqt_id_err", + &format_args!("{}", self.c_dqt_id_err().bit()), ) + .field("rst_uxp_err", &format_args!("{}", self.rst_uxp_err().bit())) .field( - "c_dht_ac_id_err_int_raw", - &format_args!("{}", self.c_dht_ac_id_err_int_raw().bit()), + "rst_check_none_err", + &format_args!("{}", self.rst_check_none_err().bit()), ) .field( - "c_dqt_id_err_int_raw", - &format_args!("{}", self.c_dqt_id_err_int_raw().bit()), + "rst_check_pos_err", + &format_args!("{}", self.rst_check_pos_err().bit()), ) + .field("out_eof", &format_args!("{}", self.out_eof().bit())) .field( - "rst_uxp_err_int_raw", - &format_args!("{}", self.rst_uxp_err_int_raw().bit()), + "sr_color_mode_err", + &format_args!("{}", self.sr_color_mode_err().bit()), ) + .field("dct_done", &format_args!("{}", self.dct_done().bit())) .field( - "rst_check_none_err_int_raw", - &format_args!("{}", self.rst_check_none_err_int_raw().bit()), + "bs_last_block_eof", + &format_args!("{}", self.bs_last_block_eof().bit()), ) .field( - "rst_check_pos_err_int_raw", - &format_args!("{}", self.rst_check_pos_err_int_raw().bit()), + "scan_check_none_err", + &format_args!("{}", self.scan_check_none_err().bit()), ) .field( - "out_eof_int_raw", - &format_args!("{}", self.out_eof_int_raw().bit()), + "scan_check_pos_err", + &format_args!("{}", self.scan_check_pos_err().bit()), ) + .field("uxp_det", &format_args!("{}", self.uxp_det().bit())) .field( - "sr_color_mode_err_int_raw", - &format_args!("{}", self.sr_color_mode_err_int_raw().bit()), + "en_frame_eof_err", + &format_args!("{}", self.en_frame_eof_err().bit()), ) .field( - "dct_done_int_raw", - &format_args!("{}", self.dct_done_int_raw().bit()), + "en_frame_eof_lack", + &format_args!("{}", self.en_frame_eof_lack().bit()), ) .field( - "bs_last_block_eof_int_raw", - &format_args!("{}", self.bs_last_block_eof_int_raw().bit()), + "de_frame_eof_err", + &format_args!("{}", self.de_frame_eof_err().bit()), ) .field( - "scan_check_none_err_int_raw", - &format_args!("{}", self.scan_check_none_err_int_raw().bit()), + "de_frame_eof_lack", + &format_args!("{}", self.de_frame_eof_lack().bit()), ) .field( - "scan_check_pos_err_int_raw", - &format_args!("{}", self.scan_check_pos_err_int_raw().bit()), + "sos_unmatch_err", + &format_args!("{}", self.sos_unmatch_err().bit()), ) .field( - "uxp_det_int_raw", - &format_args!("{}", self.uxp_det_int_raw().bit()), + "marker_err_fst_scan", + &format_args!("{}", self.marker_err_fst_scan().bit()), ) .field( - "en_frame_eof_err_int_raw", - &format_args!("{}", self.en_frame_eof_err_int_raw().bit()), + "marker_err_other_scan", + &format_args!("{}", self.marker_err_other_scan().bit()), ) + .field("undet", &format_args!("{}", self.undet().bit())) .field( - "en_frame_eof_lack_int_raw", - &format_args!("{}", self.en_frame_eof_lack_int_raw().bit()), - ) - .field( - "de_frame_eof_err_int_raw", - &format_args!("{}", self.de_frame_eof_err_int_raw().bit()), - ) - .field( - "de_frame_eof_lack_int_raw", - &format_args!("{}", self.de_frame_eof_lack_int_raw().bit()), - ) - .field( - "sos_unmatch_err_int_raw", - &format_args!("{}", self.sos_unmatch_err_int_raw().bit()), - ) - .field( - "marker_err_fst_scan_int_raw", - &format_args!("{}", self.marker_err_fst_scan_int_raw().bit()), - ) - .field( - "marker_err_other_scan_int_raw", - &format_args!("{}", self.marker_err_other_scan_int_raw().bit()), - ) - .field( - "undet_int_raw", - &format_args!("{}", self.undet_int_raw().bit()), - ) - .field( - "decode_timeout_int_raw", - &format_args!("{}", self.decode_timeout_int_raw().bit()), + "decode_timeout", + &format_args!("{}", self.decode_timeout().bit()), ) .finish() } @@ -346,154 +325,152 @@ impl W { #[doc = "Bit 0 - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] #[inline(always)] #[must_use] - pub fn done_int_raw(&mut self) -> DONE_INT_RAW_W { - DONE_INT_RAW_W::new(self, 0) + pub fn done(&mut self) -> DONE_W { + DONE_W::new(self, 0) } #[doc = "Bit 1 - The raw interrupt bit to sign that rle parallel error when decoding."] #[inline(always)] #[must_use] - pub fn rle_parallel_err_int_raw(&mut self) -> RLE_PARALLEL_ERR_INT_RAW_W { - RLE_PARALLEL_ERR_INT_RAW_W::new(self, 1) + pub fn rle_parallel_err(&mut self) -> RLE_PARALLEL_ERR_W { + RLE_PARALLEL_ERR_W::new(self, 1) } #[doc = "Bit 2 - The raw interrupt bit to sign that scan id check with component fails when decoding."] #[inline(always)] #[must_use] - pub fn cid_err_int_raw(&mut self) -> CID_ERR_INT_RAW_W { - CID_ERR_INT_RAW_W::new(self, 2) + pub fn cid_err(&mut self) -> CID_ERR_W { + CID_ERR_W::new(self, 2) } #[doc = "Bit 3 - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dht_dc_id_err_int_raw(&mut self) -> C_DHT_DC_ID_ERR_INT_RAW_W { - C_DHT_DC_ID_ERR_INT_RAW_W::new(self, 3) + pub fn c_dht_dc_id_err(&mut self) -> C_DHT_DC_ID_ERR_W { + C_DHT_DC_ID_ERR_W::new(self, 3) } #[doc = "Bit 4 - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dht_ac_id_err_int_raw(&mut self) -> C_DHT_AC_ID_ERR_INT_RAW_W { - C_DHT_AC_ID_ERR_INT_RAW_W::new(self, 4) + pub fn c_dht_ac_id_err(&mut self) -> C_DHT_AC_ID_ERR_W { + C_DHT_AC_ID_ERR_W::new(self, 4) } #[doc = "Bit 5 - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] #[inline(always)] #[must_use] - pub fn c_dqt_id_err_int_raw(&mut self) -> C_DQT_ID_ERR_INT_RAW_W { - C_DQT_ID_ERR_INT_RAW_W::new(self, 5) + pub fn c_dqt_id_err(&mut self) -> C_DQT_ID_ERR_W { + C_DQT_ID_ERR_W::new(self, 5) } #[doc = "Bit 6 - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] #[inline(always)] #[must_use] - pub fn rst_uxp_err_int_raw(&mut self) -> RST_UXP_ERR_INT_RAW_W { - RST_UXP_ERR_INT_RAW_W::new(self, 6) + pub fn rst_uxp_err(&mut self) -> RST_UXP_ERR_W { + RST_UXP_ERR_W::new(self, 6) } #[doc = "Bit 7 - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] #[inline(always)] #[must_use] - pub fn rst_check_none_err_int_raw(&mut self) -> RST_CHECK_NONE_ERR_INT_RAW_W { - RST_CHECK_NONE_ERR_INT_RAW_W::new(self, 7) + pub fn rst_check_none_err(&mut self) -> RST_CHECK_NONE_ERR_W { + RST_CHECK_NONE_ERR_W::new(self, 7) } #[doc = "Bit 8 - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] #[inline(always)] #[must_use] - pub fn rst_check_pos_err_int_raw(&mut self) -> RST_CHECK_POS_ERR_INT_RAW_W { - RST_CHECK_POS_ERR_INT_RAW_W::new(self, 8) + pub fn rst_check_pos_err(&mut self) -> RST_CHECK_POS_ERR_W { + RST_CHECK_POS_ERR_W::new(self, 8) } #[doc = "Bit 9 - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] #[inline(always)] #[must_use] - pub fn out_eof_int_raw(&mut self) -> OUT_EOF_INT_RAW_W { - OUT_EOF_INT_RAW_W::new(self, 9) + pub fn out_eof(&mut self) -> OUT_EOF_W { + OUT_EOF_W::new(self, 9) } #[doc = "Bit 10 - The raw interrupt bit to sign that the selected source color mode is not supported."] #[inline(always)] #[must_use] - pub fn sr_color_mode_err_int_raw(&mut self) -> SR_COLOR_MODE_ERR_INT_RAW_W { - SR_COLOR_MODE_ERR_INT_RAW_W::new(self, 10) + pub fn sr_color_mode_err(&mut self) -> SR_COLOR_MODE_ERR_W { + SR_COLOR_MODE_ERR_W::new(self, 10) } #[doc = "Bit 11 - The raw interrupt bit to sign that one dct calculation is finished."] #[inline(always)] #[must_use] - pub fn dct_done_int_raw(&mut self) -> DCT_DONE_INT_RAW_W { - DCT_DONE_INT_RAW_W::new(self, 11) + pub fn dct_done(&mut self) -> DCT_DONE_W { + DCT_DONE_W::new(self, 11) } #[doc = "Bit 12 - The raw interrupt bit to sign that the coding process for last block is finished."] #[inline(always)] #[must_use] - pub fn bs_last_block_eof_int_raw(&mut self) -> BS_LAST_BLOCK_EOF_INT_RAW_W { - BS_LAST_BLOCK_EOF_INT_RAW_W::new(self, 12) + pub fn bs_last_block_eof(&mut self) -> BS_LAST_BLOCK_EOF_W { + BS_LAST_BLOCK_EOF_W::new(self, 12) } #[doc = "Bit 13 - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] #[inline(always)] #[must_use] - pub fn scan_check_none_err_int_raw(&mut self) -> SCAN_CHECK_NONE_ERR_INT_RAW_W { - SCAN_CHECK_NONE_ERR_INT_RAW_W::new(self, 13) + pub fn scan_check_none_err(&mut self) -> SCAN_CHECK_NONE_ERR_W { + SCAN_CHECK_NONE_ERR_W::new(self, 13) } #[doc = "Bit 14 - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] #[inline(always)] #[must_use] - pub fn scan_check_pos_err_int_raw(&mut self) -> SCAN_CHECK_POS_ERR_INT_RAW_W { - SCAN_CHECK_POS_ERR_INT_RAW_W::new(self, 14) + pub fn scan_check_pos_err(&mut self) -> SCAN_CHECK_POS_ERR_W { + SCAN_CHECK_POS_ERR_W::new(self, 14) } #[doc = "Bit 15 - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] #[inline(always)] #[must_use] - pub fn uxp_det_int_raw(&mut self) -> UXP_DET_INT_RAW_W { - UXP_DET_INT_RAW_W::new(self, 15) + pub fn uxp_det(&mut self) -> UXP_DET_W { + UXP_DET_W::new(self, 15) } #[doc = "Bit 16 - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] #[inline(always)] #[must_use] - pub fn en_frame_eof_err_int_raw(&mut self) -> EN_FRAME_EOF_ERR_INT_RAW_W { - EN_FRAME_EOF_ERR_INT_RAW_W::new(self, 16) + pub fn en_frame_eof_err(&mut self) -> EN_FRAME_EOF_ERR_W { + EN_FRAME_EOF_ERR_W::new(self, 16) } #[doc = "Bit 17 - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] #[inline(always)] #[must_use] - pub fn en_frame_eof_lack_int_raw(&mut self) -> EN_FRAME_EOF_LACK_INT_RAW_W { - EN_FRAME_EOF_LACK_INT_RAW_W::new(self, 17) + pub fn en_frame_eof_lack(&mut self) -> EN_FRAME_EOF_LACK_W { + EN_FRAME_EOF_LACK_W::new(self, 17) } #[doc = "Bit 18 - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] #[inline(always)] #[must_use] - pub fn de_frame_eof_err_int_raw(&mut self) -> DE_FRAME_EOF_ERR_INT_RAW_W { - DE_FRAME_EOF_ERR_INT_RAW_W::new(self, 18) + pub fn de_frame_eof_err(&mut self) -> DE_FRAME_EOF_ERR_W { + DE_FRAME_EOF_ERR_W::new(self, 18) } #[doc = "Bit 19 - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] #[inline(always)] #[must_use] - pub fn de_frame_eof_lack_int_raw(&mut self) -> DE_FRAME_EOF_LACK_INT_RAW_W { - DE_FRAME_EOF_LACK_INT_RAW_W::new(self, 19) + pub fn de_frame_eof_lack(&mut self) -> DE_FRAME_EOF_LACK_W { + DE_FRAME_EOF_LACK_W::new(self, 19) } #[doc = "Bit 20 - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] #[inline(always)] #[must_use] - pub fn sos_unmatch_err_int_raw(&mut self) -> SOS_UNMATCH_ERR_INT_RAW_W { - SOS_UNMATCH_ERR_INT_RAW_W::new(self, 20) + pub fn sos_unmatch_err(&mut self) -> SOS_UNMATCH_ERR_W { + SOS_UNMATCH_ERR_W::new(self, 20) } #[doc = "Bit 21 - The raw interrupt bit to sign that the first scan has header marker error when decoding."] #[inline(always)] #[must_use] - pub fn marker_err_fst_scan_int_raw(&mut self) -> MARKER_ERR_FST_SCAN_INT_RAW_W { - MARKER_ERR_FST_SCAN_INT_RAW_W::new(self, 21) + pub fn marker_err_fst_scan(&mut self) -> MARKER_ERR_FST_SCAN_W { + MARKER_ERR_FST_SCAN_W::new(self, 21) } #[doc = "Bit 22 - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] #[inline(always)] #[must_use] - pub fn marker_err_other_scan_int_raw( - &mut self, - ) -> MARKER_ERR_OTHER_SCAN_INT_RAW_W { - MARKER_ERR_OTHER_SCAN_INT_RAW_W::new(self, 22) + pub fn marker_err_other_scan(&mut self) -> MARKER_ERR_OTHER_SCAN_W { + MARKER_ERR_OTHER_SCAN_W::new(self, 22) } #[doc = "Bit 23 - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] #[inline(always)] #[must_use] - pub fn undet_int_raw(&mut self) -> UNDET_INT_RAW_W { - UNDET_INT_RAW_W::new(self, 23) + pub fn undet(&mut self) -> UNDET_W { + UNDET_W::new(self, 23) } #[doc = "Bit 24 - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] #[inline(always)] #[must_use] - pub fn decode_timeout_int_raw(&mut self) -> DECODE_TIMEOUT_INT_RAW_W { - DECODE_TIMEOUT_INT_RAW_W::new(self, 24) + pub fn decode_timeout(&mut self) -> DECODE_TIMEOUT_W { + DECODE_TIMEOUT_W::new(self, 24) } } #[doc = "Interrupt raw registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/jpeg/int_st.rs b/esp32p4/src/jpeg/int_st.rs index 8eb6d15922..0f96079a1f 100644 --- a/esp32p4/src/jpeg/int_st.rs +++ b/esp32p4/src/jpeg/int_st.rs @@ -1,282 +1,264 @@ #[doc = "Register `INT_ST` reader"] pub type R = crate::R; -#[doc = "Field `DONE_INT_ST` reader - This status interrupt bit turns to high level when JPEG finishes encoding a picture.."] -pub type DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `RLE_PARALLEL_ERR_INT_ST` reader - The status interrupt bit to sign that rle parallel error when decoding."] -pub type RLE_PARALLEL_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `CID_ERR_INT_ST` reader - The status interrupt bit to sign that scan id check with component fails when decoding."] -pub type CID_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `C_DHT_DC_ID_ERR_INT_ST` reader - The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] -pub type C_DHT_DC_ID_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `C_DHT_AC_ID_ERR_INT_ST` reader - The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] -pub type C_DHT_AC_ID_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `C_DQT_ID_ERR_INT_ST` reader - The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] -pub type C_DQT_ID_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `RST_UXP_ERR_INT_ST` reader - The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] -pub type RST_UXP_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `RST_CHECK_NONE_ERR_INT_ST` reader - The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] -pub type RST_CHECK_NONE_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `RST_CHECK_POS_ERR_INT_ST` reader - The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] -pub type RST_CHECK_POS_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `OUT_EOF_INT_ST` reader - The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] -pub type OUT_EOF_INT_ST_R = crate::BitReader; -#[doc = "Field `SR_COLOR_MODE_ERR_INT_ST` reader - The status interrupt bit to sign that the selected source color mode is not supported."] -pub type SR_COLOR_MODE_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `DCT_DONE_INT_ST` reader - The status interrupt bit to sign that one dct calculation is finished."] -pub type DCT_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `BS_LAST_BLOCK_EOF_INT_ST` reader - The status interrupt bit to sign that the coding process for last block is finished."] -pub type BS_LAST_BLOCK_EOF_INT_ST_R = crate::BitReader; -#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_ST` reader - The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] -pub type SCAN_CHECK_NONE_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `SCAN_CHECK_POS_ERR_INT_ST` reader - The status interrupt bit to sign that SOS header marker position wrong when decoding."] -pub type SCAN_CHECK_POS_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `UXP_DET_INT_ST` reader - The status interrupt bit to sign that unsupported header marker is detected when decoding."] -pub type UXP_DET_INT_ST_R = crate::BitReader; -#[doc = "Field `EN_FRAME_EOF_ERR_INT_ST` reader - The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] -pub type EN_FRAME_EOF_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `EN_FRAME_EOF_LACK_INT_ST` reader - The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] -pub type EN_FRAME_EOF_LACK_INT_ST_R = crate::BitReader; -#[doc = "Field `DE_FRAME_EOF_ERR_INT_ST` reader - The status interrupt bit to sign that decoded blocks are smaller than expected when decoding."] -pub type DE_FRAME_EOF_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `DE_FRAME_EOF_LACK_INT_ST` reader - The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] -pub type DE_FRAME_EOF_LACK_INT_ST_R = crate::BitReader; -#[doc = "Field `SOS_UNMATCH_ERR_INT_ST` reader - The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] -pub type SOS_UNMATCH_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `MARKER_ERR_FST_SCAN_INT_ST` reader - The status interrupt bit to sign that the first scan has header marker error when decoding."] -pub type MARKER_ERR_FST_SCAN_INT_ST_R = crate::BitReader; -#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_ST` reader - The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] -pub type MARKER_ERR_OTHER_SCAN_INT_ST_R = crate::BitReader; -#[doc = "Field `UNDET_INT_ST` reader - The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] -pub type UNDET_INT_ST_R = crate::BitReader; -#[doc = "Field `DECODE_TIMEOUT_INT_ST` reader - The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] -pub type DECODE_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `DONE` reader - This status interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_R = crate::BitReader; +#[doc = "Field `RLE_PARALLEL_ERR` reader - The status interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_R = crate::BitReader; +#[doc = "Field `CID_ERR` reader - The status interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_R = crate::BitReader; +#[doc = "Field `C_DHT_DC_ID_ERR` reader - The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DHT_AC_ID_ERR` reader - The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_R = crate::BitReader; +#[doc = "Field `C_DQT_ID_ERR` reader - The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_R = crate::BitReader; +#[doc = "Field `RST_UXP_ERR` reader - The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_R = crate::BitReader; +#[doc = "Field `RST_CHECK_NONE_ERR` reader - The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_R = crate::BitReader; +#[doc = "Field `RST_CHECK_POS_ERR` reader - The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `SR_COLOR_MODE_ERR` reader - The status interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_R = crate::BitReader; +#[doc = "Field `DCT_DONE` reader - The status interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_R = crate::BitReader; +#[doc = "Field `BS_LAST_BLOCK_EOF` reader - The status interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_NONE_ERR` reader - The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_POS_ERR` reader - The status interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_R = crate::BitReader; +#[doc = "Field `UXP_DET` reader - The status interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_ERR` reader - The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_LACK` reader - The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_ERR` reader - The status interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_LACK` reader - The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_R = crate::BitReader; +#[doc = "Field `SOS_UNMATCH_ERR` reader - The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_FST_SCAN` reader - The status interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_OTHER_SCAN` reader - The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_R = crate::BitReader; +#[doc = "Field `UNDET` reader - The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_R = crate::BitReader; +#[doc = "Field `DECODE_TIMEOUT` reader - The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_R = crate::BitReader; impl R { #[doc = "Bit 0 - This status interrupt bit turns to high level when JPEG finishes encoding a picture.."] #[inline(always)] - pub fn done_int_st(&self) -> DONE_INT_ST_R { - DONE_INT_ST_R::new((self.bits & 1) != 0) + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The status interrupt bit to sign that rle parallel error when decoding."] #[inline(always)] - pub fn rle_parallel_err_int_st(&self) -> RLE_PARALLEL_ERR_INT_ST_R { - RLE_PARALLEL_ERR_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn rle_parallel_err(&self) -> RLE_PARALLEL_ERR_R { + RLE_PARALLEL_ERR_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The status interrupt bit to sign that scan id check with component fails when decoding."] #[inline(always)] - pub fn cid_err_int_st(&self) -> CID_ERR_INT_ST_R { - CID_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn cid_err(&self) -> CID_ERR_R { + CID_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] #[inline(always)] - pub fn c_dht_dc_id_err_int_st(&self) -> C_DHT_DC_ID_ERR_INT_ST_R { - C_DHT_DC_ID_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn c_dht_dc_id_err(&self) -> C_DHT_DC_ID_ERR_R { + C_DHT_DC_ID_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] #[inline(always)] - pub fn c_dht_ac_id_err_int_st(&self) -> C_DHT_AC_ID_ERR_INT_ST_R { - C_DHT_AC_ID_ERR_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn c_dht_ac_id_err(&self) -> C_DHT_AC_ID_ERR_R { + C_DHT_AC_ID_ERR_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] #[inline(always)] - pub fn c_dqt_id_err_int_st(&self) -> C_DQT_ID_ERR_INT_ST_R { - C_DQT_ID_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn c_dqt_id_err(&self) -> C_DQT_ID_ERR_R { + C_DQT_ID_ERR_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] #[inline(always)] - pub fn rst_uxp_err_int_st(&self) -> RST_UXP_ERR_INT_ST_R { - RST_UXP_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn rst_uxp_err(&self) -> RST_UXP_ERR_R { + RST_UXP_ERR_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] #[inline(always)] - pub fn rst_check_none_err_int_st(&self) -> RST_CHECK_NONE_ERR_INT_ST_R { - RST_CHECK_NONE_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn rst_check_none_err(&self) -> RST_CHECK_NONE_ERR_R { + RST_CHECK_NONE_ERR_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] #[inline(always)] - pub fn rst_check_pos_err_int_st(&self) -> RST_CHECK_POS_ERR_INT_ST_R { - RST_CHECK_POS_ERR_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn rst_check_pos_err(&self) -> RST_CHECK_POS_ERR_R { + RST_CHECK_POS_ERR_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] #[inline(always)] - pub fn out_eof_int_st(&self) -> OUT_EOF_INT_ST_R { - OUT_EOF_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The status interrupt bit to sign that the selected source color mode is not supported."] #[inline(always)] - pub fn sr_color_mode_err_int_st(&self) -> SR_COLOR_MODE_ERR_INT_ST_R { - SR_COLOR_MODE_ERR_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn sr_color_mode_err(&self) -> SR_COLOR_MODE_ERR_R { + SR_COLOR_MODE_ERR_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The status interrupt bit to sign that one dct calculation is finished."] #[inline(always)] - pub fn dct_done_int_st(&self) -> DCT_DONE_INT_ST_R { - DCT_DONE_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn dct_done(&self) -> DCT_DONE_R { + DCT_DONE_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The status interrupt bit to sign that the coding process for last block is finished."] #[inline(always)] - pub fn bs_last_block_eof_int_st(&self) -> BS_LAST_BLOCK_EOF_INT_ST_R { - BS_LAST_BLOCK_EOF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn bs_last_block_eof(&self) -> BS_LAST_BLOCK_EOF_R { + BS_LAST_BLOCK_EOF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] #[inline(always)] - pub fn scan_check_none_err_int_st(&self) -> SCAN_CHECK_NONE_ERR_INT_ST_R { - SCAN_CHECK_NONE_ERR_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + pub fn scan_check_none_err(&self) -> SCAN_CHECK_NONE_ERR_R { + SCAN_CHECK_NONE_ERR_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - The status interrupt bit to sign that SOS header marker position wrong when decoding."] #[inline(always)] - pub fn scan_check_pos_err_int_st(&self) -> SCAN_CHECK_POS_ERR_INT_ST_R { - SCAN_CHECK_POS_ERR_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + pub fn scan_check_pos_err(&self) -> SCAN_CHECK_POS_ERR_R { + SCAN_CHECK_POS_ERR_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - The status interrupt bit to sign that unsupported header marker is detected when decoding."] #[inline(always)] - pub fn uxp_det_int_st(&self) -> UXP_DET_INT_ST_R { - UXP_DET_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + pub fn uxp_det(&self) -> UXP_DET_R { + UXP_DET_R::new(((self.bits >> 15) & 1) != 0) } #[doc = "Bit 16 - The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] #[inline(always)] - pub fn en_frame_eof_err_int_st(&self) -> EN_FRAME_EOF_ERR_INT_ST_R { - EN_FRAME_EOF_ERR_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + pub fn en_frame_eof_err(&self) -> EN_FRAME_EOF_ERR_R { + EN_FRAME_EOF_ERR_R::new(((self.bits >> 16) & 1) != 0) } #[doc = "Bit 17 - The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] #[inline(always)] - pub fn en_frame_eof_lack_int_st(&self) -> EN_FRAME_EOF_LACK_INT_ST_R { - EN_FRAME_EOF_LACK_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + pub fn en_frame_eof_lack(&self) -> EN_FRAME_EOF_LACK_R { + EN_FRAME_EOF_LACK_R::new(((self.bits >> 17) & 1) != 0) } #[doc = "Bit 18 - The status interrupt bit to sign that decoded blocks are smaller than expected when decoding."] #[inline(always)] - pub fn de_frame_eof_err_int_st(&self) -> DE_FRAME_EOF_ERR_INT_ST_R { - DE_FRAME_EOF_ERR_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + pub fn de_frame_eof_err(&self) -> DE_FRAME_EOF_ERR_R { + DE_FRAME_EOF_ERR_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] #[inline(always)] - pub fn de_frame_eof_lack_int_st(&self) -> DE_FRAME_EOF_LACK_INT_ST_R { - DE_FRAME_EOF_LACK_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + pub fn de_frame_eof_lack(&self) -> DE_FRAME_EOF_LACK_R { + DE_FRAME_EOF_LACK_R::new(((self.bits >> 19) & 1) != 0) } #[doc = "Bit 20 - The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] #[inline(always)] - pub fn sos_unmatch_err_int_st(&self) -> SOS_UNMATCH_ERR_INT_ST_R { - SOS_UNMATCH_ERR_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + pub fn sos_unmatch_err(&self) -> SOS_UNMATCH_ERR_R { + SOS_UNMATCH_ERR_R::new(((self.bits >> 20) & 1) != 0) } #[doc = "Bit 21 - The status interrupt bit to sign that the first scan has header marker error when decoding."] #[inline(always)] - pub fn marker_err_fst_scan_int_st(&self) -> MARKER_ERR_FST_SCAN_INT_ST_R { - MARKER_ERR_FST_SCAN_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + pub fn marker_err_fst_scan(&self) -> MARKER_ERR_FST_SCAN_R { + MARKER_ERR_FST_SCAN_R::new(((self.bits >> 21) & 1) != 0) } #[doc = "Bit 22 - The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] #[inline(always)] - pub fn marker_err_other_scan_int_st(&self) -> MARKER_ERR_OTHER_SCAN_INT_ST_R { - MARKER_ERR_OTHER_SCAN_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + pub fn marker_err_other_scan(&self) -> MARKER_ERR_OTHER_SCAN_R { + MARKER_ERR_OTHER_SCAN_R::new(((self.bits >> 22) & 1) != 0) } #[doc = "Bit 23 - The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] #[inline(always)] - pub fn undet_int_st(&self) -> UNDET_INT_ST_R { - UNDET_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + pub fn undet(&self) -> UNDET_R { + UNDET_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] #[inline(always)] - pub fn decode_timeout_int_st(&self) -> DECODE_TIMEOUT_INT_ST_R { - DECODE_TIMEOUT_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + pub fn decode_timeout(&self) -> DECODE_TIMEOUT_R { + DECODE_TIMEOUT_R::new(((self.bits >> 24) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ST") - .field("done_int_st", &format_args!("{}", self.done_int_st().bit())) + .field("done", &format_args!("{}", self.done().bit())) .field( - "rle_parallel_err_int_st", - &format_args!("{}", self.rle_parallel_err_int_st().bit()), + "rle_parallel_err", + &format_args!("{}", self.rle_parallel_err().bit()), ) + .field("cid_err", &format_args!("{}", self.cid_err().bit())) .field( - "cid_err_int_st", - &format_args!("{}", self.cid_err_int_st().bit()), + "c_dht_dc_id_err", + &format_args!("{}", self.c_dht_dc_id_err().bit()), ) .field( - "c_dht_dc_id_err_int_st", - &format_args!("{}", self.c_dht_dc_id_err_int_st().bit()), + "c_dht_ac_id_err", + &format_args!("{}", self.c_dht_ac_id_err().bit()), ) .field( - "c_dht_ac_id_err_int_st", - &format_args!("{}", self.c_dht_ac_id_err_int_st().bit()), + "c_dqt_id_err", + &format_args!("{}", self.c_dqt_id_err().bit()), ) + .field("rst_uxp_err", &format_args!("{}", self.rst_uxp_err().bit())) .field( - "c_dqt_id_err_int_st", - &format_args!("{}", self.c_dqt_id_err_int_st().bit()), + "rst_check_none_err", + &format_args!("{}", self.rst_check_none_err().bit()), ) .field( - "rst_uxp_err_int_st", - &format_args!("{}", self.rst_uxp_err_int_st().bit()), + "rst_check_pos_err", + &format_args!("{}", self.rst_check_pos_err().bit()), ) + .field("out_eof", &format_args!("{}", self.out_eof().bit())) .field( - "rst_check_none_err_int_st", - &format_args!("{}", self.rst_check_none_err_int_st().bit()), + "sr_color_mode_err", + &format_args!("{}", self.sr_color_mode_err().bit()), ) + .field("dct_done", &format_args!("{}", self.dct_done().bit())) .field( - "rst_check_pos_err_int_st", - &format_args!("{}", self.rst_check_pos_err_int_st().bit()), + "bs_last_block_eof", + &format_args!("{}", self.bs_last_block_eof().bit()), ) .field( - "out_eof_int_st", - &format_args!("{}", self.out_eof_int_st().bit()), + "scan_check_none_err", + &format_args!("{}", self.scan_check_none_err().bit()), ) .field( - "sr_color_mode_err_int_st", - &format_args!("{}", self.sr_color_mode_err_int_st().bit()), + "scan_check_pos_err", + &format_args!("{}", self.scan_check_pos_err().bit()), ) + .field("uxp_det", &format_args!("{}", self.uxp_det().bit())) .field( - "dct_done_int_st", - &format_args!("{}", self.dct_done_int_st().bit()), + "en_frame_eof_err", + &format_args!("{}", self.en_frame_eof_err().bit()), ) .field( - "bs_last_block_eof_int_st", - &format_args!("{}", self.bs_last_block_eof_int_st().bit()), + "en_frame_eof_lack", + &format_args!("{}", self.en_frame_eof_lack().bit()), ) .field( - "scan_check_none_err_int_st", - &format_args!("{}", self.scan_check_none_err_int_st().bit()), + "de_frame_eof_err", + &format_args!("{}", self.de_frame_eof_err().bit()), ) .field( - "scan_check_pos_err_int_st", - &format_args!("{}", self.scan_check_pos_err_int_st().bit()), + "de_frame_eof_lack", + &format_args!("{}", self.de_frame_eof_lack().bit()), ) .field( - "uxp_det_int_st", - &format_args!("{}", self.uxp_det_int_st().bit()), + "sos_unmatch_err", + &format_args!("{}", self.sos_unmatch_err().bit()), ) .field( - "en_frame_eof_err_int_st", - &format_args!("{}", self.en_frame_eof_err_int_st().bit()), + "marker_err_fst_scan", + &format_args!("{}", self.marker_err_fst_scan().bit()), ) .field( - "en_frame_eof_lack_int_st", - &format_args!("{}", self.en_frame_eof_lack_int_st().bit()), + "marker_err_other_scan", + &format_args!("{}", self.marker_err_other_scan().bit()), ) + .field("undet", &format_args!("{}", self.undet().bit())) .field( - "de_frame_eof_err_int_st", - &format_args!("{}", self.de_frame_eof_err_int_st().bit()), - ) - .field( - "de_frame_eof_lack_int_st", - &format_args!("{}", self.de_frame_eof_lack_int_st().bit()), - ) - .field( - "sos_unmatch_err_int_st", - &format_args!("{}", self.sos_unmatch_err_int_st().bit()), - ) - .field( - "marker_err_fst_scan_int_st", - &format_args!("{}", self.marker_err_fst_scan_int_st().bit()), - ) - .field( - "marker_err_other_scan_int_st", - &format_args!("{}", self.marker_err_other_scan_int_st().bit()), - ) - .field( - "undet_int_st", - &format_args!("{}", self.undet_int_st().bit()), - ) - .field( - "decode_timeout_int_st", - &format_args!("{}", self.decode_timeout_int_st().bit()), + "decode_timeout", + &format_args!("{}", self.decode_timeout().bit()), ) .finish() } diff --git a/esp32p4/src/lp_huk/int_clr.rs b/esp32p4/src/lp_huk/int_clr.rs index 6f732b8d29..4602465870 100644 --- a/esp32p4/src/lp_huk/int_clr.rs +++ b/esp32p4/src/lp_huk/int_clr.rs @@ -1,11 +1,11 @@ #[doc = "Register `INT_CLR` writer"] pub type W = crate::W; -#[doc = "Field `PREP_DONE_INT_CLR` writer - Set this bit to clear the huk_prep_done_int interrupt"] -pub type PREP_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PROC_DONE_INT_CLR` writer - Set this bit to clear the huk_proc_done_int interrupt"] -pub type PROC_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `POST_DONE_INT_CLR` writer - Set this bit to clear the huk_post_done_int interrupt"] -pub type POST_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PREP_DONE` writer - Set this bit to clear the huk_prep_done_int interrupt"] +pub type PREP_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `PROC_DONE` writer - Set this bit to clear the huk_proc_done_int interrupt"] +pub type PROC_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `POST_DONE` writer - Set this bit to clear the huk_post_done_int interrupt"] +pub type POST_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -16,20 +16,20 @@ impl W { #[doc = "Bit 0 - Set this bit to clear the huk_prep_done_int interrupt"] #[inline(always)] #[must_use] - pub fn prep_done_int_clr(&mut self) -> PREP_DONE_INT_CLR_W { - PREP_DONE_INT_CLR_W::new(self, 0) + pub fn prep_done(&mut self) -> PREP_DONE_W { + PREP_DONE_W::new(self, 0) } #[doc = "Bit 1 - Set this bit to clear the huk_proc_done_int interrupt"] #[inline(always)] #[must_use] - pub fn proc_done_int_clr(&mut self) -> PROC_DONE_INT_CLR_W { - PROC_DONE_INT_CLR_W::new(self, 1) + pub fn proc_done(&mut self) -> PROC_DONE_W { + PROC_DONE_W::new(self, 1) } #[doc = "Bit 2 - Set this bit to clear the huk_post_done_int interrupt"] #[inline(always)] #[must_use] - pub fn post_done_int_clr(&mut self) -> POST_DONE_INT_CLR_W { - POST_DONE_INT_CLR_W::new(self, 2) + pub fn post_done(&mut self) -> POST_DONE_W { + POST_DONE_W::new(self, 2) } } #[doc = "HUK Generator interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -41,7 +41,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC { impl crate::Writable for INT_CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07; } #[doc = "`reset()` method sets INT_CLR to value 0"] impl crate::Resettable for INT_CLR_SPEC { diff --git a/esp32p4/src/lp_huk/int_ena.rs b/esp32p4/src/lp_huk/int_ena.rs index aec3a56c8c..1974d5a159 100644 --- a/esp32p4/src/lp_huk/int_ena.rs +++ b/esp32p4/src/lp_huk/int_ena.rs @@ -2,51 +2,42 @@ pub type R = crate::R; #[doc = "Register `INT_ENA` writer"] pub type W = crate::W; -#[doc = "Field `PREP_DONE_INT_ENA` reader - The interrupt enable bit for the huk_prep_done_int interrupt"] -pub type PREP_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `PREP_DONE_INT_ENA` writer - The interrupt enable bit for the huk_prep_done_int interrupt"] -pub type PREP_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PROC_DONE_INT_ENA` reader - The interrupt enable bit for the huk_proc_done_int interrupt"] -pub type PROC_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `PROC_DONE_INT_ENA` writer - The interrupt enable bit for the huk_proc_done_int interrupt"] -pub type PROC_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `POST_DONE_INT_ENA` reader - The interrupt enable bit for the huk_post_done_int interrupt"] -pub type POST_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `POST_DONE_INT_ENA` writer - The interrupt enable bit for the huk_post_done_int interrupt"] -pub type POST_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PREP_DONE` reader - The interrupt enable bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_R = crate::BitReader; +#[doc = "Field `PREP_DONE` writer - The interrupt enable bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC_DONE` reader - The interrupt enable bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_R = crate::BitReader; +#[doc = "Field `PROC_DONE` writer - The interrupt enable bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `POST_DONE` reader - The interrupt enable bit for the huk_post_done_int interrupt"] +pub type POST_DONE_R = crate::BitReader; +#[doc = "Field `POST_DONE` writer - The interrupt enable bit for the huk_post_done_int interrupt"] +pub type POST_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the huk_prep_done_int interrupt"] #[inline(always)] - pub fn prep_done_int_ena(&self) -> PREP_DONE_INT_ENA_R { - PREP_DONE_INT_ENA_R::new((self.bits & 1) != 0) + pub fn prep_done(&self) -> PREP_DONE_R { + PREP_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the huk_proc_done_int interrupt"] #[inline(always)] - pub fn proc_done_int_ena(&self) -> PROC_DONE_INT_ENA_R { - PROC_DONE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn proc_done(&self) -> PROC_DONE_R { + PROC_DONE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the huk_post_done_int interrupt"] #[inline(always)] - pub fn post_done_int_ena(&self) -> POST_DONE_INT_ENA_R { - POST_DONE_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn post_done(&self) -> POST_DONE_R { + POST_DONE_R::new(((self.bits >> 2) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ENA") - .field( - "prep_done_int_ena", - &format_args!("{}", self.prep_done_int_ena().bit()), - ) - .field( - "proc_done_int_ena", - &format_args!("{}", self.proc_done_int_ena().bit()), - ) - .field( - "post_done_int_ena", - &format_args!("{}", self.post_done_int_ena().bit()), - ) + .field("prep_done", &format_args!("{}", self.prep_done().bit())) + .field("proc_done", &format_args!("{}", self.proc_done().bit())) + .field("post_done", &format_args!("{}", self.post_done().bit())) .finish() } } @@ -60,20 +51,20 @@ impl W { #[doc = "Bit 0 - The interrupt enable bit for the huk_prep_done_int interrupt"] #[inline(always)] #[must_use] - pub fn prep_done_int_ena(&mut self) -> PREP_DONE_INT_ENA_W { - PREP_DONE_INT_ENA_W::new(self, 0) + pub fn prep_done(&mut self) -> PREP_DONE_W { + PREP_DONE_W::new(self, 0) } #[doc = "Bit 1 - The interrupt enable bit for the huk_proc_done_int interrupt"] #[inline(always)] #[must_use] - pub fn proc_done_int_ena(&mut self) -> PROC_DONE_INT_ENA_W { - PROC_DONE_INT_ENA_W::new(self, 1) + pub fn proc_done(&mut self) -> PROC_DONE_W { + PROC_DONE_W::new(self, 1) } #[doc = "Bit 2 - The interrupt enable bit for the huk_post_done_int interrupt"] #[inline(always)] #[must_use] - pub fn post_done_int_ena(&mut self) -> POST_DONE_INT_ENA_W { - POST_DONE_INT_ENA_W::new(self, 2) + pub fn post_done(&mut self) -> POST_DONE_W { + POST_DONE_W::new(self, 2) } } #[doc = "HUK Generator interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/lp_huk/int_raw.rs b/esp32p4/src/lp_huk/int_raw.rs index 289ca2723e..3f82183722 100644 --- a/esp32p4/src/lp_huk/int_raw.rs +++ b/esp32p4/src/lp_huk/int_raw.rs @@ -1,44 +1,35 @@ #[doc = "Register `INT_RAW` reader"] pub type R = crate::R; -#[doc = "Field `PREP_DONE_INT_RAW` reader - The raw interrupt status bit for the huk_prep_done_int interrupt"] -pub type PREP_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `PROC_DONE_INT_RAW` reader - The raw interrupt status bit for the huk_proc_done_int interrupt"] -pub type PROC_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `POST_DONE_INT_RAW` reader - The raw interrupt status bit for the huk_post_done_int interrupt"] -pub type POST_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `PREP_DONE` reader - The raw interrupt status bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_R = crate::BitReader; +#[doc = "Field `PROC_DONE` reader - The raw interrupt status bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_R = crate::BitReader; +#[doc = "Field `POST_DONE` reader - The raw interrupt status bit for the huk_post_done_int interrupt"] +pub type POST_DONE_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the huk_prep_done_int interrupt"] #[inline(always)] - pub fn prep_done_int_raw(&self) -> PREP_DONE_INT_RAW_R { - PREP_DONE_INT_RAW_R::new((self.bits & 1) != 0) + pub fn prep_done(&self) -> PREP_DONE_R { + PREP_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the huk_proc_done_int interrupt"] #[inline(always)] - pub fn proc_done_int_raw(&self) -> PROC_DONE_INT_RAW_R { - PROC_DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn proc_done(&self) -> PROC_DONE_R { + PROC_DONE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the huk_post_done_int interrupt"] #[inline(always)] - pub fn post_done_int_raw(&self) -> POST_DONE_INT_RAW_R { - POST_DONE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn post_done(&self) -> POST_DONE_R { + POST_DONE_R::new(((self.bits >> 2) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_RAW") - .field( - "prep_done_int_raw", - &format_args!("{}", self.prep_done_int_raw().bit()), - ) - .field( - "proc_done_int_raw", - &format_args!("{}", self.proc_done_int_raw().bit()), - ) - .field( - "post_done_int_raw", - &format_args!("{}", self.post_done_int_raw().bit()), - ) + .field("prep_done", &format_args!("{}", self.prep_done().bit())) + .field("proc_done", &format_args!("{}", self.proc_done().bit())) + .field("post_done", &format_args!("{}", self.post_done().bit())) .finish() } } diff --git a/esp32p4/src/lp_huk/int_st.rs b/esp32p4/src/lp_huk/int_st.rs index 01f5eba489..e104ddd77f 100644 --- a/esp32p4/src/lp_huk/int_st.rs +++ b/esp32p4/src/lp_huk/int_st.rs @@ -1,44 +1,35 @@ #[doc = "Register `INT_ST` reader"] pub type R = crate::R; -#[doc = "Field `PREP_DONE_INT_ST` reader - The masked interrupt status bit for the huk_prep_done_int interrupt"] -pub type PREP_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `PROC_DONE_INT_ST` reader - The masked interrupt status bit for the huk_proc_done_int interrupt"] -pub type PROC_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `POST_DONE_INT_ST` reader - The masked interrupt status bit for the huk_post_done_int interrupt"] -pub type POST_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `PREP_DONE` reader - The masked interrupt status bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_R = crate::BitReader; +#[doc = "Field `PROC_DONE` reader - The masked interrupt status bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_R = crate::BitReader; +#[doc = "Field `POST_DONE` reader - The masked interrupt status bit for the huk_post_done_int interrupt"] +pub type POST_DONE_R = crate::BitReader; impl R { #[doc = "Bit 0 - The masked interrupt status bit for the huk_prep_done_int interrupt"] #[inline(always)] - pub fn prep_done_int_st(&self) -> PREP_DONE_INT_ST_R { - PREP_DONE_INT_ST_R::new((self.bits & 1) != 0) + pub fn prep_done(&self) -> PREP_DONE_R { + PREP_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The masked interrupt status bit for the huk_proc_done_int interrupt"] #[inline(always)] - pub fn proc_done_int_st(&self) -> PROC_DONE_INT_ST_R { - PROC_DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn proc_done(&self) -> PROC_DONE_R { + PROC_DONE_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The masked interrupt status bit for the huk_post_done_int interrupt"] #[inline(always)] - pub fn post_done_int_st(&self) -> POST_DONE_INT_ST_R { - POST_DONE_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn post_done(&self) -> POST_DONE_R { + POST_DONE_R::new(((self.bits >> 2) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ST") - .field( - "prep_done_int_st", - &format_args!("{}", self.prep_done_int_st().bit()), - ) - .field( - "proc_done_int_st", - &format_args!("{}", self.proc_done_int_st().bit()), - ) - .field( - "post_done_int_st", - &format_args!("{}", self.post_done_int_st().bit()), - ) + .field("prep_done", &format_args!("{}", self.prep_done().bit())) + .field("proc_done", &format_args!("{}", self.proc_done().bit())) + .field("post_done", &format_args!("{}", self.post_done().bit())) .finish() } } diff --git a/esp32p4/src/lp_i2c0/int_clr.rs b/esp32p4/src/lp_i2c0/int_clr.rs index cbf855d6d8..0c2bf0f8c7 100644 --- a/esp32p4/src/lp_i2c0/int_clr.rs +++ b/esp32p4/src/lp_i2c0/int_clr.rs @@ -1,37 +1,37 @@ #[doc = "Register `INT_CLR` writer"] pub type W = crate::W; -#[doc = "Field `RXFIFO_WM_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."] -pub type RXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXFIFO_WM_INT_CLR` writer - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."] -pub type TXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_OVF_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."] -pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `END_DETECT_INT_CLR` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] -pub type END_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BYTE_TRANS_DONE_INT_CLR` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] -pub type BYTE_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ARBITRATION_LOST_INT_CLR` writer - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."] -pub type ARBITRATION_LOST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MST_TXFIFO_UDF_INT_CLR` writer - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."] -pub type MST_TXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANS_COMPLETE_INT_CLR` writer - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."] -pub type TRANS_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TIME_OUT_INT_CLR` writer - Write 1 to clear the I2C_TIME_OUT_INT interrupt."] -pub type TIME_OUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANS_START_INT_CLR` writer - Write 1 to clear the I2C_TRANS_START_INT interrupt."] -pub type TRANS_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `NACK_INT_CLR` writer - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] -pub type NACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXFIFO_OVF_INT_CLR` writer - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."] -pub type TXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_UDF_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."] -pub type RXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCL_ST_TO_INT_CLR` writer - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."] -pub type SCL_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCL_MAIN_ST_TO_INT_CLR` writer - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type SCL_MAIN_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DET_START_INT_CLR` writer - Write 1 to clear I2C_DET_START_INT interrupt."] -pub type DET_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_WM` writer - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TXFIFO_WM` writer - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXFIFO_OVF` writer - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `END_DETECT` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ARBITRATION_LOST` writer - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF` writer - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TRANS_COMPLETE` writer - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TIME_OUT` writer - Write 1 to clear the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TRANS_START` writer - Write 1 to clear the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `NACK` writer - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TXFIFO_OVF` writer - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXFIFO_UDF` writer - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SCL_ST_TO` writer - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO` writer - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DET_START` writer - Write 1 to clear I2C_DET_START_INT interrupt."] +pub type DET_START_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -42,98 +42,98 @@ impl W { #[doc = "Bit 0 - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_wm_int_clr(&mut self) -> RXFIFO_WM_INT_CLR_W { - RXFIFO_WM_INT_CLR_W::new(self, 0) + pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W { + RXFIFO_WM_W::new(self, 0) } #[doc = "Bit 1 - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."] #[inline(always)] #[must_use] - pub fn txfifo_wm_int_clr(&mut self) -> TXFIFO_WM_INT_CLR_W { - TXFIFO_WM_INT_CLR_W::new(self, 1) + pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W { + TXFIFO_WM_W::new(self, 1) } #[doc = "Bit 2 - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { - RXFIFO_OVF_INT_CLR_W::new(self, 2) + pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W { + RXFIFO_OVF_W::new(self, 2) } #[doc = "Bit 3 - Write 1 to clear the I2C_END_DETECT_INT interrupt."] #[inline(always)] #[must_use] - pub fn end_detect_int_clr(&mut self) -> END_DETECT_INT_CLR_W { - END_DETECT_INT_CLR_W::new(self, 3) + pub fn end_detect(&mut self) -> END_DETECT_W { + END_DETECT_W::new(self, 3) } #[doc = "Bit 4 - Write 1 to clear the I2C_END_DETECT_INT interrupt."] #[inline(always)] #[must_use] - pub fn byte_trans_done_int_clr(&mut self) -> BYTE_TRANS_DONE_INT_CLR_W { - BYTE_TRANS_DONE_INT_CLR_W::new(self, 4) + pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W { + BYTE_TRANS_DONE_W::new(self, 4) } #[doc = "Bit 5 - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."] #[inline(always)] #[must_use] - pub fn arbitration_lost_int_clr(&mut self) -> ARBITRATION_LOST_INT_CLR_W { - ARBITRATION_LOST_INT_CLR_W::new(self, 5) + pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W { + ARBITRATION_LOST_W::new(self, 5) } #[doc = "Bit 6 - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] #[must_use] - pub fn mst_txfifo_udf_int_clr(&mut self) -> MST_TXFIFO_UDF_INT_CLR_W { - MST_TXFIFO_UDF_INT_CLR_W::new(self, 6) + pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W { + MST_TXFIFO_UDF_W::new(self, 6) } #[doc = "Bit 7 - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] #[must_use] - pub fn trans_complete_int_clr(&mut self) -> TRANS_COMPLETE_INT_CLR_W { - TRANS_COMPLETE_INT_CLR_W::new(self, 7) + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { + TRANS_COMPLETE_W::new(self, 7) } #[doc = "Bit 8 - Write 1 to clear the I2C_TIME_OUT_INT interrupt."] #[inline(always)] #[must_use] - pub fn time_out_int_clr(&mut self) -> TIME_OUT_INT_CLR_W { - TIME_OUT_INT_CLR_W::new(self, 8) + pub fn time_out(&mut self) -> TIME_OUT_W { + TIME_OUT_W::new(self, 8) } #[doc = "Bit 9 - Write 1 to clear the I2C_TRANS_START_INT interrupt."] #[inline(always)] #[must_use] - pub fn trans_start_int_clr(&mut self) -> TRANS_START_INT_CLR_W { - TRANS_START_INT_CLR_W::new(self, 9) + pub fn trans_start(&mut self) -> TRANS_START_W { + TRANS_START_W::new(self, 9) } #[doc = "Bit 10 - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] #[inline(always)] #[must_use] - pub fn nack_int_clr(&mut self) -> NACK_INT_CLR_W { - NACK_INT_CLR_W::new(self, 10) + pub fn nack(&mut self) -> NACK_W { + NACK_W::new(self, 10) } #[doc = "Bit 11 - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."] #[inline(always)] #[must_use] - pub fn txfifo_ovf_int_clr(&mut self) -> TXFIFO_OVF_INT_CLR_W { - TXFIFO_OVF_INT_CLR_W::new(self, 11) + pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W { + TXFIFO_OVF_W::new(self, 11) } #[doc = "Bit 12 - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_udf_int_clr(&mut self) -> RXFIFO_UDF_INT_CLR_W { - RXFIFO_UDF_INT_CLR_W::new(self, 12) + pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W { + RXFIFO_UDF_W::new(self, 12) } #[doc = "Bit 13 - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."] #[inline(always)] #[must_use] - pub fn scl_st_to_int_clr(&mut self) -> SCL_ST_TO_INT_CLR_W { - SCL_ST_TO_INT_CLR_W::new(self, 13) + pub fn scl_st_to(&mut self) -> SCL_ST_TO_W { + SCL_ST_TO_W::new(self, 13) } #[doc = "Bit 14 - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] #[inline(always)] #[must_use] - pub fn scl_main_st_to_int_clr(&mut self) -> SCL_MAIN_ST_TO_INT_CLR_W { - SCL_MAIN_ST_TO_INT_CLR_W::new(self, 14) + pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W { + SCL_MAIN_ST_TO_W::new(self, 14) } #[doc = "Bit 15 - Write 1 to clear I2C_DET_START_INT interrupt."] #[inline(always)] #[must_use] - pub fn det_start_int_clr(&mut self) -> DET_START_INT_CLR_W { - DET_START_INT_CLR_W::new(self, 15) + pub fn det_start(&mut self) -> DET_START_W { + DET_START_W::new(self, 15) } } #[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -145,7 +145,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC { impl crate::Writable for INT_CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; } #[doc = "`reset()` method sets INT_CLR to value 0"] impl crate::Resettable for INT_CLR_SPEC { diff --git a/esp32p4/src/lp_i2c0/int_ena.rs b/esp32p4/src/lp_i2c0/int_ena.rs index 4dd09c1f6d..49ddad4190 100644 --- a/esp32p4/src/lp_i2c0/int_ena.rs +++ b/esp32p4/src/lp_i2c0/int_ena.rs @@ -2,220 +2,187 @@ pub type R = crate::R; #[doc = "Register `INT_ENA` writer"] pub type W = crate::W; -#[doc = "Field `RXFIFO_WM_INT_ENA` reader - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] -pub type RXFIFO_WM_INT_ENA_R = crate::BitReader; -#[doc = "Field `RXFIFO_WM_INT_ENA` writer - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] -pub type RXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXFIFO_WM_INT_ENA` reader - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] -pub type TXFIFO_WM_INT_ENA_R = crate::BitReader; -#[doc = "Field `TXFIFO_WM_INT_ENA` writer - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] -pub type TXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_OVF_INT_ENA` reader - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] -pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `RXFIFO_OVF_INT_ENA` writer - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] -pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `END_DETECT_INT_ENA` reader - Write 1 to anable the I2C_END_DETECT_INT interrupt."] -pub type END_DETECT_INT_ENA_R = crate::BitReader; -#[doc = "Field `END_DETECT_INT_ENA` writer - Write 1 to anable the I2C_END_DETECT_INT interrupt."] -pub type END_DETECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BYTE_TRANS_DONE_INT_ENA` reader - Write 1 to anable the I2C_END_DETECT_INT interrupt."] -pub type BYTE_TRANS_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `BYTE_TRANS_DONE_INT_ENA` writer - Write 1 to anable the I2C_END_DETECT_INT interrupt."] -pub type BYTE_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ARBITRATION_LOST_INT_ENA` reader - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] -pub type ARBITRATION_LOST_INT_ENA_R = crate::BitReader; -#[doc = "Field `ARBITRATION_LOST_INT_ENA` writer - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] -pub type ARBITRATION_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `MST_TXFIFO_UDF_INT_ENA` reader - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] -pub type MST_TXFIFO_UDF_INT_ENA_R = crate::BitReader; -#[doc = "Field `MST_TXFIFO_UDF_INT_ENA` writer - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] -pub type MST_TXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANS_COMPLETE_INT_ENA` reader - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] -pub type TRANS_COMPLETE_INT_ENA_R = crate::BitReader; -#[doc = "Field `TRANS_COMPLETE_INT_ENA` writer - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] -pub type TRANS_COMPLETE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TIME_OUT_INT_ENA` reader - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] -pub type TIME_OUT_INT_ENA_R = crate::BitReader; -#[doc = "Field `TIME_OUT_INT_ENA` writer - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] -pub type TIME_OUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRANS_START_INT_ENA` reader - Write 1 to anable the I2C_TRANS_START_INT interrupt."] -pub type TRANS_START_INT_ENA_R = crate::BitReader; -#[doc = "Field `TRANS_START_INT_ENA` writer - Write 1 to anable the I2C_TRANS_START_INT interrupt."] -pub type TRANS_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `NACK_INT_ENA` reader - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] -pub type NACK_INT_ENA_R = crate::BitReader; -#[doc = "Field `NACK_INT_ENA` writer - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] -pub type NACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXFIFO_OVF_INT_ENA` reader - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] -pub type TXFIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `TXFIFO_OVF_INT_ENA` writer - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] -pub type TXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_UDF_INT_ENA` reader - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] -pub type RXFIFO_UDF_INT_ENA_R = crate::BitReader; -#[doc = "Field `RXFIFO_UDF_INT_ENA` writer - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] -pub type RXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCL_ST_TO_INT_ENA` reader - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] -pub type SCL_ST_TO_INT_ENA_R = crate::BitReader; -#[doc = "Field `SCL_ST_TO_INT_ENA` writer - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] -pub type SCL_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SCL_MAIN_ST_TO_INT_ENA` reader - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type SCL_MAIN_ST_TO_INT_ENA_R = crate::BitReader; -#[doc = "Field `SCL_MAIN_ST_TO_INT_ENA` writer - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type SCL_MAIN_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DET_START_INT_ENA` reader - Write 1 to anable I2C_DET_START_INT interrupt."] -pub type DET_START_INT_ENA_R = crate::BitReader; -#[doc = "Field `DET_START_INT_ENA` writer - Write 1 to anable I2C_DET_START_INT interrupt."] -pub type DET_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_WM` reader - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_R = crate::BitReader; +#[doc = "Field `RXFIFO_WM` writer - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_WM` reader - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM` writer - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF` reader - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` writer - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `END_DETECT` reader - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_R = crate::BitReader; +#[doc = "Field `END_DETECT` writer - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE` reader - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE` writer - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_LOST` reader - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST` writer - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF` reader - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF` writer - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE` reader - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` writer - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIME_OUT` reader - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_R = crate::BitReader; +#[doc = "Field `TIME_OUT` writer - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START` reader - Write 1 to anable the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_R = crate::BitReader; +#[doc = "Field `TRANS_START` writer - Write 1 to anable the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACK` reader - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_R = crate::BitReader; +#[doc = "Field `NACK` writer - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_OVF` reader - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF` writer - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_UDF` reader - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF` writer - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_ST_TO` reader - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO` writer - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO` reader - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO` writer - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DET_START` reader - Write 1 to anable I2C_DET_START_INT interrupt."] +pub type DET_START_R = crate::BitReader; +#[doc = "Field `DET_START` writer - Write 1 to anable I2C_DET_START_INT interrupt."] +pub type DET_START_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] #[inline(always)] - pub fn rxfifo_wm_int_ena(&self) -> RXFIFO_WM_INT_ENA_R { - RXFIFO_WM_INT_ENA_R::new((self.bits & 1) != 0) + pub fn rxfifo_wm(&self) -> RXFIFO_WM_R { + RXFIFO_WM_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] #[inline(always)] - pub fn txfifo_wm_int_ena(&self) -> TXFIFO_WM_INT_ENA_R { - TXFIFO_WM_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn txfifo_wm(&self) -> TXFIFO_WM_R { + TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] #[inline(always)] - pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { - RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] #[inline(always)] - pub fn end_detect_int_ena(&self) -> END_DETECT_INT_ENA_R { - END_DETECT_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn end_detect(&self) -> END_DETECT_R { + END_DETECT_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] #[inline(always)] - pub fn byte_trans_done_int_ena(&self) -> BYTE_TRANS_DONE_INT_ENA_R { - BYTE_TRANS_DONE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R { + BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] #[inline(always)] - pub fn arbitration_lost_int_ena(&self) -> ARBITRATION_LOST_INT_ENA_R { - ARBITRATION_LOST_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R { + ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] - pub fn mst_txfifo_udf_int_ena(&self) -> MST_TXFIFO_UDF_INT_ENA_R { - MST_TXFIFO_UDF_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R { + MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] - pub fn trans_complete_int_ena(&self) -> TRANS_COMPLETE_INT_ENA_R { - TRANS_COMPLETE_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] #[inline(always)] - pub fn time_out_int_ena(&self) -> TIME_OUT_INT_ENA_R { - TIME_OUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn time_out(&self) -> TIME_OUT_R { + TIME_OUT_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - Write 1 to anable the I2C_TRANS_START_INT interrupt."] #[inline(always)] - pub fn trans_start_int_ena(&self) -> TRANS_START_INT_ENA_R { - TRANS_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn trans_start(&self) -> TRANS_START_R { + TRANS_START_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] #[inline(always)] - pub fn nack_int_ena(&self) -> NACK_INT_ENA_R { - NACK_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn nack(&self) -> NACK_R { + NACK_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] #[inline(always)] - pub fn txfifo_ovf_int_ena(&self) -> TXFIFO_OVF_INT_ENA_R { - TXFIFO_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R { + TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] #[inline(always)] - pub fn rxfifo_udf_int_ena(&self) -> RXFIFO_UDF_INT_ENA_R { - RXFIFO_UDF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R { + RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] #[inline(always)] - pub fn scl_st_to_int_ena(&self) -> SCL_ST_TO_INT_ENA_R { - SCL_ST_TO_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + pub fn scl_st_to(&self) -> SCL_ST_TO_R { + SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] #[inline(always)] - pub fn scl_main_st_to_int_ena(&self) -> SCL_MAIN_ST_TO_INT_ENA_R { - SCL_MAIN_ST_TO_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R { + SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - Write 1 to anable I2C_DET_START_INT interrupt."] #[inline(always)] - pub fn det_start_int_ena(&self) -> DET_START_INT_ENA_R { - DET_START_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + pub fn det_start(&self) -> DET_START_R { + DET_START_R::new(((self.bits >> 15) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ENA") + .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit())) + .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit())) + .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit())) + .field("end_detect", &format_args!("{}", self.end_detect().bit())) .field( - "rxfifo_wm_int_ena", - &format_args!("{}", self.rxfifo_wm_int_ena().bit()), + "byte_trans_done", + &format_args!("{}", self.byte_trans_done().bit()), ) .field( - "txfifo_wm_int_ena", - &format_args!("{}", self.txfifo_wm_int_ena().bit()), + "arbitration_lost", + &format_args!("{}", self.arbitration_lost().bit()), ) .field( - "rxfifo_ovf_int_ena", - &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), + "mst_txfifo_udf", + &format_args!("{}", self.mst_txfifo_udf().bit()), ) .field( - "end_detect_int_ena", - &format_args!("{}", self.end_detect_int_ena().bit()), + "trans_complete", + &format_args!("{}", self.trans_complete().bit()), ) + .field("time_out", &format_args!("{}", self.time_out().bit())) + .field("trans_start", &format_args!("{}", self.trans_start().bit())) + .field("nack", &format_args!("{}", self.nack().bit())) + .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit())) + .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit())) + .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit())) .field( - "byte_trans_done_int_ena", - &format_args!("{}", self.byte_trans_done_int_ena().bit()), - ) - .field( - "arbitration_lost_int_ena", - &format_args!("{}", self.arbitration_lost_int_ena().bit()), - ) - .field( - "mst_txfifo_udf_int_ena", - &format_args!("{}", self.mst_txfifo_udf_int_ena().bit()), - ) - .field( - "trans_complete_int_ena", - &format_args!("{}", self.trans_complete_int_ena().bit()), - ) - .field( - "time_out_int_ena", - &format_args!("{}", self.time_out_int_ena().bit()), - ) - .field( - "trans_start_int_ena", - &format_args!("{}", self.trans_start_int_ena().bit()), - ) - .field( - "nack_int_ena", - &format_args!("{}", self.nack_int_ena().bit()), - ) - .field( - "txfifo_ovf_int_ena", - &format_args!("{}", self.txfifo_ovf_int_ena().bit()), - ) - .field( - "rxfifo_udf_int_ena", - &format_args!("{}", self.rxfifo_udf_int_ena().bit()), - ) - .field( - "scl_st_to_int_ena", - &format_args!("{}", self.scl_st_to_int_ena().bit()), - ) - .field( - "scl_main_st_to_int_ena", - &format_args!("{}", self.scl_main_st_to_int_ena().bit()), - ) - .field( - "det_start_int_ena", - &format_args!("{}", self.det_start_int_ena().bit()), + "scl_main_st_to", + &format_args!("{}", self.scl_main_st_to().bit()), ) + .field("det_start", &format_args!("{}", self.det_start().bit())) .finish() } } @@ -229,98 +196,98 @@ impl W { #[doc = "Bit 0 - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_wm_int_ena(&mut self) -> RXFIFO_WM_INT_ENA_W { - RXFIFO_WM_INT_ENA_W::new(self, 0) + pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W { + RXFIFO_WM_W::new(self, 0) } #[doc = "Bit 1 - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] #[inline(always)] #[must_use] - pub fn txfifo_wm_int_ena(&mut self) -> TXFIFO_WM_INT_ENA_W { - TXFIFO_WM_INT_ENA_W::new(self, 1) + pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W { + TXFIFO_WM_W::new(self, 1) } #[doc = "Bit 2 - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { - RXFIFO_OVF_INT_ENA_W::new(self, 2) + pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W { + RXFIFO_OVF_W::new(self, 2) } #[doc = "Bit 3 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] #[inline(always)] #[must_use] - pub fn end_detect_int_ena(&mut self) -> END_DETECT_INT_ENA_W { - END_DETECT_INT_ENA_W::new(self, 3) + pub fn end_detect(&mut self) -> END_DETECT_W { + END_DETECT_W::new(self, 3) } #[doc = "Bit 4 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] #[inline(always)] #[must_use] - pub fn byte_trans_done_int_ena(&mut self) -> BYTE_TRANS_DONE_INT_ENA_W { - BYTE_TRANS_DONE_INT_ENA_W::new(self, 4) + pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W { + BYTE_TRANS_DONE_W::new(self, 4) } #[doc = "Bit 5 - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] #[inline(always)] #[must_use] - pub fn arbitration_lost_int_ena(&mut self) -> ARBITRATION_LOST_INT_ENA_W { - ARBITRATION_LOST_INT_ENA_W::new(self, 5) + pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W { + ARBITRATION_LOST_W::new(self, 5) } #[doc = "Bit 6 - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] #[must_use] - pub fn mst_txfifo_udf_int_ena(&mut self) -> MST_TXFIFO_UDF_INT_ENA_W { - MST_TXFIFO_UDF_INT_ENA_W::new(self, 6) + pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W { + MST_TXFIFO_UDF_W::new(self, 6) } #[doc = "Bit 7 - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] #[must_use] - pub fn trans_complete_int_ena(&mut self) -> TRANS_COMPLETE_INT_ENA_W { - TRANS_COMPLETE_INT_ENA_W::new(self, 7) + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { + TRANS_COMPLETE_W::new(self, 7) } #[doc = "Bit 8 - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] #[inline(always)] #[must_use] - pub fn time_out_int_ena(&mut self) -> TIME_OUT_INT_ENA_W { - TIME_OUT_INT_ENA_W::new(self, 8) + pub fn time_out(&mut self) -> TIME_OUT_W { + TIME_OUT_W::new(self, 8) } #[doc = "Bit 9 - Write 1 to anable the I2C_TRANS_START_INT interrupt."] #[inline(always)] #[must_use] - pub fn trans_start_int_ena(&mut self) -> TRANS_START_INT_ENA_W { - TRANS_START_INT_ENA_W::new(self, 9) + pub fn trans_start(&mut self) -> TRANS_START_W { + TRANS_START_W::new(self, 9) } #[doc = "Bit 10 - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] #[inline(always)] #[must_use] - pub fn nack_int_ena(&mut self) -> NACK_INT_ENA_W { - NACK_INT_ENA_W::new(self, 10) + pub fn nack(&mut self) -> NACK_W { + NACK_W::new(self, 10) } #[doc = "Bit 11 - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] #[inline(always)] #[must_use] - pub fn txfifo_ovf_int_ena(&mut self) -> TXFIFO_OVF_INT_ENA_W { - TXFIFO_OVF_INT_ENA_W::new(self, 11) + pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W { + TXFIFO_OVF_W::new(self, 11) } #[doc = "Bit 12 - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_udf_int_ena(&mut self) -> RXFIFO_UDF_INT_ENA_W { - RXFIFO_UDF_INT_ENA_W::new(self, 12) + pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W { + RXFIFO_UDF_W::new(self, 12) } #[doc = "Bit 13 - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] #[inline(always)] #[must_use] - pub fn scl_st_to_int_ena(&mut self) -> SCL_ST_TO_INT_ENA_W { - SCL_ST_TO_INT_ENA_W::new(self, 13) + pub fn scl_st_to(&mut self) -> SCL_ST_TO_W { + SCL_ST_TO_W::new(self, 13) } #[doc = "Bit 14 - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] #[inline(always)] #[must_use] - pub fn scl_main_st_to_int_ena(&mut self) -> SCL_MAIN_ST_TO_INT_ENA_W { - SCL_MAIN_ST_TO_INT_ENA_W::new(self, 14) + pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W { + SCL_MAIN_ST_TO_W::new(self, 14) } #[doc = "Bit 15 - Write 1 to anable I2C_DET_START_INT interrupt."] #[inline(always)] #[must_use] - pub fn det_start_int_ena(&mut self) -> DET_START_INT_ENA_W { - DET_START_INT_ENA_W::new(self, 15) + pub fn det_start(&mut self) -> DET_START_W { + DET_START_W::new(self, 15) } } #[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/lp_i2c0/int_raw.rs b/esp32p4/src/lp_i2c0/int_raw.rs index f0789cd745..ca5e8dae9b 100644 --- a/esp32p4/src/lp_i2c0/int_raw.rs +++ b/esp32p4/src/lp_i2c0/int_raw.rs @@ -1,187 +1,154 @@ #[doc = "Register `INT_RAW` reader"] pub type R = crate::R; -#[doc = "Field `RXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."] -pub type RXFIFO_WM_INT_RAW_R = crate::BitReader; -#[doc = "Field `TXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."] -pub type TXFIFO_WM_INT_RAW_R = crate::BitReader; -#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."] -pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `END_DETECT_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] -pub type END_DETECT_INT_RAW_R = crate::BitReader; -#[doc = "Field `BYTE_TRANS_DONE_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] -pub type BYTE_TRANS_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `ARBITRATION_LOST_INT_RAW` reader - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."] -pub type ARBITRATION_LOST_INT_RAW_R = crate::BitReader; -#[doc = "Field `MST_TXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."] -pub type MST_TXFIFO_UDF_INT_RAW_R = crate::BitReader; -#[doc = "Field `TRANS_COMPLETE_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."] -pub type TRANS_COMPLETE_INT_RAW_R = crate::BitReader; -#[doc = "Field `TIME_OUT_INT_RAW` reader - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."] -pub type TIME_OUT_INT_RAW_R = crate::BitReader; -#[doc = "Field `TRANS_START_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_START_INT interrupt."] -pub type TRANS_START_INT_RAW_R = crate::BitReader; -#[doc = "Field `NACK_INT_RAW` reader - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] -pub type NACK_INT_RAW_R = crate::BitReader; -#[doc = "Field `TXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."] -pub type TXFIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `RXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."] -pub type RXFIFO_UDF_INT_RAW_R = crate::BitReader; -#[doc = "Field `SCL_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."] -pub type SCL_ST_TO_INT_RAW_R = crate::BitReader; -#[doc = "Field `SCL_MAIN_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type SCL_MAIN_ST_TO_INT_RAW_R = crate::BitReader; -#[doc = "Field `DET_START_INT_RAW` reader - The raw interrupt status of I2C_DET_START_INT interrupt."] -pub type DET_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_WM` reader - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM` reader - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` reader - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `END_DETECT` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST` reader - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF` reader - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` reader - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TIME_OUT` reader - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_R = crate::BitReader; +#[doc = "Field `TRANS_START` reader - The raw interrupt status of the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_R = crate::BitReader; +#[doc = "Field `NACK` reader - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF` reader - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF` reader - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO` reader - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO` reader - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_R = crate::BitReader; +#[doc = "Field `DET_START` reader - The raw interrupt status of I2C_DET_START_INT interrupt."] +pub type DET_START_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."] #[inline(always)] - pub fn rxfifo_wm_int_raw(&self) -> RXFIFO_WM_INT_RAW_R { - RXFIFO_WM_INT_RAW_R::new((self.bits & 1) != 0) + pub fn rxfifo_wm(&self) -> RXFIFO_WM_R { + RXFIFO_WM_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."] #[inline(always)] - pub fn txfifo_wm_int_raw(&self) -> TXFIFO_WM_INT_RAW_R { - TXFIFO_WM_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn txfifo_wm(&self) -> TXFIFO_WM_R { + TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."] #[inline(always)] - pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { - RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] #[inline(always)] - pub fn end_detect_int_raw(&self) -> END_DETECT_INT_RAW_R { - END_DETECT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn end_detect(&self) -> END_DETECT_R { + END_DETECT_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] #[inline(always)] - pub fn byte_trans_done_int_raw(&self) -> BYTE_TRANS_DONE_INT_RAW_R { - BYTE_TRANS_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R { + BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."] #[inline(always)] - pub fn arbitration_lost_int_raw(&self) -> ARBITRATION_LOST_INT_RAW_R { - ARBITRATION_LOST_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R { + ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] - pub fn mst_txfifo_udf_int_raw(&self) -> MST_TXFIFO_UDF_INT_RAW_R { - MST_TXFIFO_UDF_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R { + MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] - pub fn trans_complete_int_raw(&self) -> TRANS_COMPLETE_INT_RAW_R { - TRANS_COMPLETE_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."] #[inline(always)] - pub fn time_out_int_raw(&self) -> TIME_OUT_INT_RAW_R { - TIME_OUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn time_out(&self) -> TIME_OUT_R { + TIME_OUT_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The raw interrupt status of the I2C_TRANS_START_INT interrupt."] #[inline(always)] - pub fn trans_start_int_raw(&self) -> TRANS_START_INT_RAW_R { - TRANS_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn trans_start(&self) -> TRANS_START_R { + TRANS_START_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] #[inline(always)] - pub fn nack_int_raw(&self) -> NACK_INT_RAW_R { - NACK_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn nack(&self) -> NACK_R { + NACK_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."] #[inline(always)] - pub fn txfifo_ovf_int_raw(&self) -> TXFIFO_OVF_INT_RAW_R { - TXFIFO_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R { + TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."] #[inline(always)] - pub fn rxfifo_udf_int_raw(&self) -> RXFIFO_UDF_INT_RAW_R { - RXFIFO_UDF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R { + RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."] #[inline(always)] - pub fn scl_st_to_int_raw(&self) -> SCL_ST_TO_INT_RAW_R { - SCL_ST_TO_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + pub fn scl_st_to(&self) -> SCL_ST_TO_R { + SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."] #[inline(always)] - pub fn scl_main_st_to_int_raw(&self) -> SCL_MAIN_ST_TO_INT_RAW_R { - SCL_MAIN_ST_TO_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R { + SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - The raw interrupt status of I2C_DET_START_INT interrupt."] #[inline(always)] - pub fn det_start_int_raw(&self) -> DET_START_INT_RAW_R { - DET_START_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + pub fn det_start(&self) -> DET_START_R { + DET_START_R::new(((self.bits >> 15) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_RAW") + .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit())) + .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit())) + .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit())) + .field("end_detect", &format_args!("{}", self.end_detect().bit())) .field( - "rxfifo_wm_int_raw", - &format_args!("{}", self.rxfifo_wm_int_raw().bit()), + "byte_trans_done", + &format_args!("{}", self.byte_trans_done().bit()), ) .field( - "txfifo_wm_int_raw", - &format_args!("{}", self.txfifo_wm_int_raw().bit()), + "arbitration_lost", + &format_args!("{}", self.arbitration_lost().bit()), ) .field( - "rxfifo_ovf_int_raw", - &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), + "mst_txfifo_udf", + &format_args!("{}", self.mst_txfifo_udf().bit()), ) .field( - "end_detect_int_raw", - &format_args!("{}", self.end_detect_int_raw().bit()), + "trans_complete", + &format_args!("{}", self.trans_complete().bit()), ) + .field("time_out", &format_args!("{}", self.time_out().bit())) + .field("trans_start", &format_args!("{}", self.trans_start().bit())) + .field("nack", &format_args!("{}", self.nack().bit())) + .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit())) + .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit())) + .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit())) .field( - "byte_trans_done_int_raw", - &format_args!("{}", self.byte_trans_done_int_raw().bit()), - ) - .field( - "arbitration_lost_int_raw", - &format_args!("{}", self.arbitration_lost_int_raw().bit()), - ) - .field( - "mst_txfifo_udf_int_raw", - &format_args!("{}", self.mst_txfifo_udf_int_raw().bit()), - ) - .field( - "trans_complete_int_raw", - &format_args!("{}", self.trans_complete_int_raw().bit()), - ) - .field( - "time_out_int_raw", - &format_args!("{}", self.time_out_int_raw().bit()), - ) - .field( - "trans_start_int_raw", - &format_args!("{}", self.trans_start_int_raw().bit()), - ) - .field( - "nack_int_raw", - &format_args!("{}", self.nack_int_raw().bit()), - ) - .field( - "txfifo_ovf_int_raw", - &format_args!("{}", self.txfifo_ovf_int_raw().bit()), - ) - .field( - "rxfifo_udf_int_raw", - &format_args!("{}", self.rxfifo_udf_int_raw().bit()), - ) - .field( - "scl_st_to_int_raw", - &format_args!("{}", self.scl_st_to_int_raw().bit()), - ) - .field( - "scl_main_st_to_int_raw", - &format_args!("{}", self.scl_main_st_to_int_raw().bit()), - ) - .field( - "det_start_int_raw", - &format_args!("{}", self.det_start_int_raw().bit()), + "scl_main_st_to", + &format_args!("{}", self.scl_main_st_to().bit()), ) + .field("det_start", &format_args!("{}", self.det_start().bit())) .finish() } } diff --git a/esp32p4/src/lp_i2c0/int_st.rs b/esp32p4/src/lp_i2c0/int_st.rs index e2616e8fe3..701d45384d 100644 --- a/esp32p4/src/lp_i2c0/int_st.rs +++ b/esp32p4/src/lp_i2c0/int_st.rs @@ -1,184 +1,154 @@ #[doc = "Register `INT_ST` reader"] pub type R = crate::R; -#[doc = "Field `RXFIFO_WM_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt."] -pub type RXFIFO_WM_INT_ST_R = crate::BitReader; -#[doc = "Field `TXFIFO_WM_INT_ST` reader - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt."] -pub type TXFIFO_WM_INT_ST_R = crate::BitReader; -#[doc = "Field `RXFIFO_OVF_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt."] -pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `END_DETECT_INT_ST` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] -pub type END_DETECT_INT_ST_R = crate::BitReader; -#[doc = "Field `BYTE_TRANS_DONE_INT_ST` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] -pub type BYTE_TRANS_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `ARBITRATION_LOST_INT_ST` reader - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt."] -pub type ARBITRATION_LOST_INT_ST_R = crate::BitReader; -#[doc = "Field `MST_TXFIFO_UDF_INT_ST` reader - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt."] -pub type MST_TXFIFO_UDF_INT_ST_R = crate::BitReader; -#[doc = "Field `TRANS_COMPLETE_INT_ST` reader - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt."] -pub type TRANS_COMPLETE_INT_ST_R = crate::BitReader; -#[doc = "Field `TIME_OUT_INT_ST` reader - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt."] -pub type TIME_OUT_INT_ST_R = crate::BitReader; -#[doc = "Field `TRANS_START_INT_ST` reader - The masked interrupt status status of the I2C_TRANS_START_INT interrupt."] -pub type TRANS_START_INT_ST_R = crate::BitReader; -#[doc = "Field `NACK_INT_ST` reader - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] -pub type NACK_INT_ST_R = crate::BitReader; -#[doc = "Field `TXFIFO_OVF_INT_ST` reader - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt."] -pub type TXFIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `RXFIFO_UDF_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt."] -pub type RXFIFO_UDF_INT_ST_R = crate::BitReader; -#[doc = "Field `SCL_ST_TO_INT_ST` reader - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt."] -pub type SCL_ST_TO_INT_ST_R = crate::BitReader; -#[doc = "Field `SCL_MAIN_ST_TO_INT_ST` reader - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt."] -pub type SCL_MAIN_ST_TO_INT_ST_R = crate::BitReader; -#[doc = "Field `DET_START_INT_ST` reader - The masked interrupt status status of I2C_DET_START_INT interrupt."] -pub type DET_START_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_WM` reader - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM` reader - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` reader - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `END_DETECT` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST` reader - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF` reader - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` reader - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TIME_OUT` reader - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_R = crate::BitReader; +#[doc = "Field `TRANS_START` reader - The masked interrupt status status of the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_R = crate::BitReader; +#[doc = "Field `NACK` reader - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF` reader - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF` reader - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO` reader - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO` reader - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_R = crate::BitReader; +#[doc = "Field `DET_START` reader - The masked interrupt status status of I2C_DET_START_INT interrupt."] +pub type DET_START_R = crate::BitReader; impl R { #[doc = "Bit 0 - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt."] #[inline(always)] - pub fn rxfifo_wm_int_st(&self) -> RXFIFO_WM_INT_ST_R { - RXFIFO_WM_INT_ST_R::new((self.bits & 1) != 0) + pub fn rxfifo_wm(&self) -> RXFIFO_WM_R { + RXFIFO_WM_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt."] #[inline(always)] - pub fn txfifo_wm_int_st(&self) -> TXFIFO_WM_INT_ST_R { - TXFIFO_WM_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn txfifo_wm(&self) -> TXFIFO_WM_R { + TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt."] #[inline(always)] - pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { - RXFIFO_OVF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] #[inline(always)] - pub fn end_detect_int_st(&self) -> END_DETECT_INT_ST_R { - END_DETECT_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn end_detect(&self) -> END_DETECT_R { + END_DETECT_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] #[inline(always)] - pub fn byte_trans_done_int_st(&self) -> BYTE_TRANS_DONE_INT_ST_R { - BYTE_TRANS_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R { + BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt."] #[inline(always)] - pub fn arbitration_lost_int_st(&self) -> ARBITRATION_LOST_INT_ST_R { - ARBITRATION_LOST_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R { + ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] - pub fn mst_txfifo_udf_int_st(&self) -> MST_TXFIFO_UDF_INT_ST_R { - MST_TXFIFO_UDF_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R { + MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt."] #[inline(always)] - pub fn trans_complete_int_st(&self) -> TRANS_COMPLETE_INT_ST_R { - TRANS_COMPLETE_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt."] #[inline(always)] - pub fn time_out_int_st(&self) -> TIME_OUT_INT_ST_R { - TIME_OUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn time_out(&self) -> TIME_OUT_R { + TIME_OUT_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - The masked interrupt status status of the I2C_TRANS_START_INT interrupt."] #[inline(always)] - pub fn trans_start_int_st(&self) -> TRANS_START_INT_ST_R { - TRANS_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn trans_start(&self) -> TRANS_START_R { + TRANS_START_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] #[inline(always)] - pub fn nack_int_st(&self) -> NACK_INT_ST_R { - NACK_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn nack(&self) -> NACK_R { + NACK_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt."] #[inline(always)] - pub fn txfifo_ovf_int_st(&self) -> TXFIFO_OVF_INT_ST_R { - TXFIFO_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R { + TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt."] #[inline(always)] - pub fn rxfifo_udf_int_st(&self) -> RXFIFO_UDF_INT_ST_R { - RXFIFO_UDF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R { + RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt."] #[inline(always)] - pub fn scl_st_to_int_st(&self) -> SCL_ST_TO_INT_ST_R { - SCL_ST_TO_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + pub fn scl_st_to(&self) -> SCL_ST_TO_R { + SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt."] #[inline(always)] - pub fn scl_main_st_to_int_st(&self) -> SCL_MAIN_ST_TO_INT_ST_R { - SCL_MAIN_ST_TO_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R { + SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 15 - The masked interrupt status status of I2C_DET_START_INT interrupt."] #[inline(always)] - pub fn det_start_int_st(&self) -> DET_START_INT_ST_R { - DET_START_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + pub fn det_start(&self) -> DET_START_R { + DET_START_R::new(((self.bits >> 15) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ST") + .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit())) + .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit())) + .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit())) + .field("end_detect", &format_args!("{}", self.end_detect().bit())) .field( - "rxfifo_wm_int_st", - &format_args!("{}", self.rxfifo_wm_int_st().bit()), + "byte_trans_done", + &format_args!("{}", self.byte_trans_done().bit()), ) .field( - "txfifo_wm_int_st", - &format_args!("{}", self.txfifo_wm_int_st().bit()), + "arbitration_lost", + &format_args!("{}", self.arbitration_lost().bit()), ) .field( - "rxfifo_ovf_int_st", - &format_args!("{}", self.rxfifo_ovf_int_st().bit()), + "mst_txfifo_udf", + &format_args!("{}", self.mst_txfifo_udf().bit()), ) .field( - "end_detect_int_st", - &format_args!("{}", self.end_detect_int_st().bit()), + "trans_complete", + &format_args!("{}", self.trans_complete().bit()), ) + .field("time_out", &format_args!("{}", self.time_out().bit())) + .field("trans_start", &format_args!("{}", self.trans_start().bit())) + .field("nack", &format_args!("{}", self.nack().bit())) + .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit())) + .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit())) + .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit())) .field( - "byte_trans_done_int_st", - &format_args!("{}", self.byte_trans_done_int_st().bit()), - ) - .field( - "arbitration_lost_int_st", - &format_args!("{}", self.arbitration_lost_int_st().bit()), - ) - .field( - "mst_txfifo_udf_int_st", - &format_args!("{}", self.mst_txfifo_udf_int_st().bit()), - ) - .field( - "trans_complete_int_st", - &format_args!("{}", self.trans_complete_int_st().bit()), - ) - .field( - "time_out_int_st", - &format_args!("{}", self.time_out_int_st().bit()), - ) - .field( - "trans_start_int_st", - &format_args!("{}", self.trans_start_int_st().bit()), - ) - .field("nack_int_st", &format_args!("{}", self.nack_int_st().bit())) - .field( - "txfifo_ovf_int_st", - &format_args!("{}", self.txfifo_ovf_int_st().bit()), - ) - .field( - "rxfifo_udf_int_st", - &format_args!("{}", self.rxfifo_udf_int_st().bit()), - ) - .field( - "scl_st_to_int_st", - &format_args!("{}", self.scl_st_to_int_st().bit()), - ) - .field( - "scl_main_st_to_int_st", - &format_args!("{}", self.scl_main_st_to_int_st().bit()), - ) - .field( - "det_start_int_st", - &format_args!("{}", self.det_start_int_st().bit()), + "scl_main_st_to", + &format_args!("{}", self.scl_main_st_to().bit()), ) + .field("det_start", &format_args!("{}", self.det_start().bit())) .finish() } } diff --git a/esp32p4/src/lp_i2s0/int_clr.rs b/esp32p4/src/lp_i2s0/int_clr.rs index 10d43c50e2..e0092a8ad1 100644 --- a/esp32p4/src/lp_i2s0/int_clr.rs +++ b/esp32p4/src/lp_i2s0/int_clr.rs @@ -1,17 +1,17 @@ #[doc = "Register `INT_CLR` writer"] pub type W = crate::W; -#[doc = "Field `RX_DONE_INT_CLR` writer - Set this bit to clear the i2s_rx_done_int interrupt"] -pub type RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_HUNG_INT_CLR` writer - Set this bit to clear the i2s_rx_hung_int interrupt"] -pub type RX_HUNG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_FIFOMEM_UDF_INT_CLR` writer - Set this bit to clear the i2s_rx_fifomem_udf_int interrupt"] -pub type RX_FIFOMEM_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LP_VAD_DONE_INT_CLR` writer - Set this bit to clear the vad_done_int interrupt"] -pub type LP_VAD_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LP_VAD_RESET_DONE_INT_CLR` writer - Set this bit to clear the vad_reset_done_int interrupt"] -pub type LP_VAD_RESET_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_MEM_THRESHOLD_INT_CLR` writer - Set this bit to clear the rx_mem_threshold_int interrupt"] -pub type RX_MEM_THRESHOLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DONE` writer - Set this bit to clear the i2s_rx_done_int interrupt"] +pub type RX_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RX_HUNG` writer - Set this bit to clear the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RX_FIFOMEM_UDF` writer - Set this bit to clear the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `LP_VAD_DONE` writer - Set this bit to clear the vad_done_int interrupt"] +pub type LP_VAD_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `LP_VAD_RESET_DONE` writer - Set this bit to clear the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RX_MEM_THRESHOLD` writer - Set this bit to clear the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -22,38 +22,38 @@ impl W { #[doc = "Bit 0 - Set this bit to clear the i2s_rx_done_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_done_int_clr(&mut self) -> RX_DONE_INT_CLR_W { - RX_DONE_INT_CLR_W::new(self, 0) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 0) } #[doc = "Bit 1 - Set this bit to clear the i2s_rx_hung_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_hung_int_clr(&mut self) -> RX_HUNG_INT_CLR_W { - RX_HUNG_INT_CLR_W::new(self, 1) + pub fn rx_hung(&mut self) -> RX_HUNG_W { + RX_HUNG_W::new(self, 1) } #[doc = "Bit 2 - Set this bit to clear the i2s_rx_fifomem_udf_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_fifomem_udf_int_clr(&mut self) -> RX_FIFOMEM_UDF_INT_CLR_W { - RX_FIFOMEM_UDF_INT_CLR_W::new(self, 2) + pub fn rx_fifomem_udf(&mut self) -> RX_FIFOMEM_UDF_W { + RX_FIFOMEM_UDF_W::new(self, 2) } #[doc = "Bit 3 - Set this bit to clear the vad_done_int interrupt"] #[inline(always)] #[must_use] - pub fn lp_vad_done_int_clr(&mut self) -> LP_VAD_DONE_INT_CLR_W { - LP_VAD_DONE_INT_CLR_W::new(self, 3) + pub fn lp_vad_done(&mut self) -> LP_VAD_DONE_W { + LP_VAD_DONE_W::new(self, 3) } #[doc = "Bit 4 - Set this bit to clear the vad_reset_done_int interrupt"] #[inline(always)] #[must_use] - pub fn lp_vad_reset_done_int_clr(&mut self) -> LP_VAD_RESET_DONE_INT_CLR_W { - LP_VAD_RESET_DONE_INT_CLR_W::new(self, 4) + pub fn lp_vad_reset_done(&mut self) -> LP_VAD_RESET_DONE_W { + LP_VAD_RESET_DONE_W::new(self, 4) } #[doc = "Bit 5 - Set this bit to clear the rx_mem_threshold_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_mem_threshold_int_clr(&mut self) -> RX_MEM_THRESHOLD_INT_CLR_W { - RX_MEM_THRESHOLD_INT_CLR_W::new(self, 5) + pub fn rx_mem_threshold(&mut self) -> RX_MEM_THRESHOLD_W { + RX_MEM_THRESHOLD_W::new(self, 5) } } #[doc = "I2S interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -65,7 +65,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC { impl crate::Writable for INT_CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } #[doc = "`reset()` method sets INT_CLR to value 0"] impl crate::Resettable for INT_CLR_SPEC { diff --git a/esp32p4/src/lp_i2s0/int_ena.rs b/esp32p4/src/lp_i2s0/int_ena.rs index 3dbc186b29..196537a937 100644 --- a/esp32p4/src/lp_i2s0/int_ena.rs +++ b/esp32p4/src/lp_i2s0/int_ena.rs @@ -2,89 +2,80 @@ pub type R = crate::R; #[doc = "Register `INT_ENA` writer"] pub type W = crate::W; -#[doc = "Field `RX_DONE_INT_ENA` reader - The interrupt enable bit for the i2s_rx_done_int interrupt"] -pub type RX_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `RX_DONE_INT_ENA` writer - The interrupt enable bit for the i2s_rx_done_int interrupt"] -pub type RX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_HUNG_INT_ENA` reader - The interrupt enable bit for the i2s_rx_hung_int interrupt"] -pub type RX_HUNG_INT_ENA_R = crate::BitReader; -#[doc = "Field `RX_HUNG_INT_ENA` writer - The interrupt enable bit for the i2s_rx_hung_int interrupt"] -pub type RX_HUNG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_FIFOMEM_UDF_INT_ENA` reader - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] -pub type RX_FIFOMEM_UDF_INT_ENA_R = crate::BitReader; -#[doc = "Field `RX_FIFOMEM_UDF_INT_ENA` writer - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] -pub type RX_FIFOMEM_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LP_VAD_DONE_INT_ENA` reader - The interrupt enable bit for the vad_done_int interrupt"] -pub type LP_VAD_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `LP_VAD_DONE_INT_ENA` writer - The interrupt enable bit for the vad_done_int interrupt"] -pub type LP_VAD_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LP_VAD_RESET_DONE_INT_ENA` reader - The interrupt enable bit for the vad_reset_done_int interrupt"] -pub type LP_VAD_RESET_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `LP_VAD_RESET_DONE_INT_ENA` writer - The interrupt enable bit for the vad_reset_done_int interrupt"] -pub type LP_VAD_RESET_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_MEM_THRESHOLD_INT_ENA` reader - The interrupt enable bit for the rx_mem_threshold_int interrupt"] -pub type RX_MEM_THRESHOLD_INT_ENA_R = crate::BitReader; -#[doc = "Field `RX_MEM_THRESHOLD_INT_ENA` writer - The interrupt enable bit for the rx_mem_threshold_int interrupt"] -pub type RX_MEM_THRESHOLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DONE` reader - The interrupt enable bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_R = crate::BitReader; +#[doc = "Field `RX_DONE` writer - The interrupt enable bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG` reader - The interrupt enable bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_R = crate::BitReader; +#[doc = "Field `RX_HUNG` writer - The interrupt enable bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFOMEM_UDF` reader - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_R = crate::BitReader; +#[doc = "Field `RX_FIFOMEM_UDF` writer - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VAD_DONE` reader - The interrupt enable bit for the vad_done_int interrupt"] +pub type LP_VAD_DONE_R = crate::BitReader; +#[doc = "Field `LP_VAD_DONE` writer - The interrupt enable bit for the vad_done_int interrupt"] +pub type LP_VAD_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VAD_RESET_DONE` reader - The interrupt enable bit for the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_R = crate::BitReader; +#[doc = "Field `LP_VAD_RESET_DONE` writer - The interrupt enable bit for the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MEM_THRESHOLD` reader - The interrupt enable bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_R = crate::BitReader; +#[doc = "Field `RX_MEM_THRESHOLD` writer - The interrupt enable bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"] #[inline(always)] - pub fn rx_done_int_ena(&self) -> RX_DONE_INT_ENA_R { - RX_DONE_INT_ENA_R::new((self.bits & 1) != 0) + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The interrupt enable bit for the i2s_rx_hung_int interrupt"] #[inline(always)] - pub fn rx_hung_int_ena(&self) -> RX_HUNG_INT_ENA_R { - RX_HUNG_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn rx_hung(&self) -> RX_HUNG_R { + RX_HUNG_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] #[inline(always)] - pub fn rx_fifomem_udf_int_ena(&self) -> RX_FIFOMEM_UDF_INT_ENA_R { - RX_FIFOMEM_UDF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn rx_fifomem_udf(&self) -> RX_FIFOMEM_UDF_R { + RX_FIFOMEM_UDF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The interrupt enable bit for the vad_done_int interrupt"] #[inline(always)] - pub fn lp_vad_done_int_ena(&self) -> LP_VAD_DONE_INT_ENA_R { - LP_VAD_DONE_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn lp_vad_done(&self) -> LP_VAD_DONE_R { + LP_VAD_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The interrupt enable bit for the vad_reset_done_int interrupt"] #[inline(always)] - pub fn lp_vad_reset_done_int_ena(&self) -> LP_VAD_RESET_DONE_INT_ENA_R { - LP_VAD_RESET_DONE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn lp_vad_reset_done(&self) -> LP_VAD_RESET_DONE_R { + LP_VAD_RESET_DONE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The interrupt enable bit for the rx_mem_threshold_int interrupt"] #[inline(always)] - pub fn rx_mem_threshold_int_ena(&self) -> RX_MEM_THRESHOLD_INT_ENA_R { - RX_MEM_THRESHOLD_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn rx_mem_threshold(&self) -> RX_MEM_THRESHOLD_R { + RX_MEM_THRESHOLD_R::new(((self.bits >> 5) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ENA") + .field("rx_done", &format_args!("{}", self.rx_done().bit())) + .field("rx_hung", &format_args!("{}", self.rx_hung().bit())) .field( - "rx_done_int_ena", - &format_args!("{}", self.rx_done_int_ena().bit()), + "rx_fifomem_udf", + &format_args!("{}", self.rx_fifomem_udf().bit()), ) + .field("lp_vad_done", &format_args!("{}", self.lp_vad_done().bit())) .field( - "rx_hung_int_ena", - &format_args!("{}", self.rx_hung_int_ena().bit()), + "lp_vad_reset_done", + &format_args!("{}", self.lp_vad_reset_done().bit()), ) .field( - "rx_fifomem_udf_int_ena", - &format_args!("{}", self.rx_fifomem_udf_int_ena().bit()), - ) - .field( - "lp_vad_done_int_ena", - &format_args!("{}", self.lp_vad_done_int_ena().bit()), - ) - .field( - "lp_vad_reset_done_int_ena", - &format_args!("{}", self.lp_vad_reset_done_int_ena().bit()), - ) - .field( - "rx_mem_threshold_int_ena", - &format_args!("{}", self.rx_mem_threshold_int_ena().bit()), + "rx_mem_threshold", + &format_args!("{}", self.rx_mem_threshold().bit()), ) .finish() } @@ -99,38 +90,38 @@ impl W { #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_done_int_ena(&mut self) -> RX_DONE_INT_ENA_W { - RX_DONE_INT_ENA_W::new(self, 0) + pub fn rx_done(&mut self) -> RX_DONE_W { + RX_DONE_W::new(self, 0) } #[doc = "Bit 1 - The interrupt enable bit for the i2s_rx_hung_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_hung_int_ena(&mut self) -> RX_HUNG_INT_ENA_W { - RX_HUNG_INT_ENA_W::new(self, 1) + pub fn rx_hung(&mut self) -> RX_HUNG_W { + RX_HUNG_W::new(self, 1) } #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_fifomem_udf_int_ena(&mut self) -> RX_FIFOMEM_UDF_INT_ENA_W { - RX_FIFOMEM_UDF_INT_ENA_W::new(self, 2) + pub fn rx_fifomem_udf(&mut self) -> RX_FIFOMEM_UDF_W { + RX_FIFOMEM_UDF_W::new(self, 2) } #[doc = "Bit 3 - The interrupt enable bit for the vad_done_int interrupt"] #[inline(always)] #[must_use] - pub fn lp_vad_done_int_ena(&mut self) -> LP_VAD_DONE_INT_ENA_W { - LP_VAD_DONE_INT_ENA_W::new(self, 3) + pub fn lp_vad_done(&mut self) -> LP_VAD_DONE_W { + LP_VAD_DONE_W::new(self, 3) } #[doc = "Bit 4 - The interrupt enable bit for the vad_reset_done_int interrupt"] #[inline(always)] #[must_use] - pub fn lp_vad_reset_done_int_ena(&mut self) -> LP_VAD_RESET_DONE_INT_ENA_W { - LP_VAD_RESET_DONE_INT_ENA_W::new(self, 4) + pub fn lp_vad_reset_done(&mut self) -> LP_VAD_RESET_DONE_W { + LP_VAD_RESET_DONE_W::new(self, 4) } #[doc = "Bit 5 - The interrupt enable bit for the rx_mem_threshold_int interrupt"] #[inline(always)] #[must_use] - pub fn rx_mem_threshold_int_ena(&mut self) -> RX_MEM_THRESHOLD_INT_ENA_W { - RX_MEM_THRESHOLD_INT_ENA_W::new(self, 5) + pub fn rx_mem_threshold(&mut self) -> RX_MEM_THRESHOLD_W { + RX_MEM_THRESHOLD_W::new(self, 5) } } #[doc = "I2S interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/lp_i2s0/int_raw.rs b/esp32p4/src/lp_i2s0/int_raw.rs index 908c21224c..c9469534de 100644 --- a/esp32p4/src/lp_i2s0/int_raw.rs +++ b/esp32p4/src/lp_i2s0/int_raw.rs @@ -1,76 +1,67 @@ #[doc = "Register `INT_RAW` reader"] pub type R = crate::R; -#[doc = "Field `RX_DONE_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_done_int interrupt"] -pub type RX_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `RX_HUNG_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_hung_int interrupt"] -pub type RX_HUNG_INT_RAW_R = crate::BitReader; -#[doc = "Field `RX_FIFOMEM_UDF_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] -pub type RX_FIFOMEM_UDF_INT_RAW_R = crate::BitReader; -#[doc = "Field `VAD_DONE_INT_RAW` reader - The raw interrupt status bit for the vad_done_int interrupt"] -pub type VAD_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `VAD_RESET_DONE_INT_RAW` reader - The raw interrupt status bit for the vad_reset_done_int interrupt"] -pub type VAD_RESET_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `RX_MEM_THRESHOLD_INT_RAW` reader - The raw interrupt status bit for the rx_mem_threshold_int interrupt"] -pub type RX_MEM_THRESHOLD_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_DONE` reader - The raw interrupt status bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_R = crate::BitReader; +#[doc = "Field `RX_HUNG` reader - The raw interrupt status bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_R = crate::BitReader; +#[doc = "Field `RX_FIFOMEM_UDF` reader - The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_R = crate::BitReader; +#[doc = "Field `VAD_DONE` reader - The raw interrupt status bit for the vad_done_int interrupt"] +pub type VAD_DONE_R = crate::BitReader; +#[doc = "Field `VAD_RESET_DONE` reader - The raw interrupt status bit for the vad_reset_done_int interrupt"] +pub type VAD_RESET_DONE_R = crate::BitReader; +#[doc = "Field `RX_MEM_THRESHOLD` reader - The raw interrupt status bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_R = crate::BitReader; impl R { #[doc = "Bit 0 - The raw interrupt status bit for the i2s_rx_done_int interrupt"] #[inline(always)] - pub fn rx_done_int_raw(&self) -> RX_DONE_INT_RAW_R { - RX_DONE_INT_RAW_R::new((self.bits & 1) != 0) + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The raw interrupt status bit for the i2s_rx_hung_int interrupt"] #[inline(always)] - pub fn rx_hung_int_raw(&self) -> RX_HUNG_INT_RAW_R { - RX_HUNG_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn rx_hung(&self) -> RX_HUNG_R { + RX_HUNG_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] #[inline(always)] - pub fn rx_fifomem_udf_int_raw(&self) -> RX_FIFOMEM_UDF_INT_RAW_R { - RX_FIFOMEM_UDF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn rx_fifomem_udf(&self) -> RX_FIFOMEM_UDF_R { + RX_FIFOMEM_UDF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The raw interrupt status bit for the vad_done_int interrupt"] #[inline(always)] - pub fn vad_done_int_raw(&self) -> VAD_DONE_INT_RAW_R { - VAD_DONE_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn vad_done(&self) -> VAD_DONE_R { + VAD_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The raw interrupt status bit for the vad_reset_done_int interrupt"] #[inline(always)] - pub fn vad_reset_done_int_raw(&self) -> VAD_RESET_DONE_INT_RAW_R { - VAD_RESET_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn vad_reset_done(&self) -> VAD_RESET_DONE_R { + VAD_RESET_DONE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The raw interrupt status bit for the rx_mem_threshold_int interrupt"] #[inline(always)] - pub fn rx_mem_threshold_int_raw(&self) -> RX_MEM_THRESHOLD_INT_RAW_R { - RX_MEM_THRESHOLD_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn rx_mem_threshold(&self) -> RX_MEM_THRESHOLD_R { + RX_MEM_THRESHOLD_R::new(((self.bits >> 5) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_RAW") + .field("rx_done", &format_args!("{}", self.rx_done().bit())) + .field("rx_hung", &format_args!("{}", self.rx_hung().bit())) .field( - "rx_done_int_raw", - &format_args!("{}", self.rx_done_int_raw().bit()), + "rx_fifomem_udf", + &format_args!("{}", self.rx_fifomem_udf().bit()), ) + .field("vad_done", &format_args!("{}", self.vad_done().bit())) .field( - "rx_hung_int_raw", - &format_args!("{}", self.rx_hung_int_raw().bit()), + "vad_reset_done", + &format_args!("{}", self.vad_reset_done().bit()), ) .field( - "rx_fifomem_udf_int_raw", - &format_args!("{}", self.rx_fifomem_udf_int_raw().bit()), - ) - .field( - "vad_done_int_raw", - &format_args!("{}", self.vad_done_int_raw().bit()), - ) - .field( - "vad_reset_done_int_raw", - &format_args!("{}", self.vad_reset_done_int_raw().bit()), - ) - .field( - "rx_mem_threshold_int_raw", - &format_args!("{}", self.rx_mem_threshold_int_raw().bit()), + "rx_mem_threshold", + &format_args!("{}", self.rx_mem_threshold().bit()), ) .finish() } diff --git a/esp32p4/src/lp_i2s0/int_st.rs b/esp32p4/src/lp_i2s0/int_st.rs index 08488caba8..6dda97ec0b 100644 --- a/esp32p4/src/lp_i2s0/int_st.rs +++ b/esp32p4/src/lp_i2s0/int_st.rs @@ -1,76 +1,67 @@ #[doc = "Register `INT_ST` reader"] pub type R = crate::R; -#[doc = "Field `RX_DONE_INT_ST` reader - The masked interrupt status bit for the i2s_rx_done_int interrupt"] -pub type RX_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `RX_HUNG_INT_ST` reader - The masked interrupt status bit for the i2s_rx_hung_int interrupt"] -pub type RX_HUNG_INT_ST_R = crate::BitReader; -#[doc = "Field `RX_FIFOMEM_UDF_INT_ST` reader - The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] -pub type RX_FIFOMEM_UDF_INT_ST_R = crate::BitReader; -#[doc = "Field `LP_VAD_DONE_INT_ST` reader - The masked interrupt status bit for the vad_done_int interrupt"] -pub type LP_VAD_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `LP_VAD_RESET_DONE_INT_ST` reader - The masked interrupt status bit for the vad_reset_done_int interrupt"] -pub type LP_VAD_RESET_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `RX_MEM_THRESHOLD_INT_ST` reader - The masked interrupt status bit for the rx_mem_threshold_int interrupt"] -pub type RX_MEM_THRESHOLD_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_DONE` reader - The masked interrupt status bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_R = crate::BitReader; +#[doc = "Field `RX_HUNG` reader - The masked interrupt status bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_R = crate::BitReader; +#[doc = "Field `RX_FIFOMEM_UDF` reader - The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_R = crate::BitReader; +#[doc = "Field `LP_VAD_DONE` reader - The masked interrupt status bit for the vad_done_int interrupt"] +pub type LP_VAD_DONE_R = crate::BitReader; +#[doc = "Field `LP_VAD_RESET_DONE` reader - The masked interrupt status bit for the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_R = crate::BitReader; +#[doc = "Field `RX_MEM_THRESHOLD` reader - The masked interrupt status bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_R = crate::BitReader; impl R { #[doc = "Bit 0 - The masked interrupt status bit for the i2s_rx_done_int interrupt"] #[inline(always)] - pub fn rx_done_int_st(&self) -> RX_DONE_INT_ST_R { - RX_DONE_INT_ST_R::new((self.bits & 1) != 0) + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - The masked interrupt status bit for the i2s_rx_hung_int interrupt"] #[inline(always)] - pub fn rx_hung_int_st(&self) -> RX_HUNG_INT_ST_R { - RX_HUNG_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn rx_hung(&self) -> RX_HUNG_R { + RX_HUNG_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] #[inline(always)] - pub fn rx_fifomem_udf_int_st(&self) -> RX_FIFOMEM_UDF_INT_ST_R { - RX_FIFOMEM_UDF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn rx_fifomem_udf(&self) -> RX_FIFOMEM_UDF_R { + RX_FIFOMEM_UDF_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - The masked interrupt status bit for the vad_done_int interrupt"] #[inline(always)] - pub fn lp_vad_done_int_st(&self) -> LP_VAD_DONE_INT_ST_R { - LP_VAD_DONE_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn lp_vad_done(&self) -> LP_VAD_DONE_R { + LP_VAD_DONE_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The masked interrupt status bit for the vad_reset_done_int interrupt"] #[inline(always)] - pub fn lp_vad_reset_done_int_st(&self) -> LP_VAD_RESET_DONE_INT_ST_R { - LP_VAD_RESET_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn lp_vad_reset_done(&self) -> LP_VAD_RESET_DONE_R { + LP_VAD_RESET_DONE_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - The masked interrupt status bit for the rx_mem_threshold_int interrupt"] #[inline(always)] - pub fn rx_mem_threshold_int_st(&self) -> RX_MEM_THRESHOLD_INT_ST_R { - RX_MEM_THRESHOLD_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn rx_mem_threshold(&self) -> RX_MEM_THRESHOLD_R { + RX_MEM_THRESHOLD_R::new(((self.bits >> 5) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ST") + .field("rx_done", &format_args!("{}", self.rx_done().bit())) + .field("rx_hung", &format_args!("{}", self.rx_hung().bit())) .field( - "rx_done_int_st", - &format_args!("{}", self.rx_done_int_st().bit()), + "rx_fifomem_udf", + &format_args!("{}", self.rx_fifomem_udf().bit()), ) + .field("lp_vad_done", &format_args!("{}", self.lp_vad_done().bit())) .field( - "rx_hung_int_st", - &format_args!("{}", self.rx_hung_int_st().bit()), + "lp_vad_reset_done", + &format_args!("{}", self.lp_vad_reset_done().bit()), ) .field( - "rx_fifomem_udf_int_st", - &format_args!("{}", self.rx_fifomem_udf_int_st().bit()), - ) - .field( - "lp_vad_done_int_st", - &format_args!("{}", self.lp_vad_done_int_st().bit()), - ) - .field( - "lp_vad_reset_done_int_st", - &format_args!("{}", self.lp_vad_reset_done_int_st().bit()), - ) - .field( - "rx_mem_threshold_int_st", - &format_args!("{}", self.rx_mem_threshold_int_st().bit()), + "rx_mem_threshold", + &format_args!("{}", self.rx_mem_threshold().bit()), ) .finish() } diff --git a/esp32p4/src/lp_uart/int_clr.rs b/esp32p4/src/lp_uart/int_clr.rs index 1ce042d7ed..859bc4c1b3 100644 --- a/esp32p4/src/lp_uart/int_clr.rs +++ b/esp32p4/src/lp_uart/int_clr.rs @@ -1,39 +1,39 @@ #[doc = "Register `INT_CLR` writer"] pub type W = crate::W; -#[doc = "Field `RXFIFO_FULL_INT_CLR` writer - Set this bit to clear the rxfifo_full_int_raw interrupt."] -pub type RXFIFO_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXFIFO_EMPTY_INT_CLR` writer - Set this bit to clear txfifo_empty_int_raw interrupt."] -pub type TXFIFO_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PARITY_ERR_INT_CLR` writer - Set this bit to clear parity_err_int_raw interrupt."] -pub type PARITY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FRM_ERR_INT_CLR` writer - Set this bit to clear frm_err_int_raw interrupt."] -pub type FRM_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_OVF_INT_CLR` writer - Set this bit to clear rxfifo_ovf_int_raw interrupt."] -pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DSR_CHG_INT_CLR` writer - Set this bit to clear the dsr_chg_int_raw interrupt."] -pub type DSR_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CTS_CHG_INT_CLR` writer - Set this bit to clear the cts_chg_int_raw interrupt."] -pub type CTS_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRK_DET_INT_CLR` writer - Set this bit to clear the brk_det_int_raw interrupt."] -pub type BRK_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_TOUT_INT_CLR` writer - Set this bit to clear the rxfifo_tout_int_raw interrupt."] -pub type RXFIFO_TOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SW_XON_INT_CLR` writer - Set this bit to clear the sw_xon_int_raw interrupt."] -pub type SW_XON_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SW_XOFF_INT_CLR` writer - Set this bit to clear the sw_xoff_int_raw interrupt."] -pub type SW_XOFF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GLITCH_DET_INT_CLR` writer - Set this bit to clear the glitch_det_int_raw interrupt."] -pub type GLITCH_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_BRK_DONE_INT_CLR` writer - Set this bit to clear the tx_brk_done_int_raw interrupt.."] -pub type TX_BRK_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_BRK_IDLE_DONE_INT_CLR` writer - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."] -pub type TX_BRK_IDLE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DONE_INT_CLR` writer - Set this bit to clear the tx_done_int_raw interrupt."] -pub type TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AT_CMD_CHAR_DET_INT_CLR` writer - Set this bit to clear the at_cmd_char_det_int_raw interrupt."] -pub type AT_CMD_CHAR_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `WAKEUP_INT_CLR` writer - Set this bit to clear the uart_wakeup_int_raw interrupt."] -pub type WAKEUP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_FULL` writer - Set this bit to clear the rxfifo_full_int_raw interrupt."] +pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY` writer - Set this bit to clear txfifo_empty_int_raw interrupt."] +pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `PARITY_ERR` writer - Set this bit to clear parity_err_int_raw interrupt."] +pub type PARITY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `FRM_ERR` writer - Set this bit to clear frm_err_int_raw interrupt."] +pub type FRM_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXFIFO_OVF` writer - Set this bit to clear rxfifo_ovf_int_raw interrupt."] +pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DSR_CHG` writer - Set this bit to clear the dsr_chg_int_raw interrupt."] +pub type DSR_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CTS_CHG` writer - Set this bit to clear the cts_chg_int_raw interrupt."] +pub type CTS_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BRK_DET` writer - Set this bit to clear the brk_det_int_raw interrupt."] +pub type BRK_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXFIFO_TOUT` writer - Set this bit to clear the rxfifo_tout_int_raw interrupt."] +pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SW_XON` writer - Set this bit to clear the sw_xon_int_raw interrupt."] +pub type SW_XON_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SW_XOFF` writer - Set this bit to clear the sw_xoff_int_raw interrupt."] +pub type SW_XOFF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GLITCH_DET` writer - Set this bit to clear the glitch_det_int_raw interrupt."] +pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TX_BRK_DONE` writer - Set this bit to clear the tx_brk_done_int_raw interrupt.."] +pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE` writer - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."] +pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TX_DONE` writer - Set this bit to clear the tx_done_int_raw interrupt."] +pub type TX_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET` writer - Set this bit to clear the at_cmd_char_det_int_raw interrupt."] +pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `WAKEUP` writer - Set this bit to clear the uart_wakeup_int_raw interrupt."] +pub type WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -44,104 +44,104 @@ impl W { #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W { - RXFIFO_FULL_INT_CLR_W::new(self, 0) + pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W { + RXFIFO_FULL_W::new(self, 0) } #[doc = "Bit 1 - Set this bit to clear txfifo_empty_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W { - TXFIFO_EMPTY_INT_CLR_W::new(self, 1) + pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W { + TXFIFO_EMPTY_W::new(self, 1) } #[doc = "Bit 2 - Set this bit to clear parity_err_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn parity_err_int_clr(&mut self) -> PARITY_ERR_INT_CLR_W { - PARITY_ERR_INT_CLR_W::new(self, 2) + pub fn parity_err(&mut self) -> PARITY_ERR_W { + PARITY_ERR_W::new(self, 2) } #[doc = "Bit 3 - Set this bit to clear frm_err_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn frm_err_int_clr(&mut self) -> FRM_ERR_INT_CLR_W { - FRM_ERR_INT_CLR_W::new(self, 3) + pub fn frm_err(&mut self) -> FRM_ERR_W { + FRM_ERR_W::new(self, 3) } #[doc = "Bit 4 - Set this bit to clear rxfifo_ovf_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { - RXFIFO_OVF_INT_CLR_W::new(self, 4) + pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W { + RXFIFO_OVF_W::new(self, 4) } #[doc = "Bit 5 - Set this bit to clear the dsr_chg_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn dsr_chg_int_clr(&mut self) -> DSR_CHG_INT_CLR_W { - DSR_CHG_INT_CLR_W::new(self, 5) + pub fn dsr_chg(&mut self) -> DSR_CHG_W { + DSR_CHG_W::new(self, 5) } #[doc = "Bit 6 - Set this bit to clear the cts_chg_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn cts_chg_int_clr(&mut self) -> CTS_CHG_INT_CLR_W { - CTS_CHG_INT_CLR_W::new(self, 6) + pub fn cts_chg(&mut self) -> CTS_CHG_W { + CTS_CHG_W::new(self, 6) } #[doc = "Bit 7 - Set this bit to clear the brk_det_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn brk_det_int_clr(&mut self) -> BRK_DET_INT_CLR_W { - BRK_DET_INT_CLR_W::new(self, 7) + pub fn brk_det(&mut self) -> BRK_DET_W { + BRK_DET_W::new(self, 7) } #[doc = "Bit 8 - Set this bit to clear the rxfifo_tout_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn rxfifo_tout_int_clr(&mut self) -> RXFIFO_TOUT_INT_CLR_W { - RXFIFO_TOUT_INT_CLR_W::new(self, 8) + pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W { + RXFIFO_TOUT_W::new(self, 8) } #[doc = "Bit 9 - Set this bit to clear the sw_xon_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn sw_xon_int_clr(&mut self) -> SW_XON_INT_CLR_W { - SW_XON_INT_CLR_W::new(self, 9) + pub fn sw_xon(&mut self) -> SW_XON_W { + SW_XON_W::new(self, 9) } #[doc = "Bit 10 - Set this bit to clear the sw_xoff_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn sw_xoff_int_clr(&mut self) -> SW_XOFF_INT_CLR_W { - SW_XOFF_INT_CLR_W::new(self, 10) + pub fn sw_xoff(&mut self) -> SW_XOFF_W { + SW_XOFF_W::new(self, 10) } #[doc = "Bit 11 - Set this bit to clear the glitch_det_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn glitch_det_int_clr(&mut self) -> GLITCH_DET_INT_CLR_W { - GLITCH_DET_INT_CLR_W::new(self, 11) + pub fn glitch_det(&mut self) -> GLITCH_DET_W { + GLITCH_DET_W::new(self, 11) } #[doc = "Bit 12 - Set this bit to clear the tx_brk_done_int_raw interrupt.."] #[inline(always)] #[must_use] - pub fn tx_brk_done_int_clr(&mut self) -> TX_BRK_DONE_INT_CLR_W { - TX_BRK_DONE_INT_CLR_W::new(self, 12) + pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W { + TX_BRK_DONE_W::new(self, 12) } #[doc = "Bit 13 - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn tx_brk_idle_done_int_clr(&mut self) -> TX_BRK_IDLE_DONE_INT_CLR_W { - TX_BRK_IDLE_DONE_INT_CLR_W::new(self, 13) + pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W { + TX_BRK_IDLE_DONE_W::new(self, 13) } #[doc = "Bit 14 - Set this bit to clear the tx_done_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn tx_done_int_clr(&mut self) -> TX_DONE_INT_CLR_W { - TX_DONE_INT_CLR_W::new(self, 14) + pub fn tx_done(&mut self) -> TX_DONE_W { + TX_DONE_W::new(self, 14) } #[doc = "Bit 18 - Set this bit to clear the at_cmd_char_det_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn at_cmd_char_det_int_clr(&mut self) -> AT_CMD_CHAR_DET_INT_CLR_W { - AT_CMD_CHAR_DET_INT_CLR_W::new(self, 18) + pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W { + AT_CMD_CHAR_DET_W::new(self, 18) } #[doc = "Bit 19 - Set this bit to clear the uart_wakeup_int_raw interrupt."] #[inline(always)] #[must_use] - pub fn wakeup_int_clr(&mut self) -> WAKEUP_INT_CLR_W { - WAKEUP_INT_CLR_W::new(self, 19) + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W::new(self, 19) } } #[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -153,7 +153,7 @@ impl crate::RegisterSpec for INT_CLR_SPEC { impl crate::Writable for INT_CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000c_7fff; } #[doc = "`reset()` method sets INT_CLR to value 0"] impl crate::Resettable for INT_CLR_SPEC { diff --git a/esp32p4/src/lp_uart/int_ena.rs b/esp32p4/src/lp_uart/int_ena.rs index e7fa6241b2..3d91b96662 100644 --- a/esp32p4/src/lp_uart/int_ena.rs +++ b/esp32p4/src/lp_uart/int_ena.rs @@ -2,233 +2,191 @@ pub type R = crate::R; #[doc = "Register `INT_ENA` writer"] pub type W = crate::W; -#[doc = "Field `RXFIFO_FULL_INT_ENA` reader - This is the enable bit for rxfifo_full_int_st register."] -pub type RXFIFO_FULL_INT_ENA_R = crate::BitReader; -#[doc = "Field `RXFIFO_FULL_INT_ENA` writer - This is the enable bit for rxfifo_full_int_st register."] -pub type RXFIFO_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXFIFO_EMPTY_INT_ENA` reader - This is the enable bit for txfifo_empty_int_st register."] -pub type TXFIFO_EMPTY_INT_ENA_R = crate::BitReader; -#[doc = "Field `TXFIFO_EMPTY_INT_ENA` writer - This is the enable bit for txfifo_empty_int_st register."] -pub type TXFIFO_EMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PARITY_ERR_INT_ENA` reader - This is the enable bit for parity_err_int_st register."] -pub type PARITY_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `PARITY_ERR_INT_ENA` writer - This is the enable bit for parity_err_int_st register."] -pub type PARITY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FRM_ERR_INT_ENA` reader - This is the enable bit for frm_err_int_st register."] -pub type FRM_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `FRM_ERR_INT_ENA` writer - This is the enable bit for frm_err_int_st register."] -pub type FRM_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_OVF_INT_ENA` reader - This is the enable bit for rxfifo_ovf_int_st register."] -pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `RXFIFO_OVF_INT_ENA` writer - This is the enable bit for rxfifo_ovf_int_st register."] -pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DSR_CHG_INT_ENA` reader - This is the enable bit for dsr_chg_int_st register."] -pub type DSR_CHG_INT_ENA_R = crate::BitReader; -#[doc = "Field `DSR_CHG_INT_ENA` writer - This is the enable bit for dsr_chg_int_st register."] -pub type DSR_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CTS_CHG_INT_ENA` reader - This is the enable bit for cts_chg_int_st register."] -pub type CTS_CHG_INT_ENA_R = crate::BitReader; -#[doc = "Field `CTS_CHG_INT_ENA` writer - This is the enable bit for cts_chg_int_st register."] -pub type CTS_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRK_DET_INT_ENA` reader - This is the enable bit for brk_det_int_st register."] -pub type BRK_DET_INT_ENA_R = crate::BitReader; -#[doc = "Field `BRK_DET_INT_ENA` writer - This is the enable bit for brk_det_int_st register."] -pub type BRK_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_TOUT_INT_ENA` reader - This is the enable bit for rxfifo_tout_int_st register."] -pub type RXFIFO_TOUT_INT_ENA_R = crate::BitReader; -#[doc = "Field `RXFIFO_TOUT_INT_ENA` writer - This is the enable bit for rxfifo_tout_int_st register."] -pub type RXFIFO_TOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SW_XON_INT_ENA` reader - This is the enable bit for sw_xon_int_st register."] -pub type SW_XON_INT_ENA_R = crate::BitReader; -#[doc = "Field `SW_XON_INT_ENA` writer - This is the enable bit for sw_xon_int_st register."] -pub type SW_XON_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SW_XOFF_INT_ENA` reader - This is the enable bit for sw_xoff_int_st register."] -pub type SW_XOFF_INT_ENA_R = crate::BitReader; -#[doc = "Field `SW_XOFF_INT_ENA` writer - This is the enable bit for sw_xoff_int_st register."] -pub type SW_XOFF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GLITCH_DET_INT_ENA` reader - This is the enable bit for glitch_det_int_st register."] -pub type GLITCH_DET_INT_ENA_R = crate::BitReader; -#[doc = "Field `GLITCH_DET_INT_ENA` writer - This is the enable bit for glitch_det_int_st register."] -pub type GLITCH_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_BRK_DONE_INT_ENA` reader - This is the enable bit for tx_brk_done_int_st register."] -pub type TX_BRK_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `TX_BRK_DONE_INT_ENA` writer - This is the enable bit for tx_brk_done_int_st register."] -pub type TX_BRK_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_BRK_IDLE_DONE_INT_ENA` reader - This is the enable bit for tx_brk_idle_done_int_st register."] -pub type TX_BRK_IDLE_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `TX_BRK_IDLE_DONE_INT_ENA` writer - This is the enable bit for tx_brk_idle_done_int_st register."] -pub type TX_BRK_IDLE_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DONE_INT_ENA` reader - This is the enable bit for tx_done_int_st register."] -pub type TX_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `TX_DONE_INT_ENA` writer - This is the enable bit for tx_done_int_st register."] -pub type TX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AT_CMD_CHAR_DET_INT_ENA` reader - This is the enable bit for at_cmd_char_det_int_st register."] -pub type AT_CMD_CHAR_DET_INT_ENA_R = crate::BitReader; -#[doc = "Field `AT_CMD_CHAR_DET_INT_ENA` writer - This is the enable bit for at_cmd_char_det_int_st register."] -pub type AT_CMD_CHAR_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `WAKEUP_INT_ENA` reader - This is the enable bit for uart_wakeup_int_st register."] -pub type WAKEUP_INT_ENA_R = crate::BitReader; -#[doc = "Field `WAKEUP_INT_ENA` writer - This is the enable bit for uart_wakeup_int_st register."] -pub type WAKEUP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_FULL` reader - This is the enable bit for rxfifo_full_int_st register."] +pub type RXFIFO_FULL_R = crate::BitReader; +#[doc = "Field `RXFIFO_FULL` writer - This is the enable bit for rxfifo_full_int_st register."] +pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY` reader - This is the enable bit for txfifo_empty_int_st register."] +pub type TXFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY` writer - This is the enable bit for txfifo_empty_int_st register."] +pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR` reader - This is the enable bit for parity_err_int_st register."] +pub type PARITY_ERR_R = crate::BitReader; +#[doc = "Field `PARITY_ERR` writer - This is the enable bit for parity_err_int_st register."] +pub type PARITY_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR` reader - This is the enable bit for frm_err_int_st register."] +pub type FRM_ERR_R = crate::BitReader; +#[doc = "Field `FRM_ERR` writer - This is the enable bit for frm_err_int_st register."] +pub type FRM_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF` reader - This is the enable bit for rxfifo_ovf_int_st register."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` writer - This is the enable bit for rxfifo_ovf_int_st register."] +pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG` reader - This is the enable bit for dsr_chg_int_st register."] +pub type DSR_CHG_R = crate::BitReader; +#[doc = "Field `DSR_CHG` writer - This is the enable bit for dsr_chg_int_st register."] +pub type DSR_CHG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG` reader - This is the enable bit for cts_chg_int_st register."] +pub type CTS_CHG_R = crate::BitReader; +#[doc = "Field `CTS_CHG` writer - This is the enable bit for cts_chg_int_st register."] +pub type CTS_CHG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET` reader - This is the enable bit for brk_det_int_st register."] +pub type BRK_DET_R = crate::BitReader; +#[doc = "Field `BRK_DET` writer - This is the enable bit for brk_det_int_st register."] +pub type BRK_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT` reader - This is the enable bit for rxfifo_tout_int_st register."] +pub type RXFIFO_TOUT_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT` writer - This is the enable bit for rxfifo_tout_int_st register."] +pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON` reader - This is the enable bit for sw_xon_int_st register."] +pub type SW_XON_R = crate::BitReader; +#[doc = "Field `SW_XON` writer - This is the enable bit for sw_xon_int_st register."] +pub type SW_XON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF` reader - This is the enable bit for sw_xoff_int_st register."] +pub type SW_XOFF_R = crate::BitReader; +#[doc = "Field `SW_XOFF` writer - This is the enable bit for sw_xoff_int_st register."] +pub type SW_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET` reader - This is the enable bit for glitch_det_int_st register."] +pub type GLITCH_DET_R = crate::BitReader; +#[doc = "Field `GLITCH_DET` writer - This is the enable bit for glitch_det_int_st register."] +pub type GLITCH_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE` reader - This is the enable bit for tx_brk_done_int_st register."] +pub type TX_BRK_DONE_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE` writer - This is the enable bit for tx_brk_done_int_st register."] +pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE` reader - This is the enable bit for tx_brk_idle_done_int_st register."] +pub type TX_BRK_IDLE_DONE_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE` writer - This is the enable bit for tx_brk_idle_done_int_st register."] +pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE` reader - This is the enable bit for tx_done_int_st register."] +pub type TX_DONE_R = crate::BitReader; +#[doc = "Field `TX_DONE` writer - This is the enable bit for tx_done_int_st register."] +pub type TX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET` reader - This is the enable bit for at_cmd_char_det_int_st register."] +pub type AT_CMD_CHAR_DET_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET` writer - This is the enable bit for at_cmd_char_det_int_st register."] +pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP` reader - This is the enable bit for uart_wakeup_int_st register."] +pub type WAKEUP_R = crate::BitReader; +#[doc = "Field `WAKEUP` writer - This is the enable bit for uart_wakeup_int_st register."] +pub type WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."] #[inline(always)] - pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R { - RXFIFO_FULL_INT_ENA_R::new((self.bits & 1) != 0) + pub fn rxfifo_full(&self) -> RXFIFO_FULL_R { + RXFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."] #[inline(always)] - pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R { - TXFIFO_EMPTY_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R { + TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."] #[inline(always)] - pub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R { - PARITY_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + pub fn parity_err(&self) -> PARITY_ERR_R { + PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."] #[inline(always)] - pub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R { - FRM_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + pub fn frm_err(&self) -> FRM_ERR_R { + FRM_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."] #[inline(always)] - pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { - RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."] #[inline(always)] - pub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R { - DSR_CHG_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + pub fn dsr_chg(&self) -> DSR_CHG_R { + DSR_CHG_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."] #[inline(always)] - pub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R { - CTS_CHG_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + pub fn cts_chg(&self) -> CTS_CHG_R { + CTS_CHG_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."] #[inline(always)] - pub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R { - BRK_DET_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + pub fn brk_det(&self) -> BRK_DET_R { + BRK_DET_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."] #[inline(always)] - pub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R { - RXFIFO_TOUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R { + RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."] #[inline(always)] - pub fn sw_xon_int_ena(&self) -> SW_XON_INT_ENA_R { - SW_XON_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + pub fn sw_xon(&self) -> SW_XON_R { + SW_XON_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."] #[inline(always)] - pub fn sw_xoff_int_ena(&self) -> SW_XOFF_INT_ENA_R { - SW_XOFF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + pub fn sw_xoff(&self) -> SW_XOFF_R { + SW_XOFF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."] #[inline(always)] - pub fn glitch_det_int_ena(&self) -> GLITCH_DET_INT_ENA_R { - GLITCH_DET_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + pub fn glitch_det(&self) -> GLITCH_DET_R { + GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."] #[inline(always)] - pub fn tx_brk_done_int_ena(&self) -> TX_BRK_DONE_INT_ENA_R { - TX_BRK_DONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + pub fn tx_brk_done(&self) -> TX_BRK_DONE_R { + TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."] #[inline(always)] - pub fn tx_brk_idle_done_int_ena(&self) -> TX_BRK_IDLE_DONE_INT_ENA_R { - TX_BRK_IDLE_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R { + TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."] #[inline(always)] - pub fn tx_done_int_ena(&self) -> TX_DONE_INT_ENA_R { - TX_DONE_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + pub fn tx_done(&self) -> TX_DONE_R { + TX_DONE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."] #[inline(always)] - pub fn at_cmd_char_det_int_ena(&self) -> AT_CMD_CHAR_DET_INT_ENA_R { - AT_CMD_CHAR_DET_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R { + AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."] #[inline(always)] - pub fn wakeup_int_ena(&self) -> WAKEUP_INT_ENA_R { - WAKEUP_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 19) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ENA") + .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit())) .field( - "rxfifo_full_int_ena", - &format_args!("{}", self.rxfifo_full_int_ena().bit()), + "txfifo_empty", + &format_args!("{}", self.txfifo_empty().bit()), ) + .field("parity_err", &format_args!("{}", self.parity_err().bit())) + .field("frm_err", &format_args!("{}", self.frm_err().bit())) + .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit())) + .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit())) + .field("cts_chg", &format_args!("{}", self.cts_chg().bit())) + .field("brk_det", &format_args!("{}", self.brk_det().bit())) + .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit())) + .field("sw_xon", &format_args!("{}", self.sw_xon().bit())) + .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit())) + .field("glitch_det", &format_args!("{}", self.glitch_det().bit())) + .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit())) .field( - "txfifo_empty_int_ena", - &format_args!("{}", self.txfifo_empty_int_ena().bit()), + "tx_brk_idle_done", + &format_args!("{}", self.tx_brk_idle_done().bit()), ) + .field("tx_done", &format_args!("{}", self.tx_done().bit())) .field( - "parity_err_int_ena", - &format_args!("{}", self.parity_err_int_ena().bit()), - ) - .field( - "frm_err_int_ena", - &format_args!("{}", self.frm_err_int_ena().bit()), - ) - .field( - "rxfifo_ovf_int_ena", - &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), - ) - .field( - "dsr_chg_int_ena", - &format_args!("{}", self.dsr_chg_int_ena().bit()), - ) - .field( - "cts_chg_int_ena", - &format_args!("{}", self.cts_chg_int_ena().bit()), - ) - .field( - "brk_det_int_ena", - &format_args!("{}", self.brk_det_int_ena().bit()), - ) - .field( - "rxfifo_tout_int_ena", - &format_args!("{}", self.rxfifo_tout_int_ena().bit()), - ) - .field( - "sw_xon_int_ena", - &format_args!("{}", self.sw_xon_int_ena().bit()), - ) - .field( - "sw_xoff_int_ena", - &format_args!("{}", self.sw_xoff_int_ena().bit()), - ) - .field( - "glitch_det_int_ena", - &format_args!("{}", self.glitch_det_int_ena().bit()), - ) - .field( - "tx_brk_done_int_ena", - &format_args!("{}", self.tx_brk_done_int_ena().bit()), - ) - .field( - "tx_brk_idle_done_int_ena", - &format_args!("{}", self.tx_brk_idle_done_int_ena().bit()), - ) - .field( - "tx_done_int_ena", - &format_args!("{}", self.tx_done_int_ena().bit()), - ) - .field( - "at_cmd_char_det_int_ena", - &format_args!("{}", self.at_cmd_char_det_int_ena().bit()), - ) - .field( - "wakeup_int_ena", - &format_args!("{}", self.wakeup_int_ena().bit()), + "at_cmd_char_det", + &format_args!("{}", self.at_cmd_char_det().bit()), ) + .field("wakeup", &format_args!("{}", self.wakeup().bit())) .finish() } } @@ -242,104 +200,104 @@ impl W { #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."] #[inline(always)] #[must_use] - pub fn rxfifo_full_int_ena(&mut self) -> RXFIFO_FULL_INT_ENA_W { - RXFIFO_FULL_INT_ENA_W::new(self, 0) + pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W { + RXFIFO_FULL_W::new(self, 0) } #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."] #[inline(always)] #[must_use] - pub fn txfifo_empty_int_ena(&mut self) -> TXFIFO_EMPTY_INT_ENA_W { - TXFIFO_EMPTY_INT_ENA_W::new(self, 1) + pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W { + TXFIFO_EMPTY_W::new(self, 1) } #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."] #[inline(always)] #[must_use] - pub fn parity_err_int_ena(&mut self) -> PARITY_ERR_INT_ENA_W { - PARITY_ERR_INT_ENA_W::new(self, 2) + pub fn parity_err(&mut self) -> PARITY_ERR_W { + PARITY_ERR_W::new(self, 2) } #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."] #[inline(always)] #[must_use] - pub fn frm_err_int_ena(&mut self) -> FRM_ERR_INT_ENA_W { - FRM_ERR_INT_ENA_W::new(self, 3) + pub fn frm_err(&mut self) -> FRM_ERR_W { + FRM_ERR_W::new(self, 3) } #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."] #[inline(always)] #[must_use] - pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { - RXFIFO_OVF_INT_ENA_W::new(self, 4) + pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W { + RXFIFO_OVF_W::new(self, 4) } #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."] #[inline(always)] #[must_use] - pub fn dsr_chg_int_ena(&mut self) -> DSR_CHG_INT_ENA_W { - DSR_CHG_INT_ENA_W::new(self, 5) + pub fn dsr_chg(&mut self) -> DSR_CHG_W { + DSR_CHG_W::new(self, 5) } #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."] #[inline(always)] #[must_use] - pub fn cts_chg_int_ena(&mut self) -> CTS_CHG_INT_ENA_W { - CTS_CHG_INT_ENA_W::new(self, 6) + pub fn cts_chg(&mut self) -> CTS_CHG_W { + CTS_CHG_W::new(self, 6) } #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."] #[inline(always)] #[must_use] - pub fn brk_det_int_ena(&mut self) -> BRK_DET_INT_ENA_W { - BRK_DET_INT_ENA_W::new(self, 7) + pub fn brk_det(&mut self) -> BRK_DET_W { + BRK_DET_W::new(self, 7) } #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."] #[inline(always)] #[must_use] - pub fn rxfifo_tout_int_ena(&mut self) -> RXFIFO_TOUT_INT_ENA_W { - RXFIFO_TOUT_INT_ENA_W::new(self, 8) + pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W { + RXFIFO_TOUT_W::new(self, 8) } #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."] #[inline(always)] #[must_use] - pub fn sw_xon_int_ena(&mut self) -> SW_XON_INT_ENA_W { - SW_XON_INT_ENA_W::new(self, 9) + pub fn sw_xon(&mut self) -> SW_XON_W { + SW_XON_W::new(self, 9) } #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."] #[inline(always)] #[must_use] - pub fn sw_xoff_int_ena(&mut self) -> SW_XOFF_INT_ENA_W { - SW_XOFF_INT_ENA_W::new(self, 10) + pub fn sw_xoff(&mut self) -> SW_XOFF_W { + SW_XOFF_W::new(self, 10) } #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."] #[inline(always)] #[must_use] - pub fn glitch_det_int_ena(&mut self) -> GLITCH_DET_INT_ENA_W { - GLITCH_DET_INT_ENA_W::new(self, 11) + pub fn glitch_det(&mut self) -> GLITCH_DET_W { + GLITCH_DET_W::new(self, 11) } #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."] #[inline(always)] #[must_use] - pub fn tx_brk_done_int_ena(&mut self) -> TX_BRK_DONE_INT_ENA_W { - TX_BRK_DONE_INT_ENA_W::new(self, 12) + pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W { + TX_BRK_DONE_W::new(self, 12) } #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."] #[inline(always)] #[must_use] - pub fn tx_brk_idle_done_int_ena(&mut self) -> TX_BRK_IDLE_DONE_INT_ENA_W { - TX_BRK_IDLE_DONE_INT_ENA_W::new(self, 13) + pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W { + TX_BRK_IDLE_DONE_W::new(self, 13) } #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."] #[inline(always)] #[must_use] - pub fn tx_done_int_ena(&mut self) -> TX_DONE_INT_ENA_W { - TX_DONE_INT_ENA_W::new(self, 14) + pub fn tx_done(&mut self) -> TX_DONE_W { + TX_DONE_W::new(self, 14) } #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."] #[inline(always)] #[must_use] - pub fn at_cmd_char_det_int_ena(&mut self) -> AT_CMD_CHAR_DET_INT_ENA_W { - AT_CMD_CHAR_DET_INT_ENA_W::new(self, 18) + pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W { + AT_CMD_CHAR_DET_W::new(self, 18) } #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."] #[inline(always)] #[must_use] - pub fn wakeup_int_ena(&mut self) -> WAKEUP_INT_ENA_W { - WAKEUP_INT_ENA_W::new(self, 19) + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W::new(self, 19) } } #[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/lp_uart/int_raw.rs b/esp32p4/src/lp_uart/int_raw.rs index 3c5cceeb53..dcfb481c5d 100644 --- a/esp32p4/src/lp_uart/int_raw.rs +++ b/esp32p4/src/lp_uart/int_raw.rs @@ -2,233 +2,191 @@ pub type R = crate::R; #[doc = "Register `INT_RAW` writer"] pub type W = crate::W; -#[doc = "Field `RXFIFO_FULL_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] -pub type RXFIFO_FULL_INT_RAW_R = crate::BitReader; -#[doc = "Field `RXFIFO_FULL_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] -pub type RXFIFO_FULL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TXFIFO_EMPTY_INT_RAW` reader - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] -pub type TXFIFO_EMPTY_INT_RAW_R = crate::BitReader; -#[doc = "Field `TXFIFO_EMPTY_INT_RAW` writer - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] -pub type TXFIFO_EMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PARITY_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] -pub type PARITY_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `PARITY_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] -pub type PARITY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FRM_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a data frame error ."] -pub type FRM_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `FRM_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a data frame error ."] -pub type FRM_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] -pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `RXFIFO_OVF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] -pub type RXFIFO_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DSR_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] -pub type DSR_CHG_INT_RAW_R = crate::BitReader; -#[doc = "Field `DSR_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] -pub type DSR_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CTS_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] -pub type CTS_CHG_INT_RAW_R = crate::BitReader; -#[doc = "Field `CTS_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] -pub type CTS_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BRK_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] -pub type BRK_DET_INT_RAW_R = crate::BitReader; -#[doc = "Field `BRK_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] -pub type BRK_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RXFIFO_TOUT_INT_RAW` reader - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] -pub type RXFIFO_TOUT_INT_RAW_R = crate::BitReader; -#[doc = "Field `RXFIFO_TOUT_INT_RAW` writer - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] -pub type RXFIFO_TOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SW_XON_INT_RAW` reader - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] -pub type SW_XON_INT_RAW_R = crate::BitReader; -#[doc = "Field `SW_XON_INT_RAW` writer - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] -pub type SW_XON_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SW_XOFF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] -pub type SW_XOFF_INT_RAW_R = crate::BitReader; -#[doc = "Field `SW_XOFF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] -pub type SW_XOFF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GLITCH_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] -pub type GLITCH_DET_INT_RAW_R = crate::BitReader; -#[doc = "Field `GLITCH_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] -pub type GLITCH_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_BRK_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] -pub type TX_BRK_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `TX_BRK_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] -pub type TX_BRK_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] -pub type TX_BRK_IDLE_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] -pub type TX_BRK_IDLE_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] -pub type TX_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `TX_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] -pub type TX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] -pub type AT_CMD_CHAR_DET_INT_RAW_R = crate::BitReader; -#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] -pub type AT_CMD_CHAR_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `WAKEUP_INT_RAW` reader - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] -pub type WAKEUP_INT_RAW_R = crate::BitReader; -#[doc = "Field `WAKEUP_INT_RAW` writer - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] -pub type WAKEUP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_FULL` reader - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] +pub type RXFIFO_FULL_R = crate::BitReader; +#[doc = "Field `RXFIFO_FULL` writer - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] +pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY` reader - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] +pub type TXFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY` writer - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] +pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR` reader - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] +pub type PARITY_ERR_R = crate::BitReader; +#[doc = "Field `PARITY_ERR` writer - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] +pub type PARITY_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR` reader - This interrupt raw bit turns to high level when receiver detects a data frame error ."] +pub type FRM_ERR_R = crate::BitReader; +#[doc = "Field `FRM_ERR` writer - This interrupt raw bit turns to high level when receiver detects a data frame error ."] +pub type FRM_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF` reader - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` writer - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] +pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG` reader - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] +pub type DSR_CHG_R = crate::BitReader; +#[doc = "Field `DSR_CHG` writer - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] +pub type DSR_CHG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG` reader - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] +pub type CTS_CHG_R = crate::BitReader; +#[doc = "Field `CTS_CHG` writer - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] +pub type CTS_CHG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET` reader - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] +pub type BRK_DET_R = crate::BitReader; +#[doc = "Field `BRK_DET` writer - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] +pub type BRK_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT` reader - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] +pub type RXFIFO_TOUT_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT` writer - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] +pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON` reader - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] +pub type SW_XON_R = crate::BitReader; +#[doc = "Field `SW_XON` writer - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] +pub type SW_XON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF` reader - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] +pub type SW_XOFF_R = crate::BitReader; +#[doc = "Field `SW_XOFF` writer - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] +pub type SW_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET` reader - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] +pub type GLITCH_DET_R = crate::BitReader; +#[doc = "Field `GLITCH_DET` writer - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] +pub type GLITCH_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE` reader - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] +pub type TX_BRK_DONE_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE` writer - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] +pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE` reader - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] +pub type TX_BRK_IDLE_DONE_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE` writer - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] +pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE` reader - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] +pub type TX_DONE_R = crate::BitReader; +#[doc = "Field `TX_DONE` writer - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] +pub type TX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET` reader - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] +pub type AT_CMD_CHAR_DET_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET` writer - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] +pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP` reader - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] +pub type WAKEUP_R = crate::BitReader; +#[doc = "Field `WAKEUP` writer - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] +pub type WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] #[inline(always)] - pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R { - RXFIFO_FULL_INT_RAW_R::new((self.bits & 1) != 0) + pub fn rxfifo_full(&self) -> RXFIFO_FULL_R { + RXFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] #[inline(always)] - pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R { - TXFIFO_EMPTY_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R { + TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] #[inline(always)] - pub fn parity_err_int_raw(&self) -> PARITY_ERR_INT_RAW_R { - PARITY_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + pub fn parity_err(&self) -> PARITY_ERR_R { + PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."] #[inline(always)] - pub fn frm_err_int_raw(&self) -> FRM_ERR_INT_RAW_R { - FRM_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + pub fn frm_err(&self) -> FRM_ERR_R { + FRM_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] #[inline(always)] - pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { - RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] #[inline(always)] - pub fn dsr_chg_int_raw(&self) -> DSR_CHG_INT_RAW_R { - DSR_CHG_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + pub fn dsr_chg(&self) -> DSR_CHG_R { + DSR_CHG_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] #[inline(always)] - pub fn cts_chg_int_raw(&self) -> CTS_CHG_INT_RAW_R { - CTS_CHG_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + pub fn cts_chg(&self) -> CTS_CHG_R { + CTS_CHG_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] #[inline(always)] - pub fn brk_det_int_raw(&self) -> BRK_DET_INT_RAW_R { - BRK_DET_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + pub fn brk_det(&self) -> BRK_DET_R { + BRK_DET_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] #[inline(always)] - pub fn rxfifo_tout_int_raw(&self) -> RXFIFO_TOUT_INT_RAW_R { - RXFIFO_TOUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R { + RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] #[inline(always)] - pub fn sw_xon_int_raw(&self) -> SW_XON_INT_RAW_R { - SW_XON_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + pub fn sw_xon(&self) -> SW_XON_R { + SW_XON_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] #[inline(always)] - pub fn sw_xoff_int_raw(&self) -> SW_XOFF_INT_RAW_R { - SW_XOFF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + pub fn sw_xoff(&self) -> SW_XOFF_R { + SW_XOFF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] #[inline(always)] - pub fn glitch_det_int_raw(&self) -> GLITCH_DET_INT_RAW_R { - GLITCH_DET_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + pub fn glitch_det(&self) -> GLITCH_DET_R { + GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] #[inline(always)] - pub fn tx_brk_done_int_raw(&self) -> TX_BRK_DONE_INT_RAW_R { - TX_BRK_DONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + pub fn tx_brk_done(&self) -> TX_BRK_DONE_R { + TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] #[inline(always)] - pub fn tx_brk_idle_done_int_raw(&self) -> TX_BRK_IDLE_DONE_INT_RAW_R { - TX_BRK_IDLE_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R { + TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] #[inline(always)] - pub fn tx_done_int_raw(&self) -> TX_DONE_INT_RAW_R { - TX_DONE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + pub fn tx_done(&self) -> TX_DONE_R { + TX_DONE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] #[inline(always)] - pub fn at_cmd_char_det_int_raw(&self) -> AT_CMD_CHAR_DET_INT_RAW_R { - AT_CMD_CHAR_DET_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R { + AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] #[inline(always)] - pub fn wakeup_int_raw(&self) -> WAKEUP_INT_RAW_R { - WAKEUP_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 19) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_RAW") + .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit())) .field( - "rxfifo_full_int_raw", - &format_args!("{}", self.rxfifo_full_int_raw().bit()), + "txfifo_empty", + &format_args!("{}", self.txfifo_empty().bit()), ) + .field("parity_err", &format_args!("{}", self.parity_err().bit())) + .field("frm_err", &format_args!("{}", self.frm_err().bit())) + .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit())) + .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit())) + .field("cts_chg", &format_args!("{}", self.cts_chg().bit())) + .field("brk_det", &format_args!("{}", self.brk_det().bit())) + .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit())) + .field("sw_xon", &format_args!("{}", self.sw_xon().bit())) + .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit())) + .field("glitch_det", &format_args!("{}", self.glitch_det().bit())) + .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit())) .field( - "txfifo_empty_int_raw", - &format_args!("{}", self.txfifo_empty_int_raw().bit()), + "tx_brk_idle_done", + &format_args!("{}", self.tx_brk_idle_done().bit()), ) + .field("tx_done", &format_args!("{}", self.tx_done().bit())) .field( - "parity_err_int_raw", - &format_args!("{}", self.parity_err_int_raw().bit()), - ) - .field( - "frm_err_int_raw", - &format_args!("{}", self.frm_err_int_raw().bit()), - ) - .field( - "rxfifo_ovf_int_raw", - &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), - ) - .field( - "dsr_chg_int_raw", - &format_args!("{}", self.dsr_chg_int_raw().bit()), - ) - .field( - "cts_chg_int_raw", - &format_args!("{}", self.cts_chg_int_raw().bit()), - ) - .field( - "brk_det_int_raw", - &format_args!("{}", self.brk_det_int_raw().bit()), - ) - .field( - "rxfifo_tout_int_raw", - &format_args!("{}", self.rxfifo_tout_int_raw().bit()), - ) - .field( - "sw_xon_int_raw", - &format_args!("{}", self.sw_xon_int_raw().bit()), - ) - .field( - "sw_xoff_int_raw", - &format_args!("{}", self.sw_xoff_int_raw().bit()), - ) - .field( - "glitch_det_int_raw", - &format_args!("{}", self.glitch_det_int_raw().bit()), - ) - .field( - "tx_brk_done_int_raw", - &format_args!("{}", self.tx_brk_done_int_raw().bit()), - ) - .field( - "tx_brk_idle_done_int_raw", - &format_args!("{}", self.tx_brk_idle_done_int_raw().bit()), - ) - .field( - "tx_done_int_raw", - &format_args!("{}", self.tx_done_int_raw().bit()), - ) - .field( - "at_cmd_char_det_int_raw", - &format_args!("{}", self.at_cmd_char_det_int_raw().bit()), - ) - .field( - "wakeup_int_raw", - &format_args!("{}", self.wakeup_int_raw().bit()), + "at_cmd_char_det", + &format_args!("{}", self.at_cmd_char_det().bit()), ) + .field("wakeup", &format_args!("{}", self.wakeup().bit())) .finish() } } @@ -242,104 +200,104 @@ impl W { #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] #[inline(always)] #[must_use] - pub fn rxfifo_full_int_raw(&mut self) -> RXFIFO_FULL_INT_RAW_W { - RXFIFO_FULL_INT_RAW_W::new(self, 0) + pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W { + RXFIFO_FULL_W::new(self, 0) } #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] #[inline(always)] #[must_use] - pub fn txfifo_empty_int_raw(&mut self) -> TXFIFO_EMPTY_INT_RAW_W { - TXFIFO_EMPTY_INT_RAW_W::new(self, 1) + pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W { + TXFIFO_EMPTY_W::new(self, 1) } #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] #[inline(always)] #[must_use] - pub fn parity_err_int_raw(&mut self) -> PARITY_ERR_INT_RAW_W { - PARITY_ERR_INT_RAW_W::new(self, 2) + pub fn parity_err(&mut self) -> PARITY_ERR_W { + PARITY_ERR_W::new(self, 2) } #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."] #[inline(always)] #[must_use] - pub fn frm_err_int_raw(&mut self) -> FRM_ERR_INT_RAW_W { - FRM_ERR_INT_RAW_W::new(self, 3) + pub fn frm_err(&mut self) -> FRM_ERR_W { + FRM_ERR_W::new(self, 3) } #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] #[inline(always)] #[must_use] - pub fn rxfifo_ovf_int_raw(&mut self) -> RXFIFO_OVF_INT_RAW_W { - RXFIFO_OVF_INT_RAW_W::new(self, 4) + pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W { + RXFIFO_OVF_W::new(self, 4) } #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] #[inline(always)] #[must_use] - pub fn dsr_chg_int_raw(&mut self) -> DSR_CHG_INT_RAW_W { - DSR_CHG_INT_RAW_W::new(self, 5) + pub fn dsr_chg(&mut self) -> DSR_CHG_W { + DSR_CHG_W::new(self, 5) } #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] #[inline(always)] #[must_use] - pub fn cts_chg_int_raw(&mut self) -> CTS_CHG_INT_RAW_W { - CTS_CHG_INT_RAW_W::new(self, 6) + pub fn cts_chg(&mut self) -> CTS_CHG_W { + CTS_CHG_W::new(self, 6) } #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] #[inline(always)] #[must_use] - pub fn brk_det_int_raw(&mut self) -> BRK_DET_INT_RAW_W { - BRK_DET_INT_RAW_W::new(self, 7) + pub fn brk_det(&mut self) -> BRK_DET_W { + BRK_DET_W::new(self, 7) } #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] #[inline(always)] #[must_use] - pub fn rxfifo_tout_int_raw(&mut self) -> RXFIFO_TOUT_INT_RAW_W { - RXFIFO_TOUT_INT_RAW_W::new(self, 8) + pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W { + RXFIFO_TOUT_W::new(self, 8) } #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] #[inline(always)] #[must_use] - pub fn sw_xon_int_raw(&mut self) -> SW_XON_INT_RAW_W { - SW_XON_INT_RAW_W::new(self, 9) + pub fn sw_xon(&mut self) -> SW_XON_W { + SW_XON_W::new(self, 9) } #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] #[inline(always)] #[must_use] - pub fn sw_xoff_int_raw(&mut self) -> SW_XOFF_INT_RAW_W { - SW_XOFF_INT_RAW_W::new(self, 10) + pub fn sw_xoff(&mut self) -> SW_XOFF_W { + SW_XOFF_W::new(self, 10) } #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] #[inline(always)] #[must_use] - pub fn glitch_det_int_raw(&mut self) -> GLITCH_DET_INT_RAW_W { - GLITCH_DET_INT_RAW_W::new(self, 11) + pub fn glitch_det(&mut self) -> GLITCH_DET_W { + GLITCH_DET_W::new(self, 11) } #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] #[inline(always)] #[must_use] - pub fn tx_brk_done_int_raw(&mut self) -> TX_BRK_DONE_INT_RAW_W { - TX_BRK_DONE_INT_RAW_W::new(self, 12) + pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W { + TX_BRK_DONE_W::new(self, 12) } #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] #[inline(always)] #[must_use] - pub fn tx_brk_idle_done_int_raw(&mut self) -> TX_BRK_IDLE_DONE_INT_RAW_W { - TX_BRK_IDLE_DONE_INT_RAW_W::new(self, 13) + pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W { + TX_BRK_IDLE_DONE_W::new(self, 13) } #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] #[inline(always)] #[must_use] - pub fn tx_done_int_raw(&mut self) -> TX_DONE_INT_RAW_W { - TX_DONE_INT_RAW_W::new(self, 14) + pub fn tx_done(&mut self) -> TX_DONE_W { + TX_DONE_W::new(self, 14) } #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] #[inline(always)] #[must_use] - pub fn at_cmd_char_det_int_raw(&mut self) -> AT_CMD_CHAR_DET_INT_RAW_W { - AT_CMD_CHAR_DET_INT_RAW_W::new(self, 18) + pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W { + AT_CMD_CHAR_DET_W::new(self, 18) } #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] #[inline(always)] #[must_use] - pub fn wakeup_int_raw(&mut self) -> WAKEUP_INT_RAW_W { - WAKEUP_INT_RAW_W::new(self, 19) + pub fn wakeup(&mut self) -> WAKEUP_W { + WAKEUP_W::new(self, 19) } } #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32p4/src/lp_uart/int_st.rs b/esp32p4/src/lp_uart/int_st.rs index 28c0c94055..82aaf89509 100644 --- a/esp32p4/src/lp_uart/int_st.rs +++ b/esp32p4/src/lp_uart/int_st.rs @@ -1,198 +1,156 @@ #[doc = "Register `INT_ST` reader"] pub type R = crate::R; -#[doc = "Field `RXFIFO_FULL_INT_ST` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."] -pub type RXFIFO_FULL_INT_ST_R = crate::BitReader; -#[doc = "Field `TXFIFO_EMPTY_INT_ST` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."] -pub type TXFIFO_EMPTY_INT_ST_R = crate::BitReader; -#[doc = "Field `PARITY_ERR_INT_ST` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."] -pub type PARITY_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `FRM_ERR_INT_ST` reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."] -pub type FRM_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `RXFIFO_OVF_INT_ST` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."] -pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `DSR_CHG_INT_ST` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."] -pub type DSR_CHG_INT_ST_R = crate::BitReader; -#[doc = "Field `CTS_CHG_INT_ST` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."] -pub type CTS_CHG_INT_ST_R = crate::BitReader; -#[doc = "Field `BRK_DET_INT_ST` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."] -pub type BRK_DET_INT_ST_R = crate::BitReader; -#[doc = "Field `RXFIFO_TOUT_INT_ST` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."] -pub type RXFIFO_TOUT_INT_ST_R = crate::BitReader; -#[doc = "Field `SW_XON_INT_ST` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."] -pub type SW_XON_INT_ST_R = crate::BitReader; -#[doc = "Field `SW_XOFF_INT_ST` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."] -pub type SW_XOFF_INT_ST_R = crate::BitReader; -#[doc = "Field `GLITCH_DET_INT_ST` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."] -pub type GLITCH_DET_INT_ST_R = crate::BitReader; -#[doc = "Field `TX_BRK_DONE_INT_ST` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."] -pub type TX_BRK_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `TX_BRK_IDLE_DONE_INT_ST` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."] -pub type TX_BRK_IDLE_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `TX_DONE_INT_ST` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."] -pub type TX_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `AT_CMD_CHAR_DET_INT_ST` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."] -pub type AT_CMD_CHAR_DET_INT_ST_R = crate::BitReader; -#[doc = "Field `WAKEUP_INT_ST` reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."] -pub type WAKEUP_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_FULL` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."] +pub type RXFIFO_FULL_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."] +pub type TXFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `PARITY_ERR` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."] +pub type PARITY_ERR_R = crate::BitReader; +#[doc = "Field `FRM_ERR` reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."] +pub type FRM_ERR_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."] +pub type RXFIFO_OVF_R = crate::BitReader; +#[doc = "Field `DSR_CHG` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."] +pub type DSR_CHG_R = crate::BitReader; +#[doc = "Field `CTS_CHG` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."] +pub type CTS_CHG_R = crate::BitReader; +#[doc = "Field `BRK_DET` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."] +pub type BRK_DET_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."] +pub type RXFIFO_TOUT_R = crate::BitReader; +#[doc = "Field `SW_XON` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."] +pub type SW_XON_R = crate::BitReader; +#[doc = "Field `SW_XOFF` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."] +pub type SW_XOFF_R = crate::BitReader; +#[doc = "Field `GLITCH_DET` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."] +pub type GLITCH_DET_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."] +pub type TX_BRK_DONE_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."] +pub type TX_BRK_IDLE_DONE_R = crate::BitReader; +#[doc = "Field `TX_DONE` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."] +pub type TX_DONE_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."] +pub type AT_CMD_CHAR_DET_R = crate::BitReader; +#[doc = "Field `WAKEUP` reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."] +pub type WAKEUP_R = crate::BitReader; impl R { #[doc = "Bit 0 - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."] #[inline(always)] - pub fn rxfifo_full_int_st(&self) -> RXFIFO_FULL_INT_ST_R { - RXFIFO_FULL_INT_ST_R::new((self.bits & 1) != 0) + pub fn rxfifo_full(&self) -> RXFIFO_FULL_R { + RXFIFO_FULL_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."] #[inline(always)] - pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R { - TXFIFO_EMPTY_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R { + TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } #[doc = "Bit 2 - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."] #[inline(always)] - pub fn parity_err_int_st(&self) -> PARITY_ERR_INT_ST_R { - PARITY_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + pub fn parity_err(&self) -> PARITY_ERR_R { + PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."] #[inline(always)] - pub fn frm_err_int_st(&self) -> FRM_ERR_INT_ST_R { - FRM_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + pub fn frm_err(&self) -> FRM_ERR_R { + FRM_ERR_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."] #[inline(always)] - pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { - RXFIFO_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R { + RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."] #[inline(always)] - pub fn dsr_chg_int_st(&self) -> DSR_CHG_INT_ST_R { - DSR_CHG_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + pub fn dsr_chg(&self) -> DSR_CHG_R { + DSR_CHG_R::new(((self.bits >> 5) & 1) != 0) } #[doc = "Bit 6 - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."] #[inline(always)] - pub fn cts_chg_int_st(&self) -> CTS_CHG_INT_ST_R { - CTS_CHG_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + pub fn cts_chg(&self) -> CTS_CHG_R { + CTS_CHG_R::new(((self.bits >> 6) & 1) != 0) } #[doc = "Bit 7 - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."] #[inline(always)] - pub fn brk_det_int_st(&self) -> BRK_DET_INT_ST_R { - BRK_DET_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + pub fn brk_det(&self) -> BRK_DET_R { + BRK_DET_R::new(((self.bits >> 7) & 1) != 0) } #[doc = "Bit 8 - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."] #[inline(always)] - pub fn rxfifo_tout_int_st(&self) -> RXFIFO_TOUT_INT_ST_R { - RXFIFO_TOUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R { + RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0) } #[doc = "Bit 9 - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."] #[inline(always)] - pub fn sw_xon_int_st(&self) -> SW_XON_INT_ST_R { - SW_XON_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + pub fn sw_xon(&self) -> SW_XON_R { + SW_XON_R::new(((self.bits >> 9) & 1) != 0) } #[doc = "Bit 10 - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."] #[inline(always)] - pub fn sw_xoff_int_st(&self) -> SW_XOFF_INT_ST_R { - SW_XOFF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + pub fn sw_xoff(&self) -> SW_XOFF_R { + SW_XOFF_R::new(((self.bits >> 10) & 1) != 0) } #[doc = "Bit 11 - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."] #[inline(always)] - pub fn glitch_det_int_st(&self) -> GLITCH_DET_INT_ST_R { - GLITCH_DET_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + pub fn glitch_det(&self) -> GLITCH_DET_R { + GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."] #[inline(always)] - pub fn tx_brk_done_int_st(&self) -> TX_BRK_DONE_INT_ST_R { - TX_BRK_DONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + pub fn tx_brk_done(&self) -> TX_BRK_DONE_R { + TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0) } #[doc = "Bit 13 - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."] #[inline(always)] - pub fn tx_brk_idle_done_int_st(&self) -> TX_BRK_IDLE_DONE_INT_ST_R { - TX_BRK_IDLE_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R { + TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."] #[inline(always)] - pub fn tx_done_int_st(&self) -> TX_DONE_INT_ST_R { - TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + pub fn tx_done(&self) -> TX_DONE_R { + TX_DONE_R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bit 18 - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."] #[inline(always)] - pub fn at_cmd_char_det_int_st(&self) -> AT_CMD_CHAR_DET_INT_ST_R { - AT_CMD_CHAR_DET_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R { + AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0) } #[doc = "Bit 19 - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."] #[inline(always)] - pub fn wakeup_int_st(&self) -> WAKEUP_INT_ST_R { - WAKEUP_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 19) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INT_ST") + .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit())) .field( - "rxfifo_full_int_st", - &format_args!("{}", self.rxfifo_full_int_st().bit()), + "txfifo_empty", + &format_args!("{}", self.txfifo_empty().bit()), ) + .field("parity_err", &format_args!("{}", self.parity_err().bit())) + .field("frm_err", &format_args!("{}", self.frm_err().bit())) + .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit())) + .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit())) + .field("cts_chg", &format_args!("{}", self.cts_chg().bit())) + .field("brk_det", &format_args!("{}", self.brk_det().bit())) + .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit())) + .field("sw_xon", &format_args!("{}", self.sw_xon().bit())) + .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit())) + .field("glitch_det", &format_args!("{}", self.glitch_det().bit())) + .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit())) .field( - "txfifo_empty_int_st", - &format_args!("{}", self.txfifo_empty_int_st().bit()), + "tx_brk_idle_done", + &format_args!("{}", self.tx_brk_idle_done().bit()), ) + .field("tx_done", &format_args!("{}", self.tx_done().bit())) .field( - "parity_err_int_st", - &format_args!("{}", self.parity_err_int_st().bit()), - ) - .field( - "frm_err_int_st", - &format_args!("{}", self.frm_err_int_st().bit()), - ) - .field( - "rxfifo_ovf_int_st", - &format_args!("{}", self.rxfifo_ovf_int_st().bit()), - ) - .field( - "dsr_chg_int_st", - &format_args!("{}", self.dsr_chg_int_st().bit()), - ) - .field( - "cts_chg_int_st", - &format_args!("{}", self.cts_chg_int_st().bit()), - ) - .field( - "brk_det_int_st", - &format_args!("{}", self.brk_det_int_st().bit()), - ) - .field( - "rxfifo_tout_int_st", - &format_args!("{}", self.rxfifo_tout_int_st().bit()), - ) - .field( - "sw_xon_int_st", - &format_args!("{}", self.sw_xon_int_st().bit()), - ) - .field( - "sw_xoff_int_st", - &format_args!("{}", self.sw_xoff_int_st().bit()), - ) - .field( - "glitch_det_int_st", - &format_args!("{}", self.glitch_det_int_st().bit()), - ) - .field( - "tx_brk_done_int_st", - &format_args!("{}", self.tx_brk_done_int_st().bit()), - ) - .field( - "tx_brk_idle_done_int_st", - &format_args!("{}", self.tx_brk_idle_done_int_st().bit()), - ) - .field( - "tx_done_int_st", - &format_args!("{}", self.tx_done_int_st().bit()), - ) - .field( - "at_cmd_char_det_int_st", - &format_args!("{}", self.at_cmd_char_det_int_st().bit()), - ) - .field( - "wakeup_int_st", - &format_args!("{}", self.wakeup_int_st().bit()), + "at_cmd_char_det", + &format_args!("{}", self.at_cmd_char_det().bit()), ) + .field("wakeup", &format_args!("{}", self.wakeup().bit())) .finish() } } diff --git a/esp32p4/svd/patches/esp32p4.yaml b/esp32p4/svd/patches/esp32p4.yaml index 89729fc73c..5ebbe6aab7 100644 --- a/esp32p4/svd/patches/esp32p4.yaml +++ b/esp32p4/svd/patches/esp32p4.yaml @@ -7,6 +7,9 @@ _modify: groupName: DMA LP_ANA_PERI: name: LP_ANA + groupName: LP_ANA + LCD_CAM: + groupName: LCD_CAM LP_ANA: _strip: LP_ANA_ @@ -24,7 +27,7 @@ SPI[01]: "*": _strip: SPI_MEM_ -"ADC,EFUSE,I2C0,I2S0,UART0,SPI[01],SYSTIMER,LP_WDT,PARL_IO,PAU,USB_DEVICE,MIPI_CSI_BRIDGE,MIPI_DSI_BRIDGE,ECDSA,GPIO,H264,PPA,RMT,LP_TOUCH,LP_TSENS": +"ADC,EFUSE,I2C0,I2S0,UART0,SPI[01],SYSTIMER,LP_WDT,PARL_IO,PAU,USB_DEVICE,MIPI_CSI_BRIDGE,MIPI_DSI_BRIDGE,ECDSA,GPIO,H264,PPA,RMT,LP_TOUCH,LP_TSENS,ISP,LP_HUK,LP_I2C0,LP_I2S0,LP_UART": _include: ../../../common_patches/int_strip.yaml LEDC: @@ -77,6 +80,17 @@ GPIO: GPIO_INT0: name: GPIO +I3C_MST: + _modify: + INT_ST_ENA: + name: INT_ENA + _include: ../../../common_patches/int_strip.yaml + +JPEG: + _include: ../../../common_patches/int_strip.yaml + _array: + C?: {} + PMU: _include: ../../../common_patches/pmu_int_strip.yaml