From 1d58d956bacb55049a73420b185f3a55a3cf5922 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Mon, 15 Apr 2024 08:32:48 -0700 Subject: [PATCH] Align register field name between ESP32-S2/S3 for `RTC_IO` peripheral --- esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs | 10 ++++------ esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs | 8 ++++---- esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs | 8 ++++---- esp32s2/svd/patches/esp32s2.yaml | 16 +++++++++++++++- 4 files changed, 27 insertions(+), 15 deletions(-) diff --git a/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs b/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs index 9fa8c27463..3875ee2d43 100644 --- a/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs +++ b/esp32s2/src/rtc_io/rtc_gpio_enable_w1ts.rs @@ -1,7 +1,7 @@ #[doc = "Register `RTC_GPIO_ENABLE_W1TS` writer"] pub type W = crate::W; -#[doc = "Field `REG_RTCIO_REG_GPIO_ENABLE_W1TS` writer - GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG."] -pub type REG_RTCIO_REG_GPIO_ENABLE_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +#[doc = "Field `RTC_GPIO_ENABLE_W1TS` writer - GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG."] +pub type RTC_GPIO_ENABLE_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -12,10 +12,8 @@ impl W { #[doc = "Bits 10:31 - GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG."] #[inline(always)] #[must_use] - pub fn reg_rtcio_reg_gpio_enable_w1ts( - &mut self, - ) -> REG_RTCIO_REG_GPIO_ENABLE_W1TS_W { - REG_RTCIO_REG_GPIO_ENABLE_W1TS_W::new(self, 10) + pub fn rtc_gpio_enable_w1ts(&mut self) -> RTC_GPIO_ENABLE_W1TS_W { + RTC_GPIO_ENABLE_W1TS_W::new(self, 10) } } #[doc = "RTC GPIO output enable bit set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_enable_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs b/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs index 51e56823a6..bc5daa2ec1 100644 --- a/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs +++ b/esp32s2/src/rtc_io/rtc_gpio_out_w1tc.rs @@ -1,7 +1,7 @@ #[doc = "Register `RTC_GPIO_OUT_W1TC` writer"] pub type W = crate::W; -#[doc = "Field `GPIO_OUT_DATA_W1TC` writer - GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG."] -pub type GPIO_OUT_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +#[doc = "Field `RTC_GPIO_OUT_DATA_W1TC` writer - GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG."] +pub type RTC_GPIO_OUT_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -12,8 +12,8 @@ impl W { #[doc = "Bits 10:31 - GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG."] #[inline(always)] #[must_use] - pub fn gpio_out_data_w1tc(&mut self) -> GPIO_OUT_DATA_W1TC_W { - GPIO_OUT_DATA_W1TC_W::new(self, 10) + pub fn rtc_gpio_out_data_w1tc(&mut self) -> RTC_GPIO_OUT_DATA_W1TC_W { + RTC_GPIO_OUT_DATA_W1TC_W::new(self, 10) } } #[doc = "RTC GPIO output bit clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_out_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs b/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs index 73013a157b..1aff7b3e5e 100644 --- a/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs +++ b/esp32s2/src/rtc_io/rtc_gpio_out_w1ts.rs @@ -1,7 +1,7 @@ #[doc = "Register `RTC_GPIO_OUT_W1TS` writer"] pub type W = crate::W; -#[doc = "Field `GPIO_OUT_DATA_W1TS` writer - GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG."] -pub type GPIO_OUT_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +#[doc = "Field `RTC_GPIO_OUT_DATA_W1TS` writer - GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG."] +pub type RTC_GPIO_OUT_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -12,8 +12,8 @@ impl W { #[doc = "Bits 10:31 - GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG."] #[inline(always)] #[must_use] - pub fn gpio_out_data_w1ts(&mut self) -> GPIO_OUT_DATA_W1TS_W { - GPIO_OUT_DATA_W1TS_W::new(self, 10) + pub fn rtc_gpio_out_data_w1ts(&mut self) -> RTC_GPIO_OUT_DATA_W1TS_W { + RTC_GPIO_OUT_DATA_W1TS_W::new(self, 10) } } #[doc = "RTC GPIO output bit set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_out_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32s2/svd/patches/esp32s2.yaml b/esp32s2/svd/patches/esp32s2.yaml index 0a738a4537..98565ce9cb 100644 --- a/esp32s2/svd/patches/esp32s2.yaml +++ b/esp32s2/svd/patches/esp32s2.yaml @@ -17,11 +17,25 @@ RTC_CNTL: name: INT_CLR _include: ../../../common_patches/int_strip.yaml +RTC_IO: + RTC_GPIO_ENABLE_W1TS: + _modify: + REG_RTCIO_REG_GPIO_ENABLE_W1TS: + name: RTC_GPIO_ENABLE_W1TS + RTC_GPIO_OUT_W1TC: + _modify: + GPIO_OUT_DATA_W1TC: + name: RTC_GPIO_OUT_DATA_W1TC + RTC_GPIO_OUT_W1TS: + _modify: + GPIO_OUT_DATA_W1TS: + name: RTC_GPIO_OUT_DATA_W1TS + "EFUSE,I2C0,I2S0,UART0,APB_SARADC,UHCI0,RTC_I2C": _include: ../../../common_patches/int_strip.yaml LEDC: - _include: + _include: - ../../../common_patches/ledc_collect.yaml - ../../../common_patches/ledc_int.yaml INT_RAW: